PCIE interface performance test system

Abstract

The present application relates to a PCIE interface performance testing system. The system includes a motherboard to be tested, including a PCIE interface. The motherboard to be tested is used to write each first PCIE data packet to a PCIE device through the PCIE interface and record the data write start timestamp; after each first PCIE data packet is successfully written, record the data write end timestamp; generate the write performance test result of the PCIE interface based on the write start timestamp, the write end timestamp, and the total size of each first PCIE data packet; and a PCIE device is used to receive each first PCIE data packet and discard the first PCIE data packet after each first PCIE data packet is successfully received. This method can meet the test requirements of the theoretical bandwidth of the PCIE interface.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a PCIE interface performance testing system. Background Art

[0002] The PCIE bus is the most commonly used high-speed peripheral component interconnect (PCI) standard on computer motherboards. Common graphics cards, disk array cards, sound cards, network cards, and interface expansion cards, as well as specialized data acquisition cards and AI accelerator cards, all utilize the PCIE standard. Furthermore, solid-state drives (NVMe SSDs) also utilize the PCIE standard. The PCIE interface is a crucial interface on computer motherboards. With technological advancements, the PCIE standard has evolved from the original Gen1 (2.5 Gbps / s) to Gen2 (5.0 Gbps / s), Gen3 (8.0 Gbps / s), and Gen4 (16.0 Gbps / s). Each PCIE version is categorized as x1, x2, x4, x8, and x16. x1 represents one data lane, x2 represents two data lanes (twice the speed of x1), and so on. Each generation of the PCIE protocol has almost doubled the bus bandwidth, posing significant challenges to bandwidth testing of PCIE interfaces.

[0003] In traditional technology, the read and write bandwidth test of the PCIE slot on the computer motherboard is mostly tested using PCIE devices, such as PCIE network cards, PCIE disk arrays, graphics cards, etc.

[0004] Taking PCIE network cards as an example, two motherboards are required for testing. The tester inserts two PCIE network cards into the PCIE slots on each motherboard and interconnects them with a network cable. After booting the system and entering the system, network speed testing software (such as iperf) is run on each motherboard's operating system. The measured network transmission speed can be used to derive the actual read and write bandwidth of the PCIE slot. This method is feasible for PCIE Gen3 and earlier versions, as well as for PCIE slots Gen4 x4 and below. However, it is not sufficient for PCIE Gen4 x8 and x16 slots. The fastest NICs currently on the market are 100G cards, with a theoretical communication bandwidth of no more than 10GB. However, the theoretical bandwidth of PCIE Gen4 x8 slots is 16GB, and that of x16 slots is 32GB. Therefore, a 100G NIC is far from meeting the bandwidth testing requirements for these slots. Summary of the Invention

[0005] Based on this, it is necessary to provide a PCIE interface performance testing system that can meet the test requirements of the theoretical bandwidth of the PCIE interface in order to address the above technical problems.

[0006] In a first aspect, the present application provides a PCIE interface performance testing system, the system comprising:

[0007] A motherboard to be tested, comprising a PCIE interface, wherein the motherboard to be tested is configured to write each first PCIE data packet to a PCIE device through the PCIE interface and record a data write start timestamp; after each first PCIE data packet is successfully written, record a data write end timestamp; and generate a write performance test result of the PCIE interface based on the write start timestamp, the write end timestamp, and the total size of each first PCIE data packet;

[0008] The PCIE device is configured to receive each of the first PCIE data packets and discard the first PCIE data packet after each of the first PCIE data packets is successfully received.

[0009] In one of the embodiments, the PCIE device is further configured to verify the first PCIE data packet based on a verification mechanism of the PCIE protocol after receiving the first PCIE data packet, and determine that the first PCIE data packet is successfully received if the verification of the first PCIE data packet succeeds.

[0010] In one embodiment, the PCIE device is further configured to return a data write failure message to the motherboard under test when the first PCIE data packet fails to be verified;

[0011] The motherboard to be tested is further configured to record the number of write failures of the first PCIE data packet when receiving the information that the data packet write fails.

[0012] In one embodiment, the motherboard under test is further configured to generate a first PCIE data file and determine each first PCIE data packet based on the first PCIE data file; wherein the size of the first PCIE data file is smaller than the memory of the motherboard under test, and the size of the first PCIE data file is an integer multiple of the size of the data packet corresponding to the PCIE protocol;

[0013] The mainboard to be tested is used to repeatedly determine each first PCIE data packet based on the first PCIE data file, and write each first PCIE data packet into the PCIE device.

[0014] In one embodiment, the total size of each of the first PCIE data packets is greater than a data size threshold, and the total size of each of the first PCIE data packets increases as a theoretical bandwidth corresponding to the PCIE interface increases.

[0015] In a second aspect, the present application further provides a PCIE interface performance testing system, the system comprising:

[0016] A PCIE device, configured to store second PCIE data and obtain a second PCIE data packet based on the second PCIE data;

[0017] The motherboard under test includes a PCIE interface. The motherboard under test is used to read the second PCIE data packet through the PCIE interface, record a read start timestamp, and discard the second PCIE data packet after the second PCIE data packet is successfully read, and record a read end timestamp; generate a read performance test result of the PCIE interface based on the read start timestamp, the read end timestamp, and the total size of each second PCIE data packet.

[0018] In one embodiment, the motherboard under test is further configured to read the second PCIE data packet and verify the second PCIE data packet based on a verification mechanism provided by the PCIE protocol. If the verification of the second PCIE data packet succeeds, it is determined that the second PCIE data packet has been read successfully.

[0019] In one embodiment, the motherboard to be tested is further configured to record the number of times the second PCIE data packet fails to be read when verification of the second PCIE data packet fails.

[0020] In one embodiment, the total size of each second PCIE data packet is greater than a data size threshold, and the total size of each second PCIE data packet increases as a theoretical bandwidth corresponding to the PCIE interface increases.

[0021] In one embodiment, the size of the second PCIE data is smaller than the memory of the motherboard to be tested, and the size of the second PCIE data is an integer multiple of the size of a data packet corresponding to the PCIE protocol.

[0022] The above-mentioned PCIE interface performance testing system includes a motherboard to be tested and a PCIE device, wherein the motherboard to be tested is used to write each first PCIE data packet to the PCIE device through the PCIE interface and record the data write start timestamp; after each first PCIE data packet is successfully written, the data write end timestamp is recorded; based on the write start timestamp, the write end timestamp and the total size of each first PCIE data packet, a write performance test result of the PCIE interface is generated; the PCIE device is used to receive each first PCIE data packet and discard the first PCIE data packet after each first PCIE data packet is successfully received. In this way, the PCIE device does not have to perform time-consuming operations such as data storage and protocol conversion, and will not limit the write speed of the PCIE interface. The write performance of the PCIE interface can be maximized, thereby ensuring accurate test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 This is a schematic diagram of using a PCIE network card device to test the read and write speed of a PCIE slot in traditional technology;

[0025] Figure 2 This is a schematic diagram of using a PCIE disk array card to test the read and write speed of a PCIE slot in traditional technology;

[0026] Figure 3 FIG1 is a schematic diagram of a PCIE interface performance testing system in one embodiment;

[0027] Figure 4 Write a performance test flow chart for a PCIE interface in one embodiment;

[0028] Figure 5 A flowchart of a PCIE interface read performance test in one embodiment;

[0029] Figure 6 Schematic diagram of a PCIE interface performance test in one embodiment;

[0030] Figure 7 A schematic diagram of a test interface in an embodiment. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0032] For ease of understanding, combined Figure 1 As shown, Figure 1This diagram illustrates a conventional method for testing the read and write speeds of PCIE slots using a PCIE network card. In this embodiment, using a PCIE network card as an example, two motherboards are required. The tester inserts the two PCIE network cards into the PCIE slots of the two motherboards, interconnecting them with a network cable. After booting up the system, network speed test software (such as iperf) is run on the operating systems of the two motherboards under test. The measured network transmission speed is used to derive the actual read and write bandwidth of the PCIE slot. This method is applicable to PCIE Gen3 and earlier versions, as well as Gen4 x4 and lower PCIE slots. However, it is inadequate for PCIE Gen4 x8 and x16 slots. Currently, the fastest network cards are 100G cards, with a theoretical communication bandwidth of no more than 10GB. However, the theoretical bandwidth of a PCIE Gen4 x8 slot is 16GB, and that of a x16 slot is 32GB. Therefore, a 100G network card falls far short of meeting the bandwidth testing requirements.

[0033] Combine Figure 2 As shown, Figure 2 This diagram illustrates traditional techniques for testing the read and write speeds of a PCIE slot using a PCIE disk array card. Taking a PCIE disk array as an example, the tester inserts the PCIE disk array into the motherboard under test and connects the disks. The tester boots up the motherboard's operating system and runs disk read and write testing software (such as CrystalDiskMark) to measure the disk read and write speeds. The actual bandwidth of the PCIE slot is then derived from the disk read and write speeds. However, after receiving data, the PCIE disk array card writes it to the hard drive. This process wastes significant time, and thus fails to maximize the read and write performance of the motherboard's PCIE slot.

[0034] In summary, current testing methods only indirectly estimate PCIE read and write bandwidth, but are limited by the performance of downstream devices (network cards, hard drives, etc.) and cannot fully utilize the maximum read and write speeds of the PCIE slots on the motherboard being tested. The above examples only use PCIE network cards and PCIE disk array cards; other PCIE devices also face the same problem.

[0035] In order to solve the above technical problems, this application proposes a PCIE interface performance test system. Figure 3As shown, the system includes a motherboard to be tested and a PCIE device, and the PCIE device includes an FPGA main control chip. For example, in this embodiment, a high-performance FPGA supporting PCIE Gen4 x16 is used as the main control chip (it should be noted that if there is a higher version of the PCIE standard, the main control chip is a high-performance FPGA supporting the higher version of the PCIE standard. Those skilled in the art can select a suitable FPGA based on the PCIE standard), such as Intel's Stratix 10 DX. In other embodiments, the main control chip of the PCIE device can also be other models, which is not specifically limited here.

[0036] The PCIE device can be a PCIE test card. The PCIE test card can optionally adopt the standard PCIEx16 board size and can be inserted into all motherboards to be tested that support PCIE x16. In other embodiments, the PCIE test card can also be made into other board types, such as M.2 board type, XMC board type, VPX board type, etc., which are not specifically limited here. In addition, the embodiment of the present application is described using the PCIE Gen4 x16 interface as an example. When testing other versions of the interface, the PCIE test card can also be made into PCIE test cards of different versions (Gen1~Gen4) and different widths (x1~x16) for backward compatibility. It should also be noted that after the emergence of higher versions such as PCIE Gen5D, the PCIE interface performance test system proposed in this application can upgrade the PCIE test card to support the testing of higher versions of PCIE interfaces.

[0037] The PCIE test card, combined with the host computer software, can test the read and write performance of the PCIE Gen4 x16 slot.

[0038] In addition, it should be noted that this PCIE test card only implements the read and write functions of PCIE, and directly discards the written data without any processing, so the power consumption is very low. The 75watt power provided by the PCIE gold finger (Gold Finger is a connector on a printed circuit board (PCB), usually used to connect other devices such as computer motherboards, expansion cards, etc. In the PCI Express (PCIE) interface, the gold finger is the contact point of the connector for transmitting high-speed data signals) is sufficient to support the operation of the board without the need for additional power supply.

[0039] Combine Figure 4 As shown, Figure 4This is a flowchart of a PCIE interface write performance test in one embodiment. In this embodiment, the motherboard under test is used to write each first PCIE data packet to a PCIE device through the PCIE interface and record a data write start timestamp; after each first PCIE data packet is successfully written, a data write end timestamp is recorded; and a write performance test result of the PCIE interface is generated based on the write start timestamp, the write end timestamp, and the total size of each first PCIE data packet.

[0040] The PCIE device is used to receive each first PCIE data packet and discard the first PCIE data packet after each first PCIE data packet is successfully received.

[0041] Specifically, during the actual test process, a PCIE device is first inserted into the PCIE interface of the motherboard to be tested. The motherboard to be tested writes the first PCIE data packet to the PCIE device through the PCIE interface and records the data write start timestamp; the PCIE device receives each first PCIE data packet, and after each first PCIE data packet is successfully received, it discards the first PCIE data packet and does not perform any processing on the first PCIE data packet; after each first PCIE data packet is successfully written, the motherboard to be tested records the data write end timestamp; finally, the motherboard to be tested generates a write performance test result of the PCIE interface based on the write start timestamp, the write end timestamp and the total size of each first PCIE data packet, such as the total size of the first PCIE data packet / (write end timestamp-write start timestamp), so that the maximum write speed of the PCIE interface of the motherboard to be tested can be obtained.

[0042] During the write test, no storage devices such as memory and hard drives are required, nor is additional protocol conversion required. The PCIE test card simply discards the data it receives. Without time-consuming operations like data storage and protocol conversion, the write speed of the PCIE interface is not limited, maximizing the write performance of the PCIE interface and ensuring accurate test results.

[0043] In one of the optional embodiments, the PCIE device is further used to verify the first PCIE data packet based on the verification mechanism of the PCIE protocol after receiving the first PCIE data packet, and if the verification of the first PCIE data packet is successful, it is determined that the first PCIE data packet is received successfully.

[0044] In addition, it should be noted that the PCIE test card opens up a memory space (write RAM) inside the FPGA to temporarily store the first received PCIE data packet, without having to write the first PCIE data packet to the hard disk, etc. In this way, there is no need for storage devices such as memory and hard disk, so as to maximize the write performance of the PCIE interface.

[0045] In order to avoid additional operations such as protocol conversion and data verification, the present embodiment adopts the verification mechanism of the PCIE protocol to verify the first PCIE data packet to confirm the accuracy of the first PCIE data written to the PCIE device. If the verification of the first PCIE data packet succeeds, it is determined that the first PCIE data packet is received successfully, so that the main card to be tested can continue to send the next first PCIE data packet until all the first PCIE data packets are sent successfully.

[0046] In the above embodiment, the first PCIE data packet is verified using the verification mechanism of the PCIE protocol itself, avoiding additional operations such as protocol conversion and third-party data verification, thereby not limiting the write speed of the PCIE interface and maximizing the write performance of the PCIE interface.

[0047] In one of the optional embodiments, the PCIE device is also used to return data write failure information to the motherboard under test when the first PCIE data packet verification fails; the motherboard under test is also used to record the number of write failures of the first PCIE data packet when receiving the data packet write failure information.

[0048] In this embodiment, when the first PCIE data packet fails to be verified, the PCIE device returns data verification failure information to the main card to be tested, so that the main card to be tested can rewrite the first PCIE data packet to the PCIE device.

[0049] Optionally, the main card to be tested can also record the number of write failures of the first PCIE data packet, and the number of write failures can be output so that the tester can determine the reason for the performance test failure when the performance data obtained from the test does not meet the requirements.

[0050] For example, when the performance data obtained from the test does not meet the requirements, and the proportion of the number of write failures to the total number of writes is greater than the first proportion, or greater than the first threshold, it is determined that the cause of the performance test failure is poor transmission quality of the PCIE interface. Otherwise, it can be determined that the cause of the performance test failure is a software reason, etc., which is convenient for troubleshooting.

[0051] The first ratio and the first threshold here can be determined based on experience and are not specifically limited here. The total number of write times here is the total number of first PCIE data packets.

[0052] In one of the optional embodiments, the motherboard to be tested is further used to generate a first PCIE data file and determine each first PCIE data packet based on the first PCIE data file; wherein, the size of the first PCIE data file is smaller than the memory of the motherboard to be tested, and the size of the first PCIE data file is an integer multiple of the size of the data packet corresponding to the PCIE protocol; the motherboard to be tested is used to repeatedly determine each first PCIE data packet based on the first PCIE data file, and write each first PCIE data packet to the PCIE device.

[0053] The first PCIE data packet can be generated based on a first PCIE data file, and the first PCIE data file can be randomly generated by the software of the motherboard to be tested. The content of the first PCIE data file can be a random number, and the size of the first PCIE data file is smaller than the memory of the motherboard to be tested, and the size of the first PCIE data file is an integer multiple of the size of the data packet corresponding to the PCIE protocol.

[0054] The size of a data packet corresponding to the PCIE protocol is 4KB, which is also the maximum size of a data packet corresponding to the PCIE protocol. Therefore, the size of the first PCIE data file can be an integer multiple of 4KB, such as 4MB. In other embodiments, the size of the first PCIE data file can also be other values, which are not specifically limited here. The size of the first PCIE data file needs to be smaller than the memory size of the motherboard to be tested.

[0055] Since the more first PCIE data packets written during the test process, the more accurate the test results are, in order to improve the accuracy, each first PCIE data packet can be repeatedly determined based on the first PCIE data file, and each first PCIE data packet can be written to the PCIE device, for example, the first PCIE data file can be written to the PCIE device continuously for multiple times.

[0056] In one optional embodiment, the total size of each first PCIE data packet is greater than a data size threshold, and the total size of each first PCIE data packet increases as a theoretical bandwidth corresponding to the PCIE interface increases.

[0057] The total size of each first PCIE data packet here is the total amount of data successfully written to the PCIE device, that is, the result of the first PCIE data file multiplied by the number of file writes in the above text.

[0058] In order to ensure the relative accuracy of the test results, the minimum value of the total size of each first PCIE data packet is limited, that is, the data size threshold. The data size threshold can be 1GB. In other embodiments, the data size threshold can be other values, and those skilled in the art can adjust the data size threshold based on the test scenario and test accuracy requirements.

[0059] In addition, because different PCIE interfaces support different PCIE standards, and different PCIE standards correspond to different theoretical bandwidths, if the total size of each first PCIE data packet sent for testing the same PCIE interface is the same, the accuracy of the test results will be different. To improve the accuracy of the test results, the total size of each first PCIE data packet is determined based on the theoretical bandwidth corresponding to the PCIE interface, where the total size of each first PCIE data packet increases as the theoretical bandwidth corresponding to the PCIE interface increases. This ensures the total amount of data sent during the test and the accuracy of the test. On the other hand, it eliminates the need for storage devices such as memory and hard disks, and does not require additional protocol conversion. The PCIE test card directly discards the data after receiving it. Without time-consuming operations such as data storage and protocol conversion, the PCIE write speed is not limited, and the write performance of the PCIE interface can be maximized to ensure accuracy.

[0060] This application also provides a PCIE interface read performance test system, the specific hardware structure of which can be combined with Figure 3 As shown, and for the convenience of understanding, combined Figure 5 As shown, Figure 5 This is a flowchart of a PCIE interface read performance test in one embodiment. In this embodiment, a PCIE device is configured to store second PCIE data and obtain a second PCIE data packet based on the second PCIE data. The motherboard under test is configured to read the second PCIE data packet through the PCIE interface, record a read start timestamp, and discard the second PCIE data packet after successfully reading the second PCIE data packet and record a read end timestamp. The motherboard also generates a PCIE interface read performance test result based on the read start timestamp, read end timestamp, and the total size of each second PCIE data packet.

[0061] Specifically, during the actual test process, the PCIE device first allocates a memory device in the FPGA, such as a read RAM, for storing the second PCIE data. The motherboard under test can then read the second PCIE data from the PCIE device, wherein the reading method is to read the second PCIE data packets one by one. Specifically, the motherboard under test is configured to read the second PCIE data packets through the PCIE interface and record the read start timestamp. After the second PCIE data packet is successfully read, the second PCIE data packet is discarded without any processing. After each second PCIE data packet is successfully read, the read end timestamp is recorded.

[0062] The motherboard under test subsequently generates a write performance test result of the PCIE interface based on the read start timestamp, the read end timestamp and the total size of each second PCIE data packet, such as the total size of the second PCIE data packet / (read end timestamp-read start timestamp), so as to obtain the maximum read speed of the PCIE interface of the motherboard under test.

[0063] During the write test, no storage devices such as memory or hard drives are required, nor is additional protocol conversion required. The motherboard under test simply discards the second PCIE data packet after reading it. Without time-consuming operations like data storage and protocol conversion, the PCIE interface's read speed is not limited, maximizing its read performance and ensuring accurate test results.

[0064] In one of the optional embodiments, the motherboard to be tested is further configured to read the second PCIE data packet and verify the second PCIE data packet based on the verification mechanism of the PCIE protocol. If the verification of the second PCIE data packet succeeds, it is determined that the second PCIE data packet is read successfully.

[0065] In order to avoid additional operations such as protocol conversion and data verification, the present embodiment adopts the verification mechanism provided by the PCIE protocol to verify the second PCIE data packet to confirm the accuracy of the second PCIE data read by the mainboard under test. If the verification of the second PCIE data packet succeeds, it is determined that the second PCIE data packet is read successfully, so that the main card under test can continue to read the next second PCIE data packet until all second PCIE data packets are read successfully.

[0066] In the above embodiment, the second PCIE data packet is verified using the verification mechanism of the PCIE protocol itself, avoiding additional operations such as protocol conversion and third-party data verification, thereby not limiting the read speed of the PCIE interface and maximizing the read performance of the PCIE interface.

[0067] In one of the optional embodiments, the motherboard to be tested is further configured to record the number of times the second PCIE data packet fails to be read when verification of the second PCIE data packet fails.

[0068] In this embodiment, when the second PCIE data packet fails to be verified, the master card to be tested re-reads the second PCIE data packet in the PCIE device.

[0069] Optionally, the main card to be tested can also record the number of times the second PCIE data packet fails to be read, and the number of times the read failure can be output so that the tester can determine the reason for the performance test failure when the performance data obtained from the test does not meet the requirements.

[0070] For example, when the performance data obtained from the test does not meet the requirements, and the proportion of the number of read failures to the total number of reads is greater than the first proportion, or greater than the second threshold, it is determined that the cause of the performance test failure is poor transmission quality of the PCIE interface. Otherwise, it can be determined that the cause of the performance test failure is a software reason, etc., which is convenient for troubleshooting.

[0071] The second ratio and the second threshold value can be determined based on experience and are not specifically limited here. The total number of write times is the total number of the second PCIE data packets.

[0072] In one optional embodiment, the total size of each second PCIE data packet is greater than a data size threshold, and the total size of each second PCIE data packet increases as a theoretical bandwidth corresponding to the PCIE interface increases.

[0073] The total size of each first PCIE data packet here is the total amount of data successfully written to the PCIE device, that is, the result of the first PCIE data file multiplied by the number of file writes in the above text.

[0074] To ensure the relative accuracy of the test results, a minimum total size of each second PCIE data packet, i.e., a data size threshold, is defined. This data size threshold may be 1GB. In other embodiments, this data size threshold may be other values, and those skilled in the art may adjust this data size threshold based on the test scenario and test accuracy requirements. It should be noted that the data size thresholds involved in the read performance test and the write performance test may be the same or different, and are not specifically limited here.

[0075] Because different PCIE interfaces support different PCIE standards, and different PCIE standards correspond to different theoretical bandwidths, if the total size of each second PCIE data packet sent for the test of the same PCIE interface is the same, the accuracy of the test results will be different. In order to improve the accuracy of the test results, the total size of each second PCIE data packet is determined based on the theoretical bandwidth corresponding to the PCIE interface, wherein the total size of each second PCIE data packet increases with the increase of the theoretical bandwidth corresponding to the PCIE interface. This ensures the total amount of data read during the test and the accuracy of the test on the one hand, and eliminates the need for storage devices such as memory and hard disks, and does not require additional protocol conversion. The motherboard under test directly discards the data after receiving it. Without time-consuming operations such as storing data and converting protocols, the read speed of the PCIE will not be limited, and the read performance of the PCIE interface can be maximized, ensuring accuracy.

[0076] In one optional embodiment, the size of the second PCIE data is smaller than the memory of the motherboard to be tested, and the size of the second PCIE data is an integer multiple of the size of the data packet corresponding to the PCIE protocol.

[0077] The second PCIE data packet is generated based on the second PCIE data. The second PCIE data can be randomly generated by the PCIE device. For example, the PCIE device allocates a certain amount of memory space in the FPGA as read RAM and fills it with random numbers. The random numbers stored in the space constitute the second PCIE data. The second PCIE data can be multiple random numbers, and the size of the second PCIE data is smaller than the memory of the motherboard under test, and the size of the second PCIE data is an integer multiple of the size of the data packet corresponding to the PCIE protocol.

[0078] The size of a data packet corresponding to the PCIE protocol is 4KB, which is also the maximum size of a data packet corresponding to the PCIE protocol. Therefore, the size of the second PCIE data can be an integer multiple of 4KB, such as 4MB. In other embodiments, the size of the second PCIE data can also be other values, which are not specifically limited here. The size of the second PCIE data needs to be smaller than the memory size of the motherboard to be tested.

[0079] Since the more second PCIE data packets read during the test process, the more accurate the test results are, in order to improve the accuracy, each second PCIE data packet can be repeatedly determined based on the second PCIE data and the second PCIE data packet can be read. For example, the motherboard to be tested reads the second PCIE data packet from the PCIE device multiple times in succession.

[0080] For ease of understanding, combined Figure 6 As shown, Figure 6 This is a schematic diagram of a PCIE interface performance test in one embodiment. In this embodiment, the PCIE interface performance test system includes a motherboard to be tested and a PCIE test card. The motherboard to be tested includes a PCIE interface. The PCIE test card is the PCIE device mentioned above and includes an FPGA. The FPGA includes two high-speed transceivers, one for read performance testing and one for write performance testing, a PCIE IP core, and both write and read memories. The write memory is used to temporarily store a first PCIE data packet written by the motherboard to be tested, and the read memory is used to store a second PCIE data packet to be read by the motherboard to be tested.

[0081] Combine Figure 7 As shown, Figure 7This is a schematic diagram of a test interface in an embodiment, which includes a read performance test, a write performance test, and a PCIE device selection box. After completing the hardware connection, the corresponding PCIE device, such as a PCIE test card, can be selected through the PCIE device selection box. Subsequently, the read performance test and the write performance test can be implemented by triggering the control button corresponding to the read performance test or the write performance test. The specific test process can be combined with the above Figure 4 and Figure 5 After the test is completed, the test interface can also display the test results. The write performance test results include the amount of written data (i.e., the total size of the first PCIE data packets mentioned above), the number of written frames (i.e., the number of first PCIE data packets mentioned above), the number of error frames (the number of first PCIE data packets that failed to write), and the write speed. The read performance test results include the amount of read data (i.e., the total size of the second PCIE data packets mentioned above), the number of read frames (i.e., the number of second PCIE data packets mentioned above), the number of error frames (the number of second PCIE data packets that failed to read), and the read speed.

[0082] Optionally, Figure 7 The write speed and read speed are displayed in the form of a dashboard to improve the visualization level. In other embodiments, the write speed and read speed can be displayed in other forms, such as in a table form, etc., and no specific limitation is made here.

[0083] In the above embodiment, whether in the write performance test or the read performance test, data is discarded directly after being read or written, saving data processing time and maximizing the read and write performance of the PCIE interface of the tested motherboard. Verification is performed solely through the PCIE protocol's inherent data verification mechanism, eliminating the need for data storage or data conversion, further saving data processing time. Furthermore, the data verification mechanism can be used to count error frames, facilitating subsequent troubleshooting.

[0084] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), quantum computing-based data processing logic devices, artificial intelligence (AI) processors, and the like.

[0085] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0086] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A PCIE interface performance test system, characterized in that: The system comprises: A motherboard to be tested, comprising a PCIE interface, wherein the motherboard to be tested is configured to write each first PCIE data packet to a PCIE device through the PCIE interface and record a data write start timestamp; after each first PCIE data packet is successfully written, record a data write end timestamp; and generate a write performance test result of the PCIE interface based on the write start timestamp, the write end timestamp, and the total size of each first PCIE data packet; A PCIE device, including an FPGA main control chip, is configured to receive each of the first PCIE data packets and discard the first PCIE data packet after each first PCIE data packet is successfully received; the PCIE device only implements the read and write functions of the PCIE and directly discards the written data without any processing; the PCIE device is different from a memory and a hard disk and does not require additional protocol conversion; The motherboard to be tested is further configured to generate a first PCIE data file and determine each first PCIE data packet based on the first PCIE data file; wherein the size of the first PCIE data file is smaller than the memory of the motherboard to be tested, and the size of the first PCIE data file is an integer multiple of the size of the data packet corresponding to the PCIE protocol; The motherboard to be tested is used to repeatedly determine each first PCIE data packet based on the first PCIE data file, and write each first PCIE data packet to the PCIE device; The total size of each of the first PCIE data packets is greater than a data size threshold, and the total size of each of the first PCIE data packets increases as a theoretical bandwidth corresponding to the PCIE interface increases; The PCIE device is further configured to verify the first PCIE data packet based on a verification mechanism of the PCIE protocol after receiving the first PCIE data packet, and determine that the first PCIE data packet is successfully received if the verification of the first PCIE data packet succeeds; The size of the PCIE device is determined based on the version and width of the PCIE interface of the motherboard to be tested, and is powered by 75 watt power provided by the PCIE gold finger.

2. The system according to claim 1, wherein: The PCIE device is further configured to return data write failure information to the motherboard under test when the first PCIE data packet fails to be verified; The motherboard to be tested is further configured to record the number of write failures of the first PCIE data packet when receiving the information that the data packet write fails.

3. A PCIE interface performance test system, characterized in that: The system comprises: A PCIE device, including an FPGA main control chip, is used to store second PCIE data and obtain a second PCIE data packet based on the second PCIE data; the PCIE device is different from a memory and a hard disk and does not require additional protocol conversion; A motherboard to be tested includes a PCIE interface, wherein the motherboard to be tested is configured to read the second PCIE data packet through the PCIE interface, record a read start timestamp, discard the second PCIE data packet after the second PCIE data packet is successfully read, do not perform any processing on the second PCIE data packet, and record a read end timestamp; generate a read performance test result of the PCIE interface based on the read start timestamp, the read end timestamp, and the total size of each second PCIE data packet; The size of the second PCIE data is smaller than the memory of the motherboard to be tested, and the size of the second PCIE data is an integer multiple of the size of the data packet corresponding to the PCIE protocol; The total size of each second PCIE data packet is greater than a data size threshold, and the total size of each second PCIE data packet increases as a theoretical bandwidth corresponding to the PCIE interface increases; The motherboard to be tested is further configured to, after reading the second PCIE data packet, verify the second PCIE data packet based on a verification mechanism provided by the PCIE protocol, and determine that the second PCIE data packet is read successfully if the verification of the second PCIE data packet succeeds; The size of the PCIE device is determined based on the version and width of the PCIE interface of the motherboard to be tested, and is powered by 75 watt power provided by the PCIE gold finger.

4. The system according to claim 3, characterized in that The mainboard to be tested is further configured to record the number of times the second PCIE data packet fails to be read when verification of the second PCIE data packet fails.

Images