An information reading method, an information reading apparatus, an electronic device, and a storage medium

Abstract

The application discloses an information reading method, an information reading device, an electronic device and a storage medium. The method comprises the following steps: receiving input data transmitted by a serial transceiver unit through a CPLD; when the input data comprises first indication information, turning on a first path between a sending end of the CPLD and a receiving end of the serial transceiver unit; if the first path is turned on, reading main processor state information stored in a CPLD register through the CPLD, and sending the read main processor state information through the serial transceiver unit. The first path between the CPLD and the serial transceiver unit is turned on through the first indication information in the input data, so that the CPLD sends the read main processor state information through the serial transceiver unit, and then the reading of the main processor state information can be realized in the case that the main processor or the communication bus has a problem, so that the user can debug the main processor according to the read main processor state information.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of hardware devices, and in particular relates to an information reading method, an information reading device, an electronic device and a storage medium. BACKGROUND

[0002] In some electronic devices, since the CPU (English: Central Processing Unit, Chinese: Central Processing Unit) needs to be debugged, the CPU is usually connected in communication with the CPLD (English: Complex Programmable Logic Device, Chinese: Complex Programmable Logic Device), and in the debugging process, the CPLD obtains the main processor state information, such as the power-on / off information of the CPU, the usage rate information of the CPU, etc., and stores the obtained main processor state information into its own register, and the CPU reads the main processor state information stored in the CPLD register through the communication bus, and transmits it to the serial display through the serial transceiver for display, so that the staff can intuitively monitor the current state of the CPU.

[0003] Since the serial transceiver cannot obtain the main processor state information stored in the CPLD register when the CPU is not started or is dead, the debugging of the CPU cannot be performed, and therefore, in the known technology, the CPU and the BMC (English: Baseboard Management Controller, Chinese: Baseboard Management Controller) are usually used to read the CPLD register, that is, when the CPU is not started or is dead, the BMC is used to read the CPLD register.

[0004] However, in the above information reading method, when the CPU is not started or is dead, and the BMC is not started or is dead, or when the communication bus cannot be accessed, the CPLD register still cannot be read, and thus the debugging of the CPU cannot be performed. SUMMARY

[0005] The present application provides an information reading method, an information reading device, an electronic device and a storage medium, to solve the problem that in the prior art, the information stored in the CPLD register cannot be read due to problems in the main processor or the communication bus.

[0006] In a first aspect, an information reading method is provided, which is applied to a hardware device, and the hardware device includes a main processor, a complex programmable logic device (CPLD) and a serial transceiver unit, wherein the CPLD includes a CPLD register, and the method includes:

[0007] receive the input data transmitted by the serial transceiver unit through the CPLD, wherein when the input data comprises first indication information, a first path between the transmitting end of the CPLD and the receiving end of the serial transceiver unit is turned on;

[0008] If the first path is turned on, the main processor state information stored in the CPLD register is read through the CPLD, and the read main processor state information is transmitted through the serial transceiver unit.

[0009] The information reading method disclosed by the embodiment comprises the following steps: receiving input data transmitted by a serial transceiver unit through a CPLD; when the input data comprises first indication information, turning on a first path between a transmitting end of the CPLD and a receiving end of the serial transceiver unit; and if the first path is turned on, reading main processor state information stored in a CPLD register through the CPLD, and transmitting the read main processor state information through the serial transceiver unit. The first indication information in the input data is used to turn on the first path between the CPLD and the serial transceiver unit, so that the CPLD transmits the read main processor state information through the serial transceiver unit, and thus the reading of the main processor state information can be realized in the case where the main processor or the communication bus has a problem, so that the user can debug the main processor according to the read main processor state information.

[0010] In a possible implementation, the hardware device further comprises a gating unit, a first input end of the gating unit is electrically connected with the transmitting end of the CPLD, and an output end of the gating unit is electrically connected with the receiving end of the serial transceiver unit.

[0011] When the input data comprises the first indication information, the first path between the transmitting end of the CPLD and the receiving end of the serial transceiver unit is turned on.

[0012] When the input data comprises the first indication information, the gating unit is controlled by the CPLD to turn on the path between the first input end of the gating unit and the output end of the gating unit.

[0013] In the above embodiment, the hardware device further comprises a gating unit, a first input end of the gating unit is electrically connected with the transmitting end of the CPLD, and an output end of the gating unit is electrically connected with the receiving end of the serial transceiver unit. When the input data comprises the first indication information, the gating unit is controlled by the CPLD to turn on the path between the first input end of the gating unit and the output end of the gating unit, and thus the path between the transmitting end of the CPLD and the receiving end of the serial transceiver unit is turned on, so that the CPLD can transmit the read main processor state information through the serial transceiver unit.

[0014] In a possible implementation, the CPLD further comprises an additional CPLD register, and the reading, by the CPLD, of the main processor state information stored in the plurality of CPLD registers comprises:

[0015] The CPLD traverses address information of each CPLD register;

[0016] The CPLD reads, according to the traversed address information, the main processor state information stored in the CPLD register corresponding to the address information.

[0017] In the above embodiment, the CPLD traverses address information of each CPLD register, and then the CPLD reads, according to the traversed address information, the main processor state information stored in the CPLD register corresponding to the address information. By the above method, the main processor state information stored in each CPLD register is read.

[0018] In a possible implementation, after the CPLD receives the input data transmitted by the serial transceiver unit, the CPLD further comprises:

[0019] Within a preset time length, the CPLD determines whether new input data is received;

[0020] If the new input data is not received, the CPLD turns on the first path when the input data comprises the first indication information.

[0021] If the new input data is received, the CPLD transmits the input data and the new input data as file transmission content.

[0022] In the above embodiment, after the CPLD receives the input data transmitted by the serial transceiver unit, the CPLD determines, within a preset time length, whether new input data is received. If the new input data is not received, the CPLD turns on the first path when the input data comprises the first indication information. If the new input data is not received, the CPLD transmits the input data and the new input data as file transmission content. By determining whether new input data is received within a preset time length, the possibility that the received input data is file transmission content is screened out, and the reliability of the device is improved.

[0023] In a possible implementation, after the CPLD receives the input data transmitted by the serial transceiver unit, before the CPLD determines, within a preset time length, whether new input data is received, the CPLD further comprises:

[0024] The CPLD determines that the preset data transmitted by the serial transceiver unit is received.

[0025] The CPLD takes the time of receiving the preset data as the start time of the preset time length.

[0026] In the above embodiment, first, the CPLD determines the reception of the preset data transmitted by the serial transceiver unit, and then takes the time of receiving the preset data as the start time of the preset time length. By the above method, the input data is avoided to be misjudged as the content of file transmission due to the existence of the preset data, such as the null character, and the reliability of the system is improved.

[0027] In a possible implementation, the method further includes:

[0028] When the input data includes the second indication information, the CPLD turns on a second path between the sending end of the main processor and the receiving end of the serial transceiver unit;

[0029] If the second path is turned on, the main processor reads the main processor state information stored in the CPLD memory, and sends the read main processor state information through the serial transceiver unit.

[0030] In the above embodiment, when the input data includes the second indication information, the CPLD turns on the second path between the sending end of the main processor and the receiving end of the serial transceiver unit; when the second path is turned on, the main processor reads the main processor state information stored in the CPLD memory, and sends the read main processor state information through the serial transceiver unit. By controlling the turning on of the second path, the main processor state information stored in the CPLD memory can also be read, thereby improving the reliability of the system.

[0031] In a possible implementation, the second input end of the gating unit is electrically connected with the sending end of the main processor;

[0032] When the input data includes the second indication information, the CPLD turns on the second path between the sending end of the main processor and the receiving end of the serial transceiver unit, including:

[0033] When the input data includes the second indication information, the CPLD controls the gating unit to turn on the path between the second input end of the gating unit and the output end of the gating unit.

[0034] In the above embodiment, the second input end of the gating unit is electrically connected with the sending end of the main processor; when the input data includes the second indication information, the CPLD controls the gating unit to turn on the path between the second input end of the gating unit and the output end of the gating unit, and then turns on the path between the sending end of the main processor and the receiving end of the serial transceiver unit, that is, the turning on of the second path is realized.

[0035] In a possible implementation, the input data is triggered by a user or generated according to a device state of the main processor.

[0036] In a second aspect, an information reading apparatus is provided, which is applied to a hardware device including a main processor, a complex programmable logic device (CPLD) and a serial transceiver unit, wherein the CPLD includes a CPLD register, and the apparatus includes:

[0037] a data processing module, configured to receive input data transmitted by the serial transceiver unit through the CPLD, and turn on a first path between a sending end of the CPLD and a receiving end of the serial transceiver unit when the input data includes first indication information;

[0038] an information transmission module, configured to read main processor state information stored in the CPLD register through the CPLD if the first path is turned on, and transmit the read main processor state information through the serial transceiver unit.

[0039] In a possible implementation, the hardware device further includes a gating unit, a first input end of the gating unit is electrically connected with the sending end of the CPLD, and an output end of the gating unit is electrically connected with the receiving end of the serial transceiver unit.

[0040] The data processing module is specifically configured to:

[0041] turn on a path between the first input end of the gating unit and the output end of the gating unit through the CPLD when the input data includes the first indication information.

[0042] In a possible implementation, the CPLD further includes an additional CPLD register, and the data processing module is specifically configured to:

[0043] iterate address information of each CPLD register through the CPLD;

[0044] read main processor state information stored in a CPLD register corresponding to the iterated address information through the CPLD.

[0045] In a possible implementation, the information reading apparatus further includes a first data identification module.

[0046] The first data identification module is configured to determine whether new input data is received within a preset time length.

[0047] If the new input data is not received, the first path is turned on when the input data comprises the first indication information.

[0048] If the new input data is received, the input data and the new input data are transmitted as file transmission content by the CPLD.

[0049] In a possible implementation, the information reading apparatus further comprises a second data identification module.

[0050] The second data identification module is configured to determine, by the CPLD, that preset data transmitted by the serial transceiver unit is received.

[0051] The CPLD is configured to determine a starting time of the preset time length as a time when the preset data is received.

[0052] In a possible implementation, the data processing module is further configured to:

[0053] The CPLD is configured to turn on a second path between a sending end of the main processor and a receiving end of the serial transceiver unit when the input data comprises second indication information.

[0054] If the second path is turned on, the main processor state information stored in the CPLD memory is read by the main processor, and the read main processor state information is sent by the serial transceiver unit.

[0055] In a possible implementation, a second input end of the gating unit is electrically connected to the sending end of the main processor, and the data processing module is specifically configured to:

[0056] The CPLD is configured to control a path between the second input end of the gating unit and the output end of the gating unit to be turned on when the input data comprises second indication information.

[0057] In a possible implementation, the input data is triggered by a user or generated according to a device state of the main processor.

[0058] In a third aspect, an embodiment of the present application provides an electronic device, which comprises a memory, a processor, and a computer program stored in the memory and executable by the processor, and the processor implements the information reading method according to any one of the embodiments of the first aspect.

[0059] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executable by a processor to implement the steps of the information reading method according to any one of the embodiments of the first aspect.

[0060] The technical effects that can be achieved by the information reading apparatus disclosed in the second aspect, the electronic device disclosed in the third aspect, and the computer readable storage medium disclosed in the fourth aspect are the same as those of the first aspect or the various possible solutions in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0062] Figure 1 A structural schematic diagram of a hardware device provided for known technology;

[0063] Figure 2 A structural schematic diagram of a hardware device provided for the embodiments of the present application;

[0064] Figure 3 A flowchart of an information reading method provided for the embodiments of the present application;

[0065] Figure 4 A structural schematic diagram of another hardware device provided for the embodiments of the present application;

[0066] Figure 5 A structural schematic diagram of another hardware device provided for the embodiments of the present application;

[0067] Figure 6 A flowchart of another information reading method provided for the embodiments of the present application;

[0068] Figure 7 A flowchart of another information reading method provided for the embodiments of the present application;

[0069] Figure 8 A module structural schematic diagram of an information reading apparatus provided for the embodiments of the present application;

[0070] Figure 9 A structural schematic diagram of an electronic device provided for the embodiments of the present application;

[0071] Figure 10 A schematic diagram of a program product of an information reading method provided for the embodiments of the present application. DETAILED DESCRIPTION

[0072] In order to make the purposes, technical solutions and advantages of the present application clearer, the following further describes the present application with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the scope of the present application.

[0073] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in other than the order shown or described herein. The embodiments described in the following exemplary embodiments do not represent all the embodiments consistent with the present application. Instead, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0074] In order to facilitate the user to debug the CPU, it is necessary to display the CPU state information through the display. In the known art, the CPU state information stored in the CPLD register is usually read by the CPU, such as Figure 1 As shown in FIG. 1, it is a structure diagram of a system for reading the CPLD register, including a CPU 11, a CPLD 12, a serial transceiver 13 and a display 14, wherein the CPU 11 is communicatively connected with the CPLD 12 through a communication bus, the output end of the CPU 11 is also communicatively connected with the receiving end of the CPLD 12, the TX (English: Transmit, Chinese: Send) end of the CPU 11 is communicatively connected with the RX (English: Receive, Chinese: Receive) end of the serial transceiver 13, the receiving end (RX) of the CPU 11 is communicatively connected with the sending end (TX) of the serial transceiver 13, and the output end of the serial transceiver 13 is communicatively connected with the receiving end of the display 14.

[0075] In a specific implementation, after the system is powered on, the CPLD 12 obtains the state information of the CPU 11 and stores the obtained CPU state information into the CPLD register. In order to enable the user to intuitively understand the CPU state information, the CPU 11 reads the CPU state information stored in the CPLD register according to a preset communication protocol through the communication bus, and transmits the read CPU state information to the receiving end (RX) of the serial transceiver 13 through the sending end (TX). After receiving the CPU state information, the serial transceiver 13 transmits the CPU state information to the display 14 for display, so that the user can intuitively understand the current state of the CPU and debug the CPU according to the current state.

[0076] However, if the CPU fails, for example, the CPU does not start, or the CPU hangs, the CPU cannot read the CPU state information stored in the CPLD register, and the display cannot display the CPU state information, so the user cannot know the current state of the CPU in time, and cannot debug the CPU.

[0077] To solve the above problems, an information reading method, an information reading device, an electronic device, and a storage medium are provided to enable reading of the CPLD register even when the CPU fails.

[0078] The objectives, functional features, and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. It should be understood that the specific embodiments described herein are only intended to explain the present application, and not to limit the present application.

[0079] The information reading method provided by the embodiments of the present application will be described and explained in detail below with reference to the accompanying drawings.

[0080] The information reading method provided by the embodiments of the present application is applied to a hardware device, such as Figure 2 As shown in FIG. 1, it is a structural schematic diagram of a hardware device 20, which includes a main processor 21, a CPLD 22, and a serial transceiver unit 23. The transmitting end (TX) of the serial transceiver unit 23 is respectively communicatively connected with the receiving end (RX) of the main processor 21 and the receiving end (RX) of the CPLD 22, the receiving end (RX) of the serial transceiver unit 23 is respectively communicatively connected with the transmitting end (TX) of the main processor 21 and the transmitting end (TX) of the CPLD 22, and the main processor 21 is further communicatively connected with the CPLD 22 through a communication bus. Specifically, the CPLD 22 includes a CPLD register, the CPLD 22 acquires the state information of the main processor 21, and stores the acquired main processor state information in the CPLD register.

[0081] It should be noted that the main processor in the embodiments of the present application can be a CPU, or other control-type electronic devices such as BMC according to actual application scenarios, which are not limited in the embodiments of the present application; the CPLD in the embodiments of the present application can be replaced by other logic devices such as FPGA (English: Field Programmable Gate Array, Chinese: Field Programmable Gate Array) according to actual application scenarios, which are not limited in the embodiments of the present application; the CPLD in the embodiments of the present application can include one CPLD register, or multiple CPLD registers, which are not limited in the embodiments of the present application; in addition, the serial transceiver unit in the embodiments of the present application can include a serial transceiver, which is not limited in the embodiments of the present application.

[0082] As shown in Figure 3 , a workflow diagram of an information reading method provided by an embodiment of the present application is shown, which includes the following steps:

[0083] In step S301, input data transmitted by the serial transceiver unit is received by the CPLD, wherein when the input data includes first indication information, the first path between the transmitting end of the CPLD and the receiving end of the serial transceiver unit is turned on.

[0084] It should be noted that the input data in the embodiments of the present application can be characters or bytes, and the embodiments of the present application do not make any limitation on this.

[0085] Optionally, the input data can be triggered by a user.

[0086] In a specific implementation, the serial transceiver unit can also be connected with other external devices, such as a keyboard, a mouse, etc., and a user can send input data to the serial transceiver unit through the keyboard. After the serial transceiver unit receives the input data, it transmits the input data to the CPLD, so that the CPLD determines whether to turn on the first path according to the input data.

[0087] Optionally, the input data can be generated according to the device state of the main processor.

[0088] In a specific implementation, when the main processor is in a normal startup / abnormal startup state, the main processor generates state information representing normal operation / abnormal operation, generates input data according to the aforementioned state information, and transmits the input data to the CPLD through the serial transceiver unit according to the state information generated by the main processor, so that the CPLD determines whether to turn on the first path according to the input data.

[0089] In a possible implementation, as shown in Figure 4 , another structural schematic diagram of the hardware device 20 is shown, which further includes a gating unit 24, a first input end of the gating unit 24 is electrically connected with the transmitting end (TX) of the CPLD 22, an output end of the gating unit 24 is electrically connected with the receiving end (RX) of the serial transceiver unit 23, and a control end of the gating unit 24 is electrically connected with the control end (ConTroL, CTL for short) of the CPLD 22; when the input data includes first indication information, the gating unit 24 is controlled by the CPLD 22 to turn on the path between the first input end of the gating unit 24 and the output end of the gating unit 24, and then turn on the path between the transmitting end (TX) of the CPLD 22 and the receiving end (RX) of the serial transceiver unit 23, i.e., turn on the first path.

[0090] For example, as shown in Figure 4In the structure of the hardware device 20 shown, the first indication information can be "CTRL+G", and the input data received by the CPLD 22 contains the first indication information, then the CPLD 22 outputs a control signal to the control terminal of the gating unit 24 through the CTL terminal, for example, the control signal can be a high level signal; the gating unit 24 turns on the path between the first input terminal and the output terminal thereof under the control of the control signal, thereby turning on the path between the transmitting terminal (TX) of the CPLD 22 and the receiving terminal (RX) of the serial transceiver unit 23, that is, turning on the first path.

[0091] Optionally, as shown in the figure, Figure 5 The gating unit 24 includes a gate 241, a first resistor R1 and a second resistor R2, the first input terminal of the gate 241 is the first input terminal of the gating unit 24, the output terminal of the gate 241 is the output terminal of the gating unit 24, the control terminal of the gate 241 is connected with one end of the first resistor R1 and one end of the second resistor R2 respectively, the other end of the first resistor R1 is the control terminal of the gating unit 24, and the other end of the second resistor R2 is grounded.

[0092] In the gating unit 24 shown in the figure, Figure 5 The gate 241 is used to realize the gating function of the first path, and the first resistor R1 and the second resistor R2 are connected to the control terminal of the gate 241, so as to prevent the gate 241 from being triggered by mistake, thereby improving the reliability of the system.

[0093] The above method, the hardware device further includes a gating unit, the first input terminal of the gating unit is electrically connected with the transmitting terminal of the CPLD, and the output terminal of the gating unit is electrically connected with the receiving terminal of the serial transceiver unit; when the input data contains the first indication information, the path between the first input terminal of the gating unit and the output terminal of the gating unit is turned on by the CPLD, thereby turning on the path between the transmitting terminal of the CPLD and the receiving terminal of the serial transceiver unit, so that the CPLD can send the read main processor state information through the serial transceiver unit.

[0094] In step S302, if the first path is turned on, the CPLD reads the main processor state information stored in the CPLD register, and sends the read main processor state information through the serial transceiver unit.

[0095] In the specific implementation, in the case that the first path is turned on, the CPLD reads all the main processor state information stored in the CPLD register, and sends all the read main processor state information to the serial transceiver unit, so that the serial transceiver unit sends the received main processor state information to the external device connected with the hardware device, for example, the main processor state information can be sent to the display unit, so that the display unit displays the received main processor state information.

[0096] For example, such as Figure 4 As shown, the hardware device 20 is communicatively connected to the display unit 25. Specifically, the output of the serial transceiver unit 23 is communicatively connected to the input of the display unit 25. The serial transceiver unit 23 sends the main processor status information read by the CPLD 22 to the display unit 25. The display unit 25 displays the received main processor status information so that the staff can intuitively see the main processor status information through the display unit 25, which facilitates the staff to adjust the main processor according to the main processor status information.

[0097] Optionally, the display unit 34 can be a display or other device with display function, and this application embodiment does not impose any restrictions on this.

[0098] The information reading method disclosed in this application includes receiving input data transmitted by a serial transceiver unit via a CPLD. When the input data includes first indication information, a first path is established between the transmitting end of the CPLD and the receiving end of the serial transceiver unit. If the first path is established, the CPLD reads the main processor status information stored in the CPLD register and transmits the read main processor status information through the serial transceiver unit. By establishing the first path between the CPLD and the serial transceiver unit through the first indication information in the input data, the CPLD can transmit the read main processor status information through the serial transceiver unit. This allows the main processor status information to be read even if there is a problem with the main processor or the communication bus, enabling the user to debug the main processor based on the read main processor status information.

[0099] In one possible implementation, such as Figure 6 As shown, the above method also includes:

[0100] Step S601: When the input data includes the second indication information, the second path between the transmitting end of the main processor and the receiving end of the serial transceiver unit is opened through the CPLD.

[0101] In one possible implementation, such as Figure 4 As shown, the second input terminal of the gating unit 24 is electrically connected to the transmitting terminal (TX) of the main processor 21. When the input data includes the second indication information, the CPLD 22 controls the path between the second input terminal of the gating unit 24 and the output terminal of the gating unit 24 to be turned on, thereby turning on the path between the transmitting terminal (TX) of the main processor 21 and the receiving terminal (RX) of the serial transceiver unit 23, thus realizing the turning on of the second path.

[0102] For example, in such Figure 4The second indication information can be "CTRL+U", and the input data received by the CPLD 22 contains the first indication information, so that the CPLD 22 outputs a control signal to the control terminal of the gating unit 24 through the CTL terminal, for example, the control signal can be a low-level signal; the gating unit 24 turns on the path between the second input terminal and the output terminal thereof under the control of the control signal, so as to turn on the path between the transmission terminal (TX) of the main processor 21 and the receiving terminal (RX) of the serial transceiver unit, that is, to turn on the second path.

[0103] Optionally, as shown in the figure, the second input terminal of the gate 241 is used as the second input terminal of the gating unit 24, and the gating function of the second path is realized through the gate 241, and the first resistor R1 and the second resistor R2 are connected to the control terminal of the gate 241, so as to prevent the gate 241 from being triggered by mistake, thereby improving the reliability of the system. Figure 5

[0104] The above method, when the input data includes the first indication information, turns on the first path between the transmission terminal of the CPLD and the receiving terminal of the serial transceiver unit through the CPLD; when the input data includes the second indication information, turns on the second path between the transmission terminal of the main processor and the receiving terminal of the serial transceiver unit through the CPLD, so as to realize the reading of the CPLD register in different ways.

[0105] Step S602, if the second path is turned on, reading the main processor state information stored in the CPLD memory through the main processor, and sending the read main processor state information through the serial transceiver unit.

[0106] The above method, when the input data includes the second indication information, turns on the second path between the transmission terminal of the main processor and the receiving terminal of the serial transceiver unit through the CPLD; when the second path is turned on, reading the main processor state information stored in the CPLD memory through the main processor, and sending the read main processor state information through the serial transceiver unit. By controlling the second path to be turned on, the main processor state information stored in the CPLD memory can also be read, thereby improving the reliability of the system.

[0107] In a possible implementation, if the CPLD further includes an additional CPLD register, the reading of the main processor state information stored in the CPLD register through the CPLD can be realized in the following way:

[0108] Traverse the address information of each CPLD register through the CPLD;

[0109] ​The CPLD reads the main processor state information stored in the CPLD register corresponding to the address information according to the address information.

[0110] In a specific implementation, as shown in Figure 4 When the first path is turned on by the gating unit 24, that is, the path between the transmitting end (TX) of the CPLD 22 and the receiving end (RX) of the serial transceiver unit 23 is turned on, the path between the transmitting end (TX) of the main processor 21 and the receiving end (RX) of the serial transceiver unit 23 is disconnected. At this time, the CPLD 22 directly reads the main processor state information stored in each CPLD memory. Specifically, the CPLD 22 traverses the address information of each CPLD register, and according to each address information, one-to-one reads the main processor state information stored in the CPLD register corresponding to the address information, until the main processor state information stored in each CPLD register in the CPLD 22 is read completely. The read main processor state information is transmitted through the serial transceiver unit 24.

[0111] For example, the CPLD starts from address information 0X00, reads the main processor state information stored in the CPLD register corresponding to the address information 0X00, then the CPLD adds 1 to the address information, that is, reads the main processor state information stored in the CPLD register corresponding to the address information 0X01, then the CPLD adds 1 to the address information again, until the main processor state information stored in the CPLD register corresponding to the last address information is read, that is, the reading operation of the main processor state information stored in the CPLD register is completed. Then all the read main processor state information is transmitted to the display unit through the serial transceiver unit, so that the display unit displays the main processor state information.

[0112] The above method traverses the address information of each CPLD register by the CPLD; then, the CPLD reads the main processor state information stored in the CPLD register corresponding to the address information according to the traversed address information. Through the above method, the main processor state information stored in each CPLD register is read.

[0113] In a specific implementation, as shown in Figure 4 When the second path is turned on by the gating unit 24, that is, the path between the transmitting end (TX) of the main processor 21 and the receiving end (RX) of the serial transceiver unit 23 is turned on, the path between the transmitting end (TX) of the CPLD 22 and the receiving end (RX) of the serial transceiver unit 23 is disconnected. At this time, the main processor 21 selectively reads the main processor state information stored in the CPLD 22 memory through the communication bus, and then the main processor 21 sends the read main processor state information to the serial transceiver unit.

[0114] For example, the main processor can read the main processor state information stored in the CPLD register according to the preset communication protocol. For example, the main processor can read the main processor state information stored in all CPLD registers in the CPLD, the main processor can also read the main processor state information stored in any one or more CPLD registers in the CPLD, and the main processor can also read the main processor state information stored in the CPLD register corresponding to the preset address. The embodiments of the present application do not make any limitation on this. The main processor transmits the read main processor state information to the display unit through the serial transceiver unit, so that the display unit displays the main processor state information.

[0115] In a specific implementation, as shown in Figure 4 When the control end (CTL) of the CPLD 22 outputs a high-level signal, the path between the first input end and the output end of the gate 241 is controlled to be turned on, and then the first path between the transmission end (TX) of the CPLD 22 and the receiving end (RX) of the serial transceiver 231 is turned on. When the control end (CTL) of the CPLD 22 outputs a low-level signal, the path between the second input end and the output end of the gate 241 is controlled to be turned on, and then the second path between the transmission end (TX) of the main processor 21 and the receiving end (RX) of the serial transceiver 231 is turned on. If the CPLD 22 fails, the control end (CTL) of the CPLD 22 outputs a high-impedance state to the control end of the gate 241. When the control end of the gate 241 receives the high-impedance state, the path between the second input end and the output end of the gate 241 is turned on, and then the second path between the transmission end (TX) of the main processor 21 and the receiving end (RX) of the serial transceiver 231 is turned on, so that the serial transceiver 231 is still available. The first resistor R1 is used to prevent the gate 241 from being triggered by mistake.

[0116] It should be noted that in the initial state, the path between the transmission end (TX) of the main processor 21 and the receiving end (RX) of the serial transceiver 231 can be turned on by default.

[0117] In a possible implementation, after the CPLD receives the input data transmitted by the serial transceiver unit, the following processing is further performed: within a preset time length, it is judged whether new input data is received; if no new input data is received, the first path is turned on when the input data includes first indication information; if new input data is received, the input data and the new input data are transmitted as the content of file transmission by the CPLD.

[0118] In a specific implementation, when a file is being transmitted, there can be a case that the content of the file transmission includes the same information as the first indication information or the second indication information, for example, the content of the file transmission is "ALT+CTRL+G+HALLO", in which the content of the file transmission includes the same information as the first indication information "CTRL+G", and it is easy to misjudge the content of the file transmission as input data containing the first indication information, thereby incorrectly generating a corresponding control signal. Therefore, in order to avoid the occurrence of the above problem, after receiving the input data, the CPLD will determine whether there is new input data within a preset time period. If the CPLD receives new input data within the preset time period, it indicates that the current input data received by the CPLD is the content of the file transmission. If the CPLD does not receive new input data within the preset time period, and the current received input data includes the first indication information, the first path between the sending end of the CPLD and the receiving end of the serial transceiver unit is turned on. If the CPLD does not receive new input data within the preset time period, and the current received input data includes the second indication information, the second path between the sending end of the main processor and the receiving end of the serial transceiver unit is turned on.

[0119] For example, the preset time period can be 100 ms, that is, after the CPLD receives the input data "CTRL+G", it detects whether new input data is received within 100 ms. If the CPLD receives the input data "ATE" 10 ms after receiving the input data "CTRL+G", it indicates that the current received input data "CTRL+G" and the newly received input data "ATE" are the content of the file transmission, that is, the user is currently transmitting a file, and the content of the transmission is "CTRL+GATE". If the CPLD does not receive new input data 100 ms after receiving the input data "CTRL+G", the first path between the sending end of the CPLD and the receiving end of the serial transceiver unit is turned on. Similarly, if the CPLD does not receive new input data 100 ms after receiving the input data "CTRL+U", the second path between the sending end of the main processor and the receiving end of the serial transceiver unit is turned on.

[0120] The above method, after receiving the input data transmitted by the serial transceiver unit through the CPLD, determines whether new input data is received within a preset time period through the CPLD. If no new input data is received, the first path is turned on in the case that the input data includes the first indication information. If new input data is received, the CPLD regards the input data and the new input data as the content of the file transmission. By determining whether new input data is input within a preset time period, the possibility that the received input data is the content of the file transmission is screened out, and the reliability of the device is improved.

[0121] In a possible implementation, after receiving the input data transmitted by the serial transceiver unit through the CPLD, the CPLD determines whether preset data transmitted by the serial transceiver unit is received; then, the CPLD takes the time when the preset data is received as the starting time of the preset time length, and determines whether new input data is received within the preset time length.

[0122] It should be noted that the preset data in the embodiments of the present application can be a blank character (BLANK), and the embodiments of the present application do not make any limitation on this.

[0123] In a specific implementation, the following method can be used to determine whether the preset data is received:

[0124] The CPLD determines whether the preset data exists in the preset position, wherein the preset position is a position adjacent to the last position in the positions occupied by the input data. For example, the input data "CTRL+G" can occupy the 6th character position, and the preset position is the 7th character position; the input data "CTRL+U" can occupy the 12th character position, and the preset position is the 13th character position.

[0125] In a specific implementation, due to the external device connected to the serial transceiver unit, the input data is usually followed by a blank character, for example, the octopus device can cause the above phenomenon. If the blank character is not processed, the CPLD will judge it as new input data, and then identify the received input data as the content of file transmission, causing misjudgment. Therefore, in order to avoid the occurrence of the above phenomenon, after receiving the input data transmitted by the serial transceiver unit, the CPLD first determines whether the preset data transmitted by the serial transceiver unit is received; if the preset data is received, the time when the preset data is received is taken as the starting time of the preset time length, and the CPLD determines whether new input data is received within the preset time length; if the preset data is not received, the time when the input data is received is taken as the starting time of the preset time length, and the CPLD determines whether new input data is received within the preset time length.

[0126] The above method first determines, by the CPLD, whether the preset data transmitted by the serial transceiver unit is received, and then takes the time when the preset data is received as the starting time of the preset time length. Through the above method, the input data is avoided to be misjudged as the content of file transmission due to the existence of the preset data, such as a blank character, thereby improving the reliability of the system.

[0127] In the following, in order to further understand the scheme proposed in the present application, specific embodiments are introduced. Referring to Figure 7A workflow diagram of an information reading method provided in the embodiment of the present application is shown in FIG. 7, and the method flow specifically includes the following steps:

[0128] In step S701, input data transmitted by the serial transceiver unit is received through the CPLD;

[0129] In step S702, it is determined whether the preset data transmitted by the serial transceiver unit is received through the CPLD, if yes, step S703 is executed, otherwise, step S704 is executed;

[0130] In step S703, the moment when the preset data is received is taken as the starting moment of the preset time length;

[0131] In step S704, it is determined whether new input data is received within the preset time length, if yes, step S705 is executed, otherwise, step S706 or step S708 is executed;

[0132] In step S705, the input data and the new input data are transmitted as the content of the file through the CPLD;

[0133] In step S706, when the input data includes the first indication information, the passage between the first input end of the gating unit and the output end of the gating unit is controlled through the CPLD;

[0134] In step S707, the first passage between the transmitting end of the CPLD and the receiving end of the serial transceiver unit is turned on through the gating unit;

[0135] In step S708, when the input data includes the second indication information, the passage between the second input end of the gating unit and the output end of the gating unit is controlled through the CPLD;

[0136] In step S709, the second passage between the transmitting end of the main processor and the receiving end of the serial transceiver unit is turned on through the gating unit;

[0137] In step S7010, the main processor state information stored in the CPLD register is read according to the turned-on passage, and the read main processor state information is transmitted through the serial transceiver unit.

[0138] Based on the same concept, the embodiment of the present application further provides an information reading device applied to a hardware device, the hardware device including a central processing unit (CPU), a complex programmable logic device (CPLD), a serial transceiver unit, and the like, wherein the CPLD includes a CPLD register. Since the device is the device in the method in the embodiment of the present application, and the principle of solving problems of the device is similar to that of the method, the implementation of the device can be referred to the implementation of the method, and the repeated parts will not be described herein.

[0139] As Figure 8As shown in the above device includes the following modules:

[0140] The data processing module 801 is configured to receive input data transmitted by the serial transceiver unit through the CPLD, and when the input data includes first indication information, turn on the first path between the transmitting end of the CPLD and the receiving end of the serial transceiver unit.

[0141] The information transmission module 802 is configured to read the main processor state information stored in the CPLD register through the CPLD if the first path is turned on, and send the read main processor state information through the serial transceiver unit.

[0142] In a possible implementation, the hardware device further includes a gating unit, a first input end of the gating unit is electrically connected with the transmitting end of the CPLD, and an output end of the gating unit is electrically connected with the receiving end of the serial transceiver unit.

[0143] The data processing module 801 is specifically configured to:

[0144] When the input data includes the first indication information, the gating unit is controlled by the CPLD to turn on the path between the first input end and the output end.

[0145] In a possible implementation, the CPLD further includes an additional CPLD register, and the data processing module 801 is specifically configured to:

[0146] Iterate the address information of each CPLD register through the CPLD;

[0147] Read the main processor state information stored in the CPLD register corresponding to the address information according to the iterated address information through the CPLD.

[0148] In a possible implementation, the information reading device further includes a first data identification module.

[0149] The first data identification module is configured to determine whether new input data is received within a preset time length.

[0150] If no new input data is received, the first path is turned on when the input data includes the first indication information.

[0151] If new input data is received, the input data and the new input data are transmitted as the content of the file transmission through the CPLD.

[0152] In a possible implementation, the information reading device further includes a second data identification module.

[0153] The second data identification module is configured to determine, through the CPLD, that preset data transmitted through the serial transceiver unit is received.

[0154] The CPLD takes the time of receiving the preset data as the start time of the preset time length.

[0155] In a possible implementation, the data processing module 801 is further configured to:

[0156] When the input data comprises the second indication information, the CPLD turns on the second path between the sending end of the main processor and the receiving end of the serial transceiver unit.

[0157] If the second path is turned on, the main processor reads the main processor state information stored in the CPLD memory, and sends the read main processor state information through the serial transceiver unit.

[0158] In a possible implementation, the second input end of the gating unit is electrically connected with the sending end of the main processor; and the data processing module 801 is specifically configured to:

[0159] When the input data comprises the second indication information, the CPLD controls the path between the second input end of the gating unit and the output end of the gating unit to be turned on.

[0160] In a possible implementation, the input data is triggered by a user or generated according to the device state of the main processor.

[0161] Based on the same idea, the embodiment of the present application also provides an electronic device. Since the electronic device is the electronic device in the method of the embodiment of the present application, and the principle of solving the problem of the electronic device is similar to that of the method, the implementation of the electronic device can be referred to the implementation of the method, and the repeated parts will not be described here.

[0162] The electronic device 90 according to the embodiment of the present application will be described below with reference to Figure 9 Figure 9 The displayed electronic device 90 is only an example, and should not bring any limitation to the function and use range of the embodiment of the present application.

[0163] As shown in Figure 9 , the electronic device 90 can be in the form of a general computing device, for example, it can be a terminal device. The components of the electronic device 90 can include but are not limited to: the above-mentioned at least one processor 91, the above-mentioned at least one memory 92 storing processor-executable instructions, the bus 93 connecting different system components (including the memory 92 and the processor 91), and the processor 91 is the processor of an intelligent device.

[0164] The processor 91 realizes the following steps by running the executable instructions.

[0165] ​The CPLD receives input data transmitted by the serial transceiver unit, and when the input data includes first indication information, the first path between the transmitting end of the CPLD and the receiving end of the serial transceiver unit is turned on.

[0166] If the first path is turned on, the CPLD reads the main processor state information stored in the CPLD register, and sends the read main processor state information through the serial transceiver unit.

[0167] In a possible implementation, the hardware device further includes a gating unit, a first input end of the gating unit is electrically connected with the transmitting end of the CPLD, and an output end of the gating unit is electrically connected with the receiving end of the serial transceiver unit.

[0168] The processor 91 is specifically configured to:

[0169] When the input data includes the first indication information, the CPLD controls the path between the first input end of the gating unit and the output end of the gating unit to be turned on.

[0170] In a possible implementation, the CPLD further includes an additional CPLD register, and the processor 91 is specifically configured to:

[0171] The CPLD traverses the address information of each CPLD register;

[0172] The CPLD reads the main processor state information stored in the CPLD register corresponding to the address information according to the traversed address information.

[0173] In a possible implementation, the processor 91 is further configured to:

[0174] Within a preset time length, it is judged whether new input data is received;

[0175] If the new input data is not received, when the input data includes the first indication information, the first path is turned on;

[0176] If the new input data is received, the CPLD takes the input data and the new input data as the content of file transmission.

[0177] In a possible implementation, the processor 91 is further configured to:

[0178] The CPLD determines that preset data transmitted through the serial transceiver unit is received;

[0179] The CPLD takes the moment when the preset data is received as the starting moment of the preset time length.

[0180] In a possible implementation, the processor 91 is further configured to:

[0181] When the input data comprises the second indication information, the second path between the sending end of the main processor and the receiving end of the serial transceiver unit is turned on by the CPLD.

[0182] If the second path is turned on, the main processor state information stored in the CPLD memory is read by the main processor, and the read main processor state information is sent by the serial transceiver unit.

[0183] In a possible implementation, the second input end of the gating unit is electrically connected with the sending end of the main processor.

[0184] The processor 91 is specifically configured to:

[0185] When the input data comprises the second indication information, the path between the second input end of the gating unit and the output end of the gating unit is turned on by the CPLD.

[0186] In a possible implementation, the input data is triggered by a user, or is generated according to the device state of the main processor.

[0187] The bus 93 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a processor or a local bus using any of a variety of bus structures.

[0188] The memory 92 can include a readable medium in the form of volatile memory, such as a random access memory (RAM) 921 and / or a cache memory 922, and can further include a read-only memory (ROM) 923.

[0189] The memory 92 can also include a program / utility 925 having a set of program modules 924, including but not limited to an operating system, one or more application programs, other program modules, and program data, each of which or some combination thereof can include implementation of a network environment.

[0190] The electronic device 90 can also communicate with one or more external devices 94 such as a keyboard or a pointing device, which can be disposed on or off the electronic device 90, by I / O interface 95. Further, the electronic device 90 can communicate with one or more devices that enable a user to interact with the electronic device 90 and / or one or more devices that enable the electronic device 90 to communicate with one or more other computing devices. Such communication can be via an I / O interface 95. The electronic device 90 can also communicate with one or more networks, such as a local area network (LAN), a wide area network (WAN), and / or the public network, such as the Internet, by network adapter 96. As depicted, the network adapter 96 is in communication with the other modules of the electronic device 90 through the bus 93. It will be appreciated that other hardware and / or software modules can be used in conjunction with the electronic device 90, such as, but not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0191] In some possible embodiments, various aspects of the present application can also be implemented as a program product, including a program code, which, when run on a terminal device, causes the terminal device to execute the steps of the various modules of the information reading device according to various exemplary embodiments of the present disclosure described in the above "Exemplary Methods" section of the present specification, such as receiving input data transmitted by the serial port transceiver unit through the CPLD, wherein when the input data comprises first indication information, turning on the first path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit; if the first path is turned on, reading the main processor state information stored in the CPLD register through the CPLD, and transmitting the read main processor state information through the serial port transceiver unit.

[0192] The program product can employ any combination of one or more computer-readable media. The computer-readable media can be a computer-readable storage medium or a computer-readable signal medium. The computer-readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include the following: an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0193] As Figure 10As shown, a program product 100 for an information reading method according to an embodiment of the present application is described, which can take a portable compact disc read-only memory (CD-ROM) and include a program code, and can be run on a terminal device, such as a personal computer. However, the program product of the present application is not limited thereto, and in the present document, the readable storage medium can be any tangible medium that contains or stores a program, which can be used by or in connection with an instruction execution system, apparatus, or device.

[0194] The program code can be transmitted over any suitable medium, including, but not limited to, wireless, wired, optical fiber cable, RF, etc., or any suitable combination thereof.

[0195] The program code contained on the readable medium can be transmitted using any suitable medium, including, but not limited to, wireless, wired, optical fiber cable, RF, etc., or any suitable combination thereof.

[0196] The program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++, etc., and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's device and partly on a remote computing device or entirely on the remote computing device or server. In the latter scenario, the remote computing device can be connected to the user's device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computing device, such as through the Internet using an Internet Service Provider.

[0197] It should be noted that, although several modules or sub-modules of the system are mentioned in the above detailed description, such a division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules described above can be embodied in one module. Conversely, the features and functions of one module described above can be further divided into modules for embodiment.

[0198] Moreover, although the operations of the method(s) herein can be described in a particular, sequential order, this order is not meant to be a limitation and one or more of the operations can be performed in different orders, or omitted, without being beyond the scope of the application. Further, not all operations can be performed, and / or more than one operation can be performed concurrently. Additionally, or alternatively, certain operations can be performed in parallel, or in sub-operations.

[0199] The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0200] Accordingly, the present application can be embodied in hardware and / or in software (including firmware, resident software, micro-code, etc.). Furthermore, the present application can take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium for use by or in connection with an instruction execution system. In the context of the present application, a computer-usable or computer-readable medium can be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

[0201] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the application, the application can be practiced otherwise than as specifically described, without departing from the spirit and scope of the application.

Claims

1. An information reading method characterized by comprising: The application is applied to a hardware device, the hardware device comprises a main processor, a complex programmable logic device (CPLD) and a serial transceiver unit, wherein the CPLD comprises a CPLD register, and the method comprises the following steps: receiving input data transmitted by the serial transceiver unit through the CPLD, wherein when the input data comprises first indication information, a first path between the transmitting end of the CPLD and the receiving end of the serial transceiver unit is turned on; if the first path is turned on, reading the main processor state information stored in the CPLD register through the CPLD, and transmitting the read main processor state information through the serial transceiver unit.

2. The method of claim 1, wherein, The hardware device further comprises a gating unit, a first input end of the gating unit is electrically connected with the transmitting end of the CPLD, and an output end of the gating unit is electrically connected with the receiving end of the serial transceiver unit. When the input data comprises first indication information, the first path between the transmitting end of the CPLD and the receiving end of the serial transceiver unit is turned on. When the input data comprises first indication information, the first path between the transmitting end of the CPLD and the receiving end of the serial transceiver unit is turned on.

3. The method of claim 1, wherein, The CPLD further comprises an additional CPLD register, and the reading of the main processor state information stored in the CPLD register through the CPLD comprises the following steps: traversing the address information of each CPLD register through the CPLD; reading the main processor state information stored in the CPLD register corresponding to the address information according to the traversed address information through the CPLD.

4. The method of claim 1, wherein, After the receiving of the input data transmitted by the serial transceiver unit through the CPLD, the method further comprises the following steps: determining whether new input data is received within a preset time length; if the new input data is not received, when the input data comprises the first indication information, the first path is turned on; if the new input data is received, the input data and the new input data are taken as the content of file transmission through the CPLD.

5. The method of claim 4, wherein, After the receiving of the input data transmitted by the serial transceiver unit through the CPLD, before the determining of whether new input data is received within a preset time length through the CPLD, the method further comprises the following steps: determining that the preset data transmitted through the serial transceiver unit is received through the CPLD; taking the time point of receiving the preset data as the starting time point of the preset time length through the CPLD.

6. The method of claim 2, wherein, The method further comprises the following steps: when the input data comprises second indication information, a second path between the transmitting end of the main processor and the receiving end of the serial transceiver unit is turned on through the CPLD; if the second path is turned on, the main processor state information stored in the CPLD memory is read through the main processor, and the read main processor state information is transmitted through the serial transceiver unit.

7. The method of claim 6, wherein, A second input end of the gating unit is electrically connected with the transmitting end of the main processor. The second path between the transmitting end of the CPLD and the receiving end of the serial transceiver unit is turned on when the input data includes second indication information, comprising: The path between the second input end of the gating unit and the output end of the gating unit is turned on by the CPLD when the input data includes second indication information.

8. The method according to any one of claims 1 to 7, characterized in that The input data is triggered by a user or generated according to the device state of the main processor.

9. An information reading apparatus characterized by comprising: The application is applied to a hardware device, which comprises a main processor, a complex programmable logic device (CPLD) and a serial transceiver unit, wherein the CPLD comprises a CPLD register, and the device comprises: A data receiving module is configured to receive input data transmitted by the serial transceiver unit through the CPLD, wherein a first path between the transmitting end of the CPLD and the receiving end of the serial transceiver unit is turned on when the input data includes first indication information. An information reading module is configured to read main processor state information stored in the CPLD register through the CPLD if the first path is turned on, and send the read main processor state information through the serial transceiver unit.

10. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the method of any one of claims 1-8.

11. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1-8.

Images