Processor, electronic device, and data communication method

Abstract

The invention relates to a processor, electronic equipment and a data communication method. Based on the invention, the communication interconnection between the processor and other processors is realized through the network switching device, and the data communication can be realized by utilizing a plurality of groups of QP receiving and transmitting channels borne on the same port cascade transmission link. Wherein the multiple groups of QP receiving and transmitting channels correspond to multiple types of interactive data involved in data communication, and the multiple types of interactive data can concurrently realize mutually independent stream transmission through the multiple groups of QP receiving and transmitting channels respectively. Therefore, compared with a serial mode of cascading transmission links of streaming transmission time division multiplexing ports of multiple types of interactive data, the transmission deadlock risk of data communication between processors can be reduced.

Description

Technical Field

[0001] The present application relates to the field of data communication, and in particular to a processor, an electronic device, and a data communication method. Background Art

[0002] Multiple processors can collaborate to complete processing tasks that require high computing power, such as large model training, through data communication between each other. Among them, multiple processors can be connected to different physical ports of the network switching device, so that any two processors can communicate and interconnect through the port cascade transmission link with the network switching device as the forwarding node.

[0003] The data communication between multiple processors may involve multiple types of interactive data, and the multiple types of interactive data involved in the data communication between any two processors can time-multiplex the port cascade transmission link between the two processors.

[0004] However, time-sharing multiplexing of multiple types of interactive data on the same port cascade transmission link may cause deadlock in stream transmission. In addition, how to reduce the risk of transmission deadlock in data communication between processors has become a technical problem to be solved. Summary of the invention

[0005] An embodiment of the present application provides a processor, an electronic device, and a data communication method, which can utilize a QP (Queue Pair) connection based on RDMA (Remote Direct Memory Access) to reduce the risk of transmission deadlock in data communication between processors.

[0006] In one embodiment of the present application, a processor is provided, the processor comprising: A chip communication port, wherein the chip communication port is used to realize communication interconnection between the processor and other processors through a network switching device, the communication interconnection is used for data communication between the processor and the other processors, the communication interconnection includes a port cascade transmission link between the processor and the other processors based on port switching forwarding of the network switching device, and the data communication includes stream transmission of multiple types of interactive data through the port cascade transmission link; A port driving circuit, wherein the port driving circuit is used to create a plurality of groups of QP transceiver channels based on RDMA, wherein the plurality of groups of QP transceiver channels are carried in the same port cascade transmission link between the processor and the other processors, and the plurality of types of interactive data are based on a correspondence between the plurality of types and the plurality of groups of QP transceiver channels, and are respectively transmitted independently of each other through the plurality of groups of QP transceiver channels.

[0007] In some examples, optionally, the processor further includes: a chip processing core, the chip processing core being connected to the port driving circuit via an on-chip bus of the processor, the on-chip bus carrying a plurality of bus logic channels, and the plurality of bus logic channels being used to respectively implement on-chip transmission of the plurality of types of interactive data in the processor; wherein the correspondence between the plurality of groups of QP transceiver channels and the plurality of types matches the correspondence between the plurality of bus logic channels and the plurality of types, so that the stream transmission of the plurality of types of interactive data and the transmission connection between the on-chip transmission are independent of each other.

[0008] In some examples, optionally, the multiple types include: write requests, atomic requests, read requests, and read responses; the multiple bus logical channels include: a first bus logical channel corresponding to the write requests and the atomic requests, a second bus logical channel corresponding to the read requests, and a third bus logical channel corresponding to the read responses; the multiple groups of QP transceiver channels include a group of write request QP transceiver channels corresponding to the write requests and the atomic requests, a group of read request QP transceiver channels corresponding to the read requests, and a group of read response QP transceiver channels corresponding to the read responses.

[0009] In some examples, optionally, the transmission priority of the read response QP transceiver channel is higher than the transmission priority of the write request QP transceiver channel and the read request QP transceiver channel.

[0010] In some examples, optionally, the multiple bus logical channels also include a fourth bus logical channel for transmitting write responses, and the port driver circuit is further used to respond to the write request received from the chip processing core and return the corresponding write response to the chip processing core through the fourth bus logical channel; the write response corresponding to the write request received through the write request QP receiving channel is generated internally by the other processor that initiates the write request.

[0011] In some examples, optionally, the on-chip bus is an AXI bus, and: the first bus logical channel includes at least one of the AW channel and the W channel of the AXI bus; the second bus logical channel includes the AR channel of the AXI bus; the third bus logical channel includes the R channel of the AXI bus; and the fourth bus logical channel includes the B channel of the AXI bus.

[0012] In some examples, optionally, the write request QP transceiver channel includes a write request QP sending channel, the read request QP transceiver channel includes a read request QP sending channel, and the read response QP transceiver channel includes a read response QP sending channel, wherein: the transmission order of the write request and the atomic request in the stream transmission implemented by the write request QP sending channel is the same as the transmission order in the intra-chip transmission implemented by the first bus logical channel; the transmission order of the read request in the stream transmission implemented by the read request QP sending channel is the same as the transmission order in the intra-chip transmission implemented by the second bus logical channel; the transmission order of the read response in the stream transmission implemented by the read response QP sending channel is the same as the transmission order in the intra-chip transmission implemented by the third bus logical channel.

[0013] In some examples, optionally, the write request QP transceiver channel includes a write request QP receiving channel, the read request QP transceiver channel includes a read request QP receiving channel, and the read response QP transceiver channel includes a read response QP receiving channel, wherein: the write requests with the same other processor as the data source, the transmission order in the intra-chip transmission implemented by the first bus logical channel is the same as the transmission order in the stream transmission implemented by the write request QP receiving channel; the atomic requests with the same other processor as the data source, the transmission order in the intra-chip transmission implemented by the first bus logical channel is de-associated with the transmission order in the stream transmission implemented by the write request QP receiving channel; the read requests with the same other processor as the data source, the transmission order in the intra-chip transmission implemented by the second bus logical channel is de-associated with the transmission order in the stream transmission implemented by the read request QP receiving channel; the read responses with the same other processor as the data source, the transmission order in the intra-chip transmission implemented by the third bus logical channel is the same as the transmission order in the stream transmission implemented by the read response QP receiving channel.

[0014] In some examples, optionally, the on-chip bus is configured to implement the on-chip transmission in an order-preserving manner for interactive data with the same bus identifier, and: the bus identifier includes a first bus identifier applied to the first bus logical channel, and the port driver circuit is also used to: allocate the same first bus identifier corresponding to the data source to all write requests with the same other processor as the data source; the bus identifier includes a first exclusive identifier applied to the first bus logical channel, and the port driver circuit is also used to: allocate different first exclusive identifiers to different atomic requests, and the first exclusive identifier allocated to each atomic request is recycled in response to the success of the operation of the atomic request; the bus identifier includes a first bus identifier applied to the first bus logical channel, and the port driver circuit is also used to: allocate different first exclusive identifiers to different atomic requests, and the first exclusive identifier allocated to each atomic request is recycled in response to the success of the operation of the atomic request; the bus identifier includes a first bus identifier applied to the first bus logical channel, and the port driver circuit is also used to: allocate different first exclusive identifiers to different atomic requests, and the first exclusive identifier allocated to each atomic request is recycled in response to the success of the operation of the atomic request The second exclusive identifier of the second bus logical channel, the port driver circuit is also used to: assign different second exclusive identifiers to different read requests respectively, and the second exclusive identifier assigned to each read request is recycled in response to the successful operation of the read request; the bus identifier includes the second bus identifier applied to the third bus logical channel, and the port driver circuit is also used to: query the second bus identifier stored in association with the read operation tag of the read response; wherein the read response and the corresponding read request carry the same read operation tag, and the second bus identifier is pre-assigned for the corresponding read response and stored in association with the corresponding read operation tag when the read request sent to the same other processor is issued.

[0015] In some examples, optionally, the chip communication port is connected to the first network switching port of the network switching device, and the network switching device also includes a second network switching port connected to other chip communication ports of the other processors, and the port cascade transmission link includes a first port serial link between the chip communication port and the first network switching port, a second port serial link between the second network switching port and the other chip communication port, and a port switching link between the first network switching port and the second network switching port for implementing the port switching forwarding; wherein the multiple groups of QP transceiver channels are created between the chip communication port and the other chip communication ports, and the multiple groups of QP transceiver channels are respectively carried on two sections of the first port serial link and the second port serial link, and are bridged through the corresponding multiple groups of switching channels between the first network switching port and the second network switching port.

[0016] In some examples, optionally, the processor further includes: a chip processing core, the chip processing core is connected to the port driving circuit through an on-chip bus of the processor, the on-chip bus carries multiple bus logical channels, and the multiple bus logical channels are used to respectively realize the on-chip transmission of the multiple types of interactive data in the processor; the correspondence between the multiple groups of QP transceiver channels and the multiple types matches the correspondence between the multiple bus logical channels and the multiple types, so that the stream transmission and the on-chip transmission of the multiple types of interactive data are independent of each other; the port driving circuit is used to maintain multiple groups of first on-chip transceiver cache queues, the multiple groups of first on-chip transceiver cache queues are used to realize the association and docking between the multiple groups of QP transceiver channels and the multiple bus logical channels, and the association and docking are used for the transmission connection between the on-chip transmission and the stream transmission.

[0017] In some examples, optionally, the multiple groups of first on-chip transceiver cache queues include multiple receive cache queues, each of the multiple receive cache queues is used to cache interactive data of the same corresponding type from different data sources, the different data sources include multiple different other processors, any one of the multiple receive cache queues is connected to a corresponding bus logical channel among the multiple bus logical channels through a parallel FIFO queue group, and the parallel FIFO queue group includes multiple FIFO queues corresponding one-to-one to different data sources; interactive data of different data sources cached in any one of the multiple receive cache queues are distributed in order to FIFO queues corresponding to the same data source in the parallel FIFO queue group by polling lookup tables of different data sources.

[0018] In some examples, optionally, the multiple types include: write request, atomic request, read request, and read response; the multiple bus logical channels include: a first bus logical channel corresponding to the write request and the atomic request, a second bus logical channel corresponding to the read request, and a third bus logical channel corresponding to the read response; the multiple groups of QP transceiver channels include: a write request QP sending channel and a write request QP receiving channel corresponding to the write request and the atomic request, a read request QP sending channel and a read request QP receiving channel corresponding to the read request, and a read response QP sending channel and a read response QP receiving channel corresponding to the read response. P receiving channel; the multiple groups of first on-chip transceiver cache queues include: multiple receiving cache queues corresponding to the write request QP receiving channel, the read request QP receiving channel, and the read response QP receiving channel respectively; the receiving cache queue corresponding to the write request QP receiving channel and the first bus logical channel, and the receiving cache queue corresponding to the read request QP receiving channel and the second bus logical channel are respectively connected through different parallel FIFO queue groups, and the receiving cache queue corresponding to the read response QP receiving channel is connected to the third bus logical channel through one FIFO queue.

[0019] In some examples, optionally, the port driver circuit also has a receive status register group corresponding to the multiple receive cache queues, and each register bit of the receive status register group is used to represent whether a corresponding receive cache queue among the multiple receive cache queues currently caches a polling result of interaction data of a corresponding data source.

[0020] In some examples, optionally, the port driver circuit also has a stock status register group corresponding to the parallel FIFO queue group, each register bit of the stock status register group is used to indicate whether a corresponding FIFO queue in the parallel FIFO queue group is currently filled with interaction data from a corresponding data source, and an execution scope of the lookup table excludes the data source corresponding to the FIFO queue indicated by the stock status register group as currently filled.

[0021] In some examples, optionally, any type of interaction data carries a network global identifier for uniquely characterizing a data source.

[0022] Another embodiment of the present application provides a multi-processor system, which includes a first processor, a second processor, and a network switching device, wherein the first processor is configured as the processor described in the aforementioned embodiment, and the second processor includes other processors that communicate data with the processor described in the aforementioned embodiment.

[0023] Another embodiment of the present application provides an electronic device, which includes a network switching device and at least two computing devices, one of the at least two computing devices includes the processor as described in the above embodiment, and the other computing devices in the at least two computing devices include other processors that realize data communication with the processor described in the above embodiment based on communication interconnection.

[0024] Another embodiment of the present application provides a data communication method, which is applied to a processor; the processor has a chip communication port, the chip communication port is used to realize the communication interconnection between the processor and other processors through a network switching device, the communication interconnection is used for data communication between the processor and the other processors, the communication interconnection includes a port cascade transmission link between the processor and the other processors based on port switching forwarding of the network switching device, the data communication includes stream transmission of multiple types of interactive data through the port cascade transmission link, and the data communication method includes: Creating multiple groups of QP transceiver channels based on RDMA, wherein the multiple groups of QP transceiver channels are carried in the same port cascade transmission link between the processor and the other processors; Based on the correspondence between the multiple types and the multiple groups of QP transceiver channels, the multiple groups of QP transceiver channels are used to independently implement the stream transmission of the multiple types of interactive data.

[0025] In some examples, optionally, the on-chip bus of the processor carries multiple bus logical channels; the data communication method also includes: utilizing the multiple bus logical channels to respectively implement on-chip transmission of the multiple types of interactive data in the processor; wherein the correspondence between the multiple groups of QP transceiver channels and the multiple types matches the correspondence between the multiple bus logical channels and the multiple types, so that the transmission connection between the stream transmission and the on-chip transmission of the multiple types of interactive data is independent of each other.

[0026] In some examples, optionally, the multiple types include: write requests, atomic requests, read requests, and read responses; the multiple bus logical channels include: a first bus logical channel corresponding to the write requests and the atomic requests, a second bus logical channel corresponding to the read requests, and a third bus logical channel corresponding to the read responses; the multiple groups of QP transceiver channels include a group of write request QP transceiver channels corresponding to the write requests and the atomic requests, a group of read request QP transceiver channels corresponding to the read requests, and a group of read response QP transceiver channels corresponding to the read responses.

[0027] In some examples, optionally, the transmission priority of the read response QP transceiver channel is higher than the transmission priority of the write request QP transceiver channel and the read request QP transceiver channel.

[0028] In some examples, optionally, the multiple bus logical channels also include a fourth bus logical channel for transmitting write responses, and the data communication method also includes: in response to a write request generated from within the processor on the fourth bus logical channel, returning a corresponding write response through the fourth bus logical channel; the write response corresponding to the write request received through the write request QP receiving channel is generated within the other processor that initiated the write request.

[0029] In some examples, optionally, the write request QP transceiver channel includes a write request QP sending channel, the read request QP transceiver channel includes a read request QP sending channel, and the read response QP transceiver channel includes a read response QP sending channel; the use of the multiple bus logical channels to respectively implement the intra-chip transmission of the multiple types of interactive data in the processor includes: keeping the transmission order of the write requests and the atomic requests in the stream transmission implemented by the write request QP sending channel the same as the transmission order in the intra-chip transmission implemented by the first bus logical channel; keeping the transmission order of the read requests in the stream transmission implemented by the read request QP sending channel the same as the transmission order in the intra-chip transmission implemented by the second bus logical channel; keeping the transmission order of the read responses in the stream transmission implemented by the read response QP sending channel the same as the transmission order in the intra-chip transmission implemented by the third bus logical channel.

[0030] In some examples, optionally, the write request QP transceiver channel includes a write request QP receiving channel, the read request QP transceiver channel includes a read request QP receiving channel, and the read response QP transceiver channel includes a read response QP receiving channel; based on the correspondence between the multiple types and the multiple groups of QP transceiver channels, the corresponding QP sending channels and QP receiving channels in the multiple groups of QP transceiver channels are used to independently implement the stream transmission of the multiple types of interactive data, including: maintaining the transmission order of the write request with the same other processor as the data source in the intra-chip transmission implemented by the first bus logic channel to be the same as the transmission order in the stream transmission implemented by the write request QP receiving channel. the same; de-correlating the transmission order of the atomic requests with the same other processor as the data source in the intra-chip transmission implemented by the first bus logical channel from the transmission order in the stream transmission implemented by the write request QP receiving channel; de-correlating the transmission order of the read requests with the same other processor as the data source in the intra-chip transmission implemented by the second bus logical channel from the transmission order in the stream transmission implemented by the read request QP receiving channel; keeping the transmission order of the read responses with the same other processor as the data source in the intra-chip transmission implemented by the third bus logical channel the same as the transmission order in the stream transmission implemented by the read response QP receiving channel.

[0031] In some examples, optionally, the on-chip bus is configured to implement the on-chip transmission of interactive data with the same bus identifier in an order-preserving manner, and: the bus identifier includes a first bus identifier applied to the first bus logical channel, and the transmission order of the write request with the same other processor as the data source in the on-chip transmission implemented by the first bus logical channel is maintained to be the same as the transmission order in the stream transmission implemented by the write request QP receiving channel, including: allocating the same first bus identifier corresponding to the data source to all write requests with the same other processor as the data source; the bus identifier includes a first exclusive identifier applied to the first bus logical channel, and the transmission order of the atomic request with the same other processor as the data source in the on-chip transmission implemented by the first bus logical channel is de-associated with the transmission order in the stream transmission implemented by the write request QP receiving channel, including: assigning different first exclusive identifiers to different atomic requests, and assigning different first exclusive identifiers to each atomic request. The first exclusive identifier of the request is recycled in response to the successful operation of the atomic request; the bus identifier includes the second exclusive identifier applied to the second bus logical channel, and the transmission order of the read request with the same other processor as the data source in the intra-chip transmission implemented by the second bus logical channel is de-associated with the transmission order in the stream transmission implemented by the read request QP receiving channel, including: different second exclusive identifiers are assigned to different read requests, and the second exclusive identifier assigned to each read request is recycled in response to the successful operation of the read request; the bus identifier includes the second bus identifier applied to the third bus logical channel, and the transmission order of the read response with the same other processor as the data source in the intra-chip transmission implemented by the third bus logical channel is kept the same as the transmission order in the stream transmission implemented by the read response QP receiving channel, including: for all read responses with the same other processor as the data source, the same second bus identifier corresponding to the data source is assigned.

[0032] In some examples, optionally, the chip communication port is connected to the first network switching port of the network switching device, and the network switching device also includes a second network switching port connected to the other chip communication ports of the other processors, and the port cascade transmission link includes a first port serial link between the chip communication port and the first network switching port, a second port serial link between the second network switching port and the other chip communication ports, and a port switching link between the first network switching port and the second network switching port for implementing the port switching forwarding; wherein the multiple groups of QP transceiver channel segments are created between the chip communication port and the other chip communication ports, and the multiple groups of QP transceiver channels are respectively carried on two segments of the first port serial link and the second port serial link, and are bridged through the corresponding multiple groups of switching channels between the first network switching port and the second network switching port.

[0033] In some examples, optionally, the processor's on-chip bus carries multiple bus logical channels, and the multiple bus logical channels are used to respectively implement the on-chip transmission of the multiple types of interactive data in the processor; the correspondence between the multiple groups of QP transceiver channels and the multiple types matches the correspondence between the multiple bus logical channels and the multiple types, so that the stream transmission and the on-chip transmission of the multiple types of interactive data are independent of each other; the processor maintains multiple groups of first on-chip transceiver cache queues, and the multiple groups of first on-chip transceiver cache queues are used to implement the association and docking between the multiple groups of QP transceiver channels and the multiple bus logical channels, and the association and docking are used for the transmission connection between the on-chip transmission and the stream transmission; the multiple groups of first on-chip transceiver cache queues include multiple receive cache queues, the Each of the multiple receive cache queues is used to cache the same corresponding type of interactive data from different data sources, and the different data sources include multiple different other processors. Any one of the multiple receive cache queues is connected to the corresponding bus logical channel of the multiple bus logical channels through a parallel FIFO queue group, and the parallel FIFO queue group includes multiple FIFO queues corresponding to different data sources one by one. The use of the multiple bus logical channels to respectively realize the on-chip transmission of the multiple types of interactive data in the processor includes: the interactive data of different data sources cached in any one of the multiple receive cache queues is distributed in order to the FIFO queues corresponding to the same data source in the parallel FIFO queue group by polling the lookup table of different data sources.

[0034] In some examples, optionally, any type of interaction data carries a network global identifier for uniquely characterizing a data source.

[0035] Another embodiment of the present application provides an electronic device, which includes a network switching device, a processor for executing the data communication method as described in the above embodiment, and other processors that realize data communication based on communication interconnection between the network switching device and the processor described in the above embodiment.

[0036] Based on the above-mentioned embodiments of the present application, the communication interconnection between the processor and other processors realized through the network switching device can realize data communication by using multiple groups of QP transceiver channels carried on the same port cascade transmission link. There is a corresponding relationship between the multiple groups of QP transceiver channels and the multiple types of interactive data involved in the data communication, and the multiple types of interactive data can be streamed independently of each other through the multiple groups of QP transceiver channels. Therefore, compared with the serial mode of the time-division multiplexing port cascade transmission link for the stream transmission of multiple types of interactive data, the transmission deadlock risk of data communication between processors can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The following drawings are only used to illustrate and explain the present application, and do not limit the scope of the present application: Figure 1 A schematic diagram of the structure of a multi-processor network in an embodiment of the present application; Figure 2 A schematic diagram of the structure of the communication interconnection between multiple processors in an embodiment of the present application; Figure 3 A schematic diagram of an extended structure of communication interconnection between multiple processors in an embodiment of the present application; Figure 4 A schematic diagram of the principle of data communication between multiple processors in an embodiment of the present application; Figure 5 is a schematic diagram of a transmission deadlock in a comparative example; Figure 6 A schematic diagram of the effect of avoiding transmission deadlock in data communication between multiple processors in an embodiment of the present application; Figure 7 is a schematic diagram of an exemplary internal structure of a processor in an embodiment of the present application; Figure 8 A schematic diagram of the extended principle of data communication between multiple processors in an embodiment of the present application; Fig. 9 is a schematic diagram of multi-source mutual interference in a comparative example; Fig.10 It is a schematic diagram of the optimized structure of the chip communication port of the processor in the embodiment of the present application; Fig.11 The figure is a schematic diagram of an exemplary flow chart of a data communication method in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and examples.

[0039] Figure 1 This is a schematic diagram of the structure of a multi-processor network in an embodiment of the present application. Figure 1 In an embodiment of the present application, the network switching device SW may include multiple network switching ports Ps_1~Ps_N, and the multiple network switching ports Ps_1~Ps_N may be physically connected to the chip communication ports Pu_1~Pu_N of the multiple processors U_1~U_N, respectively, and the multiple processors U_1~U_N may be interconnected through the network switching device SW. Wherein, N is a positive integer greater than 1. For example, the embodiment of the present application takes N as 32 as an example for an exemplary graphical expression. Furthermore, in an embodiment of the present application, the network switching device SW may have the physical form of a board, or the network switching device SW may have the physical form of a complete device.

[0040] For example, in the embodiment of the present application, any one of the processors U_i among the multiple processors U_1~U_N may be a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural Network Processing Unit), a DPU (Deep Learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit). That is, the above description of the processor type in the embodiment of the present application is intended to express that the communication interconnection between each processor U_i and other processors U_j through the network switching device SW can be free from the restriction of the processor type.

[0041] Exemplarily, in an embodiment of the present application, multiple processors U_1~U_N can be distributed in multiple computing devices Dev_1~Dev_M, and each processor U_i and any other processor U_j that is interconnected through the network switching device SW can be located in the same computing device Dev_k in the multiple computing devices Dev_1~Dev_M, or can be located in different computing devices in the multiple computing devices Dev_1~Dev_M. Wherein, M is a positive integer greater than or equal to 1, and M and N can be the same, or N can be greater than M. Exemplarily, the embodiment of the present application is illustrated by taking N as 32 and M as 4 as an example. In this case, the 32 processors U_1~U_32 can be divided into 4 groups of 8 and deployed in 4 computing devices Dev_1~Dev_4 in groups. It can be understood that the embodiments of the present application describe the distribution of multiple processors U_1~U_N in multiple computing devices Dev_1~Dev_M, which is intended to express that the communication interconnection between each processor U_i and other processors U_j through the network switching device SW can be free from the restriction of the device ownership of the processor.

[0042] For example, in an embodiment of the present application, data communication between multiple processors may be implemented based on an Ethernet protocol. In this case, the network switching device may include an Ethernet switch.

[0043] Figure 2 This is a schematic diagram of the structure of the communication interconnection between multiple processors in the embodiment of the present application. Figure 2 In the embodiment of the present application, the communication interconnection between any one processor U_i among the multiple processors U_1~U_N and other processors U_j may include a port cascade transmission link based on port switching forwarding of the network switch device SW. In the embodiment of the present application, i is 25 and j is 8 as an example to illustrate the communication interconnection between a processor U_i and another other processor U_j.

[0044] Exemplarily, in an embodiment of the present application, each network switching port Ps_i of the plurality of network switching ports Ps_1 to Ps_N of the network switching device SW may be physically connected to a chip communication port Pu_i of a corresponding processor U_i, and the physical connection between each network switching port Ps_i of the network switching device SW and a chip communication port Pu_i of a corresponding processor U_i may be referred to as a port serial link corresponding to the processor U_i in the network switching device SW. Wherein, i is a positive integer greater than or equal to 1 and less than or equal to N.

[0045] Exemplarily, in the embodiment of the present application, data can be forwarded mutually between any two network switching ports Ps_i and Ps_j of the network switching device SW, and the internal forwarding link between any two network switching ports Ps_i and Ps_j of the network switching device SW can be referred to as a port switching link inside the network switching device SW. Wherein, j is a positive integer greater than or equal to 1 and less than or equal to N, and j is different from i.

[0046] Exemplarily, in order to facilitate the distinction between the network switching ports Ps_i and Ps_j of different network switching devices SW connected to different processors U_i and U_j, respectively, the embodiments of the present application refer to the network switching ports Ps_i and Ps_j as the first network switching port and the second network switching port, respectively, in the following text. The first network switching port can be considered as the network switching port connected to the processor in the network switching device SW determined from the perspective of the processor U_i, and the second network switching port can be considered as the network switching port connected to any other processor U_j in the network switching device SW determined from the perspective of each processor U_i. In this case, for any processor U_i among the multiple processors U_1~U_N, its chip communication port Pu_i can be connected to a corresponding network switching port Ps_i among the multiple network switching ports Ps_1~Ps_N of the network switching device SW; and, for any other processor U_ j among the multiple processors U_1~U_N except the processor U_i, its chip communication port Pu_i can be connected to another corresponding network switching port Ps_ j among the multiple network switching ports Ps_1~Ps_N of the network switching device SW.

[0047] Exemplarily, in order to distinguish the port serial links corresponding to different processors U_i and U_j in the network switching device SW, the embodiments of the present application may hereinafter refer to the port serial link between the chip communication port Pu_i of any processor U_i and the first network switching port Ps_i as the first port serial link, and the port serial link between the chip communication port Pu_j of any other processor U_j and the second network switching port Ps_j as the second port serial link.

[0048] Exemplarily, in an embodiment of the present application, the first port serial link and the second port serial link respectively corresponding to any one of the processors U_i and any other processor U_j among the multiple processors U_1~U_N, and the port switching link between the first network switching port Ps_i and the second network switching port Ps_j inside the network switching device SW can be cascaded between the two processors U_i and U_j into a port cascade transmission link; and any one of the processors U_i and any other processor U_j among the multiple processors U_1~U_N can realize communication and interconnection with each other based on the port cascade transmission link between the two. Thus, there is a port cascade transmission link passing through the network switching device SW between each processor U_i among the multiple processors U_1~U_N and any other processor U_j, and each processor U_i among the multiple processors U_1~U_N can communicate and interconnect with any other processor U_j among the multiple processors U_1~U_N through the network switching device SW. That is, the port cascade transmission link between any one processor U_i among the multiple processors U_1~U_N and other processors U_j based on port switching and forwarding of the network switching device SW may include: a first port serial link between the chip communication port Pu_i of the processor U_i and the first network switching port Ps_i of the network switching device SW, a second port serial link between the second network switching port Ps_j of the network switching device SW and other chip communication ports Pu_j of other processors U_j, and a port switching link between the first network switching port Ps_i and the second network switching port Ps_j for implementing port switching and forwarding inside the network switching device SW.

[0049] Figure 3 This is a schematic diagram of the extended structure of the communication interconnection between multiple processors in the embodiment of the present application. Figure 3 In the embodiment of the present application, for any processor U_i among the multiple processors U_1~U_N, the network switching device SW may have multiple second network switching ports Ps_j respectively connected to multiple different other processors U_j, and the chip communication port Pu_i of the processor U_i can realize communication interconnection between the processor U_i and multiple different other processors U_j through the network switching device SW. For example, the embodiment of the present application takes i as 25 and j as 8 and 16 as an example to illustrate an exemplary diagram of the communication interconnection between a processor U_i and multiple different other processors U_j.

[0050] Exemplarily, in an embodiment of the present application, the port cascade transmission link between the processor U_i and each other processor U_j that realizes communication interconnection through the network switching device SW can physically multiplex the first port serial link between the chip communication port Pu_i of the processor U_i and the first network switching port Ps_i of the network switching device SW, that is, the port cascade transmission link between the processor U_i and each other processor U_j that realizes communication interconnection includes the first port serial link between the chip communication port Pu_i of the processor U_i and the first network switching port Ps_i of the network switching device SW; and, the port switching link and the second port serial link in the port cascade transmission link between the processor U_i and multiple different other processors U_j that realize communication interconnection through the network switching device SW are different from each other, that is, the port switching link and the second port serial link in the port cascade transmission link between the processor U_i and multiple different other processors U_j that realize communication interconnection through the network switching device SW are respectively located between the first network switching port Ps_i and different second network switching ports Ps_j, and between different second network switching ports Ps_ Between j and other chip communication ports Pu_ j of different other processors U_ j.

[0051] It is understandable that in the embodiments of the present application Figure 3 The above description is intended to express: Any processor U_i among the multiple processors U_1~U_N can realize communication interconnection with at least one other processor U_j through the network switching device SW; and The port cascade transmission link for realizing communication interconnection between any processor U_i among the multiple processors U_1~U_N and any other processor U_j includes a first port serial link between the chip communication port Pu_i of the processor U_i and the first network switching port Ps_i of the network switching device SW.

[0052] Figure 4 Schematic diagram of the principle of data communication between multiple processors in the embodiment of the present application. Figure 4In an embodiment of the present application, the chip communication port Pu_i of the processor U_i can realize the communication interconnection between the processor U_i and other processors U_j through the network switching device SW, and the communication interconnection between the processor U_i and any other processor U_j can be used for data communication between the processor U_i and the other processor U_j. The communication interconnection between the processor U_i and any other processor U_j may include a port cascade transmission link between the processor U_i and the other processor U_j based on port switching forwarding of the network switching device SW, and the data communication between the processor U_i and the other processor U_j may include stream transmission of multiple types of interactive data through the port cascade transmission link (for example, Ethernet stream transmission).

[0053] Exemplarily, in an embodiment of the present application, data communication between any processor U_i among multiple processors U_1~U_N and any other processor U_j can be used to realize multi-processor computing power fusion of the processor U_i and at least one other processor U_j. For example, multi-processor computing power fusion can be suitable for application scenarios with high computing power requirements such as large model training.

[0054] Exemplarily, in an embodiment of the present application, the processor U_i and other processors U_j among the multiple processors U_1~U_N may include a chip processing core, and the data communication between the processor U_i and other processors U_j may be generated by the chip processing core of the processor U_i and processed by the chip processing cores of other processors U_j, or generated by the chip processing cores of other processors U_j and processed by the chip processing core of the processor U_i. For example, the chip processing core may include a DMA (Direct Memory Access) module, and the initiation and processing of the interactive data by the chip processing core may be performed by the DMA module.

[0055] Exemplarily, in an embodiment of the present application, multiple types of interactive data may include: a write request for writing write data to a specified address, an atomic request for performing an atomic operation on a specified address, a read request for reading data from a specified address, and a read response for returning read data successfully obtained from the specified address.

[0056] Exemplarily, in an embodiment of the present application, multiple processors U_1~U_N may include respective port driver circuits MP_1~MP_N. The port driver circuit MP_i of any processor U_i among the multiple processors U_1~U_N may be used to: create multiple groups of QP transceiver channels based on RDMA (such as Figure 4 As shown by the dotted arrows in the figure, multiple groups of QP transceiver channels can be carried in the same port cascade transmission link between the processor U_i and any other processor U_j. There is a preset correspondence between the multiple groups of QP transceiver channels and multiple types of interactive data. In addition, multiple types of interactive data can be independently streamed through the multiple groups of QP transceiver channels based on the correspondence between the multiple types and the multiple groups of QP transceiver channels. Such stream transmission can be referred to as classified stream transmission in the embodiments of the present application.

[0057] Exemplarily, in an embodiment of the present application, a plurality of groups of QP transceiver channels corresponding to multiple types of interactive data created by negotiation between the port driving circuit MP_i of the processor U_i and other port driving circuits MP_j of other processors U_j may be located between the chip communication port Pu_i of the processor U_i and other chip communication ports Pu_j of other processors U_j, and the plurality of groups of QP transceiver channels may include: a first channel segment of a first port serial link carried between the chip communication port Pu_i of the processor U_i and other chip communication ports Pu_j of other processors U_j, and a second channel segment of a second port serial link carried between the chip communication port Pu_j of the other processor U_j and the second network switching port Ps_j of the network switching device SW. In this case, multiple groups of QP transceiver channels are respectively carried on two sections (i.e., the first channel section and the second channel end) of the first port serial link and the second port serial link, and multiple groups of switching channels between two network switching ports (i.e., the first network switching port Ps_i and the second network switching port Ps_j) can be bridged through the network switching device SW, thereby realizing the stream transmission of multiple types of interactive data between the processor U_i and the other processor U_j through the multiple groups of QP transceiver channels.

[0058] For example, in an embodiment of the present application, different groups of QP transceiver channels of multiple groups of QP transceiver channels carried in the same port cascade transmission link between processor U_i and any other processor U_j can occupy different link bandwidth resources in each segment of the port serial link (first port serial link or port switching link or second port serial link). Thus, it is possible to support multiple types of interactive data to be independently concurrently streamed in each segment of the port serial link and the port switching link.

[0059] Exemplarily, in an embodiment of the present application, the chip processing core of processor U_i and the port driver circuit MP_i, as well as the chip processing cores of other processors U_j and the port driver circuit MP_j can be connected through an on-chip bus, and the on-chip bus can be distributed in the NOC (Network on Chip) of the chip processing core, so that each core module in the chip processing core, such as a DMA module, can be connected to the on-chip bus.

[0060] Exemplarily, in an embodiment of the present application, the on-chip bus bearer may include multiple bus logic channels, and the multiple bus logic channels may be used to respectively implement on-chip transmission of multiple types of interactive data in processor U_i or other processors U_j. In this embodiment, the on-chip transmission using multiple bus logic channels may be referred to as classified on-chip transmission.

[0061] Exemplarily, in an embodiment of the present application, if multiple types of interactive data include write requests, atomic requests, read requests, and read responses, then the multiple bus logical channels of the on-chip bus may include: a first bus logical channel corresponding to write requests and atomic requests, a second bus logical channel corresponding to read requests, and a third bus logical channel corresponding to read responses.

[0062] Exemplarily, in an embodiment of the present application, the on-chip bus of processor U_i or other processor U_j may include any AMBA (Advanced Microcontroller Bus Architecture) bus such as APB (Advanced Peripheral Bus), AHB (Advanced High-performance Bus), or AXI (Advanced eXtensible Interface) bus. Preferably, in an embodiment of the present application, the on-chip bus may include an AXI bus, in which case the first bus logic channel may include: at least one of an AW channel and a W channel of the AXI bus for on-chip transmission of write requests and atomic requests, the second bus logic channel includes an AR channel for on-chip transmission of read requests by the AXI bus, and the third bus logic channel may include an R channel of the AXI bus for on-chip transmission of read responses.

[0063] Exemplarily, in an embodiment of the present application, the correspondence between multiple groups of QP transceiver channels (i.e., two segments carried on the first port serial link and the second port serial link, respectively) between processor U_i and any other processor U_j and multiple types of interactive data, as well as the correspondence between multiple groups of switching channels in the network switching device SW and multiple types of interactive data, can be matched with the correspondence between multiple bus logical channels and multiple types, so that the transmission connection between the stream transmission and on-chip transmission of multiple types of interactive data can be independent of each other.

[0064] Exemplarily, in an embodiment of the present application, in the QP transceiver channel (including two sections respectively carried on the first port serial link or the second port serial link) carried in the same port cascade transmission link between the processor U_i and any other processor U_j, each group of QP transceiver channels corresponding to each type may include a QP sending channel and a QP receiving channel. Among them, the QP sending channel of the processor U_i can be regarded as a QP receiving channel for the other processor U_j at the opposite end; similarly, the QP receiving channel of the processor U_i can be regarded as a QP sending channel for the other processor U_j at the opposite end.

[0065] Moreover, among the multiple groups of switching channels of the port switching link carried between any two network switching ports (e.g., the first network switching port Ps_i and the second network switching port Ps_j) in the network switching device SW, each group of switching channels corresponding to each type may include a first switching channel and a second switching channel in opposite directions. Thus, the multiple groups of QP transceiver channels between the processor U_i and any other processor U_j may include multiple QP sending channels and multiple QP receiving channels corresponding to multiple types of interactive data; and the multiple groups of switching channels of the port switching link carried between any two network switching ports (e.g., the first network switching port Ps_i and the second network switching port Ps_j) in the network switching device SW may include multiple first switching channels and multiple second switching channels corresponding to multiple types of interactive data. Thus, bidirectional stream transmission of multiple types of interactive data can be realized.

[0066] Exemplarily, in an embodiment of the present application, if multiple types of interactive data include write requests, atomic requests, read requests, and read responses, then multiple QP sending channels in multiple groups of QP transceiver channels between processor U_i and any other processor U_j may include: a write request QP sending channel corresponding to write requests and atomic requests and connected to the first bus logical channel, a read request QP sending channel corresponding to read requests and connected to the second bus logical channel, and a read response QP sending channel corresponding to read responses and connected to the third bus logical channel.

[0067] Exemplarily, in an embodiment of the present application, if multiple types of interactive data include write requests, atomic requests, read requests, and read responses, then multiple QP receiving channels in multiple groups of QP transceiver channels between processor U_i and any other processor U_j may include: a write request QP receiving channel corresponding to write requests and atomic requests and connected to the first bus logical channel, a read request QP receiving channel corresponding to read requests and connected to the second bus logical channel, and a read response QP receiving channel corresponding to read responses and connected to the third bus logical channel.

[0068] Exemplarily, in an embodiment of the present application, if the multiple types of interactive data include a write request, an atomic request read request, and a read response, then the multiple first switching channels in the multiple groups of switching channels between the first network switching port Ps_i and the second network switching port Ps_j inside the network switching device SW may include: A first write request exchange channel corresponding to write requests and atomic requests, and the first write request exchange channel is used to cascade two channel segments of a write request QP sending channel for sending write requests and atomic requests from processor U_i to other processors U_j. As mentioned above, the write request QP sending channel for sending write requests and atomic requests from processor U_i to other processors U_j is a write request QP receiving channel for receiving write requests and atomic requests from processor U_i for other processors U_j at the opposite end. A first read request exchange channel corresponding to a read request, and the first read request exchange channel is used to cascade two channel segments of a read request QP sending channel for sending a read request from the processor U_i to other processors U_j. As mentioned above, the read request QP sending channel for sending a read request from the processor U_i to other processors U_j is a read request QP receiving channel for receiving a read request from the processor U_i for other processors U_j at the opposite end; and The first read response exchange channel corresponds to the read response, and the first read response exchange channel is used to cascade the two channel segments of the read response QP sending channel for sending a read response from the processor U_i to other processors U_j. As mentioned above, the read response QP sending channel for sending a read response from the processor U_i to other processors U_j belongs to the read response QP receiving channel for receiving the read response from the processor U_i for the other processors U_j at the opposite end.

[0069] Exemplarily, in an embodiment of the present application, if multiple types of interactive data include write requests, atomic requests, read requests, and read responses, then the multiple second switching channels in the multiple groups of switching channels between the first network switching port Ps_i and the second network switching port Ps_j inside the network switching device SW may include: a second write request switching channel that is opposite to the first write request switching channel, a second read request switching channel that is opposite to the first read request switching channel, and a second read response switching channel that is opposite to the first read response switching channel.

[0070] Exemplarily, in an embodiment of the present application, processor U_i (for example, the port driver circuit MP_i of the processor U_i) can be used to maintain multiple groups of first on-chip transceiver cache queues connected to the on-chip bus of the processor U_i, other processors U_j (for example, the port driver circuit MP_j of other processors U_j) can be used to maintain multiple groups of second transceiver cache queues connected to the on-chip bus of other processors U_j, the network switching device SW can maintain multiple groups of first switching transceiver cache queues for the first network switching port Ps_i, and the network switching device SW can maintain multiple groups of second switching transceiver cache queues for the second network switching port Ps_j.

[0071] Exemplarily, in an embodiment of the present application, multiple groups of first on-chip transceiver cache queues of processor U_i, multiple groups of second transceiver cache queues of other processors U_j, and multiple groups of first switching transceiver cache queues and multiple groups of second switching transceiver cache queues of the network switching device SW can all have a corresponding relationship with multiple types of interactive data, that is, multiple groups of first on-chip transceiver cache queues and multiple groups of first switching transceiver cache queues correspond one to one.

[0072] Exemplarily, in an embodiment of the present application, multiple groups of QP transceiver channels between processor U_i and any other processor U_j (i.e., multiple groups of QP transceiver channels between chip communication port Pu_i and other chip communication ports Pu_j) can be created between multiple groups of first on-chip transceiver cache queues of processor U_i and multiple groups of second transceiver cache queues of other processors U_j, so that multiple groups of QP transceiver channels can be connected to the on-chip buses of processor U_i and other processor U_j respectively through multiple groups of first on-chip transceiver cache queues of processor U_i and multiple groups of second transceiver cache queues of other processors U_j.

[0073] Exemplarily, in an embodiment of the present application, multiple groups of switching channels between the first network switching port Ps_i and the second network switching port Ps_j of the network switching device SW can be used to implement data exchange between multiple groups of first switching transceiver cache queues maintained by the network switching device SW for the first network switching port Ps_i and multiple groups of second switching transceiver cache queues maintained for the second network switching port Ps_j. Thus, multiple groups of QP transceiver channels between the processor U_i and any other processor U_j (i.e., multiple groups of QP transceiver channels between the chip communication port Pu_i and other chip communication ports Pu_j) can be relay cache nodes using the multiple groups of first switching transceiver cache queues maintained by the network switching device SW for the first network switching port Ps_i and the multiple groups of second switching transceiver cache queues maintained for the first network switching port Ps_j as described above.

[0074] Exemplarily, in an embodiment of the present application, if the multiple groups of QP transceiver channels between the processor U_i and any other processor U_j include multiple QP sending channels and multiple QP receiving channels, and the multiple groups of switching channels of the port switching link carried by the first network switching port Ps_i and the second network switching port Ps_j in the network switching device SW include multiple first switching channels and multiple second switching channels, then each group of first on-chip transceiver cache queues in the multiple groups of first on-chip transceiver cache queues, each group of first switching transceiver cache queues in the multiple groups of first switching transceiver cache queues, each group of second switching transceiver cache queues in the multiple groups of second switching transceiver cache queues, and each group of second on-chip cache queues in the multiple groups of second on-chip cache queues can include a sending cache queue and a receiving cache queue, that is, the multiple groups of first on-chip transceiver cache queues, the multiple groups of first switching transceiver cache queues, the multiple groups of second switching transceiver cache queues, and the multiple groups of second on-chip cache queues can include multiple sending cache queues and multiple receiving cache queues.

[0075] Exemplarily, in an embodiment of the present application, among the multiple groups of QP transceiver channels between processor U_i and any other processor U_j (i.e., the multiple groups of QP transceiver channels between chip communication port Pu_i and other chip communication ports Pu_j): the multiple QP sending channels used by processor U_i to send interactive data to any other processor U_j (i.e., the multiple QP receiving channels used by any other processor U_j to receive interactive data from processor U_i) can be created between the multiple sending cache queues in the multiple groups of first on-chip transceiver cache queues and the multiple receiving cache queues in the multiple groups of second on-chip transceiver cache queues, and the multiple receiving cache queues in the multiple groups of first exchange transceiver cache queues and the multiple sending cache queues in the multiple groups of second exchange transceiver cache queues are used as relay cache nodes, that is, the interactive data is transmitted from the multiple receiving cache queues in the first exchange transceiver cache queue to the multiple sending cache queues in the multiple groups of second exchange transceiver cache queues.

[0076] Exemplarily, in an embodiment of the present application, among the multiple groups of QP transceiver channels of processor U_i (i.e., the multiple groups of QP transceiver channels between chip communication port Pu_i and other chip communication ports Pu_j): the multiple QP receiving channels used for processor U_i to receive interactive data from any other processor U_j (the multiple QP sending channels used for any other processor U_j to send interactive data to processor U_i) can be created between the multiple receiving cache queues in the multiple groups of first on-chip transceiver cache queues and the multiple sending cache queues in the multiple groups of second on-chip transceiver cache queues, and the multiple sending cache queues in the multiple groups of first switching transceiver cache queues and the multiple receiving cache queues in the multiple groups of second switching transceiver cache queues are used as relay cache nodes, that is, the interactive data is sent from the multiple receiving cache queues in the second switching transceiver cache queues to the multiple sending cache queues in the multiple groups of first switching transceiver cache queues.

[0077] Exemplarily, in an embodiment of the present application, in the multiple groups of switching channels between the first network switching port Ps_i and the second network switching port Ps_j of the network switching device SW, the multiple first switching channels can be located between the multiple receiving cache queues in the multiple groups of first switching transceiver cache queues and the multiple sending cache queues in the multiple groups of second switching transceiver cache queues, and the multiple second switching channels can be located between the multiple sending cache queues in the multiple groups of first switching transceiver cache queues and the multiple receiving cache queues in the multiple groups of second switching transceiver cache queues, and the exchange direction of the interactive data between the first network switching port Ps_i and the second network switching port Ps_j of the network switching device SW by the multiple first switching channels and the multiple second switching channels are set according to the following principle: between the multiple groups of first switching transceiver cache queues and the multiple groups of second switching transceiver cache queues, the exchange forwarding from the receiving cache queue to the sending cache queue is adopted.

[0078] Exemplarily, in an embodiment of the present application, if the multiple groups of QP transceiver channels between the processor U_i and any other processor U_j include a write request QP sending channel and a write request QP receiving channel (i.e., a group of write request QP transceiver channels), a read request QP sending channel and a read request QP receiving channel (i.e., a group of read request QP transceiver channels), and a read response QP sending channel and a read response QP receiving channel (i.e., a group of read response QP transceiver channels), and the multiple groups of switching channels carried between the first network switch port Ps_i and the second network switch port Ps_j include a first write request switching channel and a second write request switching channel (i.e., a group of write request switching channels), a first read request switching channel and a second read request switching channel (i.e., a group of read request switching channels), and a first read response switching channel and a second read response switching channel (i.e., a group of read request switching channels), then the multiple groups of first on-chip transceiver cache queues of the processor U_i, the multiple groups of first switching transceiver cache queues maintained by the network switch device SW for the first network switch port Ps_i, and the network switch device SW for the second network switch port Ps_i. The multiple groups of second exchange transceiver cache queues maintained by processor U_j, as well as the multiple groups of second on-chip transceiver cache queues of other processors U_j, can include a group of send cache queues Wt and receive cache queues Wr corresponding to write requests and atomic requests, a group of send queues Rt and receive queues Rr corresponding to read requests, and a group of send cache queues Ct and receive cache queues Cr corresponding to read responses.

[0079] Exemplarily, in an embodiment of the present application, among the multiple groups of QP transceiver channels between the processor U_i and other processors U_j, a write request QP sending channel for the processor U_i to send a write request and an atomic request to any other processor U_j (i.e., a write request QP receiving channel for the other processor U_j on the opposite end to receive interactive data from the processor U_i) can be connected to the first bus logic channel (e.g., AW or W channel of AXI) in the processor U_i and the other processor U_j at both ends, and a sending cache queue Wt corresponding to the write request and the atomic request in the first on-chip transceiver cache queue group of the processor U_i and a receiving cache queue Wr corresponding to the write request and the atomic request in the second on-chip transceiver cache queue group of the other processor U_j can be created. Thus, from the perspective of the processor U_i, the stream transmission process of the write request and the atomic request in the write request QP sending channel of the processor U_i (i.e., the write request QP receiving channel of the other processor U_j on the opposite end) can be exemplarily represented as "Wt—>Wr".

[0080] Exemplarily, in an embodiment of the present application, the write request QP sending channel of processor U_i (i.e., the write request QP receiving channel of other processors U_j at the opposite end) can also use the receiving cache queue Wr corresponding to the write request and atomic request in the first switching transceiver cache queue group of the network switching device SW mentioned above, and the sending cache queue Wt corresponding to the write request and atomic request in the second switching transceiver cache queue group as relay cache nodes, and the stream transmission process of the write request and atomic request in the write request QP sending channel of processor U_i (i.e., the write request QP receiving channel of other processors U_j at the opposite end) can also include data exchange from the corresponding receiving cache queue Wr to the sending cache queue Wt in the network switching device SW, that is, from the perspective of processor U_i, the stream transmission process of the write request and atomic request in the write request QP sending channel of processor U_i (i.e., the write request QP receiving channel of other processors U_j at the opposite end) can be further expressed as "Wt—>Wr-switch-Wt—>Wr".

[0081] Exemplarily, in an embodiment of the present application, among the multiple groups of QP transceiver channels between the processor U_i and other processors U_j, a write request QP sending channel for the processor U_i to receive write requests and atomic requests from any other processor U_j (i.e., a write request QP sending channel for the other processor U_j on the opposite end to receive interactive data from the processor U_i) can be connected to the first bus logic channel (e.g., AW or W channel of AXI) in the processor U_i and the other processor U_j at both ends, and a receiving cache queue Wr corresponding to the write request and atomic request in the first on-chip transceiver cache queue group of the processor U_i and a sending cache queue Wt corresponding to the write request and atomic request in the second on-chip transceiver cache queue group of the other processor U_j can be created. Thus, from the perspective of the processor U_i, the stream transmission process of the write request and atomic request in the write request QP receiving channel of the processor U_i (i.e., the write request QP sending channel of the other processor U_j on the opposite end) can be exemplarily represented as "Wr<—Wt".

[0082] Exemplarily, in an embodiment of the present application, the write request QP receiving channel of processor U_i (i.e., the write request QP sending channel of other processors U_j at the opposite end) in the network switching device SW can utilize the receiving cache queue Wr corresponding to the write request and the atomic request in the second switching transceiver cache queue group, and the sending cache queue Wt corresponding to the write request and the atomic request in the second switching transceiver cache queue group to realize data exchange, that is, from the perspective of processor U_i, the stream transmission process in the write request QP receiving channel of processor U_i (i.e., the write request QP sending channel of other processors U_j at the opposite end) can be further expressed as "Wr<—Wt - exchange - Wr<—Wt".

[0083] Exemplarily, in an embodiment of the present application, among the multiple groups of QP transceiver channels between the processor U_i and other processors U_j, a read request QP sending channel for the processor U_i to send a read request to any other processor U_j (i.e., a read request QP receiving channel for the other processor U_j on the opposite end to receive a read request from the processor U_i) can be connected to the second bus logic channel (e.g., the AR channel of AXI) in the processor U_i and the other processor U_j at both ends, respectively, and a sending cache queue Rt corresponding to the read request in the first on-chip transceiver cache queue group of the processor U_i and a receiving cache queue Rr corresponding to the read request in the second on-chip transceiver cache queue group of the other processor U_j can be created. Thus, from the perspective of the processor U_i, the flow transmission process of the read request in the read request QP sending channel of the processor U_i (i.e., the read request QP receiving channel of the other processor U_j on the opposite end) can be expressed as "Rt—>Rr".

[0084] Exemplarily, in an embodiment of the present application, the read request QP sending channel of processor U_i (i.e., the read request QP receiving channel of other processors U_j at the opposite end) can also use the receiving cache queue Rr corresponding to the read request in the first switching transceiver cache queue group of the network switching device SW mentioned above, and the sending cache queue Rt corresponding to the read request in the second switching transceiver cache queue group as relay cache nodes, and the stream transmission process of the read request in the read request QP sending channel of processor U_i (i.e., the read request QP receiving channel of other processors U_j at the opposite end) can also include data exchange from the receiving cache queue Rr corresponding to the read request to the sending cache queue Rt corresponding to the read request in the network switching device SW, that is, from the perspective of processor U_i, the stream transmission process of the read request in the read request QP sending channel of processor U_i (i.e., the read request QP receiving channel of other processors U_j at the opposite end) can also be further expressed as "Rt—>Rr-exchange-Rt—>Rr".

[0085] Exemplarily, in an embodiment of the present application, among the multiple groups of QP transceiver channels between the processor U_i and other processors U_j, a read request QP receiving channel for the processor U_i to receive a read request from any other processor U_j (i.e., a read request QP receiving channel for the other processor U_j on the opposite end to send a read request to the processor U_i) can be connected to the second bus logic channel (e.g., the AR channel of AXI) in the processor U_i and the other processor U_j at both ends, respectively, and a receiving cache queue Rr corresponding to the read request in the first on-chip transceiver cache queue group of the processor U_i and a sending cache queue Rt corresponding to the read request in the second on-chip transceiver cache queue group of the other processor U_j can be created. Thus, from the perspective of the processor U_i, the stream transmission process of the read request in the read request QP receiving channel of the processor U_i (i.e., the read request QP sending channel of the other processor U_j on the opposite end) can be exemplarily represented as "Rr<—Rt".

[0086] Exemplarily, in an embodiment of the present application, the read request QP receiving channel of the processor U_i (i.e., the read request QP sending channel of other processors U_j on the opposite end) can also use the sending cache queue Rt corresponding to the read request in the first switching transceiver cache queue group of the network switching device SW mentioned above, and the receiving cache queue Rr corresponding to the read request in the second switching transceiver cache queue group as relay cache nodes, and the stream transmission process of the read request in the read request QP receiving channel of the processor U_i (i.e., the read request QP sending channel of other processors U_j on the opposite end) can also include data exchange from the receiving cache queue Rr corresponding to the read request to the sending cache queue Rt corresponding to the read request in the network switching device SW, that is, from the perspective of the processor U_i, the stream transmission process of the read request in the read request QP sending channel of the processor U_i (i.e., the read request QP receiving channel of other processors U_j on the opposite end) can also be further expressed as "Rr<—Rt - exchange - Rr<— Rt".

[0087] Exemplarily, in an embodiment of the present application, among the multiple groups of QP transceiver channels between the processor U_i and other processors U_j, a read response QP sending channel for the processor U_i to send a read response to any other processor U_j (i.e., a read response QP receiving channel for the other processor U_j at the opposite end to receive a read response from the processor U_i) can be connected to the third bus logic channel (e.g., R channel of AXI) in the processor U_i and the other processor U_j at both ends, respectively, and a sending cache queue Ct corresponding to the read response in the first on-chip transceiver cache queue group of the processor U_i and a receiving cache queue Cr corresponding to the read response in the second on-chip transceiver cache queue group of the other processor U_j can be created. Thus, from the perspective of the processor U_i, the stream transmission process of the read response in the read response QP sending channel of the processor U_i (i.e., the read response QP receiving channel of the other processor U_j at the opposite end) can be expressed as "Ct—>Cr".

[0088] Exemplarily, in an embodiment of the present application, the read response QP sending channel of the processor U_i (i.e., the read response QP receiving channel of other processors U_j at the opposite end) can also use the receiving cache queue Cr corresponding to the read response in the first switching transceiver cache queue group of the network switching device SW mentioned above, and the sending cache queue Ct corresponding to the read response in the second switching transceiver cache queue group as relay cache nodes, and the stream transmission process of the read response in the read response QP sending channel of the processor U_i (i.e., the read response QP receiving channel of other processors U_j at the opposite end) can also include data exchange from the receiving cache queue Cr corresponding to the read response to the sending cache queue Ct corresponding to the read response in the network switching device SW, that is, from the perspective of the processor U_i, the stream transmission process of the read response in the read response QP sending channel of the processor U_i (i.e., the read response QP receiving channel of other processors U_j at the opposite end) can also be further expressed as "Ct—>Cr-exchange-Ct—>Cr".

[0089] Exemplarily, in an embodiment of the present application, among the multiple groups of QP transceiver channels between the processor U_i and other processors U_j, a read response QP receiving channel for the processor U_i to receive a read response from any other processor U_j (i.e., a read response QP receiving channel for the other processor U_j on the opposite end to send a read response to the processor U_i) can be connected to the third bus logic channel (e.g., R channel of AXI) in the processor U_i and the other processor U_j at both ends, respectively, and a receiving cache queue Cr corresponding to the read response in the first on-chip transceiver cache queue group of the processor U_i and a sending cache queue Ct corresponding to the read response in the second on-chip transceiver cache queue group of the other processor U_j can be created. Thus, from the perspective of the processor U_i, the stream transmission process of the read response in the read response QP receiving channel of the processor U_i (i.e., the read response QP sending channel of the other processor U_j on the opposite end) can be exemplarily represented as "Cr<—Ct".

[0090] Exemplarily, in an embodiment of the present application, the read response QP receiving channel of the processor U_i (i.e., the read response QP sending channel of other processors U_j at the opposite end) can also use the sending cache queue Ct corresponding to the read response in the first switching transceiver cache queue group of the network switching device SW mentioned above, and the receiving cache queue Cr corresponding to the read response in the second switching transceiver cache queue group as relay cache nodes, and the stream transmission process of the read response in the read response QP receiving channel of the processor U_i (i.e., the read response QP sending channel of other processors U_j at the opposite end) can also include data exchange from the receiving cache queue Cr corresponding to the read response to the sending cache queue Ct of the corresponding read response in the network switching device SW, that is, from the perspective of the processor U_i, the stream transmission process of the read response in the read response QP sending channel of the processor U_i (i.e., the read response QP receiving channel of other processors U_j at the opposite end) can also be further expressed as "Cr<—Ct - exchange - Cr<— Ct".

[0091] Exemplarily, in an embodiment of the present application, each sending cache queue in multiple groups of first on-chip sending and receiving cache queues of processor U_i (for example, the sending cache queue Wt corresponding to write requests and atomic requests, or the sending cache queue Rt corresponding to read requests, or the sending cache queue Ct corresponding to read responses) can be used to cache the corresponding type of interactive data waiting to be transmitted from the corresponding QP sending channel to other processors U_j; accordingly, each receiving cache queue in multiple groups of second on-chip sending and receiving queues of other processors U_j (for example, the receiving cache queue Wr corresponding to write requests and atomic requests, or the receiving cache queue Rr corresponding to read requests, or the receiving cache queue Cr corresponding to read responses) can be used to cache the corresponding type of interactive data from processor U_i successfully received from the corresponding QP sending channel.

[0092] Exemplarily, in an embodiment of the present application, each receive cache queue in multiple groups of first on-chip transceiver cache queues of processor U_i (for example, the receive cache queue Wr corresponding to write requests and atomic requests, or the receive cache queue Rr corresponding to read requests, or the receive cache queue Cr corresponding to read responses) can be used to cache the corresponding type of interactive data successfully received from the corresponding QP receive channel from other processors U_j; accordingly, each receive cache queue in multiple groups of second on-chip transceiver queues of other processors U_j (for example, the send cache queue Wt corresponding to write requests and atomic requests, or the send cache queue Rt corresponding to read requests, or the send cache queue Ct corresponding to read responses) can be used to cache the corresponding type of interactive data waiting to be transmitted from the corresponding QP send channel to processor U_i.

[0093] Exemplarily, in an embodiment of the present application, the forwarding direction of the port switching forwarding between the first network switching port Ps_i and the second network switching port Ps_j of the network switching device may include: A first forwarding direction from any receiving cache queue in the first exchange receiving and transmitting cache queue (e.g., a sending cache queue Wt corresponding to write requests and atomic requests, or a sending cache queue Rt corresponding to read requests, or a sending cache queue Ct corresponding to read responses) to a corresponding sending cache queue in the second exchange receiving and transmitting cache queue (e.g., a receiving cache queue Wr corresponding to write requests and atomic requests, or a receiving cache queue Rr corresponding to read requests, or a receiving cache queue Cr corresponding to read responses), that is, the first forwarding direction is the same as the sending direction of the processor U_ j and the receiving direction of other processors U_ j; and The second forwarding direction from the receiving cache queue in the second switching transceiver cache queue (for example, the receiving cache queue Wr corresponding to write requests and atomic requests, or the receiving cache queue Rr corresponding to read requests, or the receiving cache queue Cr corresponding to read responses) to the sending cache queue in the first switching transceiver cache queue (for example, the sending cache queue Wt corresponding to write requests and atomic requests, or the sending cache queue Rt corresponding to read requests, or the sending cache queue Ct corresponding to read responses), that is, the first forwarding direction is the same as the receiving direction of processor U_ j and the sending direction of other processors U_ j.

[0094] Thus, in an embodiment of the present application, for the stream transmission from any processor U_i to any other processor U_j, it can sequentially include the segmented stream transmission from the processor U_i in the sending direction using multiple QP sending channels to the network switching device SW, the segmented stream transmission inside the network switching device SW using multiple first switching channels in the first forwarding direction, and the segmented stream transmission received by the other processor U_j from the network switching device SW in the receiving direction using multiple QP sending channels; conversely, for the stream transmission received from any processor U_i from any other processor U_j, it can sequentially include the segmented stream transmission sent by the other processor U_j in the sending direction using multiple QP sending channels to the network switching device SW, the segmented stream transmission inside the network switching device SW using multiple second switching channels in the second forwarding direction, and the segmented stream transmission received by the processor U_i from the network switching device SW in the receiving direction.

[0095] Based on the above embodiments of the present application, the processor U_i among the multiple processors U_1~U_N and any other processor U_j realize SW communication interconnection through the network switching device, and can realize data communication by using multiple groups of QP transceiver channels carried on the same port cascade transmission link. Among them, there is a corresponding relationship between the multiple groups of QP transceiver channels and the multiple types of interactive data involved in the data communication, and the multiple types of interactive data can be respectively transmitted through the corresponding QP sending channels and QP receiving channels in the multiple groups of QP transceiver channels, and can concurrently realize independent stream transmission.

[0096] If processor U_i among multiple processors U_1~U_N and any other processor U_j realize stream transmission of multiple types of interactive data through a serial mode of time-sharing multiplexing port cascade transmission link, and when the receiver of the interactive data in processor U_i and other processors U_j processes a certain type of interactive data, a processing interrupt occurs due to the need for the processing result of other types of interactive data, then once the processing interruption causes transmission congestion in the port cascade transmission link between processor U_i and other processors U_j, other types of interactive data that can resolve the processing interruption will not be able to be transmitted to the receiver due to the transmission congestion, thereby forming a transmission deadlock between processor U_i and other processors U_j.

[0097] Figure 5 A diagram of a transmission deadlock in a comparative example. Figure 5 , assuming that processor U_i among multiple processors U_1~U_N and any other processor U_j realize stream transmission of multiple types of interactive data through the serial mode of time-division multiplexing port cascade transmission link, and: At time T1, processor U_i sends a read request R_req to other processors U_j through the port cascade transmission link; At time T2 after time T1, other processors U_j send several write requests W_req to processor U_i through the port cascade transmission link; At time T3 after time T2, other processors U_j send a read response R_rsp corresponding to the read request R_req to processor U_i through the port cascade transmission link.

[0098] Therefore, in the flow transmission direction from other processors U_ j to processor U_i through the port cascade transmission link, the read response R_rsp is ranked after several write requests W_req. If the result of processor U_i's processing of the write request W_req of other processors U_ j needs to wait for the read response R_rsp of other processors U_ j, then the waiting will cause congestion in the flow transmission direction from other processors U_ j to processor U_i, for example, congestion caused by flow control mechanisms such as PFC (Priority Flow Control) or ECN (Explicit Congestion Notification). In this case, the read response R_rsp ranked after several write requests W_req will cause the congestion to continue because it cannot reach processor U_i, and the congestion will continue to prevent the read response R_rsp from reaching processor U_i, so that a transmission deadlock occurs in the flow transmission direction from other processors U_ j to processor U_i.

[0099] Figure 6 This is a schematic diagram of the effect of avoiding transmission deadlock in data communication between multiple processors in an embodiment of the present application. Figure 6 Based on the embodiments of the present application, in the flow transmission direction from other processors U_j to processor U_i through the port cascade transmission link, the read response R_rsp can be independently and concurrently transmitted with several write requests W_req through multiple groups of QP transceiver channels. Therefore, even if several write requests W_req cause congestion, the read response R_rsp can also reach processor U_i smoothly, so that the processor U_i (that is, the chip processing core of the processor U_i) starts processing several write requests W_req after successfully processing the read response R_rsp received from other processors U_j, thereby relieving the congestion of several write requests W_req.

[0100] Therefore, compared with the serial method of time-division multiplexing port cascade transmission links for stream transmission of multiple types of interactive data, the embodiment of the present application utilizes multiple groups of QP transceiver channels to concurrently realize mutually independent stream transmission of multiple types of interactive data, which can reduce the risk of transmission deadlock in data communication between any two of the multiple processors U_1~U_N.

[0101] For example, in an embodiment of the present application, in order to further reduce the risk of transmission deadlock, the transmission priority of a group of read response QP transceiver channels in the multiple groups of QP transceiver channels may preferably be higher than the transmission priorities of the write request QP transceiver channel and the read request QP transceiver channel. That is, the transmission priority of the read response QP sending channel is preferably higher than the transmission priority of the write request QP sending channel and the read request QP sending channel; and the transmission priority of the read response QP receiving channel is preferably higher than the transmission priority of the write request QP receiving channel and the read request QP receiving channel.

[0102] Figure 7 Schematic diagram of an exemplary internal structure of a processor in an embodiment of the present application. Figure 7 In an embodiment of the present application, the port driving circuit MP_i of any processor U_i may include a port sending circuit TX_i and a port receiving circuit RX_i that are physically connected to the chip communication port Pu_i or physically integrated in the chip communication port Pu_i. The port driving circuit MP_i of the processor U_i also includes a bus bridge Brg_i for being physically connected to the NOC_i of the chip processing core of the processor U_i. Multiple sending cache queues in multiple groups of first on-chip transceiver cache queues of the processor U_i (for example, the sending cache queue Wt corresponding to write requests and atomic requests, the sending queue Rt and the receiving queue Rr corresponding to read requests, and the sending cache queue Ct corresponding to read responses) are connected between the bus bridge Brg_i and the port sending circuit TX_i, and multiple receiving cache queues in multiple groups of first on-chip transceiver cache queues of the processor U_i (for example, the receiving cache queue Wr corresponding to write requests and atomic requests, the receiving queue Rr corresponding to read requests, and the receiving cache queue Cr corresponding to read responses) are connected between the bus bridge Brg_i and the port receiving circuit RX_i.

[0103] Exemplarily, in an embodiment of the present application, multiple send cache queues in multiple groups of first on-chip send and receive cache queues of the processor U_i (for example, the send cache queue Wt corresponding to write requests and atomic requests, the send queue Rt and the receive queue Rr corresponding to read requests, and the send cache queue Ct corresponding to read responses) and the port sending circuit TX_i can be connected through the sending arbiter Atrtx_i, so that multiple types of interactive data cached in multiple parallel send cache queues can be alternately sent by the port sending circuit TX_i in a multiple-type polling sending manner based on the equal-weight polling of the arbiter Atrtx_i (that is, the chance weights of multiple types of interactive data being hit by the polling are equal).

[0104] Exemplarily, in an embodiment of the present application, in the transmission direction from the chip communication port Pu_i to the network switching port Ps_i of the network switching device SW (ie, the transmission direction from the processor U_i to other processors U_j): The transmission order of the write request and the atomic request in the stream transmission realized by the write request QP sending channel “Wt—>Wr” may be the same as the transmission order of the write request and the atomic request in the intra-chip transmission realized by the first bus logical channel (e.g., at least one of the AW channel and the W channel of AXI), that is, the write request and the atomic request in the sending direction are transmitted in the write request QP sending channel “Wt—>Wr” in an order-preserving manner; The transmission order of the read request in the stream transmission implemented by the read request QP sending channel "Rt—>Rr" is the same as the transmission order of the read request in the intra-chip transmission implemented by the second bus logic channel (such as the AR channel of AXI), that is, the read request in the sending direction is transmitted in the read request QP sending channel "Rt—>Rr" in order preservation; The transmission order of the read responses in the stream transmission implemented by the read response QP sending channel "Ct—>Cr" is the same as the transmission order of the read responses in the intra-chip transmission implemented by the third bus logical channel (e.g., Ar channel of AXI), that is, the read responses in the sending direction are transmitted in the read response QP sending channel "Ct—>Cr" in an order-preserving manner; wherein each read response is generated for a previously received read request, the generation order of the read responses may not be the same as the reception order of the read requests, and the transmission order of the intra-chip transmission implemented by the read responses in the third bus logical channel (e.g., R channel of AXI) may not be consistent with the reception order of the read requests, therefore, the transmission order of the read responses in the stream transmission implemented by the read response QP sending channel may be de-associated with the reception order of the corresponding read requests; and, There is no order requirement between the stream transmissions implemented by the write request QP sending channel "Wt—>Wr", the read request QP sending channel "Rt—>Rr", and the read response QP sending channel "Ct—>Cr".

[0105] Exemplarily, in an embodiment of the present application, in the receiving direction from the network switching port Ps_i of the network switching device SW to the chip communication port Pu_i (ie, the transmission direction from other processors U_j to the processor U_i): The transmission order of the write request with the same other processor U_j as the data source in the intra-chip transmission implemented by the first bus logic channel (for example, at least one of the AW channel and the W channel of AXI) is the same as the transmission order in the stream transmission implemented by the write request QP receiving channel "Wr<—Wt", that is, the write request in the receiving direction is transmitted in the first bus logic channel (for example, at least one of the AW channel and the W channel of AXI) in order preservation; The transmission order of the atomic requests with the same other processor U_j as the data source in the intra-chip transmission implemented by the first bus logic channel (for example, at least one of the AW channel and the W channel of AXI) is de-associated with the transmission order in the stream transmission implemented by the write request QP receiving channel "Wr<—Wt", that is, because the operation addresses of different atomic requests in the processor U_i are usually different, the atomic requests in the receiving direction can be transmitted out of order in the first bus logic channel (for example, at least one of the AW channel and the W channel of AXI); The transmission order of the read requests with the same other processor U_j as the data source in the intra-chip transmission implemented in the second bus logic channel (e.g., the AR channel of AXI) is de-associated with the transmission order in the stream transmission implemented in the read request QP receiving channel "Rr<—Rt", that is, since the access addresses of different read requests in the processor U_i are usually different, the read requests in the receiving direction can be transmitted out of order in the second bus logic channel (e.g., the AR channel of AXI); For the read responses with the same other processor U_j as the data source, the transmission order in the intra-chip transmission implemented by the third bus logical channel (e.g., the R channel of AXI) is the same as the transmission order in the stream transmission implemented by the read response QP receiving channel "Cr<—Ct", that is, the read responses in the receiving direction are transmitted in the third bus logical channel (e.g., the R channel of AXI) in an order-preserving manner.

[0106] Exemplarily, in an embodiment of the present application, the on-chip bus is configured to implement on-chip transmission of interactive data with the same bus identifier in an order-preserving manner. In this case: In order to achieve order-preserving transmission of write requests in the receiving direction in the first bus logical channel (for example, at least one of the AW channel and the W channel of AXI), the bus identifier of the on-chip bus may include a first bus identifier applied to the first bus logical channel, and the port driver circuit MP_i of the processor U_i may also be used to: allocate the same first bus identifier corresponding to the data source to all write requests with the same other processor U_j as the data source, that is, allocate the first bus identifier with the data source as the granularity; In order to realize the out-of-order transmission of atomic requests in the receiving direction in the first bus logical channel (for example, at least one of the AW channel and the W channel of AXI), the bus identifier of the on-chip bus of the processor U_i may include a first exclusive identifier applied to the first bus logical channel, and the first exclusive identifier and the first bus identifier may belong to different identifier sequences (idsequence) or different identifier pools (id pool). The port driver circuit MP_i (for example, the bus bridge Brg_i) of the processor U_i can also be used to: assign different first exclusive identifiers to different atomic requests, that is, assign the first exclusive identifier with the atomic request as the granularity, and the first exclusive identifier assigned to each atomic request can be recycled in response to the successful operation of the atomic request.

[0107] Exemplarily, in an embodiment of the present application, the port driver circuit MP_i (e.g., bus bridge Brg_i) of the processor U_i may include a first identifier generator Gw, which may be located between the write request QP receiving channel "Wr<—Wt" (i.e., the receiving cache queue Wr corresponding to the write request and the atomic request in the multiple groups of first on-chip transceiver cache queues) and the first bus logic channel (e.g., at least one of the AW channel and the W channel of AXI), and the first identifier generator Gw may generate a first bus identifier allocated with the data source as the granularity for each write request, and generate a first exclusive identifier allocated with the atomic request as the granularity for each atomic request, according to the type of interactive data cached in the receiving cache queue Wr.

[0108] Exemplarily, in an embodiment of the present application, in order to realize out-of-order transmission of read requests in the receiving direction in the second bus logical channel (for example, the AR channel of AXI), the bus identifier of the processor U_i may also include a second exclusive identifier applied to the second bus logical channel, and the port driver circuit MP_i of the processor U_i (for example, the bus bridge Brg_i) may also be used to: assign different second exclusive identifiers to different read requests, that is, assign the second exclusive identifier based on the granularity of the read request, and the second exclusive identifier assigned to each read request is recycled in response to the success of the read request operation (for example, generating a read response returned corresponding to the read request in the sending direction).

[0109] Exemplarily, in an embodiment of the present application, the port driver circuit MP_i (for example, a bus bridge Brg_i) of the processor U_i may further include a second identifier generator Gr, which may be located between the read request QP receiving channel "Rr<—Rt" (that is, the receiving cache queue Rr corresponding to the read request in multiple groups of first on-chip transceiver cache queues) and the first bus logic channel (for example, the AR channel of AXI), and the second identifier generator Gr may generate a second exclusive identifier allocated with the read request as the granularity for each read request.

[0110] Exemplarily, in an embodiment of the present application, in order to realize the order-preserving transmission of the read response in the receiving direction on the third bus logical channel (for example, the R channel of AXI), the bus identifier of the intra-chip bus of the processor U_i may include a second bus identifier applied to the third bus logical channel, and the port driver circuit MP_i (for example, the bus bridge Brg_i) of the processor U_i may also be used to: query the second bus identifier stored in association with the read operation tag of the read response, and the read response may be transmitted intra-chip on the third bus logical channel using the queried second bus identifier; wherein any read response may carry the same read operation tag (tag) as the corresponding read request, and the second bus identifier is pre-assigned for the read response corresponding to the read request when the read request is sent to the same other processor U_j (that is, the data source of the read response) and is stored in association with the read operation tag used together with the read request and the corresponding read response, therefore, whenever a read response is received in response to the issued read request, the predetermined second bus identifier may be directly hit using the read operation tag (tag).

[0111] Exemplarily, in an embodiment of the present application, the port driver circuit MP_i (for example, a bus bridge Brg_i) of the processor U_i may further include a third identifier generator Gc, which may be located between the read response QP receiving channel "Cr<—Ct" (that is, the receiving cache queue Cr corresponding to the read response in multiple groups of first on-chip transceiver cache queues) and the third bus logic channel (for example, the R channel of AXI), and the third identifier generator Gc may pre-generate a second bus identifier allocated with the data source as the granularity for the corresponding read response for each read request, and stored in association with the read operation tag of the read request and the corresponding read response.

[0112] Exemplarily, in an embodiment of the present application, the multiple bus logic channels of the on-chip bus of the processor U_i may also include a fourth bus logic channel for transmitting write responses. For example, the fourth logic bus channel may include the B channel of AXI, and the port driver circuit MP_i (for example, the bus bridge Brg_i) of the processor U_i may also be used to respond to the write request received from the NOC_i of the chip processing core, and return the corresponding write response to the NOC_i of the chip processing core through the fourth bus logic channel, that is, the port driver circuit MP_i (for example, the bus bridge Brg_i) of the processor U_i may be configured to predict the successful result of the write request in the sending direction.

[0113] Exemplarily, in an embodiment of the present application, the write response corresponding to the write request received through the write request QP receiving channel "Wr<—Wt" can be generated internally by the other processor U_j that initiates the write request, that is, the other processor U_j can be configured as the successful result of the issued write request, and there is no need for the chip processing core of the processor U_i to generate a corresponding write response and issue it in the sending direction to the other processor U_j that initiates the write request.

[0114] Figure 8 This is a schematic diagram of the extended principle of data communication between multiple processors in the embodiment of the present application. Figure 8 If any processor U_i among the multiple processors U_1~U_N realizes communication interconnection with multiple different other processors U_j through the network switching device SW, then the first port serial link between the processor U_i and the first network switching port Ps_i of the network switching device SW can reuse the channel segment on the side of the processor U_i that carries multiple groups of QP transceiver channels between the processor U_i and multiple different other processors U_j, and can be reused to realize the stream transmission between the processor U_i and multiple different other processors U_j in a segment of the first port serial link. In this case, each receiving cache queue of the multiple groups of first on-chip transceiver cache queues of the processor U_i will cache the same corresponding type of interactive data from different data sources (i.e., different other processors U_j), that is, there is a multi-source mutual interference situation of the same type of interactive data from multiple data sources in the receiving direction in the port driving circuit MP_i (e.g., bus bridge Brg_i) of the processor U_i.

[0115] Fig. 9 is a schematic diagram of multi-source interference in a comparative example. Fig. 9 , the port driver circuit MP_i (e.g. bus bridge Brg_i) of the processor U_i may also include a corresponding FIFO (First Input First Output) queue corresponding to each type of interactive data, and the received data of different data sources (i.e., different other processors U_j) cached in each receiving cache queue of the multiple groups of first on-chip transceiver cache queues of the processor U_i are sequentially assigned bus identifiers through the corresponding FIFO queues and sent to the corresponding bus logic channel of the on-chip bus of the processor U_i. That is: A write request FIFO queue corresponding to the write request and the atomic request may be provided between the write request QP receiving channel "Wr<—Wt" (i.e., the receiving cache queue Wr corresponding to the write request and the atomic request in the plurality of first intra-chip transceiver cache queues) and the first identifier generator Gw or the first bus logic channel (e.g., at least one of the AW channel and the W channel of AXI), and the write requests and the atomic requests from different data sources (i.e., different other processors U_j) are assigned bus identifiers one by one through the write request FIFO queue in the order of arriving at the receiving cache queue Wr of the processor U_i, and then sent to the first bus logic channel (e.g., at least one of the AW channel and the W channel of AXI); A read request FIFO queue corresponding to a write request may be provided between the read request QP receiving channel "Rr<—Rt" (i.e., the receiving cache queue Rr corresponding to the read request in the plurality of first intra-chip transceiver cache queues) and the second identifier generator Gr or the second bus logic channel (e.g., the AR channel of AXI), and the read requests from different data sources (i.e., different other processors U_j) are assigned bus identifiers one by one through the read request FIFO queue in the order of arriving at the receiving cache queue Rr of the processor U_i, and then sent to the second bus logic channel (e.g., the AR channel of AXI); A read response FIFO queue corresponding to the write request may be provided between the read response QP receiving channel "Cr<—Ct" (i.e., the receiving cache queue Cr corresponding to the read response in the multiple groups of first on-chip transceiver cache queues) and the third identifier generator Gc or the third bus logic channel (e.g., the R channel of AXI), and the read responses from different data sources (i.e., different other processors U_j) are assigned bus identifiers one by one through the read response FIFO queue and sent to the third bus logic channel (e.g., the R channel of AXI) in the order of arriving at the receiving cache queue Cr of the processor U_i.

[0116] In this case, if the chip processing core of processor U_i processes a certain type of interactive data from any data source slowly, it will affect the efficiency of the same type of interactive data from other data sources entering the on-chip bus of processor U_i.

[0117] Fig.10 This is a schematic diagram of the optimized structure of the chip communication port of the processor in the embodiment of the present application. Fig.10In an embodiment of the present application, among the multiple receiving cache queues of the multiple groups of first on-chip transceiver cache queues of the processor U_i, any one or at least one receiving cache queue can be connected to the corresponding bus logical channel among the multiple bus logical channels through a corresponding parallel FIFO queue group, and the number of FIFO queues included in a parallel FIFO queue group corresponding to any receiving cache queue can include the same as the total number of other processors U_j (for example, N-1), and the number of FIFO queues in a parallel FIFO queue group corresponding to any receiving cache queue can correspond to different data sources (that is, different other processors U_j), respectively, and the interactive data cached in the receiving queue from different data sources (that is, different other processors U_j) can be distributed in order to the FIFO queues corresponding to the same data source (that is, the same other processor U_j) in the corresponding parallel FIFO queue group by polling (Polling) the look up tables (Look Up Table, LUT) of different data sources (that is, different other processors U_j). Among them, the interactive data distributed in order to multiple FIFO queues in the parallel FIFO queue group can be assigned bus identifiers based on the equal polling (that is, the chance weights of interactive data from multiple data sources being hit by polling) of different data sources (that is, different other processors U_j) by the channel arbitrator, and sent to the corresponding bus logic channel of the on-chip bus.

[0118] Based on the above embodiment, the same type of interactive data from different data sources (i.e., different other processors U_j) can be independently cached in the parallel FIFO queue group by combining the polling LUT, and the same type of interactive data independently cached in the parallel FIFO queue group can be sent to the corresponding bus logic channel of the on-chip bus in a polling manner in an equal manner (i.e., with equal weight). Therefore, even if the chip processing core of processor U_i processes a certain type of interactive data from any data source slowly, it will not affect the efficiency of the same type of interactive data from other data sources entering the on-chip bus of the processor U_i.

[0119] Exemplarily, in an embodiment of the present application, a parallel FIFO queue group corresponding to write requests and atomic requests may be provided between a write request QP receiving channel "Wr<—Wt" (i.e., a receiving cache queue Wr corresponding to write requests and atomic requests in multiple groups of first on-chip transceiver cache queues) and a first identifier generator Gw or a first bus logical channel (e.g., at least one of the AW channel and the W channel of AXI). The parallel FIFO queue group may include a plurality of FIFO queues that are the same as the total number of other processors U_j (e.g., N-1). The plurality of FIFO queues in the parallel FIFO queue group may correspond to different data sources (i.e., different other processors U_j), respectively. Moreover, the plurality of FIFO queues in the parallel FIFO queue group may be connected to the first identifier generator Gw or the first bus logical channel (e.g., at least one of the AW channel and the W channel of AXI) through a first channel arbiter Atrw. In this case, the write requests and atomic requests cached in the receiving queue Wr from different data sources (i.e., different other processors U_ j) can be distributed to the FIFO queues corresponding to the same data source (i.e., the same other processor U_ j) in the corresponding parallel FIFO queue group in a sequence-preserving manner by polling the LUTs of different data sources (i.e., different other processors U_ j). Moreover, the write requests and atomic requests distributed to multiple FIFO queues in the corresponding parallel FIFO queue group in a sequence-preserving manner through the LUT can be transmitted to the first identifier generator Gw to allocate the corresponding bus identifier by polling different data sources (i.e., different other processors U_ j) through the first channel arbiter Atrw, and then sent to the first bus logic channel (e.g., at least one of the AW channel and the W channel of AXI).

[0120] Exemplarily, in an embodiment of the present application, a read request receiving channel "Rr<-Rt" (i.e., a receiving cache queue Rr corresponding to a read request in a plurality of first on-chip transceiver cache queues) and a second identifier generator Gr or a second bus logic channel (e.g., an AR channel of AXI) may have a parallel FIFO queue group corresponding to a write request, and the parallel FIFO queue group may include a plurality of FIFO queues having the same total number (e.g., N-1) of other processors U_j, and the plurality of FIFO queues in the parallel FIFO queue group may correspond to different data sources (i.e., different other processors U_j), respectively, and the plurality of FIFO queues in the parallel FIFO queue group may be connected to the second identifier generator Gr or the second bus logic channel (e.g., an AR channel of AXI) through a second channel arbiter Atrr. In this case, the read requests cached in the receiving queue Rr from different data sources (i.e., different other processors U_j) may be distributed in order to the FIFO queues corresponding to the same data source (i.e., the same other processor U_j) in the corresponding parallel FIFO queue group by polling the LUTs of different data sources (i.e., different other processors U_j). Moreover, the read requests that are distributed in order to multiple FIFO queues in the corresponding parallel FIFO queue group through the LUT can be transmitted to the second identifier generator Gr through the second channel arbiter Atrr in a manner of polling different data sources (i.e., different other processors U_j) to be assigned the corresponding bus identifier, and then sent to the second bus logic channel (such as the AR channel of AXI).

[0121] Exemplarily, in an embodiment of the present application, the port driver circuit MP_i (for example, the bus bridge Brg_i) of the processor U_i can also maintain a corresponding receiving status register group Reg_valid for any receiving cache queue (for example, the receiving cache queue Wr or Rr), and the receiving status register group Reg_valid may include the same register bits as the total number of data sources or the total number of other processors U_j (for example, N-1), and the multiple register bits of the receiving status register group Reg_valid correspond to different total numbers of data sources or other processors U_j, respectively, and each register bit of the receiving status register group Reg_valid is used to represent whether the corresponding receiving cache queue currently caches the polling result of the interaction data of the data source corresponding to the register bit. In this case, if the data source currently polled (i.e., the other processor U_ j) indicates validity in the corresponding register bit of the receiving status register group Reg_valid (i.e., the corresponding type of interactive data of the data source is currently cached), then it can trigger an interactive data of the corresponding type cached by the data source (i.e., the other processor U_ j) to be transferred through the LUT to the FIFO queue corresponding to the same data source (i.e., the same other processor U_ j) in the corresponding parallel FIFO queue group; otherwise, jump to the next data source (i.e., another other processor U_ j).

[0122] Exemplarily, in an embodiment of the present application, the port driver circuit MP_i (e.g., bus bridge Brg_i) of the processor U_i may also maintain a corresponding inventory status register group Reg_full for a parallel FIFO queue group corresponding to any receive cache queue (e.g., receive cache queue Wr or Rr). The inventory status register group Reg_full may include the same register bits as the total number of data sources or the total number of other processors U_j (e.g., N-1). The multiple register bits of the inventory status register group Reg_full correspond to different total numbers of data sources or other processors U_j, respectively, and each register bit of the inventory status register group Reg_full is used to characterize whether the FIFO queue in the parallel FIFO queue group corresponding to the same data source (i.e., other processors U_j) as the register bit is currently filled with the corresponding type of interaction data of the data source. In this case, when an interactive data of the corresponding type cached by any data source (i.e., other processor U_ j) is triggered through the transfer of LUT, the corresponding register bit of the inventory status register group Reg_full can be used to determine whether the FIFO queue of the data source (i.e., other processor U_ j) corresponding to the same data source (i.e., the same other processor U_ j) in the parallel FIFO queue group is currently in a full state. If the FIFO queue corresponding to any data source (i.e., other processor U_ j) in the parallel FIFO queue group is currently in a full state, the currently triggered LUT transfer is abandoned; if the FIFO queue corresponding to any data source (i.e., other processor U_ j) in the parallel FIFO queue group is not currently in a full state, the currently triggered LUT transfer is allowed to be executed. That is, the execution scope of LUT excludes the data source (i.e., other processor U_ j) corresponding to the FIFO queue indicated as currently full by the inventory status register group Reg_full.

[0123] For example, in the embodiment of the present application, since the data volume of the read response is small and the impact on other types of interactive data is small, a FIFO queue corresponding to the read response may be provided between the read response QP receiving channel "Cr<—Ct" (i.e., the receiving cache queue Cr corresponding to the read response in the plurality of first intra-chip transceiver cache queues) and the third identifier generator Gc or the third bus logic channel (e.g., the R channel of AXI). In this case, the read responses from different data sources (i.e., different other processors U_j) can be assigned bus identifiers one by one through the read response FIFO queue in the order of arriving at the receiving cache queue Cr of the processor U_i and then sent to the third bus logic channel (e.g., the R channel of AXI), or they can also be sent to the FIFO for reordering by polling different data sources, and the read responses from different data sources (i.e., different other processors U_j) can be assigned bus identifiers one by one according to the reordering of the polling and then sent to the third bus logic channel (e.g., the R channel of AXI).

[0124] Exemplarily, in an embodiment of the present application, multiple processors U_1~U_N can be respectively assigned a unique network global identifier (Global ID), and any type of interaction data carries a network global identifier for uniquely representing the data source of the interaction data, and the port driver circuit MP_i (for example, the bus bridge Brg_i) of the processor U_i can identify the data source of the interaction data (that is, the processor U_j that generates the interaction data) through the network global identifier carried by the interaction data.

[0125] In another embodiment of the present application, an electronic device is provided, which may include a network switching device, and at least two computing power devices, one of the at least two computing power devices may include the processor U_i described in the aforementioned embodiment, and the other computing power devices of the at least two computing power devices may include other processors U_j that perform data communication with the processor U_i based on communication interconnection.

[0126] In another embodiment of the present application, a multi-processor system is provided, which may include a first processor, a second processor, and a network switching device, wherein the first processor is configured as the processor U_i described in the aforementioned embodiment, and the second processor may include other processors U_j that perform data communication with the processor U_i based on communication interconnection.

[0127] Fig.11 FIG. 1 is an exemplary flow chart of the data communication method in the embodiment of the present application. Fig.11In another embodiment of the present application, a data communication method is provided. The data communication method can be applied to a processor. The processor has a chip communication port. The chip communication port is used to realize communication interconnection between the processor and other processors through a network switching device. The communication interconnection is used for data communication between the processor and other processors. The communication interconnection between the processor and other processors may include a port cascade transmission link between the processor and other processors based on port switching forwarding of the network switching device. The data communication between the processor and other processors may include multiple types of interactive data stream transmission through the port cascade transmission link, and the data communication method may include: S1110: Create multiple groups of QP transceiver channels based on RDMA, where the multiple groups of QP transceiver channels are carried in the same port cascade transmission link between the processor and other processors.

[0128] Exemplarily, in an embodiment of the present application, the chip communication port of the processor applying the data communication method is connected to the first network switching port of the network switching device, and the network switching device also includes a second network switching port connected to other chip communication ports of other processors. The port cascade transmission link between the processor applying the data communication method and other processors may include: a first port serial link between the chip communication port of the processor and the first network switching port of the network switching device, a second port serial link between the second network switching port of the network switching device and other chip communication ports of other processors, and a port switching link between the first network switching port and the second network switching port of the network switching device to realize port switching forwarding. In this case, the data communication method may include creating multiple groups of QP transceiver channels between the chip communication port of the processor and other chip communication ports of other processors through S1110, and the multiple groups of QP transceiver channel segments created by S1110 are carried on the first port serial link between the chip communication port of the processor and the first network switching port of the network switching device, and the second port serial link between the other chip communication ports of other processors and the second network switching port of the network switching device, and the two channel segments of the multiple groups of QP transceiver channels created by S1110 can be bridged through the corresponding multiple groups of switching channels between the first network switching port and the second network switching port of the network switching device.

[0129] S1130: Based on the correspondence between the multiple types and the multiple groups of QP transceiver channels, the multiple groups of QP transceiver channels are used to independently implement the stream transmission of the multiple types of interactive data.

[0130] Based on the above-mentioned data communication method of the embodiment of the present application, the communication interconnection between the processor and other processors realized through the network switching device can realize data communication by using multiple groups of QP transceiver channels carried on the same port cascade transmission link. Among them, there is a corresponding relationship between the multiple groups of QP transceiver channels and the multiple types of interactive data involved in the data communication, and the multiple types of interactive data can be streamed independently of each other through the multiple groups of QP transceiver channels. Therefore, compared with the serial method of time-division multiplexing of the port cascade transmission link for the stream transmission of multiple types of interactive data, the risk of transmission deadlock in the data communication between processors can be reduced.

[0131] Illustratively, in an embodiment of the present application, an on-chip bus (e.g., an AXI bus) of a processor to which the data communication method is applied may carry multiple bus logical channels, and the data communication method may further include: utilizing multiple bus logical channels to respectively implement on-chip transmission of multiple types of interactive data in the processor; wherein the correspondence between multiple groups of QP transceiver channels and multiple types matches the correspondence between multiple bus logical channels and multiple types, so that the streaming transmission of multiple types of interactive data and the transmission connection between on-chip transmission are independent of each other.

[0132] Exemplarily, in an embodiment of the present application, the multiple types of interactive data may include write requests, atomic requests, read requests, and read responses; the multiple bus logic channels of the processor's on-chip bus may include a first bus logic channel corresponding to write requests and atomic requests (e.g., at least one of the AW channel and the W channel of the AXI bus), a second bus logic channel corresponding to read requests (e.g., the AR channel of the AXI bus), and a third bus logic channel corresponding to read responses (e.g., the R channel of the AXI bus). In this case, the multiple groups of QP transceiver channels may include a group of write request QP transceiver channels corresponding to write requests and atomic requests (i.e., one write request QP sending channel and one write request QP receiving channel), a group of read request QP transceiver channels corresponding to read requests (i.e., one read request QP sending channel and one read request QP receiving channel), and a group of read response QP transceiver channels corresponding to read responses (i.e., one read response QP sending channel and one read response QP receiving channel).

[0133] Exemplarily, in an embodiment of the present application, the transmission priority of the read response QP transceiver channel may be higher than the transmission priority of the write request QP transceiver channel and the read request QP transceiver channel. That is, the transmission priority of the read response QP sending channel is preferably higher than the transmission priority of the write request QP sending channel and the read request QP sending channel; and the transmission priority of the read response QP receiving channel is preferably higher than the transmission priority of the write request QP receiving channel and the read request QP receiving channel.

[0134] Exemplarily, in an embodiment of the present application, the multiple bus logic channels carried by the on-chip bus of the processor to which the data communication method is applied may also include a fourth bus logic channel (e.g., channel B of the AXI bus) for transmitting write responses, and the data communication method may also include: in response to a write request generated from within the processor on the fourth bus logic channel, returning a corresponding write response through the fourth bus logic channel.

[0135] Exemplarily, in an embodiment of the present application, a write response corresponding to a write request received through a write request QP receiving channel may be generated internally by another processor that initiates the write request, and the data communication method may not be required to generate a corresponding write response for the write request received through the write request QP receiving channel.

[0136] Exemplarily, in an embodiment of the present application, S1130 of the data communication method may specifically include: (a1) maintaining the transmission order of write requests and atomic requests in the stream transmission realized by the write request QP sending channel to be the same as the transmission order of write requests and atomic requests in the intra-chip transmission realized by the first bus logical channel (e.g., at least one of the AW channel and the W channel of AXI), that is, the write requests and atomic requests in the sending direction are transmitted in order-preserving manner in the write request QP sending channel; (a2) maintaining the transmission order of the read requests in the stream transmission implemented by the read request QP sending channel to be the same as the transmission order of the read requests in the intra-chip transmission implemented by the second bus logic channel (e.g., the AR channel of AXI), that is, the read requests in the sending direction are transmitted in the read request QP sending channel in an order-preserving manner; (a3) The transmission order of the read responses in the stream transmission implemented by the read response QP sending channel is maintained to be the same as the transmission order of the read responses in the intra-chip transmission implemented by the third bus logical channel (e.g., the Ar channel of AXI), that is, the read responses in the sending direction are transmitted in the read response QP sending channel in an order-preserving manner. It can be understood that each read response is generated for the previously received read request, and the generation order of the read responses may not be the same as the reception order of the read requests, and the transmission order of the intra-chip transmission implemented by the read responses in the third bus logical channel (e.g., the R channel of AXI) may not be consistent with the reception order of the read requests. Therefore, the transmission order of the read responses in the stream transmission implemented by the read response QP sending channel can be de-associated with the reception order of the corresponding read requests.

[0137] Exemplarily, in an embodiment of the present application, S1130 of the data communication method may specifically include: (b1) maintaining the transmission order of the write requests with the same other processor as the data source in the on-chip transmission implemented in the first bus logical channel (e.g., at least one of the AW channel and the W channel of AXI) to be the same as the transmission order in the stream transmission implemented in the write request QP receiving channel, that is, the write requests in the receiving direction are transmitted in the first bus logical channel (e.g., at least one of the AW channel and the W channel of AXI) in order; (b2) de-associating the transmission order of the atomic requests with the same other processor as the data source in the on-chip transmission implemented in the first bus logic channel (e.g., at least one of the AW channel and the W channel of AXI) from the transmission order in the stream transmission implemented in the write request QP receiving channel, that is, since the operation addresses of different atomic requests in the processor U_i are usually different, the atomic requests in the receiving direction can be transmitted out of order in the first bus logic channel (e.g., at least one of the AW channel and the W channel of AXI); (b3) maintaining the transmission order of the read requests with the same other processor as the data source in the on-chip transmission implemented in the second bus logic channel (e.g., the AR channel of AXI) to be decoupled from the transmission order in the stream transmission implemented in the read request QP receiving channel, that is, since the access addresses of different read requests in the processor are usually different, the read requests in the receiving direction can be transmitted out of order in the second bus logic channel (e.g., the AR channel of AXI); (b4) The transmission order of the read responses with the same other processor as the data source in the on-chip transmission implemented by the third bus logical channel (e.g., the R channel of AXI) is kept the same as the transmission order in the stream transmission implemented by the read response QP receiving channel, that is, the read responses in the receiving direction are transmitted in the third bus logical channel (e.g., the R channel of AXI) in an order-preserving manner.

[0138] Exemplarily, in an embodiment of the present application, the on-chip bus of the processor to which the data communication method is applied may be configured to implement on-chip transmission of interactive data having the same bus identifier in an order-preserving manner. In this case: The bus identifier of the on-chip bus of the processor to which the data communication method is applied may include a first bus identifier applied to a first bus logical channel, and the above step (b1) in S1130 of the data communication method may include: allocating the same first bus identifier corresponding to the data source to all write requests with the same other processor as the data source, that is, allocating the first bus identifier with the data source as the granularity; The bus identifier of the on-chip bus of the processor to which the data communication method is applied may include a first exclusive identifier applied to a first bus logical channel, the first exclusive identifier and the first bus identifier may belong to different identifier sequences or different identifier pools, and the above step (b2) in S1130 of the data communication method may include: assigning different first exclusive identifiers to different atomic requests, that is, assigning the first exclusive identifier with the atomic request as the granularity, and the first exclusive identifier assigned to each atomic request may be recycled in response to the success of the operation of the atomic request; The bus identifier of the on-chip bus of the processor to which the data communication method is applied may further include a second exclusive identifier applied to the second bus logical channel, and the above step (b3) in S1130 of the data communication method may include: assigning different second exclusive identifiers to different read requests, that is, assigning the second exclusive identifier with the read request as the granularity, and the second exclusive identifier assigned to each read request is recycled in response to the success of the operation of the read request (for example, generating a read response returned corresponding to the read request in the sending direction); The bus identifier of the on-chip bus of the processor to which the data communication method is applied may include a second bus identifier applied to a third bus logical channel, and the above-mentioned step (b4) in S1130 of the data communication method may include: querying the second bus identifier stored in association with the read operation tag of the read response, and the read response may be transmitted on-chip in the third bus logical channel using the queried second bus identifier; wherein any read response may carry the same read operation tag (tag) as the corresponding read request, and the second bus identifier is pre-assigned to the read response corresponding to the read request when the read request is sent to the same other processor U_j (i.e., the data source of the read response) and is stored in association with the read operation tag used jointly by the read request and the corresponding read response, so that whenever a read response is received in response to the issued read request, the predetermined second bus identifier may be directly hit using the read operation tag (tag).

[0139] Exemplarily, in an embodiment of the present application, a processor applying the data communication method can maintain multiple groups of first on-chip transceiver cache queues, and the multiple groups of first on-chip transceiver cache queues are used to realize the association and docking between the multiple groups of QP transceiver channels created by S1110 and the multiple bus logic channels in the processor, and the association and docking are used for the transmission connection between the on-chip transmission in the processor and the stream transmission of the processor. Among them, the multiple groups of first on-chip transceiver cache queues of the processor may include multiple receive cache queues, each of the multiple receive cache queues is used to cache the same corresponding type of interactive data from different data sources, and the different data sources include multiple different other processors. Any one of the multiple receive cache queues can be connected to the corresponding bus logic channel in the multiple bus logic channels through a parallel FIFO queue group, and the parallel FIFO queue group includes multiple FIFO queues corresponding to different data sources one by one. In this case, the data communication method utilizes multiple bus logic channels to respectively realize the on-chip transmission of multiple types of interactive data in the processor, and may specifically include: distributing the interactive data of different data sources cached in any one of the multiple receiving cache queues to the FIFO queues corresponding to the same data source in the parallel FIFO queue group by polling the lookup tables of different data sources in order.

[0140] Exemplarily, in an embodiment of the present application, any type of interaction data carries a network global identifier for uniquely characterizing the data source of the interaction data, and a processor applying the data communication method can identify the data source of the interaction data (i.e., the other processor that generates the interaction data) through the network global identifier carried by the interaction data.

[0141] In an embodiment of the field of the present application, an electronic device is provided, which may include a network switching device, a processor for executing the above-mentioned data communication method, and other processors that realize data communication with the processor based on communication interconnection through the network switching device.

[0142] It can be understood that, in the embodiments of the present application, the various parts of the contents exemplified can be in an "and / or" relationship. In this article, the meaning of "and / or" refers to the contexts connected by it, which can be in a common limiting relationship of "and", or can also be in an alternative limiting relationship of "or". Therefore, the various parts of the contents with an "and / or" relationship can be understood as including different combinations of situations in which "and / or" between each two parts of the contents respectively represents a common limiting relationship of "and" or an alternative limiting relationship of "or", and this combination of different situations can be considered to be basically equivalent to the limiting scope of "at least one of the parts".

[0143] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A processor, characterized in that: The processor comprises: A chip communication port, wherein the chip communication port is used to realize communication interconnection between the processor and other processors through a network switching device, the communication interconnection is used to realize data communication between the processor and the other processors, the communication interconnection includes a port cascade transmission link between the processor and the other processors based on port switching forwarding of the network switching device, and the data communication includes stream transmission of multiple types of interactive data through the port cascade transmission link; A port driving circuit, wherein the port driving circuit is used to create a plurality of groups of QP transceiver channels based on RDMA, wherein the plurality of groups of QP transceiver channels are carried in the same port cascade transmission link between the processor and the other processors, and the plurality of types of interactive data are based on a correspondence between the plurality of types and the plurality of groups of QP transceiver channels, and are respectively transmitted independently of each other through the plurality of groups of QP transceiver channels.

2. The processor according to claim 1, characterized in that The processor further includes: a chip processing core, the chip processing core is connected to the port driving circuit via an on-chip bus of the processor, the on-chip bus carries a plurality of bus logic channels, and the plurality of bus logic channels are used to respectively realize on-chip transmission of the plurality of types of interactive data in the processor; Among them, the correspondence between the multiple groups of QP transceiver channels and the multiple types matches the correspondence between the multiple bus logical channels and the multiple types, so that the transmission connection between the stream transmission of the multiple types of interactive data and the intra-chip transmission is independent of each other.

3. The processor according to claim 2, characterized in that The multiple types include: write request, atomic request, read request, and read response; The plurality of bus logic channels include: a first bus logic channel corresponding to the write request and the atomic request, a second bus logic channel corresponding to the read request, and a third bus logic channel corresponding to the read response; The multiple groups of QP transceiver channels include a group of write request QP transceiver channels corresponding to the write request and the atomic request, a group of read request QP transceiver channels corresponding to the read request, and a group of read response QP transceiver channels corresponding to the read response.

4. The processor according to claim 3, characterized in that The transmission priority of the read response QP transceiver channel is higher than the transmission priority of the write request QP transceiver channel and the read request QP transceiver channel; and / or, The plurality of bus logic channels also include a fourth bus logic channel for transmitting a write response, and the port driver circuit is further configured to respond to the write request received from the chip processing core and return the corresponding write response to the chip processing core through the fourth bus logic channel; and / or, The write response corresponding to the write request received through the write request QP receiving channel is generated internally by the other processor that initiates the write request.

5. The processor according to claim 3, characterized in that The write request QP transceiver channel includes a write request QP sending channel, the read request QP transceiver channel includes a read request QP sending channel, and the read response QP transceiver channel includes a read response QP sending channel, wherein: The transmission order of the write request and the atomic request in the stream transmission implemented by the write request QP sending channel is the same as the transmission order in the intra-chip transmission implemented by the first bus logical channel; The transmission order of the read requests in the stream transmission implemented by the read request QP sending channel is the same as the transmission order in the intra-chip transmission implemented by the second bus logical channel; The transmission order of the read responses in the stream transmission implemented by the read response QP sending channel is the same as the transmission order in the intra-chip transmission implemented by the third bus logical channel.

6. The processor according to claim 3, characterized in that The write request QP transceiver channel includes a write request QP receiving channel, the read request QP transceiver channel includes a read request QP receiving channel, and the read response QP transceiver channel includes a read response QP receiving channel, wherein: The write request with the same other processor as the data source has the same transmission order in the intra-chip transmission implemented by the first bus logic channel and the same transmission order in the stream transmission implemented by the write request QP receiving channel; For the atomic request with the same other processor as the data source, the transmission order in the intra-chip transmission implemented by the first bus logic channel is de-associated with the transmission order in the stream transmission implemented by the write request QP receiving channel; For the read request with the same other processor as the data source, the transmission order in the intra-chip transmission implemented by the second bus logic channel is de-associated with the transmission order in the stream transmission implemented by the read request QP receiving channel; The read responses with the same other processor as the data source have the same transmission order in the intra-chip transmission implemented by the third bus logic channel and the same transmission order in the stream transmission implemented by the read response QP receiving channel.

7. The processor according to claim 6, characterized in that The on-chip bus is configured to implement the on-chip transmission in an order-preserving manner for interactive data with the same bus identifier, and: The bus identifier includes a first bus identifier applied to the first bus logical channel, and the port driver circuit is further used to: allocate the same first bus identifier corresponding to the data source to all write requests with the same other processor as the data source; The bus identifier includes a first exclusive identifier applied to the first bus logical channel, and the port driver circuit is further used to: assign different first exclusive identifiers to different atomic requests respectively, and the first exclusive identifier assigned to each atomic request is recycled in response to the success of the operation of the atomic request; The bus identifier includes a second exclusive identifier applied to the second bus logical channel, and the port driver circuit is further used to: allocate different second exclusive identifiers to different read requests respectively, and the second exclusive identifier allocated to each read request is recycled in response to the success of the operation of the read request; The bus identifier includes a second bus identifier applied to the third bus logical channel, and the port driver circuit is further used to: query the second bus identifier stored in association with the read operation tag of the read response; wherein the read response and the corresponding read request carry the same read operation tag, and the second bus identifier is pre-allocated for the corresponding read response and stored in association with the corresponding read operation tag when the read request sent to the same other processor is issued.

8. The processor according to claim 1, wherein: The chip communication port is connected to a first network switching port of the network switching device, the network switching device further comprises a second network switching port connected to other chip communication ports of the other processors, the port cascade transmission link comprises a first port serial link between the chip communication port and the first network switching port, a second port serial link between the second network switching port and the other chip communication port, and a port switching link between the first network switching port and the second network switching port for implementing the port switching forwarding; The multiple groups of QP transceiver channels are created between the chip communication port and the other chip communication ports, and the multiple groups of QP transceiver channels are respectively carried on two sections of the first port serial link and the second port serial link, and are bridged by the corresponding multiple groups of switching channels between the first network switching port and the second network switching port.

9. The processor according to claim 8, characterized in that The processor further includes: a chip processing core, the chip processing core is connected to the port driving circuit via an on-chip bus of the processor, the on-chip bus carries a plurality of bus logic channels, and the plurality of bus logic channels are used to respectively realize on-chip transmission of the plurality of types of interactive data in the processor; The correspondence between the multiple groups of QP transceiver channels and the multiple types matches the correspondence between the multiple bus logical channels and the multiple types, so that the transmission connection between the stream transmission and the intra-chip transmission of the multiple types of interactive data is independent of each other; The port driving circuit is used to maintain multiple groups of first on-chip transceiver cache queues, and the multiple groups of first on-chip transceiver cache queues are used to realize the association and docking between the multiple groups of QP transceiver channels and the multiple bus logical channels, and the association and docking is used for the transmission continuation of the on-chip transmission and the stream transmission.

10. The processor according to claim 9, characterized in that The multiple groups of first on-chip transceiver cache queues include multiple receive cache queues, each of the multiple receive cache queues is used to cache the same corresponding type of interactive data from different data sources, the different data sources include multiple different other processors, any one of the multiple receive cache queues is connected to a corresponding bus logical channel in the multiple bus logical channels through a parallel FIFO queue group, and the parallel FIFO queue group includes multiple FIFO queues corresponding to different data sources one by one; The interactive data from different data sources cached in any one of the multiple receiving cache queues are distributed in order to the FIFO queues corresponding to the same data source in the parallel FIFO queue group by polling the lookup tables of different data sources.

11. The processor according to claim 10, characterized in that The multiple types include: write request, atomic request, read request, and read response; the multiple bus logic channels include: a first bus logic channel corresponding to the write request and the atomic request, a second bus logic channel corresponding to the read request, and a third bus logic channel corresponding to the read response; the multiple groups of QP transceiver channels include: a write request QP sending channel and a write request QP receiving channel corresponding to the write request and the atomic request, a read request QP sending channel and a read request QP receiving channel corresponding to the read request, and a read response QP sending channel and a read response QP receiving channel corresponding to the read response; The multiple groups of first on-chip transceiver buffer queues include: multiple receive buffer queues corresponding to the write request QP receive channel, the read request QP receive channel, and the read response QP receive channel respectively; the receive buffer queue corresponding to the write request QP receive channel and the first bus logical channel, and the receive buffer queue corresponding to the read request QP receive channel and the second bus logical channel are respectively connected through different parallel FIFO queue groups, and the receive buffer queue corresponding to the read response QP receive channel and the third bus logical channel are connected through one FIFO queue; and / or, The port driver circuit also has a receiving status register group corresponding to the multiple receiving cache queues, and each register bit of the receiving status register group is used to indicate whether a corresponding receiving cache queue in the multiple receiving cache queues currently caches a polling result of interaction data of a corresponding data source; and / or, The port driver circuit further comprises a stock status register group corresponding to the parallel FIFO queue group, each register bit of the stock status register group is used to indicate whether a corresponding FIFO queue in the parallel FIFO queue group is currently filled with interactive data of a corresponding data source, and the execution scope of the lookup table excludes the data source corresponding to the FIFO queue indicated as currently filled by the stock status register group; and / or, Any type of interactive data carries a network global identifier that uniquely identifies the data source.

12. A multiprocessor system, characterized in that: The invention comprises a first processor, a second processor and a network switching device, wherein the first processor is configured as the processor according to any one of claims 1 to 11, and the second processor comprises other processors that perform data communication with the processor according to any one of claims 1 to 11.

13. A data communication method, characterized in that: The data communication method is applied to a processor; the processor has a chip communication port, the chip communication port is used to realize the communication interconnection between the processor and other processors through a network switching device, the communication interconnection is used for data communication between the processor and the other processors, the communication interconnection includes a port cascade transmission link between the processor and the other processors based on port switching forwarding of the network switching device, the data communication includes stream transmission of multiple types of interactive data through the port cascade transmission link, and the data communication method includes: Creating multiple groups of QP transceiver channels based on RDMA, wherein the multiple groups of QP transceiver channels are carried in the same port cascade transmission link between the processor and the other processors; Based on the correspondence between the multiple types and the multiple groups of QP transceiver channels, the multiple groups of QP transceiver channels are used to independently implement the stream transmission of the multiple types of interactive data.

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