Chip SoC and electronic devices

Abstract

The present application relates to a chip SoC and an electronic device. The chip SoC includes multiple subsystems, and the subsystem includes a control subblock and a data subblock. The data subblock can be controlled and accessed by the chip SoC, or the data subblock can be controlled and accessed by the control subblock; the interrupt information of the data subblock can be reported to the control subblock for interrupt processing, or the interrupt information of the data subblock can be reported to the chip SoC for interrupt processing. With this chip SoC, control access and interrupt information reporting can be performed between the chip SoC and the subsystem in a variety of ways, which improves the flexibility and selectivity of information interaction between the chip SoC and the subsystem. Therefore, the efficiency of control access and interrupt processing is higher, and the delay of control access and interrupt processing is reduced.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a chip SoC and an electronic device. Background Art

[0002] Chips are the cornerstone of modern society and technological development. Chip SoC is a system that integrates multiple chip subsystems on one chip. This approach can improve the performance and functional density of the chip, while helping to reduce energy consumption and manufacturing costs. The chip subsystem is one of the basic modules on the chip to implement various complex functions. Usually, a chip SoC includes multiple chip subsystems. The management of multiple subsystems on the chip by the chip SoC is often directly related to the performance and efficiency of the chip.

[0003] Currently, the control access method of the chip SoC to multiple subsystems on the chip is relatively simple, and the control access efficiency is low. Summary of the invention

[0004] Based on this, it is necessary to provide a chip SoC and an electronic device that can improve the access system in response to the above technical problems.

[0005] In a first aspect, the present application provides a chip SoC, which includes multiple subsystems, including a control sub-block and a data sub-block. The data sub-block can be controlled and accessed by the chip SOC, or the data sub-block can be controlled and accessed by the control sub-block; the interrupt information of the data sub-block can be reported to the control sub-block for interrupt processing, or the interrupt information of the data sub-block can be reported to the chip SoC for interrupt processing.

[0006] In one embodiment, the data sub-block includes a first data sub-block and a second data sub-block; wherein the chip SoC is connected to the first data sub-block through a first system bus to control access to the first data sub-block; the chip SoC is connected to the control sub-block through a second system bus to control access to the control sub-block; the control sub-block is also used to connect to the second data sub-block through a third system bus to control access to the second data sub-block.

[0007] In one embodiment, the control sub-block is further used to control access to the first data sub-block through the second system bus and the first system bus.

[0008] In one of the embodiments, the control sub-block is also used to receive interrupt information from the data sub-block, schedule and process the interrupt information of the data sub-block; and report the interrupt information after scheduling and processing to the controller of the control sub-block for interrupt processing, or report the interrupt information to the chip SoC for interrupt processing.

[0009] In one of the embodiments, the data sub-block is also used to schedule the interrupt information of the data sub-block, and report the interrupt information after scheduling to the control sub-block for interrupt processing, or report the interrupt information to the chip SoC for interrupt processing.

[0010] In one of the embodiments, the data sub-block is further used to aggregate the interrupt information of the data sub-blocks and report the aggregated interrupt information to the control sub-block, or report the aggregated interrupt information to the chip SoC.

[0011] In one of the embodiments, the data sub-block is also used to perform interrupt masking processing on the interrupt information, and report the interrupt information after the interrupt masking processing to the control sub-block, or report the interrupt information after the interrupt masking processing to the chip SoC; the control sub-block is also used to perform interrupt masking processing on the interrupt information, and report the interrupt information after the interrupt masking processing to the controller of the control sub-block, or report the interrupt information after the interrupt masking processing to the chip SoC.

[0012] In one of the embodiments, the data sub-block also includes an interrupt setting signal, which is used to generate a debug interrupt source, which is used to generate debug interrupt information so that the data sub-block tests the interrupt reporting path of the data sub-block through the debug interrupt information; the control sub-block also includes an interrupt setting signal, which is used to generate a debug interrupt source, which is used to generate debug interrupt information so that the control sub-block tests the interrupt reporting path of the control sub-block through the debug interrupt information.

[0013] In one embodiment, the interrupt information includes an identifier of the subsystem and an identifier of the interrupt source.

[0014] In a second aspect, the present application further provides an electronic device, comprising a chip SoC as described in any one of the first aspects above.

[0015] The above-mentioned chip SoC and electronic device, the chip SoC includes multiple subsystems, the subsystem includes a control sub-block and a data sub-block, the data sub-block can be controlled and accessed by the chip SoC, or the data sub-block can be controlled and accessed by the control sub-block; the interrupt information of the data sub-block can be reported to the control sub-block for interrupt processing, or the interrupt information of the data sub-block can be reported to the chip SoC for interrupt processing. In this way, the chip SoC and the subsystems can control access and report interrupt information in a variety of ways, which improves the flexibility and selectivity of information interaction between the chip SoC and the subsystems, so that the efficiency of control access and interrupt processing is higher, and the delay of control access and interrupt processing is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of the structure of a chip SoC in an embodiment;

[0018] Figure 2 A schematic diagram of the structure of a chip SoC and a subsystem in another embodiment;

[0019] Figure 3 A schematic diagram of control access between a chip SoC and a subsystem in another embodiment;

[0020] Figure 4 A schematic diagram of interrupt processing between a chip SoC and a subsystem in another embodiment;

[0021] Figure 5 The figure is a schematic diagram of the format of interrupt information according to an embodiment. DETAILED DESCRIPTION

[0022] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It should be understood that many specific details are set forth in the following description to facilitate a full understanding of the present application, but the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0023] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0024] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0025] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0026] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0027] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0028] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0029] Currently, the control access of the chip SoC to each subsystem is often performed by the chip SoC directly accessing the control sub-block and data sub-block of each subsystem. This control access method is relatively simple, and therefore, the control access efficiency is low.

[0030] In view of this, the present application proposes a chip SoC, which includes multiple subsystems, including a control sub-block and a data sub-block. The data sub-block can be controlled and accessed by the chip SoC, or the data sub-block can be controlled and accessed by the control sub-block; the interrupt information of the data sub-block can be reported to the control sub-block for interrupt processing, or the interrupt information of the data sub-block can be reported to the chip SoC for interrupt processing. In this way, the chip SoC and the subsystems can control access and report interrupt information in a variety of ways, which improves the flexibility and selectivity of information interaction between the chip SoC and the subsystems. Therefore, the efficiency of control access and interrupt processing is higher, and the delay of control access and interrupt processing is reduced.

[0031] Figure 1 This is a structural block diagram of a chip SoC provided in an embodiment of the present application. Figure 1 As shown, the chip SoC10 includes multiple subsystems 20, and the subsystem includes a control sub-block 21 and a data sub-block 22. The data sub-block 22 can be controlled and accessed by the chip SoC10, or the data sub-block 22 can be controlled and accessed by the control sub-block 21; the interrupt information of the data sub-block 22 can be reported to the control sub-block 21 for interrupt processing, or the interrupt information of the data sub-block 22 can be reported to the chip SoC10 for interrupt processing.

[0032] Among them, the chip SoC10 may include multiple subsystems with different functions, and the subsystem 20 is a subsystem in the chip SoC. The chip SoC manages the subsystem 20, including managing the control access path and interrupt reporting path of the subsystem 20. The chip SoC10 manages the subsystem 20 through multiple groups of communication buses between the chip SoC10 and the subsystem 20. The chip SoC10 manages the subsystem 20, that is, manages the control sub-block 21 and the data sub-block 22 in the subsystem 20. Optionally, the control sub-block 21 and the data sub-block 22 in the subsystem 20 may include multiple, such as Figure 2As shown, the subsystem 20 includes M control subblocks 21, for example, {control subblock Subblock1, control subblock Subblock2, …, control subblock Subblockm, …, control subblock SubblockM}, where control subblock Subblockm is the mth control subblock Subblock in the subsystem 20, and the value range of m is 1 to M; the subsystem 20 includes N data subblocks 22, for example, {data subblock Subblock1, data subblock Subblock2, …, data subblock Subblockn, …, data subblock SubblockN}, where data subblock Subblockn is the nth data subblock Subblock in the subsystem 20, and the value range of n is 1 to N.

[0033] Optionally, the control sub-block 21 may include an MCU (Microcontroller Unit) or a RISC-V (RISC-V instruction set architecture) controller, and the data sub-block 22 does not include a controller. The data sub-block 22 may be controlled and accessed by the chip SoC10, that is, the data sub-block 22 is connected to the chip SoC10 through a system bus, and the chip SoC10 may directly control and access the data sub-block 22 through the system bus. The data sub-block 22 may also be controlled and accessed by the control sub-block 21 of the subsystem 20, that is, the data sub-block 22 is connected to the control sub-block 21, and the control sub-block 21 directly controls and accesses the data sub-block 22.

[0034] The control sub-block 21 is connected to the chip SoC10 through a system bus, and the chip SoC10 controls and accesses the control sub-block 21 through the system bus. The control sub-block 21 can also control and access other data sub-blocks 22 in the subsystem 20 through the system bus between the chip SoC10 and the control sub-block 21.

[0035] In the above embodiment, the chip SoC includes multiple subsystems, and the subsystem includes a control subblock and a data subblock. The data subblock can be controlled and accessed by the chip SoC, or the data subblock can be controlled and accessed by the control subblock; the interrupt information of the data subblock can be reported to the control subblock for interrupt processing, or the interrupt information of the data subblock can be reported to the chip SoC for interrupt processing. In this way, the chip SoC and the subsystem can control access and report interrupt information in a variety of ways, which improves the flexibility and selectivity of information interaction between the chip SoC and the subsystem. Therefore, the efficiency of control access and interrupt processing is higher, and the delay of control access and interrupt processing is reduced.

[0036] In one embodiment, the data sub-block 22 includes a first data sub-block and a second data sub-block; wherein, the chip SoC10 is connected to the first data sub-block through a first system bus to control access to the first data sub-block; the chip SoC10 is connected to the control sub-block 21 through a second system bus to control access to the control sub-block 21; the control sub-block 21 is also used to connect to the second data sub-block through a third system bus to control access to the second data sub-block.

[0037] The first data sub-block and the second data sub-block are two types of data sub-blocks in the data sub-block 22. The first data sub-block is connected to the chip SoC 10, that is, the first data sub-block is directly controlled by the chip SoC 10. The second data sub-block is connected to the control sub-block 21, that is, the second data sub-block is directly controlled by the control sub-block 21.

[0038] Optional, with Figure 3 The subsystem shown is used as an example for explanation. The subsystem 20 includes four subblocks, a control subblock Subblock1, a data subblock Subblock1, a data subblock Subblock2, and a data subblock Subblock3. Among them, the first data subblock may include a data subblock Subblock2, a data subblock Subblock3, and the second data subblock may include a data subblock Subblock1. The chip SoC10 and the subsystem 20 are connected through three groups of system buses, for example, a system bus Bus1, a system bus Bus2, and a system bus Bus3. Among them, the first system bus may include a system bus Bus2, and the second system bus may include a system bus Bus1. The system bus Bus1 is connected to the control subblock Subblock1 in the subsystem 20, and the chip SoC10 can control and access the control subblock Subblock1 through the system bus Bus1.

[0039] The system bus Bus2 is connected to the data sub-block Subblock2 in the subsystem 20, and the chip SOC10 can control access to the data sub-block Subblock2 through the system bus Bus2. The system bus Bus3 is connected to the data sub-block Subblock3 in the chip subsystem Subsystem. The chip SoC10 can control access to the data sub-block Subblock3 through the system bus Bus3. The control sub-block Subblock1 can also be connected to the data sub-block Subblock1 through a third system bus, and the control sub-block Subblock1 can control access to the data sub-block Subblock1 through the third system bus. Optionally, the data sub-block Subblock1 is managed by the control sub-block Subblock1, and is no longer directly managed by the chip SoC10.

[0040] The control sub-block is further used to control access to the first data sub-block through the second system bus and the first system bus.

[0041] Among them, the control subblock Subblock1 in the subsystem 20 can also control access to the data subblock Subblock2 in the subsystem 20 through the system bus Bus1 and the system bus Bus2, and control access to the data subblock Subblock3 in the subsystem 20 through the system bus Bus1 and the system bus Bus3.

[0042] In one embodiment, the control access between the chip SoC10 and the subsystem 20 is described by taking the reset Reset of the subsystem 20 controlled by the chip SoC10 as an example. The chip SoC10 controls the reset Reset of the control subblock Subblock1 and the data subblock Subblock1 in the subsystem 20 through the system bus Bus1. The chip SoC10 controls the reset Reset of the data subblock Subblock2 in the subsystem 20 through the system bus Bus2, and the chip SoC10 controls the reset Reset of the data subblock Subblock3 in the subsystem 20 through the system bus Bus3. Optionally, the control subblock Subblock1 in the subsystem 20 can also control the reset Reset of the data subblock Subblock2 in the subsystem 20 through the system bus Bus1 and the system bus Bus2, and can also control the reset Reset of the data subblock Subblock3 in the subsystem 20 through the system bus Bus1 and the system bus Bus3.

[0043] Exemplarily, the control access between chip SoC10 and subsystem 20 is described by taking chip SoC10 accessing the register of subsystem 20 as an example. If chip SoC10 allocates a register access space of 16KB for subsystem 20, the register access space of the control subblock Subblock1 in subsystem 20 after allocation is 4KB in size, and the address range is 0x0~0xFFF. The register access space of the data subblock Subblock1 in subsystem 20 is 4KB in size, and the address range is 0x1000~0x1FFF. The register access space of the data subblock Subblock2 in subsystem 20 is 4KB in size, and the address range is 0x2000~0x2FFF. The register access space of the data subblock Subblock3 in subsystem 20 is 4KB in size, and the address range is 0x3000~0x3FFF.

[0044] At this time, when the address range that the chip SoC10 needs to access is 0x0~0xFFF, the system bus Bus will be routed to the system bus Bus1, and the register access space of the control subblock Subblock1 in the subsystem 20 will be accessed through the system bus Bus1. Similarly, when the address range that the chip SoC10 needs to access is 0x1000~0x1FFF, the system bus Bus will be routed to the system bus Bus1, and the control subblock Subblock1 in the subsystem 20 will be accessed through the system bus Bus1, and the control subblock Subblock1 will then route the access to the register access space of the data subblock Subblock1 in the subsystem 20. When the address range that the chip SoC10 needs to access is 0x2000~0x2FFF, the system bus Bus will be routed to the system bus Bus2, and the register access space of the data subblock Subblock2 in the subsystem 20 will be accessed through the system bus Bus2. When the address range that the chip SoC needs to access is 0x3000-0x3FFF, the system bus Bus will be routed to the system bus Bus3, and the register access space of the data subblock Subblock3 in the subsystem 20 will be accessed through the system bus Bus3.

[0045] Optionally, when the RISC-V controller access address range of the control subblock Subblock1 in the subsystem 20 is 0x0~0xFFF and 0x1000~0x1FFF, the control subblock Subblock1 in the subsystem 20 will be routed to the register access space of the control subblock Subblock1 and the data subblock Subblock1. When the RISC-V controller access address range of the control subblock Subblock1 in the subsystem 20 is 0x2000~0x2FFF, the control subblock Subblock1 in the subsystem 20 will be routed to the register access space of the data subblock Subblock2 in the subsystem 20 through the system bus Bus1 and the system bus Bus2. When the RISC-V controller access address range of the control subblock Subblock1 in the subsystem 20 is 0x3000~0x3FFF, the control subblock Subblock1 in the subsystem 20 will be routed to the register access space of the data subblock Subblock3 in the subsystem 20 through the system bus Bus1 and the system bus Bus3.

[0046] In the above embodiments, the chip SoC and the subsystems can be controlled and accessed in a variety of ways, thereby improving the flexibility of chip SoC management.

[0047] In an embodiment of the present application, the control sub-block 21 is also used to receive the interrupt information of the data sub-block 22, and schedule the interrupt information of the data sub-block 22; and report the interrupt information after scheduling to the controller of the control sub-block 21 for interrupt processing, or report the interrupt information to the chip SoC10 for interrupt processing.

[0048] The management of the subsystem 20 by the chip SoC 10 also includes the interrupt processing of the subsystem 20 , and the interrupt reporting of the subsystem 20 includes the interrupt reporting of the control sub-block 21 and the interrupt reporting of the data sub-block 22 .

[0049] Both the control sub-block 21 and the data sub-block 22 include interrupt sources and may generate interrupts, so interrupt reporting is required. Since the MCU controller or RISC-V controller of the control sub-block 21 in the subsystem 20 includes an interrupt processing function, it is possible to choose to report the interrupt to the MCU controller or RISC-V controller of the control sub-block 21 for processing, or to report the interrupt to the chip SoC10. For the interrupt information of the data sub-block 22, for example Figure 3 In the data sub-block Subblock1, the control sub-block 21 receives the interrupt information of the data sub-block Subblock1 for scheduling processing. The interrupt information after scheduling processing can be reported to the controller of the control sub-block 21 for interrupt processing, or reported to the chip SoC10 for interrupt processing.

[0050] Optionally, the control sub-block 21 in the sub-system 20 may include 8-bit width interrupt sources {Int1, Int2, ..., Int7, Int8}, and the data sub-block 22 in the sub-system 20, such as Figure 3 The data subblock Subblock1, data subblock Subblock2 and data subblock Subblock3 may each include an 8-bit width interrupt source {Int1, Int2, ..., Int7, Int8}.

[0051] In one embodiment, the data sub-block 22 is further used to aggregate the interrupt information of the data sub-block 22 and report the aggregated interrupt information to the control sub-block 21 , or report the aggregated interrupt information to the chip SoC10 .

[0052] Among them, the interrupt sources of the data sub-block 22 in the subsystem 20 can all be directly aggregated to the control sub-block 21 through multiple interrupt lines, and the scheduling process is performed in the control sub-block 21. After the interrupt sources of the data sub-block 22 in the subsystem 20 are scheduled and processed in the control sub-block 21, they can be reported to the MCU controller or RISC-V controller in the control sub-block 21, or the interrupt information can be sent to the chip system SoC10 for processing.

[0053] Optionally, the interruption information includes the identifier of the subsystem 20 and the identifier of the interruption source, and the interruption information may also include information defined by the system user. The identifier of the subsystem 20 may be an identification number of the subsystem 20, such as Figure 4 As shown, the identity identification number is 1, indicating that the identification number of the subsystem 20 that sends the interrupt information is 1, and the subsystem 20 includes 1 control subblock Subblock and 3 data subblocks Subblock. The interrupt source identifier can be an interrupt source identification number, and the interrupt source identification number 0 can indicate that the interrupt information comes from the control subblock Subblock of the subsystem 20, the interrupt source identification number 1 can indicate that the interrupt information comes from the data subblock Subblock1 of the subsystem 20, the interrupt source identification number 2 can indicate that the interrupt information comes from the data subblock Subblock2 of the subsystem 20, and the interrupt source identification number 3 can indicate that the interrupt information comes from the data subblock Subblock3 of the subsystem 20. User-defined information can be defined by the user according to the needs, and the above interrupt information can be sent to the chip SoC10, so as to facilitate the chip SoC10 to perform interrupt processing according to the interrupt information.

[0054] In one embodiment, the data sub-block 22 is also used to schedule the interrupt information of the data sub-block 22, and report the interrupt information after scheduling to the control sub-block 21 for interrupt processing, or report the interrupt information to the chip SoC10 for interrupt processing.

[0055] The interrupt sources of the data sub-block 22 in the subsystem 20 can be aggregated into a single interrupt line after being scheduled once in the data sub-block 22, and then aggregated into the control sub-block 21 for scheduling in the control sub-block 21. Figure 4 As shown. The 8-bit interrupt source of the data subblock Subblock1 in the subsystem 20 is aggregated into a 1-bit interrupt sideband signal after a scheduling process in the data subblock Subblock1. Similarly, the data subblocks Subblock2 and Subblock3 are also aggregated into 1-bit interrupt sideband signals. At this time, the 1-bit interrupt sideband signals aggregated by the data subblocks Subblock1, Subblock2 and Subblock3 are then aggregated into the control subblock Subblock, and the scheduling process is performed in the control subblock Subblock.

[0056] In another case, the interrupt source of the data sub-block 22 in the subsystem 20 can be scheduled once in the data sub-block 22, and then the data sub-block 22 directly reports the interrupt information to the chip SoC10 for processing. Figure 3As shown. After the 8-bit-wide interrupt source of the data sub-block Subblock2 in the subsystem 20 completes the scheduling process in the data sub-block Subblock2, the interrupt information can be reported to the chip SoC10 through the system bus Bus2 for processing. Similarly, after the 8-bit-wide interrupt source of the data sub-block Subblock3 in the subsystem 20 completes the scheduling process in the data sub-block Subblock3, the interrupt information can be reported to the chip SoC10 through the system bus Bus3 for processing.

[0057] Optionally, each 8-bit wide interrupt source of the data sub-block Subblock1, data sub-block Subblock2 and data sub-block Subblock3 in the subsystem 20 is aggregated to the control sub-block Subblock through the interrupt sideband signal Sideband1, interrupt sideband signal Sideband2 and interrupt sideband signal Sideband3, and is scheduled and processed together with the 8-bit wide interrupt source in the control sub-block Subblock. The interrupt source scheduled in the control sub-block Subblock can be reported to the RISC-V controller in the control sub-block, or the interrupt information can be sent to the chip system SoC10 for processing.

[0058] In the above embodiment, by aggregating the interrupt sources in the data sub-block 22 and then reporting them, the amount of data reported in the interrupt information can be reduced, thereby improving the efficiency of reporting the interrupt information.

[0059] In an embodiment of the present application, the data sub-block 22 is also used to perform interrupt masking processing on the interrupt information, and report the interrupt information after the interrupt masking processing to the control sub-block 21, or report the interrupt information after the interrupt masking processing to the chip SoC10; the control sub-block 21 is also used to perform interrupt masking processing on the interrupt information, and report the interrupt information after the interrupt masking processing to the controller of the control sub-block 21, or report the interrupt information after the interrupt masking processing to the chip SoC10.

[0060] Among them, the interrupt source of the data sub-block 22 in the subsystem 20 can be shielded by interrupt masking processing to shield the interrupt source that does not need to be reported, and the selection after the scheduling processing of the control sub-block 21 can also be shielded by interrupt masking processing. Optionally, interrupt processing can be performed by adding interrupt masking bits, for example, the corresponding data position of the interrupt source that needs to be masked is set to 1 to perform interrupt masking processing. The data sub-block 22 or the control sub-block 21 can report the interrupt information after the masking processing to the controller of the control sub-block 21, or report the interrupt information after the interrupt masking processing to the chip SoC10. Optionally, as Figure 4As shown, each 1 bit of each 8-bit width interrupt source of the data sub-block Subblock1, the data sub-block Subblock2 and the data sub-block Subblock3 in the subsystem 20 can be shielded by interrupt masking. When the interrupt source generates an interrupt, the interrupt is shielded and not aggregated to the control sub-block 21.

[0061] In the above embodiment, after the interrupt masking process, the interrupt sources that do not need to be reported are masked to avoid generating too many interrupts that need to be processed by the control sub-block 21 or the chip SoC10, thereby affecting the operating efficiency of the control sub-block 21 or the chip SoC10.

[0062] Optionally, the data sub-block 22 also includes an interrupt setting signal, which is used to generate a debug interrupt source, and the debug interrupt source is used to generate debug interrupt information so that the data sub-block 22 tests the interrupt reporting path of the data sub-block 22 through the debug interrupt information; the control sub-block 21 also includes an interrupt setting signal, which is used to generate a debug interrupt source, and the debug interrupt source is used to generate debug interrupt information so that the control sub-block 21 tests the interrupt reporting path of the control sub-block 21 through the debug interrupt information.

[0063] Optionally, an interrupt setting signal, such as a SET signal, may be added to the control sub-block 21 and the data sub-block 22 in the subsystem 20 to debug the interrupt reporting path. If the function of the interrupt processing reporting path needs to be tested when the functional business is not required, a debug interrupt source may be generated by setting an interrupt signal for each 1-bit interrupt source. The debug interrupt source is used to generate debug interrupt information. The data sub-block 22 tests the interrupt reporting path of the data sub-block 22 through the debug interrupt information, and aggregates the interrupt to the control sub-block 21. The control sub-block 21 may generate debug interrupt information through the debug interrupt source, so that the control sub-block 21 tests the interrupt reporting path of the control sub-block 21 through the debug interrupt information.

[0064] Optionally, the interrupt information may be reported in an ACK (Acknowledge character) manner to communicate with the control sub-block 21 or the chip SoC 10. Figure 5As shown, the interrupt information reported by the control sub-block 21 and the data sub-block 22 in the subsystem 20 may include N interrupt information, for example, {Int Cookie1, Int Cookie2, ..., Int Cookien, ..., Int CookieN}, where Int Cookien is the interrupt information of the nth interrupt, and the range of n is 1 to N. After the control sub-block 21 and the data sub-block 22 in the subsystem 20 report the interrupt information, the chip SoC10 will return an ACK indication signal through the system bus Bus, indicating that the chip SoC has successfully received the interrupt information sent by the subsystem 20 and can perform interrupt processing.

[0065] In the above embodiment, by adding an interrupt setting signal, it can be used to debug the interrupt information reporting path of the control sub-block or the data sub-block, which is convenient for users.

[0066] In an embodiment of the present application, the present application further provides an electronic device, the electronic device comprising a chip SoC10 as described in any one of the above embodiments. The electronic device may be a mobile phone, a mobile power supply, an electric car, a laptop computer, a drone, a tablet computer, an e-book, an electronic cigarette, a wearable device (such as a watch, a bracelet, smart glasses, etc.), a robot (such as a sweeping robot, a floor scrubber, etc.), a wireless headset, a Bluetooth speaker, a radio mouse, etc., and the present application embodiment does not limit this.

[0067] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0068] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0069] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0070] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A system-on-chip (SoC), characterized in that: The chip SoC includes a plurality of subsystems, wherein the subsystem includes a control sub-block and a data sub-block, wherein the data sub-block can be controlled and accessed by the chip SoC, or the data sub-block can be controlled and accessed by the control sub-block; The interrupt information of the data sub-block may be reported to the control sub-block for interrupt processing, or the interrupt information of the data sub-block may be reported to the chip SoC for interrupt processing; The data sub-blocks include a first data sub-block and a second data sub-block; The chip SoC is connected to the first data sub-block via a first system bus to control access to the first data sub-block; The chip SoC is connected to the control sub-block via a second system bus to control access to the control sub-block; The control sub-block is further used to connect to the second data sub-block via a third system bus to control access to the second data sub-block; The control sub-block is further used to control access to the first data sub-block through the second system bus and the first system bus; The control sub-block is further used to receive the interruption information of the data sub-block and perform scheduling processing on the interruption information of the data sub-block; The interrupt information after scheduling is reported to the controller of the control sub-block for interrupt processing, or the interrupt information is reported to the chip SoC for interrupt processing.

2. The chip SoC according to claim 1, characterized in that: The data sub-block is also used to schedule the interrupt information of the data sub-block, and report the interrupt information after scheduling to the control sub-block for interrupt processing, or report the interrupt information to the chip SoC for interrupt processing.

3. The chip SoC according to claim 2, characterized in that: The data sub-block is further used to aggregate the interrupt information of the data sub-blocks and report the aggregated interrupt information to the control sub-block, or report the aggregated interrupt information to the chip SoC.

4. The chip SoC according to claim 2, characterized in that: The data sub-block is further used to perform interrupt masking processing on the interrupt information, and report the interrupt information after the interrupt masking processing to the control sub-block, or report the interrupt information after the interrupt masking processing to the chip SoC; The control sub-block is further used to perform the interrupt masking process on the interrupt information, and report the interrupt information after the interrupt masking process to the controller of the control sub-block, or report the interrupt information after the interrupt masking process to the chip SoC.

5. The chip SoC according to claim 2, characterized in that: The data sub-block further includes an interrupt setting signal, wherein the interrupt setting signal is used to generate a debug interrupt source, and the debug interrupt source is used to generate debug interrupt information, so that the data sub-block tests the interrupt reporting path of the data sub-block through the debug interrupt information; The control sub-block also includes an interrupt setting signal, which is used to generate a debug interrupt source, and the debug interrupt source is used to generate debug interrupt information, so that the control sub-block tests the interrupt reporting path of the control sub-block through the debug interrupt information.

6. The chip SoC according to any one of claims 1 or 5, characterized in that: The interruption information includes the identifier of the subsystem and the identifier of the interruption source.

7. The chip SoC according to claim 1, characterized in that: The control sub-block includes a controller.

8. The chip SoC according to claim 1, characterized in that: The data sub-block does not include a controller.

9. The chip SoC according to claim 1, characterized in that: The interrupt information is reported in an ACK manner for communication.

10. An electronic device, characterized in that: The electronic device comprises a chip SoC as described in any one of claims 1 to 9 above.

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