Display device

Abstract

The present disclosure relates to a display device including: a pixel; and a first scan driving circuit that applies a write scan signal to the pixels in response to the write clock signal. The first scan driving circuit outputs a write scan signal having a first operating frequency in a normal mode, and outputs a write scan signal having a second operating frequency lower than the first operating frequency in a low frequency mode. The write clock signal has a direct current (DC) level in a low frequency mode in response to a first setting signal applied to the first scan drive circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0082409 filed in the Korean Intellectual Property Office on June 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a scan driving circuit and a display device including the scan driving circuit. Background Art

[0004] Generally, electronic devices that provide images to users, such as smart phones, digital cameras, notebook computers, navigation systems, and smart TVs, include a display device for displaying images. The display device generates images and provides the generated images to the user through a display screen.

[0005] The display device includes a plurality of pixels for generating an image, a scan driving circuit for applying a scan signal to the pixel, a data driver for applying a data voltage to the pixel, and a light emitting driver for applying an emission signal to the pixel. The pixel receives the data voltage in response to the scan signal. The pixel displays an image by emitting light of a brightness corresponding to the data voltage in response to the emission signal.

[0006] The pixel can display video and still images. When the pixel displays video, the pixel can receive images that are continuously updated in this way. When the pixel displays a still image, the pixel retains the image initially provided and may not receive subsequent images. Summary of the invention

[0007] Embodiments of the present disclosure provide a scan driving circuit capable of reducing power consumption and a display device including the scan driving circuit.

[0008] According to an embodiment, a display device includes: a pixel; and a first scan drive circuit that applies a write scan signal to the pixel in response to a write clock signal. The first scan drive circuit outputs the write scan signal having a first operating frequency in a normal mode, and outputs the write scan signal having a second operating frequency lower than the first operating frequency in a low frequency mode. The write clock signal has a direct current (DC) level in the low frequency mode in response to a first setting signal applied to the first scan drive circuit.

[0009] According to an embodiment, a display device includes: a pixel receiving a scan signal; and a scan driving circuit outputting the scan signal having a first operating frequency during a normal mode, and outputting the scan signal having a second operating frequency less than the first operating frequency during a low frequency mode. The scan driving circuit includes: a first node controller connected to a first node and a second node, and the first node controller receives a first high voltage, a first low voltage, a start signal, a first clock signal, and a second clock signal, and controls a voltage level of the first node and a voltage level of the second node, the first low voltage having a level lower than that of the first high voltage, and the second clock signal having a phase opposite to that of the first clock signal; a first buffer part connected to the first node and receiving the first high voltage; a second buffer part connected to the second node, and the second buffer part receiving one of the first clock signal and the second clock signal or the first low voltage; and a switch element connected to the second node and an input terminal for receiving the start signal, and switched by a setting signal. The first buffer part and the second buffer part output the scan signal according to the voltage level of the first node and the voltage level of the second node. When the scan signal is not applied to the pixel in the low frequency mode, the switching element is turned off in response to the setting signal.

[0010] According to an embodiment, a scan driving circuit includes: a node controller connected to a first node and a second node, and the node controller receives a first high voltage, a first low voltage, a start signal, a first clock signal, and a second clock signal, and controls a voltage level of the first node and a voltage level of the second node, the first low voltage having a level lower than that of the first high voltage, and the second clock signal having a phase opposite to that of the first clock signal; a first buffer part connected to the first node and receiving the first high voltage; a second buffer part connected to the second node and receiving one of the first clock signal and the second clock signal or the first low voltage; and a setting part connected to the first node and the second node, and the setting part receives the first high voltage, the first low voltage, and a setting signal. The first buffer part and the second buffer part output a scan signal according to the voltage level of the first node and the voltage level of the second node. The setting part sets the voltage level of the first node and the voltage level of the second node in response to the setting signal, so that the disabled scan signal is output. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0012] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0013] Figure 2 It is shown Figure 1 FIG. 4 is a diagram of a cross section of a display device shown in FIG.

[0014] Figure 3 It is shown Figure 2 FIG. 4 is a diagram of a cross section of a display panel shown in FIG.

[0015] Figure 4A is a diagram for describing the operation of the display device in a normal mode.

[0016] Figure 4B is a diagram for describing the operation of the display device in the low frequency mode.

[0017] Figure 5 is a block diagram of a display device according to an embodiment of the present disclosure.

[0018] Figure 6 It is shown Figure 5 A diagram of an equivalent circuit of one pixel among the pixels shown in .

[0019] Figure 7 Is used to describe Figure 6 0 is a timing diagram of scanning signals and emission signals for the operation of a pixel shown in FIG.

[0020] Figure 8 is a diagram showing timings of scan signals and emission signals applied to pixels in one frame.

[0021] Fig. 9 When Figure 6 0 is a timing diagram of scanning signals and emission signals when the pixel shown in 0 operates in the normal mode.

[0022] Fig.10 When Figure 6 is a timing diagram of scanning signals and emission signals when the pixel shown in is operated in the low frequency mode.

[0023] Fig.11 yes Figure 5 0 is a block diagram of a first scan driving circuit of the scan driving circuit shown in .

[0024] Fig.12 It is shown Fig.11 The circuit configurations of the first and second stages are shown in the diagram.

[0025] Fig.13is shown in the normal mode from Fig.11 2 is a diagram showing the timing of the write scan signal output by the stage shown in FIG.

[0026] Fig.14 is shown in the low frequency mode from Fig.11 2 is a diagram showing the timing of the write scan signal output by the stage shown in FIG.

[0027] Fig.15 is a diagram showing the timing of the first and second clock signals, the write scan signal, and the first setting signal in the normal mode.

[0028] Fig.16 is a diagram showing the timing of the first and second clock signals, the write scan signal, and the first setting signal in the low frequency mode.

[0029] Fig.17 is a diagram showing the timing of the write clock signal in the low frequency mode.

[0030] Fig.18 is a diagram showing the timing of the first setting signal in the low frequency mode.

[0031] Fig.19 is a diagram showing a circuit configuration of a first stage and a second stage of a first scan driving circuit according to an embodiment of the present disclosure.

[0032] Fig. 20 is a diagram showing a circuit configuration of a first stage and a second stage of a first scan driving circuit according to an embodiment of the present disclosure.

[0033] Fig.21 is shown in the low frequency mode applied to Fig. 20 3 is a diagram showing the timing of the control signals of the switching elements shown in FIG.

[0034] Fig. 22 yes Figure 5 0 is a block diagram of a second scan driving circuit of the scan driving circuit shown in .

[0035] Fig.23 It is shown Fig. 22 The circuit configurations of the first and second stages are shown in the diagram.

[0036] Fig.24 is shown in the normal mode from Fig. 22 2 is a diagram showing the timing of the initialization scan signal output by the stage shown in FIG.

[0037] Fig.25 is shown in the low frequency mode from Fig. 22 2 is a diagram showing the timing of the initialization scan signal output by the stage shown in FIG.

[0038] Fig.26is a diagram showing the timing of the third and fourth clock signals, the initialization scan signal, and the second setting signal in the normal mode.

[0039] Fig. 27 is a diagram showing the timing of the third and fourth clock signals, the initialization scan signal, and the second setting signal in the low frequency mode.

[0040] Fig.28 is a diagram showing a circuit configuration of a first stage and a second stage of a second scan driver according to an embodiment of the present disclosure.

[0041] Fig.29 is a diagram showing the timing of a transmission clock, a transmission signal, and a bias scanning signal in a normal mode and a low frequency mode. DETAILED DESCRIPTION

[0042] In the specification, the statement that a first component (or region, layer, part, etc.) is "on" a second component, "connected to" a second component, or "coupled to" a second component means that the first component is directly on, directly connected to, or directly coupled to the second component, or that a third component is between the first component and the second component.

[0043] The same reference numerals denote the same components. In addition, in the drawings, in order to effectively describe the technical contents, the thickness, ratio and size of the components are exaggerated.

[0044] The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] Although the terms "first", "second", etc. can be used to describe various components, these components should not be interpreted as being limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope and spirit of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. The articles "a", "one", and "the" are singular when they have a single referent, but in the specification, the use of the singular form should not exclude the presence of more than one referent.

[0046] In addition, the terms "below", "under", "on", "over", etc. are used to describe the relationship between components shown in the drawings. These terms are relative and are described with reference to the directions indicated in the drawings.

[0047] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formal sense.

[0048] It will also be understood that the terms “comprises,” “including,” “having,” etc. indicate the presence of the stated features, numbers, steps, operations, elements, components, or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0049] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0050] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0051] Reference Figure 1 The display device DD according to an embodiment of the present disclosure may have long sides extending in the first direction DR1, and may have short sides extending in the second direction DR2 crossing the first direction DR1. Each of the corners of the display device DD may also have a rounded shape. Figure 1 The shape of the display device DD shown in FIG. 1 is shown as an example, and the shape of the display device DD is not limited to Figure 1 The shapes shown in .

[0052] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3.

[0053] When viewed in the third direction DR3, the image IM generated by the display device DD may be provided to the user through the upper surface of the display device DD. The upper surface of the display device DD may include a display area DA and a non-display area NDA around the display area DA. The display area DA may display the image IM, and the non-display area NDA may not display the image IM. The non-display area NDA may surround the display area DA and may define a boundary of the display device DD printed in a predetermined color.

[0054] The display device DD is shown as a mobile phone, but is not limited thereto. For example, the display device DD can be used in various electronic devices. For example, the display device DD can be used in large electronic devices such as televisions, monitors, or outdoor billboards. In addition, the display device DD can be used in small and medium-sized electronic devices such as personal computers (e.g., notebook computers or tablet computers), car navigation systems, game consoles, or cameras.

[0055] Figure 2 It is shown Figure 1 FIG. 4 is a diagram of a cross section of a display device shown in FIG.

[0056] Figure 2 A cross section of the display device DD when viewed in a first direction DR1 is shown.

[0057] Reference Figure 2 , the display device DD may include a display panel DP, an input sensing part ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first and second adhesive layers AL1 and AL2.

[0058] According to an embodiment of the present disclosure, the display panel DP may include a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots or quantum rods, etc. In the following, it is described that the display panel DP is an organic light-emitting display panel.

[0059] The input sensing part ISP may be disposed on the display panel DP. The input sensing part ISP may include a plurality of sensing parts (not shown) for sensing external input in a capacitive scheme. When the display device DD is manufactured, the input sensing part ISP may be directly formed on the display panel DP. However, the embodiment is not limited thereto, and the input sensing part ISP may be manufactured as a panel separated from the display panel DP and attached to the display panel DP through an adhesive layer.

[0060] The anti-reflection layer RPL may be disposed on the input sensing part ISP. When the display device DD is manufactured, the anti-reflection layer RPL may be directly formed on the input sensing part ISP. However, the embodiment is not limited thereto, and the anti-reflection layer RPL may be manufactured as a separate plate and attached to the input sensing part ISP through an adhesive layer.

[0061] The anti-reflection layer RPL may be an external light anti-reflection film. The anti-reflection layer RPL may reduce the reflectivity of external light incident from the top surface of the display device DD toward the display panel DP. Due to the anti-reflection layer RPL, the external light may not be perceived by the user.

[0062] When external light directed to the display panel DP is reflected from the display panel DP and provided to an external user again, the user may visually perceive the external light (like a mirror). To prevent this phenomenon, the anti-reflection layer RPL may include a plurality of color filters for displaying the same color as the color displayed by the pixels of the display panel DP.

[0063] The color filter may filter the external light into the same color as the color displayed by the pixel. In this case, the external light may not be perceived by the user. However, the embodiment is not limited thereto, and the anti-reflection layer RPL may include a phase retarder and / or a polarizer to reduce the reflectivity of the external light.

[0064] The window WIN may be disposed on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensing part ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0065] The panel protection film PPF may be disposed under the display panel DP. The panel protection film PPF may protect the bottom surface of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).

[0066] The first adhesive layer AL1 may be interposed between the display panel DP and the panel protection film PPF, and the display panel DP and the panel protection film PPF may be bonded to each other through the first adhesive layer AL1. The second adhesive layer AL2 may be interposed between the window WIN and the anti-reflection layer RPL, and the window WIN and the anti-reflection layer RPL may be bonded to each other through the second adhesive layer AL2.

[0067] Figure 3 It is shown Figure 2 FIG. 4 is a diagram of a cross section of a display panel shown in FIG.

[0068] Figure 3 A cross section of the display panel DP when viewed in the first direction DR1 is shown.

[0069] Reference Figure 3 The display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0070] The substrate SUB may include a display area DA and a non-display area NDA around the display area DA. The substrate SUB may include a flexible plastic material such as glass or polyimide (PI). The display element layer DP-OLED may be disposed in the display area DA.

[0071] The plurality of pixels may include a circuit element layer DP-CL and a display element layer DP-OLED. Each of the pixels may include a transistor disposed in the circuit element layer DP-CL and a light emitting element disposed in the display element layer DP-OLED and connected to the transistor.

[0072] The thin film encapsulation layer TFE may be disposed on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the pixels from moisture, oxygen, and foreign substances.

[0073] Figure 4A is a diagram for describing the operation of the display device in a normal mode. Figure 4B is a diagram for describing the operation of the display device in the low frequency mode.

[0074] Reference Figure 4A and Figure 4B , the display device DD can be driven by a normal mode NFD and a low frequency mode LFD. The normal mode NFD can be defined as a video mode for displaying a video DIM. The low frequency mode LFD can be defined as a still image mode for displaying a still image SIM. In the normal mode NFD, the display device DD can display a video DIM. In the low frequency mode LFD, the display device DD can display a still image SIM.

[0075] In the normal mode NFD, the display device DD may be driven at a first operating frequency (or a normal frequency). In the low frequency mode LFD, the display device DD may be driven at a second operating frequency. The second operating frequency may be lower than the first operating frequency.

[0076] Reference Figure 4A , also refer to Figure 3 , when the display device DD displays the video DIM in the normal mode NFD, the first operating frequency may be set to 120 Hz. For example, 120 images IM1 may be provided to the display panel DP at 120 frames per second. The images IM1 of the first frame F1, the second frame F2, the third frame F3, the fourth frame F4, ..., the 118th frame F118, the 119th frame F119, and the 120th frame F120 every 1 second are provided to the display panel DP, and the video DIM may be displayed.

[0077] From the first frame F1 to the 120th frame F120, the image IM1 may be updated and provided to the display panel DP. In order to display the video DIM, during the first frame F1 to the 120th frame F120, the image IM1 of the current frame is different from the image IM1 of the previous frame and may be the image IM1 updated from the previous frame. In order to display the video DIM, the continuously updated image IM1 may be provided to the display panel DP.

[0078] Reference Figure 4B , also refer to Figure 3, when the display device DD displays the still image SIM in the low frequency mode LFD, the second operating frequency may be set to 1 Hz. In this case, in the first frame F1, the image IM2 may be provided to the display panel DP. During the second frame F2 to the 120th frame F120, the image IM2 may not be provided to the display panel DP. That is, the second operating frequency may be set to 1 Hz, so that the image IM2 may be provided to the display panel DP once every 1 second.

[0079] In the low frequency mode LFD, the display panel DP may maintain the image IM2 received in the first frame F1 during the second frame F2 to the 120th frame F120. For example, the pixel may store and display the image IM2 received during the first frame F1, and may display the image IM2 by maintaining the image IM2 during the second frame F2 to the 120th frame F120. Therefore, the image IM2 may remain unchanged so that the still image SIM is displayed.

[0080] For example, video may refer to images that change in real time like a movie. Still images may refer to non-moving images such as a keyboard.

[0081] The second operating frequency is set to 1 Hz, but is not limited thereto. For example, the second operating frequency may be variously changed to 60 Hz, 30 Hz, and 10 Hz, etc. That is, the display panel DP may receive an image 60 times, 30 times, or 10 times per second. In this case, in each of the frames in which an image is not received among the 120 frames, an image of a previous frame may be maintained.

[0082] Figure 5 is a block diagram of a display device according to an embodiment of the present disclosure.

[0083] Reference Figure 5 , the display device DD includes a display panel DP, a driving controller 100, a data driving circuit 200, a scan driving circuit SDC, an emission driving circuit EDC, and a voltage generator 300. The driving controller 100 may be defined as a timing controller.

[0084] The display panel DP may include a plurality of scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn, a plurality of emission lines EML1 to EMLn, a plurality of data lines DL1, DL2, . . . , and DLm, and a plurality of pixels PX. “n” and “m” may be natural numbers greater than zero.

[0085] In a plan view, the area of ​​the display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA. The pixels PX may be located in the display area DA. The pixels PX may be electrically connected to the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn, the emission lines EML1 to EMLn, and the data lines DL1 to DLm.

[0086] Each of the plurality of pixels PX may be electrically connected to corresponding four scan lines and a corresponding one emission line. For example, the pixel PX of the jth row may be connected to the jth scan lines GILj, GCLj, GWLj, and GBLj and the jth emission line EMLj. "j" may be a natural number greater than or equal to 1 and less than or equal to n.

[0087] The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn may include a plurality of initialization scan lines GIL1 to GILn, a plurality of compensation scan lines GCL1 to GCLn, a plurality of write scan lines GWL1 to GWLn, and a plurality of bias scan lines GBL1 to GBLn.

[0088] Each of the pixels PX may be connected to a corresponding one of the initialization scan lines GIL1 to GILn, a corresponding one of the compensation scan lines GCL1 to GCLn, a corresponding one of the write scan lines GWL1 to GWLn, and a corresponding one of the bias scan lines GBL1 to GBLn.

[0089] The scan driving circuit SDC may be located on the first side of the display panel DP. The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn may extend from the scan driving circuit SDC in the second direction DR2.

[0090] The emission driving circuit EDC may be located on the second side of the display panel DP. The emission lines EML1 to EMLn may extend from the emission driving circuit EDC in a direction opposite to the second direction DR2.

[0091] exist Figure 5 In the example shown in , the scan driving circuit SDC and the emission driving circuit EDC are positioned to face each other, and the pixel PX is interposed between the scan driving circuit SDC and the emission driving circuit EDC, but the present disclosure is not limited thereto. For example, the scan driving circuit SDC and the emission driving circuit EDC may be positioned adjacent to each other on one of the first side and the second side of the display panel DP. In an embodiment, the scan driving circuit SDC and the emission driving circuit EDC may be implemented in one circuit.

[0092] The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn and the emission lines EML1 to EMLn may be spaced apart from each other in the first direction DR1. The data lines DL1 to DLm may extend from the data driving circuit 200 in a direction opposite to the first direction DR1 and may be spaced apart from each other in the second direction DR2.

[0093] The driving controller 100 may receive the image signal RGB, the control signal CTRL, and the mode signal MFD_EN. The driving controller 100 may generate the image data signal DS by converting the data format of the image signal RGB to be suitable for the interface specification of the data driving circuit 200. The driving controller 100 may output the scan control signal SCS, the data control signal DCS, and the emission control signal ECS in response to the control signal CTRL.

[0094] The data driving circuit 200 may receive a data control signal DCS and an image data signal DS from the driving controller 100. The data driving circuit 200 may convert the image data signal DS into a data signal and may output the converted data signal. The data signal may be defined as an analog voltage corresponding to the grayscale of the image data signal DS. The data signal may be applied to the pixel PX through the data lines DL1 to DLm.

[0095] The voltage generator 300 may generate voltages required for operating the display panel DP. The voltage generator 300 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage AINT. The first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT, and the second initialization voltage AINT may be applied to the pixel PX.

[0096] The scan driving circuit SDC may receive a scan control signal SCS from the driving controller 100. The scan driving circuit SDC may output a scan signal to the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn in response to the scan control signal SCS. The scan signal may be applied to the pixels PX through the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn.

[0097] The emission driving circuit EDC may receive an emission control signal ECS from the driving controller 100. The emission driving circuit EDC may output an emission signal to the emission lines EML1 to EMLn in response to the emission control signal ECS. The emission signal may be applied to the pixel PX through the emission lines EML1 to EMLn.

[0098] The driving controller 100 may determine the operation mode in response to the mode signal MFD_EN. In an embodiment, the mode signal MFD_EN may indicate whether the operation mode is a normal mode or a low frequency mode. In an embodiment, the mode signal MFD_EN may be provided from a host processor (eg, a graphics processor or an application processor).

[0099] When the operation mode is the normal mode, the driving controller 100 may drive the display panel DP at a first operation frequency. When the operation mode is the low frequency mode, the driving controller 100 may drive the display panel DP at a second operation frequency.

[0100] When the operation mode is the low frequency mode, the driving controller 100 may change the clock signal applied to the scan driving circuit from alternating current (AC) to direct current (DC). Hereinafter, this operation will be described in detail.

[0101] The pixel PX may receive a data voltage in response to the scan signal, and may display an image by emitting light having a brightness corresponding to the data voltage in response to the emission signal.

[0102] Figure 6 It is shown Figure 5 A diagram of an equivalent circuit of one pixel among the pixels shown in .

[0103] Figure 6 Pixels PXij connected to the i-th data line DLi, the j-th scan lines GWLj, GCLj, GILj and GBLj, and the j-th emission line EMLj are shown. "i" may be a natural number greater than or equal to 1 and less than or equal to m, and "j" may be a natural number greater than or equal to 1 and less than or equal to n.

[0104] Reference Figure 6 , the pixel PXij may include a pixel circuit PC and a light emitting element OLED connected to the pixel circuit PC. The pixel circuit PC may drive the light emitting element OLED.

[0105] The pixel circuit PC may include a plurality of transistors T1 to T8 and a capacitor CST. The transistors T1 to T8 and the capacitor CST may control the amount of current flowing through the light emitting element OLED. The light emitting element OLED may generate light with a predetermined brightness according to the amount of current supplied to the light emitting element OLED.

[0106] The jth write scan line GWLj may receive the jth write scan signal GWj. The jth compensation scan line GCLj may receive the jth compensation scan signal GCj. The jth initialization scan line GILj may receive the jth initialization scan signal GIj. The jth bias scan line GBLj may receive the jth bias scan signal GBj. The jth emission line EMLj may receive the jth emission signal EMj.

[0107] Pixel PXij can be connected to the i-th data line DLi, the j-th write scan line GWLj, the j-th compensation scan line GCLj, the j-th initialization scan line GILj, the j-th bias scan line GBLj, the j-th emission line EMLj, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL, and the first power line PL1 and the second power line PL2.

[0108] The first initialization line VIL1 may supply a first initialization voltage VINT. The second initialization line VIL2 may supply a second initialization voltage AINT. The bias line VBL may supply a bias voltage VBIAS. The first power line PL1 may supply a first driving voltage ELVDD. The second power line PL2 may supply a second driving voltage ELVSS.

[0109] Each of the transistors T1 to T8 may include a source electrode, a drain electrode, and a gate electrode. Figure 5 In the embodiment, one of the source electrode and the drain electrode is defined as a first electrode, and the other of the source electrode and the drain electrode is defined as a second electrode. In addition, the gate electrode is defined as a control electrode.

[0110] The transistors T1 to T8 may include first to eighth transistors T1 to T8. The first transistor T1, the second transistor T2, and the fifth to eighth transistors T5 to T8 may be PMOS transistors. The third transistor T3 and the fourth transistor T4 may be NMOS transistors.

[0111] The first transistor T1 may be defined as a driving transistor. The second transistor T2 may be defined as a switching transistor. The third transistor T3 may be defined as a compensation transistor. The fourth transistor T4 and the seventh transistor T7 may be defined as initialization transistors. The fifth transistor T5 and the sixth transistor T6 may be defined as emission control transistors. The eighth transistor T8 may be defined as a bias transistor.

[0112] The light emitting element OLED may be an organic light emitting element. The light emitting element OLED may include an anode AE ​​and a cathode CE. The anode AE ​​may receive a first driving voltage ELVDD through the sixth transistor T6, the first transistor T1, and the fifth transistor T5. The first driving voltage ELVDD may be applied to the pixel circuit PC through the first power line PL1.

[0113] The cathode CE may receive a second driving voltage ELVSS having a lower level than the first driving voltage ELVDD. The second driving voltage ELVSS may be applied to the pixel circuit PC through the second power line PL2.

[0114] The first transistor T1 may be interposed between and connected to the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may be connected to the first power line PL1 through the fifth transistor T5 and may be connected to the anode AE ​​through the sixth transistor T6.

[0115] The first transistor T1 may include a first electrode connected to the first power line PL1 through a fifth transistor T5 , a second electrode connected to the anode AE ​​through a sixth transistor T6 , and a control electrode connected to the first node N1 .

[0116] The first electrode of the first transistor T1 may be connected to the fifth transistor T5. The second electrode of the first transistor T1 may be connected to the sixth transistor T6. The first transistor T1 may control the amount of current flowing through the light emitting element OLED according to a voltage applied to the control electrode of the first transistor T1 by the first node N1.

[0117] The second transistor T2 may be interposed between the first transistor T1 and the i-th data line DLi and connected to the first transistor T1 and the i-th data line DLi. The second transistor T2 may include a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the j-th write scan line GWLj.

[0118] The second transistor T2 may be turned on in response to a j-th write scan signal GWj received through the j-th write scan line GWLj to electrically connect the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 may perform a switching operation to supply a data voltage VD (corresponding to the above-mentioned data signal) supplied from the i-th data line DLi to the first electrode of the first transistor T1.

[0119] The third transistor T3 may be interposed between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the jth compensation scan line GCLj.

[0120] The third transistor T3 may be turned on in response to the jth compensation scan signal GCj supplied from the jth compensation scan line GCLj to electrically connect the second electrode of the transistor T1 and the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 may be diode-connected.

[0121] The fourth transistor T4 may be connected to the first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the first initialization line VIL1, and a control electrode connected to the j-th initialization scan line GILj. The fourth transistor T4 may be turned on in response to a j-th initialization scan signal GIj supplied from the j-th initialization scan line GILj to provide the first initialization voltage VINT supplied from the first initialization line VIL1 to the first node N1.

[0122] The fifth transistor T5 may include a first electrode connected to the first power line PL1 , a second electrode connected to the first electrode of the first transistor T1 , and a control electrode connected to the j-th emission line EMLj.

[0123] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE, and a control electrode connected to the j-th emission line EMLj.

[0124] The fifth transistor T5 and the sixth transistor T6 may be turned on in response to the jth emission signal EMj supplied from the jth emission line EMLj. The first driving voltage ELVDD may be provided to the light emitting element OLED through the turned-on fifth transistor T5 and the turned-on sixth transistor T6, so that the driving current Id can flow through the light emitting element OLED. Therefore, the light emitting element OLED may emit light.

[0125] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the j-th bias scan line GBLj. The seventh transistor T7 is turned on in response to the j-th bias scan signal GBj supplied from the j-th bias scan line GBLj to supply the second initialization voltage AINT received from the second initialization line VIL2 to the anode AE ​​of the light emitting element OLED.

[0126] In an embodiment of the present disclosure, the seventh transistor T7 may be omitted. In an embodiment of the present invention, the second initialization voltage AINT may have a different level from the first initialization voltage VINT, but is not limited thereto. For example, the second initialization voltage AINT may have the same level as the first initialization voltage VINT. In this document, "level" and "voltage level" may have substantially the same meaning.

[0127] The seventh transistor T7 can improve the black performance of the pixel PXij. When the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the light emitting element OLED can be discharged. When black brightness is achieved, the light emitting element OLED may not emit light due to the leakage current from the first transistor T1, thereby improving the black performance.

[0128] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth and sixth transistors T5 and T6 are turned on, the amount of current flowing through the first transistor T1 may be determined according to the voltage stored in the capacitor CST.

[0129] The eighth transistor T8 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the j-th bias scan line GBLj.

[0130] The eighth transistor T8 may be turned on in response to the j-th bias scan signal GBj to provide the bias voltage VBIAS to the first electrode of the first transistor T1 .

[0131] Figure 7 Is used to describe Figure 6 0 is a timing diagram of scanning signals and emission signals for the operation of a pixel shown in FIG.

[0132] Reference Figure 6 and Figure 7 , the j-th transmission signal EMj may have a high level during the non-transmission period NLP, and have a low level during the transmission period LP.

[0133] An effective period of each of the jth write scan signal GWj and the jth bias scan signal GBj may be defined at a low level of each of the jth write scan signal GWj and the jth bias scan signal GBj.

[0134] An effective period of each of the j-th compensation scan signal GCj and the j-th initialization scan signal GIj may be defined at a high level of each of the j-th compensation scan signal GCj and the j-th initialization scan signal GIj.

[0135] After the jth initialization scan signal GIj is activated, the jth compensation scan signal GCj and the jth write scan signal GWj may be activated. Thereafter, the jth bias scan signal GBj may be activated.

[0136] During the non-emission period NLP, the activated jth initialization scan signal GIj, the activated jth compensation scan signal GCj, the activated jth write scan signal GWj, and the activated jth bias scan signal GBj may be applied to the pixel PXij.

[0137] The jth initialization scan signal GIj may be applied to the fourth transistor T4 so that the fourth transistor T4 is turned on. The first initialization voltage VINT may be provided to the first node N1 through the fourth transistor T4. Therefore, the first initialization voltage VINT may be applied to the control electrode of the first transistor T1, and the first transistor T1 may be initialized by the first initialization voltage VINT. This operation may be defined as an initialization operation.

[0138] The jth write scan signal GWj may be applied to the second transistor T2 so that the second transistor T2 is turned on. In addition, the jth compensation scan signal GCj may be applied to the third transistor T3 so that the third transistor T3 is turned on.

[0139] The first transistor T1 may be diode-connected. In this case, a compensation voltage "VD-Vth" obtained by subtracting a threshold voltage (Vth) of the first transistor T1 from a data voltage VD supplied via the i-th data line DLi may be applied to a control electrode of the first transistor T1. This operation may be defined as a write operation (or programming operation) or a compensation operation.

[0140] The first driving voltage ELVDD and the compensation voltage "VD-Vth" may be applied to the first electrode of the capacitor CST and the second electrode of the capacitor CST, respectively. Charge corresponding to the difference between the voltage of the first electrode of the capacitor CST and the voltage of the second electrode of the capacitor CST may be stored in the capacitor CST.

[0141] Afterwards, the jth bias scan signal GBj can be applied to the seventh transistor T7 and the eighth transistor T8, so that the seventh transistor T7 and the eighth transistor T8 are turned on. The second initialization voltage AINT can be provided to the anode AE ​​through the seventh transistor T7, and thus the anode AE ​​can be initialized to the second initialization voltage AINT. The bias voltage VBIAS can be applied to the first electrode of the first transistor T1 through the eighth transistor T8.

[0142] Afterwards, during the emission period LP, the j-th emission signal EMj may be applied to the fifth transistor T5 and the sixth transistor T6 through the j-th emission line EMLj, so that the fifth transistor T5 and the sixth transistor T6 are turned on. In this case, a driving current Id corresponding to a voltage difference between a voltage of the control electrode of the first transistor T1 and the first driving voltage ELVDD may be generated. The driving current Id may be provided to the light emitting element OLED through the sixth transistor T6, and thus the light emitting element OLED may emit light.

[0143] During the emission period LP, the gate-source voltage (Vgs) of the first transistor T1 may be “Vgs=ELVDD-(VD-Vth)”. The equation for the relationship between the current and voltage of the first transistor T1 may be defined as “Id=(1 / 2)μCox(W / L)(Vgs-Vth)”. 2 ”. This equation represents the relationship between the current and voltage of a typical transistor.

[0144] When the gate-source voltage (Vgs) of the first transistor T1 is substituted into the equation of the relationship between current and voltage, the threshold voltage (Vth) can be eliminated, and the driving current Id can be equal to the square value of the value obtained by subtracting the data voltage VD from the first driving voltage ELVDD "(ELVDD-VD) 2 " is proportional. Therefore, regardless of the threshold voltage (Vth) of the first transistor T1, the driving current Id can be determined. This operation can be defined as a threshold voltage compensation operation.

[0145] After the threshold voltage of the first transistor T1 is compensated, before the light emitting element OLED emits light, the bias voltage VBIAS can be applied to the first electrode of the first transistor T1 through the eighth transistor T8. The offset of the hysteresis curve of the first transistor T1 can be suppressed by the bias voltage VBIAS. This operation can be defined as a bias operation.

[0146] Figure 8 is a diagram showing timings of scan signals and emission signals applied to pixels in one frame.

[0147] Figure 8 The frame FRM shown in may refer to one of the frames in which a data signal is written to the pixel PXij.

[0148] Reference Figure 6 , Figure 7 and Figure 8 During the frame FRM, the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj may be provided to the pixel PXij only once. Therefore, each of the initialization operation, the write operation, and the compensation operation may be performed once.

[0149] However, the j-th bias scanning signal GBj may be supplied to the pixel PXij a plurality of times. For this reason, the j-th emission signal EMj having a high level may be supplied to the pixel PXij a plurality of times. Therefore, the bias operation may be performed a plurality of times.

[0150] For example, during one frame FRM, the j-th bias scan signal GBj and the j-th emission signal EMj are provided to the pixel PXij twice, but embodiments of the present disclosure are not limited thereto.

[0151] For example, like other scan signals GIj, GCj and GWj, the jth bias scan signal GBj and the jth emission signal EMj may be provided to the pixel PXij only once during one frame FRM. In addition, the jth bias scan signal GBj and the jth emission signal EMj may be provided to the pixel PXij twice or more during the frame FRM.

[0152] Hereinafter, an operation in which the j-th bias scan signal GBj and the j-th emission signal EMj are supplied to the pixel PXij twice during one frame FRM will be described.

[0153] Fig. 9 When Figure 6 0 is a timing diagram of scanning signals and emission signals when the pixel shown in 0 operates in the normal mode.

[0154] Hereinafter, an operation in which the scan signals GIj, GCj, GWj, and GBj are applied to the pixel PXij is defined as an activation operation. An operation in which the scan signals GIj, GCj, GWj, and GBj are not applied to the pixel PXij is defined as a deactivation operation.

[0155] Reference Fig. 9 During the normal mode NFD, during each of the first frame F1, the second frame F2, and the third frame F3, the scan signals GIj, GCj, GWj, and GBj may be applied to the pixel PXij, and thus the pixel PXij may be driven. Although not shown in the drawings, the scan signals GIj, GCj, GWj, and GBj may be applied to the pixel PXij until the 120th frame F120 of the normal mode NFD described above, and thus the pixel PXij may be driven. Therefore, during the first frame F1 to the 120th frame F120, the image may be updated to display a video.

[0156] Fig.10 When Figure 6 is a timing diagram of scanning signals and emission signals when the pixel shown in is operated in the low frequency mode.

[0157] Reference Fig.10 , also refer to Figure 6 In the low frequency mode LFD, the scan signals GIj, GCj, GWj, and GBj are applied to the pixel PXij during the first frame F1 so that the pixel PXij is driven. During the first frame F1, the data voltage VD may be applied to the pixel PXij in response to the jth write scan signal GWj.

[0158] During the second frame F2 and the third frame F3, the image may not be updated and the previous image may be displayed. During the second frame F2 and the third frame F3, the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj may not be applied to the pixel PXij.

[0159] Although not shown in the drawings, the image may not be updated until the 120th frame F120 of the low frequency mode LFD described above, and the previous image may be displayed. Therefore, from the second frame F2 to the 120th frame F120, the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj may not be applied to the pixel PXij.

[0160] In the same manner as the first frame F1, the jth emission signal EMj may be applied to the pixel PXij during the second frame F2 to the 120th frame F120. Even when the data voltage VD is not applied to the pixel PXij during the second frame F2 to the 120th frame F120, the light emitting element OLED may emit light due to the charges stored in the capacitor CST.

[0161] In the same manner as the first frame F1, the jth bias scan signal GBj may be applied to the pixel PXij during the second frame F2 to the 120th frame F120. Therefore, during the second frame F2 to the 120th frame F120, the bias voltage VBIAS may be applied to the first electrode of the first transistor T1.

[0162] The state of the first transistor T1 may be changed to an on bias state by the bias voltage VBIAS. In this case, the variation of the hysteresis characteristic of the first transistor T1 for displaying a static image may be reduced so that the hysteresis characteristic of the first transistor T1 may be kept constant.

[0163] Fig.11 yes Figure 5 0 is a block diagram of a first scan driving circuit of the scan driving circuit shown in .

[0164] Reference Figure 5 and Fig.11 , the scan drive circuit SDC may include a first scan drive circuit SDC1. The first scan drive circuit SDC1 may include a plurality of stages ST1 to STn connected in a sequential manner. The stages ST1 to STn may generate and output write scan signals GW1, GW2, GW3, GW4, . . . , GWn-1, and GWn, respectively. The write scan signals GW1 to GWn may be respectively Figure 5 The write scanning lines GWL1 to GWLn shown in FIG.

[0165] The stages ST1 to STn may receive a first start signal FLM1 or a write scan signal output from a previous stage, a write clock signal WCK, a first setting signal SET1, a first high voltage VGH1, and a first low voltage VGL1. The scan control signal SCS may include the first start signal FLM1, the write clock signal WCK, and the first setting signal SET1. The first high voltage VGH1 and the first low voltage VGL1 may be generated by the voltage generator 300 and may be provided to the first scan driving circuit SDC1. The first low voltage VGL1 may have a lower level than the first high voltage VGH1.

[0166] The stages ST1 to STn may include first to fourth input terminals IN1 to IN4, first and second voltage terminals V1 and V2, and an output terminal OUT. The stages ST1 to STn may receive a first start signal FLM1 or a write scan signal output from a previous stage, a write clock signal WCK, a first setting signal SET1, a first high voltage VGH1, and a first low voltage VGL1 through the first to fourth input terminals IN1 to IN4 and the first and second voltage terminals V1 and V2. The stages ST1 to STn may output write scan signals GW1 to GWn, respectively, through the output terminals OUT.

[0167] The stages ST1 to STn may receive a write clock signal WCK through first and second input terminals IN1 and IN2. The write clock signal WCK may include a first clock signal CK1 and a second clock signal CK2 having a phase opposite to that of the first clock signal CK1.

[0168] The first clock signal CK1 and the second clock signal CK2 may be alternately applied to the first input terminal IN1 and the second input terminal IN2 of each of the stages ST1 to STn. For example, the first clock signal CK1 may be applied to the first input terminal IN1 of the odd-numbered stages (ST1, ST3, ..., STn-1), and the second clock signal CK2 may be applied to the second input terminal IN2 of the odd-numbered stages (ST1, ST3, ..., STn-1).

[0169] The second clock signal CK2 may be applied to the first input terminals IN1 of the even-numbered stages (ST2, ST4, . . . , STn), and the first clock signal CK1 may be applied to the second input terminals IN2 of the even-numbered stages (ST2, ST4, . . . , STn).

[0170] The first stage ST1 among the stages ST1 to STn may receive the first start signal FLM1 through the third input terminal IN3. In the second to nth stages ST2 to STn, the current stage may receive the write scan signal output from the previous stage through the third input terminal IN3.

[0171] The stages ST1 to STn may receive a first high voltage VGH1 through a first voltage terminal V1. The stages ST1 to STn may receive a first low voltage VGL1 through a second voltage terminal V2.

[0172] The first stage ST1 may be activated in response to the first start signal FLM1. Among the second to n-th stages ST2 to STn, a current stage may be activated in response to a write scan signal output from a previous stage.

[0173] The activated stages ST1 to STn may apply write scan signals GW1 to GWn to the pixels PX in response to the write clock signal WCK. The activated stages ST1 to STn may output write scan signals GW1 to GWn by using the first and second clock signals CK1 and CK2, the first high voltage VGH1, and the first low voltage VGL1.

[0174] In the normal mode NFD, each of the stages ST1 to STn may output a write scan signal having a first operating frequency. In the low frequency mode LFD, each of the stages ST1 to STn may output a write scan signal having a second operating frequency. In the low frequency mode LFD, the stages ST1 to STn may output disabled write scan signals GW1 to GWn in response to the first setting signal SET1. Hereinafter, the operation will be described in detail.

[0175] Fig.12 It is shown Fig.11 The circuit configurations of the first and second stages are shown in the diagram.

[0176] Although not shown in the drawings, each of the other stages ST3 to STn may have the same Fig.12 The first stage ST1 and the second stage ST2 have substantially the same configuration, and therefore, the configuration of the first stage ST1 will be described below.

[0177] Reference Fig.12 , also refer to Fig.11 , the first stage ST1 may include a first node controller NCT1, a first output buffer part OBP1, and a first setting part SEP1.

[0178] The first node controller NCT1 may be connected to the first node ND1 and the second node ND2. The first node controller NCT1 may receive the first high voltage VGH1, the first low voltage VGL1, the first start signal FLM1, the first clock signal CK1, and the second clock signal CK2. The first node controller NCT1 may control the voltage level of the first node ND1 and the voltage level of the second node ND2 in response to the first high voltage VGH1, the first low voltage VGL1, the first start signal FLM1, the first clock signal CK1, and the second clock signal CK2.

[0179] The first output buffer part OBP1 may be connected to the first node ND1 and the second node ND2. The first output buffer part OBP1 may receive the first high voltage VGH1 and the second clock signal CK2. The first output buffer part OBP1 may output the write scan signal GW1 according to the voltage levels of the first node ND1 and the second node ND2.

[0180] The first output buffer part OBP1 may output one of the first high voltage VGH1 and the second clock signal CK2 according to the voltage levels of the first and second nodes ND2 .

[0181] The first output buffer part OBP1 may output the write scan signal GW1 including the second clock signal CK2 according to the voltage levels of the first node ND1 and the second node ND2. For example, the write scan signal GW1 may be a single pulse signal (such as a pulse signal) that transitions to a low level once per frame in response to a low level of the second clock signal CK2. Fig.13 ). Therefore, the first stage ST1 may output the write scan signal GW1 in response to the second clock signal CK2 of the write clock signal WCK.

[0182] In the second stage ST2, the first clock signal CK1 may be applied to the second input terminal IN2, and the second clock signal CK2 may be applied to the first input terminal IN1. Therefore, the second stage ST2 may output the write scan signal GW2 in response to the first clock signal CK1 of the write clock signal WCK.

[0183] The activated write scan signal GW1 may have a low level. The disabled write scan signal GW1 may have a high level. The write scan signal GW1 output from the first output buffer part OBP1 may be provided to the third input terminal IN3 of the second stage ST2. The second stage ST2 may operate to output the write scan signal GW2 in response to the write scan signal GW1 output from the first stage ST1 of the previous stage.

[0184] The first setting part SEP1 may be connected to the first node ND1 and the second node ND2. The first setting part SEP1 may receive a first setting signal SET1. In response to the first setting signal SET1, the first setting part SEP1 may set the voltage of the first node ND1 to the first low voltage VGL1, and may set the voltage of the second node ND2 to the first high voltage VGH1. In this case, the first output buffer part OBP1 may stably output the disabled write scan signal GW1.

[0185] For the above operation, the first node controller NCT1 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and an eighth transistor M8. For the above operation, the first output buffer part OBP1 may include a sixth transistor M6 and a seventh transistor M7 and a first capacitor C1 and a second capacitor C2. For the above operation, the first setting part SEP1 may include a ninth transistor M9 and a tenth transistor M10.

[0186] The first to tenth transistors M1 to M10 may be PMOS transistors, but are not limited thereto. For example, the first to tenth transistors M1 to M10 may be NMOS transistors. The first to tenth transistors M1 to M10 may be defined as switch elements.

[0187] Each of the first to tenth transistors M1 to M10 may include a source electrode, a drain electrode, and a gate electrode. Hereinafter, for ease of description, one of the source electrode and the drain electrode is defined as a first electrode, and the other of the source electrode and the drain electrode is defined as a second electrode. In addition, the gate electrode is defined as a control electrode.

[0188] The first transistor M1 may include a first electrode connected to the third input terminal IN3, a second electrode connected to the third node ND3, and a control electrode connected to the first input terminal IN1. The third node ND3 may be connected to the second node ND2 through the eighth transistor M8.

[0189] The first transistor M1 may be switched in response to a first clock signal CK1 received through the first input terminal IN1. When the first clock signal CK1 is at a low level, the first transistor M1 may be turned on to apply a first start signal FLM1 received through the third input terminal IN3 to the third node ND3. The first start signal FLM1 may be a single pulse signal ( Fig.13 ).

[0190] The second transistor M2 may include a first electrode receiving the first high voltage VGH1, a second electrode connected to the third transistor M3, and a control electrode connected to the first node ND1. The second transistor M2 may be connected to the third node ND3 through the third transistor M3. The second transistor M2 may be switched according to the voltage of the first node ND1.

[0191] The third transistor M3 may include a first electrode connected to the second electrode of the second transistor M2, a second electrode connected to the third node ND3, and a control electrode connected to the second input terminal IN2. The third transistor M3 may switch in response to the second clock signal CK2 received through the second input terminal IN2.

[0192] The second transistor M2 and the third transistor M3 may be connected in series. When the second transistor M2 and the third transistor M3 are turned on at the same time, the first high voltage VGH1 may be applied to the third node ND3. Therefore, the first transistor M1 to the third transistor M3 may provide the first start signal FLM1 or the first high voltage VGH1 to the third node ND3 based on the first clock signal CK1 and the second clock signal CK2.

[0193] The fourth transistor M4 may include a first electrode connected to the first node ND1, a second electrode connected to the first input terminal IN1, and a control electrode connected to the third node ND3. The fourth transistor M4 may be switched according to the voltage of the third node ND3. When the fourth transistor M4 is turned on, the fourth transistor M4 may apply the first clock signal CK1 received through the first input terminal IN1 to the first node ND1.

[0194] The fifth transistor M5 may include a first electrode connected to the first node ND1, a second electrode receiving the first low voltage VGL1, and a control electrode connected to the first input terminal IN1. The fifth transistor M5 may be switched in response to the first clock signal CK1 received through the first input terminal IN1. When the fifth transistor M5 is turned on, the fifth transistor M5 may apply the first low voltage VGL1 to the first node ND1.

[0195] Therefore, the fourth transistor M4 and the fifth transistor M5 may provide the first low voltage VGL1 or the first clock signal CK1 to the first node ND1 based on the first clock signal CK1 and the voltage level of the third node ND3 .

[0196] The eighth transistor M8 may include a first electrode connected to the third node ND3, a second electrode connected to the second node ND2, and a control electrode receiving the first low voltage VGL1. The eighth transistor M8 may be turned on in response to the first low voltage VGL1. The eighth transistor M8 may be kept in a turned-on state by the first low voltage VGL1. The eighth transistor M8 may connect the second node ND2 and the third node ND3.

[0197] The eighth transistor M8 may limit the voltage drop range of the third node ND3. For example, even when the voltage of the second node ND2 drops to a voltage lower than the first low voltage VGL1, the voltage of the third node ND3 may not be lower than a voltage obtained by subtracting the threshold voltage of the eighth transistor M8 from the first low voltage VGL1. The eighth transistor M8 may be omitted.

[0198] The sixth transistor M6 may be defined as a pull-up switching element. The seventh transistor M7 may be defined as a pull-down switching element.

[0199] The sixth transistor M6 may include a first electrode receiving a first high voltage VGH1, a second electrode connected to the output terminal OUT, and a control electrode connected to the first node ND1. The sixth transistor M6 may be switched according to the voltage level of the first node ND1. The sixth transistor M6 may be defined as a first buffer part. That is, the first buffer part may be connected to the first node ND1 and the output terminal OUT, and may receive the first high voltage VGH1.

[0200] The sixth transistor M6 may determine the output of the first high voltage VGH1 according to the voltage of the first node ND1. For example, when the sixth transistor M6 is turned on, the sixth transistor M6 may provide the first high voltage VGH1 to the output terminal OUT. In this case, the disabled write scan signal GW1 may be output.

[0201] The seventh transistor M7 may include a first electrode connected to the output terminal OUT, a second electrode connected to the second input terminal IN2, and a control electrode connected to the second node ND2. The seventh transistor M7 may be switched according to the voltage level of the second node ND2. The seventh transistor M7 may be defined as a second buffer part. In other words, the second buffer part may be connected to the second node ND2 and the output terminal OUT, and may receive the second clock signal CK2 through the second input terminal IN2.

[0202] The seventh transistor M7 may determine the output of the second clock signal CK2 according to the voltage of the second node ND2. For example, when the seventh transistor M7 is turned on, the seventh transistor M7 may provide the second clock signal CK2 to the output terminal OUT. In this case, the second clock signal CK2 of a low level may be output as the activated write scan signal GW1. Therefore, the sixth transistor M6 as the first buffer part and the seventh transistor M7 as the second buffer part may operate to output the write scan signal GW1 according to the voltage levels of the first node ND1 and the second node ND2.

[0203] The first capacitor C1 may include a first electrode receiving the first high voltage VGH1 and a second electrode connected to the first node ND1. The second capacitor C2 may include a first electrode connected to the output terminal OUT and a second electrode connected to the second node ND2.

[0204] The ninth transistor M9 may include a first electrode connected to the first node ND1, a second electrode receiving the first low voltage VGL1, and a control electrode connected to the fourth input terminal IN4. The tenth transistor M10 may include a first electrode receiving the first high voltage VGH1, a second electrode connected to the second node ND2, and a control electrode connected to the fourth input terminal IN4.

[0205] The ninth transistor M9 and the tenth transistor M10 may be switched in response to the first setting signal SET1 received through the fourth input terminal IN4. When the ninth transistor M9 is turned on, the first low voltage VGL1 may be provided to the first node ND1 through the ninth transistor M9. When the tenth transistor M10 is turned on, the first high voltage VGH1 may be provided to the second node ND2 through the tenth transistor M10.

[0206] The first node ND1 may have the first low voltage VGL1 , and thus the sixth transistor M6 may be turned on. Therefore, when the first node ND1 has the first low voltage VGL1 , the first output buffer part OBP1 may output the first high voltage VGH1 .

[0207] The second node ND2 has the first high voltage VGH1, and thus the seventh transistor M7 may be turned off. Therefore, when the second node ND2 has the first high voltage VGH1, the first output buffer part OBP1 may not output the second clock signal CK2. Therefore, through the output terminal OUT, the first high voltage VGH1 may be output instead of the second clock signal CK2, and thus the disabled write scan signal GW1 may be output.

[0208] When a still image is displayed, the write scan signal GW1 may not be applied to the pixel PX from the second frame F2 (refer to Figure 5). Therefore, the write scan signal GW1 needs to remain disabled. However, when the voltage levels of the first node ND1 and the second node ND2 change, the write scan signal GW1 may not remain disabled.

[0209] In an embodiment of the present disclosure, when a still image is displayed, the first setting part SEP1 may set the voltage levels of the first node ND1 and the second node ND2 so that the first output buffer part OBP1 outputs the disabled write scan signal GW1. For example, as described above, the first setting part SEP1 may set the voltage of the first node ND1 to the first low voltage VGL1, and may set the voltage of the second node ND2 to the first high voltage VGH1.

[0210] Therefore, when a still image is displayed, the write scan signal GW1 can be stably maintained at the disable level by the first setting part SEP1. In this case, power consumption can be reduced. The timing of the first setting signal SET1 is as follows Fig.16 Shown in.

[0211] The configuration of the first stage ST1 has been described, but the second stage ST2 may operate in substantially the same manner as the first stage ST1. However, the second stage ST2 may operate in response to the write scan signal GW1 output from the first stage ST1. The seventh transistor M7 as the second buffer portion of the second stage ST2 may receive the first clock signal CK1. In other words, the second buffer portion of each of the first stage ST1 and the second stage ST2 may receive one of the first clock signal CK1 and the second clock signal CK2.

[0212] Fig.13 is shown in the normal mode from Fig.11 2 is a diagram showing the timing of the write scan signal output by the stage shown in FIG. Fig.14 is shown in the low frequency mode from Fig.11 2 is a diagram showing the timing of the write scan signal output by the stage shown in FIG.

[0213] exist Fig.13 and Fig.14 , the first frame F1 to the fourth frame F4 are shown.

[0214] Reference Fig.11 , Fig.12 and Fig.13 , the first stage ST1 receiving the first start signal FLM1 may operate first. Thereafter, the second stage ST2 to the nth stage STn may sequentially operate according to the write scan signal output from the previous stage. Therefore, the write scan signals GW1 to GWn may be sequentially output during each of the first frame F1 to the fourth frame F4. In the normal mode NFD, this operation may be repeated until the 120th frame F120.

[0215] Therefore, in the normal mode NFD, write scan signals GW1 to GWn having a first operating frequency (eg, 120 Hz) may be output by stages ST1 to STn, respectively. In other words, in the normal mode NFD, the first scan driving circuit SDC1 may output write scan signals GW1 to GWn having a first operating frequency.

[0216] Reference Fig.11 , Fig.12 and Fig.14 , in the low frequency mode LFD, the write scan signals GW1 to GWn may be sequentially output during the first frame F1. However, from the second frame F2, the first start signal FLM1 may not be applied to the first scan driving circuit SDC1. Therefore, the write scan signals GW1 to GWn may not be output from the second frame F2. In the low frequency mode LFD, this operation may be repeated until the 120th frame F120.

[0217] The operation in which the write scan signals GW1 to GWn are not output may be defined as an operation in which the activated write scan signals GW1 to GWn are not output. In other words, the operation in which the write scan signals GW1 to GWn are not output may be defined as an operation in which the disabled write scan signals GW1 to GWn are output. Since the write scan signals GW1 to GWn are not output during the second frame F2 to the 120th frame F120 in the low frequency mode LFD, power consumption can be reduced.

[0218] Therefore, in the low frequency mode LFD, write scan signals GW1 to GWn having a second operating frequency (eg, 1 Hz) may be output by stages ST1 to STn, respectively. That is, in the low frequency mode LFD, the first scan driving circuit SDC1 may output write scan signals GW1 to GWn having a second operating frequency.

[0219] Fig.15 is a diagram showing the timing of the first and second clock signals, the write scan signal, and the first setting signal in the normal mode. Fig.16 is a diagram showing the timing of the first and second clock signals, the write scan signal, and the first setting signal in the low frequency mode.

[0220] exist Fig.15 and Fig.16 , the first frame F1 to the fourth frame F4 are shown as Fig.13 and Fig.14 correspond.

[0221] Reference Fig.11 , Fig.12 and Fig.15 , also refer to Figure 5During each of the frames F1 to F4 of the normal mode NFD, the write scan signals GW1 to GWn may be output based on the first clock signal CK1 and the second clock signal CK2. This operation may be repeated until a 120th frame F120.

[0222] In the normal mode NFD, each of the frames F1 to F4 may include an active period AP and a blanking period BLK after the active period AP. Although not shown in the drawings, in the normal mode NFD, each of the fifth to 120th frames F5 to F120 may also include an active period AP and a blanking period BLK.

[0223] In the effective period AP of each of the frames F1 to F4, the write scan signals GW1 to GWn may be generated and output. That is, the period in which the write scan signals GW1 to GWn are output may be defined as the effective period AP. During the effective period AP, the write scan signals GW1 to GWn may be applied to the pixels PX.

[0224] The blank period BLK may be defined as an idle period. During the blank period BLK, the write scan signals GW1 to GWn may not be generated. The blank period BLK may be defined as a waiting period for an operation of a next frame.

[0225] In the normal mode NFD, the first setting signal SET1 may be a DC signal having a high level. Therefore, the ninth transistor M9 and the tenth transistor M10 of the first setting part SEP1 may be turned off in the normal mode NFD.

[0226] Reference Fig.11 , Fig.12 and Fig.16 , in the low frequency mode LFD, the write clock signal WCK may have an AC signal in the first frame F1, and may have a DC signal in the second frame F2 to the fourth frame F4. That is, the write clock signal WCK may be changed to a DC level from the second frame F2. When the first setting signal SET1 is applied to the first scan driving circuit SDC1, the write clock signal WCK may have a DC level. The write clock signal WCK may maintain a DC level until the 120th frame F120.

[0227] The first clock signal CK1 and the second clock signal CK2 may have an AC signal in the first frame F1, and may have a DC signal in the second frame F2 to the 120th frame F120, but the embodiments of the present disclosure are not limited thereto. For example, during one of the third frame F3 to the 120th frame F120, each of the first clock signal CK1 and the second clock signal CK2 may be changed to have an AC signal again.

[0228] During the first frame F1, each of the first clock signal CK1 and the second clock signal CK2 may have an amplitude defined as a difference between a first high voltage VH1 and a first low voltage VL1, the first low voltage VL1 having a level lower than the first high voltage VH1. From the second frame F2, each of the first clock signal CK1 and the second clock signal CK2 may be changed to a DC signal having the first high voltage VH1. However, the embodiment is not limited thereto. For example, from the second frame F2, each of the first clock signal CK1 and the second clock signal CK2 may be changed to a DC signal having the first low voltage VL1.

[0229] When the write clock signal WCK has a DC signal, power consumption can be reduced compared to the case where the write clock signal WCK has an AC signal. Therefore, in the embodiment of the present disclosure, power consumption of the display device DD can be reduced.

[0230] In the low frequency mode LFD, the first frame F1 may include an active period AP and a blanking period BLK. In the low frequency mode LFD, the second frame F2 may include a non-active period NAP in which the write scan signals GW1 to GWn are not output and a blanking period BLK after the non-active period NAP. In the low frequency mode LFD, each of the subsequent frames F3 to F120 after the second frame F2 may also include a non-active period NAP and a blanking period BLK.

[0231] In the non-active period NAP, the write scan signals GW1 to GWn may not be applied to the pixels PX. In other words, in the non-active period NAP, the write scan signals GW1 to GWn may maintain a non-active high level. In the non-active period NAP, the first scan driving circuit SDC1 may output disabled write scan signals GW1 to GWn.

[0232] During a period between an active period AP of the first frame F1 and a non-active period NAP of the second frame F2, the first setting signal SET1 may be activated at a low level. That is, during a blanking period BLK of the first frame F1, the first setting signal SET1 may be activated at a low level and applied to the first scan driving circuit SDC1. An operation in which the first setting signal SET1 is applied to the first scan driving circuit SDC1 may be defined as an operation in which the activated first setting signal SET1 is applied to the first scan driving circuit SDC1.

[0233] The first scan driving circuit SDC1 may output disabled write scan signals GW1 to GWn in response to the first setting signal SET1 received during the blank period BLK of the first frame F1. For example, each of the first setting parts SEP1 of the stages ST1 to STn may set the first node ND1 to the first low voltage VGL1 and may set the second node ND2 to the first high voltage VGH1 in response to the first setting signal SET1 received during the blank period BLK of the first frame F1.

[0234] Therefore, the disabled write scan signals GW1 to GWn are output, and thus the write scan signals GW1 to GWn can be more stably maintained at the disabled level. As a result, power consumption can be reduced.

[0235] Fig.17 is a diagram showing the timing of the write clock signal in the low frequency mode.

[0236] Fig.17 Shown with Fig.16 The corresponding timing.

[0237] Reference Fig.16 and Fig.17 , the level of the DC signal of the write clock signal WCK can be set in various ways. For example, Fig.16 Differently, from the second frame F2 , each of the first and second clock signals CK1 and CK2 may have a second high voltage VH2 having a voltage level lower than the first high voltage VH1 and higher than the first low voltage VL1 .

[0238] Fig.18 is a diagram showing the timing of the first setting signal in the low frequency mode.

[0239] Fig.18 Shown with Fig.16 The corresponding timing.

[0240] Reference Fig.11 , Fig.12 , Fig.16 and Fig.18 , the first setting signal SET1 may be provided to the first setting part SEP1 a plurality of times. For example, the first setting signal SET1 may be applied to the first scan driving circuit SDC1 during the blanking period BLK of the first frame F1, and may be further applied to the first scan driving circuit SDC1 during at least one blanking period BLK among the subsequent blanking periods BLK.

[0241] like Fig.18As shown in FIG. 1 , during the blanking period BLK of the third frame F3 , the first setting signal SET1 may be applied to the first scan driving circuit SDC1 , but is not limited thereto. For example, the first setting signal SET1 may be applied to the first scan driving circuit SDC1 during various blanking periods BLK.

[0242] The first setting signal SET1 may be applied to the first scan driving circuit SDC1 in inverse proportion to the second operating frequency. For example, when the second operating frequency is changed to 60 Hz, 30 Hz, 10 Hz, or 1 Hz, the first setting signal SET1 may be applied to the first scan driving circuit SDC1 1 time, 20 times, 30 times, or 60 times.

[0243] Fig.19 is a diagram showing a circuit configuration of a first stage and a second stage of a first scan driving circuit according to an embodiment of the present disclosure.

[0244] Fig.19 The first stage ST1-1 and the second stage ST2-1 shown in FIG. Fig.12 The first stage ST1 and the second stage ST2 shown in FIG. Fig.12 Although not shown in the drawings, the first scan driving circuit SDC1-1 may include third to n-th stages, each of which has the same configuration as the first stage ST1-1 or the second stage ST2-1.

[0245] Reference Fig.19 ,and Fig.12 Unlike the embodiment in FIG. 1 , the first setting part SEP1 ′ of the first stage ST1-1 may receive the second high voltage VGH2 and the second low voltage VGL2. The first stage ST1-1 may include a third voltage terminal V3 receiving the second high voltage VGH2 and a fourth voltage terminal V4 receiving the second low voltage VGL2.

[0246] In response to the first setting signal SET1, the first setting part SEP1' may set the voltage of the first node ND1 to the second low voltage VGL2, and may set the voltage of the second node ND2 to the second high voltage VGH2. The second high voltage VGH2 may have a different level from the first high voltage VGH1, and the second low voltage VGL2 may have a different level from the first low voltage VGL1. The second low voltage VGL2 may have a lower level than the second high voltage VGH2.

[0247] The ninth transistor M9 may include a first electrode connected to the first node ND1, a second electrode receiving the second low voltage VGL2, and a control electrode connected to the fourth input terminal IN4. The tenth transistor M10 may include a first electrode receiving the second high voltage VGH2, a second electrode connected to the second node ND2, and a control electrode connected to the fourth input terminal IN4.

[0248] When the ninth transistor M9 is turned on, the second low voltage VGL2 may be supplied to the first node ND1 through the ninth transistor M9. When the tenth transistor M10 is turned on, the second high voltage VGH2 may be supplied to the second node ND2 through the tenth transistor M10.

[0249] Because the first node ND1 has the second low voltage VGL2, the sixth transistor M6 can be turned on. Because the second node ND2 has the second high voltage VGH2, the seventh transistor M7 can be turned off. Therefore, the first high voltage VGH1 can be output through the output terminal OUT, and thus the disabled write scan signal GW1 can be output.

[0250] Fig. 20 is a diagram showing a circuit configuration of a first stage and a second stage of a first scan driving circuit according to an embodiment of the present disclosure.

[0251] Fig. 20 The first stage ST1-2 and the second stage ST2-2 shown in FIG. Fig.12 The first stage ST1 and the second stage ST2 shown in FIG. Fig.12 Although not shown in the drawings, the first scan driving circuit SDC1-2 may include third to n-th stages, each of which has the same configuration as the first stage ST1-2 or the second stage ST2-2.

[0252] Reference Fig. 20 ,and Fig.12 Unlike the first stage ST1 shown in FIG. 1 , the first stage ST1-2 does not include the first setting portion SEP1 but may include a switching element SWD. The switching element SWD may be an NMOS transistor.

[0253] The switch element SWD may be connected to the second node ND2 and the third input terminal IN3 receiving the first start signal FLM1, and may be switched in response to the control signal SS. The control signal SS may be defined as a setting signal. The switch element SWD may be connected to the third input terminal IN3 through the third node ND3. The switch element SWD may be connected to the third input terminal IN3 through the first transistor M1. The switch element SWD may be connected to the second node ND2 through the eighth transistor M8. When the eighth transistor M8 is omitted, the switch element SWD may be directly connected to the second node ND2.

[0254] The switch element SWD may include a first electrode connected to the third node ND3, a second electrode connected to the second node ND2 through the eighth transistor M8, and a control electrode receiving a control signal SS. The switch element SWD may switch the connection between the second node ND2 and the third node ND3 in response to the control signal SS.

[0255] Fig.21 is shown in the low frequency mode applied to Fig. 20 3 is a diagram showing the timing of the control signals of the switching elements shown in FIG.

[0256] Fig.21 is corresponding to Fig.16 Timing diagram of .

[0257] Reference Fig. 20 and Fig.21 , during the first frame F1 of the low frequency mode LFD, the control signal SS may have a high level and the switch element SWD may be turned on. The third node ND3 may be connected to the second node ND2 through the switch element SWD and the turned-on eighth transistor M8. Therefore, the write scan signals GW1 to GWn may be generated and output. Although not shown in the drawings, even in the normal mode NFD, the control signal SS may maintain a high level like the first frame F1.

[0258] From the second frame F2 of the low frequency mode LFD, the control signal SS may have a low level, and the switch element SWD may be turned off. That is, during a period in which the write scan signals GW1 to GWn are not applied to the pixel PX, the switch element SWD may be turned off. Therefore, the connection between the second node ND2 and the third node ND3 may be disconnected. In addition, the connection between the second node ND2 and the third input terminal IN3 may be disconnected. In detail, the connection between the eighth transistor M8 and the third node ND3 may be disconnected.

[0259] In the low frequency mode LFD, during a period in which the write scan signals GW1 to GWn are not applied to the pixel PX, leakage current may occur through various paths. For example, for the voltage of the second node ND2, leakage current may occur through the third node ND3, the second transistor M2, the third transistor M3, and the first voltage terminal V1. In addition, for the voltage of the second node ND2, leakage current may occur through the third node ND3 and the third input terminal IN3.

[0260] When the write scan signals GW1 to GWn are disabled after being activated during the first frame F1, the first node ND1 can be substantially maintained at a low voltage, and the second node ND2 can be maintained at a high voltage. Therefore, the sixth transistor M6 can be turned on, and the seventh transistor M7 can be turned off. Therefore, the first high voltage VGH1 can be output as the disabled write scan signals GW1 to GWn. However, when the voltage level of the second node ND2 changes due to leakage current, the write scan signals GW1 to GWn may not be maintained in an inactive state.

[0261] In the embodiment of the present disclosure, the leakage current path can be blocked by turning off the switching element SWD from the second frame F2 of the low frequency mode LFD. Therefore, the voltage level of the second node ND2 can be stably maintained, and thus the write scan signals GW1 to GWn can be maintained in an inactive state.

[0262] Fig. 22 yes Figure 5 0 is a block diagram of a second scan driving circuit of the scan driving circuit shown in .

[0263] Reference Figure 5 and Fig. 22 The scan driving circuit SDC may include a second scan driving circuit SDC2 for generating initialization scan signals GI1 to GIn. The second scan driving circuit SDC2 may include a plurality of stages ST1' to STn' connected in sequence. The stages ST1' to STn' may output the initialization scan signals GI1 to GIn. The initialization scan signals GI1 to GIn may be Figure 5 The initialization scan lines GIL1 to GILn shown in FIG.

[0264] Although not shown in the drawings, the scan driving circuit SDC may include a third scan driving circuit for generating the compensation scan signals GC1 to GCn. The third scan driving circuit may have substantially the same configuration as the second scan driving circuit SDC2 except for the output timing of the compensation scan signals GC1 to GCn. In addition, although not shown in the drawings, the emission driving circuit EDC may have substantially the same configuration as the second scan driving circuit SDC2.

[0265] Stages ST1' to STn' may receive a second start signal FLM2 or an initialization scan signal from a previous stage, an initialization clock signal ICK, a second set signal SET2, a first high voltage VGH1, and a first low voltage VGL1. The scan control signal SCS may include the second start signal FLM2, the initialization clock signal ICK, and the second set signal SET2.

[0266] Each of the stages ST1' to STn' may include first to fourth input terminals IN1' to IN4', first and second voltage terminals V1' and V2', and an output terminal OUT'. Each of the stages ST1' to STn' may receive the second start signal FLM2 or the initialization scan signal output from the previous stage, the initialization clock signal ICK, the second setting signal SET2, the first high voltage VGH1, and the first low voltage VGL1 through the first input terminals IN1' to IN4' and the first and second voltage terminals V1' and V2'. The stages ST1' to STn' may output initialization scan signals GI1 to GIn respectively through the output terminal OUT'.

[0267] The stages ST1' to STn' may receive an initialization clock signal ICK or an initialization scan signal output from a previous stage through a first input terminal IN1' and a second input terminal IN2'. The initialization clock signal ICK may include a third clock signal CK3 and a fourth clock signal CK4, the fourth clock signal CK4 having a phase opposite to that of the third clock signal CK3. In an embodiment of the present disclosure, the third clock signal CK3 and the fourth clock signal CK4 may be referred to differently. For example, in the second scan driving circuit SDC2, the third clock signal CK3 may be referred to as the first clock signal CK3, and the fourth clock signal CK4 may be referred to as the second clock signal CK4.

[0268] The third clock signal CK3 and the fourth clock signal CK4 may be alternately applied to the first input terminal IN1' and the second input terminal IN2'. For example, the third clock signal CK3 may be applied to the first input terminal IN1' of the odd-numbered stages ST1', ST3', ..., and STn-1'. The fourth clock signal CK4 may be applied to the second input terminal IN2' of the odd-numbered stages ST1', ST3', ..., and STn-1'.

[0269] The fourth clock signal CK4 may be applied to the first input terminals IN1' of the even-numbered stages ST2', ST4', ..., and STn'. The third clock signal CK3 may be applied to the second input terminals IN2' of the even-numbered stages ST2', ST4', ..., and STn'.

[0270] The first stage ST1 among the stages ST1' to STn' may receive the second start signal FLM2 through the third input terminal IN3'. In the second stage ST2' to the nth stage STn', the current stage may receive the initialization scan signal output from the previous stage through the third input terminal IN3'. The stages ST1' to STn' may receive the first high voltage VGH1 through the first voltage terminal V1', and may receive the first low voltage VGL1 through the second voltage terminal V2'.

[0271] The first stage ST1' may be activated in response to the second start signal FLM2. Among the second to n-th stages ST2' to STn', a current stage may be activated in response to an initialization scan signal output from a previous stage.

[0272] The activated stages ST1' to STn' may apply initialization scan signals GI1 to GIn to the pixels PX in response to the initialization clock signal ICK. The activated stages ST1' to STn' may output the initialization scan signals GI1 to GIn by using the third and fourth clock signals CK3 and CK4, the first high voltage VGH1, and the first low voltage VGL1.

[0273] In the normal mode NFD, each of the stages ST1' to STn' may output an initialization scan signal having a first operating frequency. In the low frequency mode LFD, each of the stages ST1' to STn' may output an initialization scan signal having a second operating frequency. In the low frequency mode LFD, the stages ST1' to STn' may output disabled initialization scan signals GI1 to GIn in response to the second setting signal SET2. Hereinafter, the operation will be described in detail.

[0274] Fig.23 It is shown Fig. 22 The circuit configurations of the first and second stages are shown in the diagram.

[0275] Although not shown in the drawings, each of the other stages ST3' to STn' may have Fig. 22 The first stage ST1' and the second stage ST2' have substantially the same configuration, and therefore, the configuration of the first stage ST1' will be described below.

[0276] Reference Fig.23 , the first stage ST1 ′ may include a second node controller NCT2 , a second output buffer part OBP2 , a second setting part SEP2 , and a reset part RSP.

[0277] The second node controller NCT2 may be connected to the first node ND1' and the second node ND2'. The second node controller NCT2 may receive the first high voltage VGH1, the first low voltage VGL1, the second start signal FLM2, the third clock signal CK3, and the fourth clock signal CK4. The second node controller NCT2 may control the voltage level of the first node ND1' and the voltage level of the second node ND2' in response to the first high voltage VGH1, the first low voltage VGL1, the second start signal FLM2, the third clock signal CK3, and the fourth clock signal CK4.

[0278] The second output buffer part OBP2 may be connected to the first node ND1' and the second node ND2'. The second output buffer part OBP2 may receive the first high voltage VGH1 and the first low voltage VGL1. The second output buffer part OBP2 may output the initialization scan signal GI1 according to the voltage level of the first node ND1' and the voltage level of the second node ND2'. The initialization scan signal GI1 may be provided to the third input terminal IN3' of the second stage ST2'.

[0279] The second output buffer part OBP2 may determine the output of the first high voltage VGH1 according to the voltage of the first node ND1 ′. The second output buffer part OBP2 may determine the output of the first low voltage VGL1 according to the voltage of the second node ND2 ′.

[0280] The second setting part SEP2 may be connected to the first node ND1' and the second node ND2'. The second setting part SEP2 may receive a second setting signal SET2. In response to the second setting signal SET2, the second setting part SEP2 may set the voltage of the first node ND1' to the first high voltage VGH1, and may set the voltage of the second node ND2' to the first low voltage VGL1. In this case, the second output buffer part OBP2 may stably output the disabled initialization scan signal GI1.

[0281] For the above operation, the second node controller NCT2 may include first to eighth transistors Q1 to Q8, eleventh transistors Q11 and twelfth transistors Q12, fourteenth transistors Q14 to sixteenth transistors Q16, and first capacitors C1', second capacitors C2', and third capacitors C3. For the above operation, the second output buffer part OBP2 may include a ninth transistor Q9 and a tenth transistor Q10. For the above operation, the second setting part SEP2 may include a seventeenth transistor Q17 and an eighteenth transistor Q18. The reset part RSP may include a thirteenth transistor Q13.

[0282] The first transistor Q1 to the eighteenth transistor Q18 may be PMOS transistors, but are not limited thereto. For example, the first transistor Q1 to the eighteenth transistor Q18 may be NMOS transistors. The first transistor Q1 to the eighteenth transistor Q18 may be defined as a switching element.

[0283] The first transistor Q1 may include a first electrode connected to the third input terminal IN3', a second electrode connected to the third node ND3', and a control electrode connected to the first input terminal IN1'. The third node ND3' may be connected to the second node ND2' through the twelfth transistor Q12.

[0284] Although not shown in the drawings, Fig. 20 The switching element SWD shown in FIG. can also be applied to Fig.23 The second scanning driving circuit SDC2 shown in FIG. Fig. 20 The switching element SWD shown in FIG. 1 can be connected to Fig.23 Between the second node ND2' and the third input terminal IN3', and can be switched in response to the control signal SS. Fig.23 middle, Fig. 20 The switching element SWD shown in FIG. 1 may be connected to the second node ND2 ′ through the twelfth transistor Q12 , and may be connected to the third input terminal IN3 ′ through the first transistor Q1 .

[0285] The first transistor Q1 may be switched in response to the third clock signal CK3 received through the first input terminal IN1'. When the third clock signal CK3 is at a low level, the first transistor Q1 may be turned on to apply the second start signal FLM2 received through the third input terminal IN3' to the third node ND3'. The second start signal FLM2 may be a single pulse signal ( Fig.24 ).

[0286] The second transistor Q2 may include a first electrode receiving the first high voltage VGH1, a second electrode connected to the third transistor Q3, and a control electrode connected to the fourth node ND4. The second transistor Q2 may be switched according to the voltage of the fourth node ND4.

[0287] The third transistor Q3 may include a first electrode connected to the second electrode of the second transistor Q2, a second electrode connected to the second input terminal IN2', and a control electrode connected to the sixth node ND6. The third transistor Q3 may be switched according to the voltage of the sixth node ND6. The third transistor Q3 may receive the fourth clock signal CK4 through the second input terminal IN2'.

[0288] The third capacitor C3 may be connected between the sixth node ND6 and the first electrode of the third transistor Q3. When the third transistor Q3 is turned on, the fourth clock signal CK4 may be supplied through the third transistor Q3. According to the change in the voltage level of the fourth clock signal CK4, the voltage level of the sixth node N6 may swing within a predetermined range due to the coupling of the third capacitor C3.

[0289] The fourth transistor Q4 may have a dual gate structure. The fourth transistor Q4 may include a first electrode connected to a fourth node ND4, a second electrode connected to the first input terminal IN1', and a control electrode connected to the third node ND3'. The fourth transistor Q4 may be switched according to the voltage of the third node ND3'. When the fourth transistor Q4 is turned on, the fourth transistor Q4 may apply the third clock signal CK3 received through the first input terminal IN1' to the fourth node ND4.

[0290] The fifth transistor Q5 may include a first electrode connected to the fourth node ND4, a second electrode receiving the first low voltage VGL1, and a control electrode connected to the first input terminal IN1'. The fifth transistor Q5 may be switched in response to the third clock signal CK3 received through the first input terminal IN1'. When the fifth transistor Q5 is turned on, the fifth transistor Q5 may apply the first low voltage VGL1 to the fourth node ND4.

[0291] The sixth transistor Q6 may include a first electrode connected to the first node ND1', a second electrode connected to the seventh transistor Q7, and a control electrode connected to the second input terminal IN2'. The sixth transistor Q6 may switch in response to the fourth clock signal CK4 received through the second input terminal IN2'.

[0292] The seventh transistor Q7 may include a first electrode connected to the second electrode of the sixth transistor Q6, a second electrode connected to the second input terminal IN2', and a control electrode connected to the fifth node ND5. The seventh transistor Q7 may be switched according to the voltage of the fifth node ND5. The second capacitor C2' may be connected between the fifth node ND5 and the second electrode of the sixth transistor Q6.

[0293] The eighth transistor Q8 may include a first electrode receiving the first high voltage VGH1, a second electrode connected to the first node ND1', and a control electrode connected to the third node ND3'. The eighth transistor Q8 may be switched according to the voltage of the third node ND3'.

[0294] The first capacitor C1' may be connected between the first node ND1' and the first voltage terminal V1'. The first capacitor C1' may charge a voltage applied to the first node ND1' and may stably maintain the voltage of the first node ND1'.

[0295] The eleventh transistor Q11 may include a first electrode connected to the fourth node ND4, a second electrode connected to the fifth node ND5, and a control electrode receiving the first low voltage VGL1. The eleventh transistor Q11 may be turned on by the first low voltage VGL1 and may remain turned on.

[0296] The twelfth transistor Q12 may include a first electrode connected to the third node ND3', a second electrode connected to the second node ND2', and a control electrode receiving the first low voltage VGL1. The twelfth transistor Q12 may be turned on by the first low voltage VGL1 and may remain turned on. The twelfth transistor Q12 may perform a function similar to that of the eighth transistor M8 described above.

[0297] The fourteenth transistor Q14 may include a first electrode and a control electrode connected to the sixth node ND6 and a second electrode connected to the second node ND2 ′. According to the connection structure, the fourteenth transistor Q14 may be diode-connected.

[0298] The fourteenth transistor Q14 can operate as a rectifier between the second node ND2' and the sixth node ND6. For example, the voltage of the sixth node ND6 in a form similar to an AC voltage can be converted into a form of a DC voltage at the second node ND2' by the fourteenth transistor Q14. Therefore, although the voltage of the sixth node ND6 changes, the voltage of the second node ND2' can be maintained at a constant level by the charge pump operation of the fourteenth transistor Q14.

[0299] The fifteenth transistor Q15 may include a first electrode connected to the third input terminal IN3', a second electrode connected to the sixteenth transistor Q16, and a control electrode connected to the first input terminal IN1'. The fifteenth transistor Q15 may be switched in response to the third clock signal CK3 received through the first input terminal IN1'. The fifteenth transistor Q15 may be turned on in response to the third clock signal CK3, and may provide a signal received from the third input terminal IN3' to the sixth node ND6.

[0300] The sixteenth transistor Q16 may include a first electrode connected to the second electrode of the fifteenth transistor Q15, a second electrode connected to the sixth node ND6, and a control electrode receiving the first low voltage VGL1. The sixteenth transistor Q16 may be turned on by the first low voltage VGL1 and may remain turned on. The sixteenth transistor Q16 may relieve the bias stress applied to the fifteenth transistor Q15.

[0301] The ninth transistor Q9 may include a first electrode receiving a first high voltage VGH1, a second electrode connected to an output terminal OUT', and a control electrode connected to a first node ND1'. The ninth transistor Q9 may be switched according to the voltage level of the first node ND1'. The ninth transistor Q9 may determine the output of the first high voltage VGH1 according to the voltage of the first node ND1'. The activated initialization scan signal GI1 may be output according to the change of the voltage level of the first node ND1'. The tenth transistor Q10 may include a first electrode connected to the output terminal OUT', a second electrode receiving a first low voltage VGL1, and a control electrode connected to the second node ND2'. The tenth transistor Q10 may be switched according to the voltage level of the second node ND2'. The tenth transistor Q10 may determine the output of the first low voltage VGL1 according to the voltage of the second node ND2'.

[0302] The ninth transistor Q9 may be defined as a first buffer part. That is, the first buffer part may be connected between the first voltage terminal V1' and the output terminal OUT', and may receive the first high voltage VGH1. The tenth transistor Q10 may be defined as a second buffer part. That is, the second buffer part may be connected between the second voltage terminal V2' and the output terminal OUT', and may receive the first low voltage VGL1. The ninth transistor Q9 as the first buffer part and the tenth transistor Q10 as the second buffer part may operate to output the initialization scan signal GI1 according to the voltage levels of the first node ND1' and the second node ND2'.

[0303] The seventh transistor M7 as the second buffer part can receive one of the first clock signal CK1 and the second clock signal CK2. The tenth transistor Q10 as the second buffer part can receive the first low voltage VGL1. Therefore, the second buffer part of each stage of the first scan driving circuit SDC1 and the second scan driving circuit SDC2 can receive one of the first clock signal CK1 and the second clock signal CK2 or the first low voltage VGL1.

[0304] The thirteenth transistor Q13 may include a first electrode receiving the first high voltage VGH1, a second electrode connected to the third node ND3', and a control electrode receiving the reset signal ESR. Fig. 22 Each of the stages ST1 ′ to STn′ shown in may further include an input terminal for receiving a reset signal ESR.

[0305] The reset signal ESR may be a signal activated at a low level when the display device DD is powered on or reset. When the reset signal ESR is at a low level, the thirteenth transistor Q13 may be turned on to apply the first high voltage VGH1 to the third node ND3' and the second node ND2'. Therefore, the initialization scan signal GI1 output to the output terminal OUT' when the fourth transistor Q4, the eighth transistor Q8, and the tenth transistor Q10 are turned off may be prevented from being output at an undesired level.

[0306] The seventeenth transistor Q17 may include a first electrode receiving the first high voltage VGH1, a second electrode connected to the first node ND1', and a control electrode connected to the fourth input terminal IN4'. The eighteenth transistor Q18 may include a first electrode connected to the second node ND2' through the fourteenth transistor Q14, a second electrode receiving the first low voltage VGL1, and a control electrode connected to the fourth input terminal IN4'.

[0307] The seventeenth transistor Q17 and the eighteenth transistor Q18 may be switched in response to the second setting signal SET2 received through the fourth input terminal IN4'. When the seventeenth transistor Q17 is turned on, the first high voltage VGH1 may be provided to the first node ND1' through the seventeenth transistor Q17. When the eighteenth transistor Q18 is turned on, the first low voltage VGL1 may be provided to the second node ND2' through the eighteenth transistor Q18.

[0308] Because the first node ND1 ′ has the first high voltage VGH1 , the ninth transistor Q9 may be turned off. Therefore, when the first node ND1 has the first high voltage VGH1 , the first output buffer part OBP1 may not output the first high voltage VGH1 .

[0309] Because the second node ND2' has the first low voltage VGL1, the tenth transistor Q10 may be turned on. Therefore, when the second node ND2' has the first low voltage VGL1, the first low voltage VGL1 may be output through the output terminal OUT', and thus the disabled initialization scan signal GI1 may be output.

[0310] When a still image is displayed, the initialization scan signal GI1 may not be applied to the pixel PX from the second frame F2 in the same manner as the above-mentioned write scan signal GW1. Therefore, the initialization scan signal GI1 needs to remain disabled. However, when the voltage level of the first node ND1 and the voltage level of the second node ND2 change, the initialization scan signal GI1 may not remain disabled.

[0311] In an embodiment of the present disclosure, when a still image is displayed, the second setting part SEP2 may set the voltage level of the first node ND1' and the voltage level of the second node ND2' so that the second output buffer part OBP2 outputs a disabled initialization scan signal GI1. The second setting part SEP2 may set the voltage of the first node ND1' to the first high voltage VGH1, and may set the voltage of the second node ND2' to the first low voltage VGL1. Therefore, when a still image is displayed, the initialization scan signal GI1 may be stably maintained at a disabled level by the second setting part SEP2.

[0312] Fig.24 is shown in the normal mode from Fig. 22 2 is a diagram showing the timing of the initialization scan signal output by the stage shown in FIG. Fig.25 is shown in the low frequency mode from Fig. 22 2 is a diagram showing the timing of the initialization scan signal output by the stage shown in FIG.

[0313] Fig.24 and Fig.25 Shown with Fig.13 and Fig.14 The timing diagram in corresponds to the timing diagram.

[0314] Reference Fig. 22 , Fig.23 and Fig.24 , the first stage ST1' receiving the second start signal FLM2 may operate first. Thereafter, the second to n-th stages ST2' to STn' may sequentially operate according to the initialization scan signal output from the previous stage.

[0315] During each of the frames F1 to F4, initialization scan signals GI1 to GIn may be sequentially output and applied to the pixels PX. Therefore, in the normal mode NFD, initialization scan signals GI1 to GIn having a first operating frequency (eg, 120 Hz) may be output by the stages ST1' to STn', respectively.

[0316] An operation in which the initialization scan signals GI1 to GIn are applied to the pixels PX may be defined as an active operation in which the active initialization scan signals GI1 to GIn having a high level are applied to the pixels PX.

[0317] Reference Fig. 22 , Fig.23 and Fig.25, in the low frequency mode LFD, the initialization scan signals GI1 to GIn may be sequentially output during the first frame F1. Since the second start signal FLM2 is not applied to the second scan driving circuit SDC2 from the second frame F2, the initialization scan signals GI1 to GIn may not be output from the second frame F2. Therefore, in the low frequency mode LFD, the initialization scan signals GI1 to GIn having the second operating frequency (e.g., 1 Hz) may be output by the stages ST1' to STn', respectively.

[0318] The operation in which the initialization scan signals GI1 to GIn are not outputted may be defined as a disabling operation in which the disabled initialization scan signals GI1 to GIn having a low level are outputted. That is, the operation in which the initialization scan signals GI1 to GIn are not outputted may be defined as a disabling operation in which the disabled initialization scan signals GI1 to GIn are applied to the pixels PX.

[0319] Since the initialization scan signals GI1 to GIn are not output during the second frame F2 to the 120th frame F120 in the low frequency mode LFD, power consumption can be reduced.

[0320] Fig.26 is a diagram showing the timing of the third and fourth clock signals, the initialization scan signal, and the second setting signal in the normal mode. Fig. 27 is a diagram showing the timing of the third and fourth clock signals, the initialization scan signal, and the second setting signal in the low frequency mode.

[0321] Fig.26 and Fig. 27 Shown with Fig.15 and Fig.16 The timing diagram in corresponds to the timing diagram.

[0322] Reference Fig. 22 , Fig.23 and Fig.26 During each of the frames F1 to F4 of the normal mode NFD, the initialization scan signals GI1 to GIn may be output based on the third clock signal CK3 and the fourth clock signal CK4. The initialization scan signals GI1 to GIn may be output from the effective period AP of each of the frames F1 to F4 and may be applied to the pixels PX.

[0323] In the normal mode NFD, the second setting signal SET2 may be a DC signal having a high level. Therefore, the seventeenth transistor Q17 and the eighteenth transistor Q18 of the second setting part SEP2 may be turned off in the normal mode NFD.

[0324] Reference Fig. 22 , Fig.23 and Fig. 27In the low frequency mode LFD, the initialization clock signal ICK may have an AC signal in the first frame F1 and may have a DC signal in the second frame F2. In addition, the initialization clock signal ICK may have an AC signal in the third frame F3 and may have a DC signal in the fourth frame F4.

[0325] However, this is an example. The initialization clock signal ICK may have a DC signal in all of the second frame F2 to the 120th frame F120. In addition, the initialization clock signal ICK may have a DC signal during some consecutive frames among the second frame F2 to the 120th frame F120, and may have an AC signal during other consecutive frames. When the second setting signal SET2 is applied to the second scan driving circuit SDC2, the level of the initialization clock signal ICK may be changed to a DC level.

[0326] In the low frequency mode LFD, the second scan driving circuit SDC2 may apply the initialization scan signals GI1 to GIn to the pixels PX during the active period AP of the first frame F1. In the low frequency mode LFD, the second scan driving circuit SDC2 may not apply the initialization scan signals GI1 to GIn to the pixels PX during the non-active period NAP. During the non-active period NAP, the initialization scan signals GI1 to GIn may be maintained at a non-active low level.

[0327] The second setting signal SET2 may be activated to a low level during the blank period BLK of the first frame F1. The second scan driving circuit SDC2 may output the disabled initialization scan signals GI1 to GIn in response to the second setting signal SET2 received during the blank period BLK of the first frame F1.

[0328] In response to the second setting signal SET2, the second setting part SEP2 may set the voltage of the first node ND1' to the first high voltage VGH1, and may set the voltage of the second node ND2' to the first low voltage VGL1. Therefore, the disabled initialization scan signals GI1 to Gin are output, and thus the initialization scan signals GI1 to GIn may be more stably maintained at the disabled level.

[0329] Fig.28 is a diagram showing a circuit configuration of a first stage and a second stage of a second scan driver according to an embodiment of the present disclosure.

[0330] Fig.28 The first stage ST1-1' and the second stage ST2-1' shown in FIG. Fig.23 The first stage ST1' and the second stage ST2' shown in FIG. Fig.23 The configuration of the first stage ST1' shown in FIG. Fig.28 The configuration of the first stage ST1-1' is shown in FIG.

[0331] Reference Fig.28 ,and Fig.23 Unlike the illustration of FIG. 1 , the second setting part SEP2′ may not include the eighteenth transistor Q18 but may include the seventeenth transistor Q17. Therefore, the second setting part SEP2′ may receive the first high voltage VGH1 and may apply the first high voltage VGH1 to the first node ND1′ in response to the second setting signal SET2.

[0332] The voltage at the first node ND1' may be set to the first high voltage VGH1, and thus the second output buffer part OBP2 may not output the first high voltage VGH1. Because the voltage at the first node ND1' is set to the first high voltage VGH1 and the ninth transistor Q9 is turned off, the first high voltage VGH1 may not be output.

[0333] Fig.29 is a diagram showing the timing of a transmission clock, a transmission signal, and a bias scanning signal in a normal mode and a low frequency mode.

[0334] Despite Fig.29 , the first frame F1 and the second frame F2 are shown in FIG. 1 , but the emission signals EM1 to EMn and the bias scan signals GB1 to GBn may be generated identically until the 120th frame.

[0335] Reference Fig.29 , also refer to Figure 5 ,like Fig. 9 and Fig.10 As described above, in the low frequency mode LFD, emission signals EM1 to EMn and bias scan signals GB1 to GBn may be generated during each frame. The emission signals EM1 to EMn and the bias scan signals GB1 to GBn may be applied to the pixels PX through the emission lines EML1 to EMLn and the bias scan lines GBL1 to GBLn.

[0336] In the low frequency mode LFD, during the first frame F1, each of the emission signals EM1 to EMn and each of the bias scan signals GB1 to GBn may have a first high voltage VGH1 and a first low voltage VGL1. Although not shown in the drawings, the emission signals EM1 to EMn and the bias scan signals GB1 to GBn in the normal mode NFD may have the first high voltage VGH1 and the first low voltage VGL1 in the same manner as during the first frame F1 of the low frequency mode LFD.

[0337] In the low frequency mode LFD, during the second frame F2, each of the emission signals EM1 to EMn and each of the bias scan signals GB1 to GBn may have a second high voltage VGH2 and a first low voltage VGL1. The second high voltage VGH2 may have a level lower than the first high voltage VGH1. The first low voltage VGL1 may have a level lower than the second high voltage VGH2.

[0338] A first voltage difference ΔV1 between the first high voltage VGH1 and the first low voltage VGL1 in the first frame F1 may be greater than a second voltage difference ΔV2 between the second high voltage VGH2 and the first low voltage VGL1 in the second frame F2. As the voltage difference between the high voltage and the low voltage decreases, power consumption may be reduced.

[0339] Since each of the emission signals EM1 to EMn and each of the bias scan signals GB1 to GBn has the second high voltage VGH2 and the first low voltage VGL1 in the low frequency mode LFD, power consumption may be reduced.

[0340] The emission signals EM1 to EMn and the bias scan signals GB1 to GBn may be sequentially outputted. In this case, some of the emission signals EM1 to EMn of the first frame F1 may overlap with a boundary between the first frame F1 and the second frame F2.

[0341] The n-1th transmission signal EMn-1 and the nth transmission signal EMn among the transmission signals EM1 to EMn may overlap with the boundary between the first frame F1 and the second frame F2. However, the embodiment is not limited thereto. Various transmission signals at the rear end portion among the transmission signals EM1 to EMn may overlap with the boundary between the first frame F1 and the second frame F2.

[0342] A portion of the n-1th emission signal EMn-1 overlapping the first frame F1 and a portion of the n-th emission signal EMn overlapping the first frame F1 may have a first high voltage VGH1 and a first low voltage VGL1. A portion of the n-1th emission signal EMn-1 overlapping the second frame F2 and a portion of the n-th emission signal EMn overlapping the second frame F2 may have a second high voltage VGH2 and a first low voltage VGL1.

[0343] In the second frame F2, the first high voltage VGH1 is changed to the second high voltage VGH2, but the embodiments of the present disclosure are not limited thereto. For example, in the second frame F2, the first high voltage VGH1 may be maintained, and the first low voltage VGL1 may be changed to a second low voltage having a higher level than the first low voltage VGL1. In this case, the difference between the first high voltage VGH1 and the second low voltage may be a second voltage difference ΔV2.

[0344] Although described above with reference to embodiments, it will be appreciated by those skilled in the art that various modifications and changes may be made in the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the appended claims. In addition, the embodiments of the present disclosure are not intended to limit the technical spirit of the present disclosure. All technical spirits within the scope of the appended claims and all their equivalents should be interpreted as being included within the scope of the present disclosure.

[0345] According to an embodiment of the present disclosure, when a still image is displayed, the display panel can be driven in a low-frequency mode. In the low-frequency mode, during a frame in which a write scan signal is not applied to a pixel, a clock signal applied to a scan drive circuit can have a DC signal, and the DC level of the clock signal can be set to a lower voltage level. In addition, in the low-frequency mode, during a frame in which a write scan signal is not applied to a pixel, a high voltage level of an emission signal can have a lower level. Therefore, the power consumption of the display device can be reduced.

[0346] In addition, in the period between the active period of the first frame and the inactive period of the second frame, the scan signal output from the scan driving circuit can be stably maintained at an inactive level by the setting signal applied to the scan driving circuit. Therefore, the power consumption of the display device can be reduced.

[0347] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, wherein: The display device comprises: pixels; and a first scan driving circuit configured to apply a write scan signal to the pixel in response to a write clock signal, wherein the first scan driving circuit is configured to output the write scan signal having a first operating frequency in a normal mode, and to output the write scan signal having a second operating frequency lower than the first operating frequency in a low frequency mode, and The write clock signal has a direct current in the low frequency mode in response to a first setting signal applied to the first scan driving circuit.

2. The display device according to claim 1, wherein: The first scan driving circuit outputs a disabled write scan signal in response to the first setting signal received in a period between an active period in which the write scan signal is applied to the pixel and an inactive period in which the write scan signal is not applied to the pixel.

3. The display device according to claim 2, wherein: The low frequency mode includes: A first frame including the active period and a blanking period after the active period; and a second frame including the non-effective period and a blanking period after the non-effective period, wherein the first setting signal is applied to the first scan driving circuit in the blanking period of the first frame, and The write clock signal has an alternating current during the first frame and a direct current during the second frame.

4. The display device according to claim 3, wherein: The write clock signal has a first high voltage and a first low voltage lower than the first high voltage during the first frame, and has a second high voltage lower than the first high voltage and higher than the first low voltage during the second frame.

5. The display device according to claim 3, wherein: The low frequency mode further includes a plurality of subsequent frames after the second frame, wherein each of the plurality of subsequent frames comprises the non-effective period and the blanking period after the non-effective period, and The first setting signal is also applied to the first scan driving circuit in at least one blanking period among the blanking period of the second frame and the blanking periods of the plurality of subsequent frames.

6. The display device according to claim 5, wherein: The first setting signal is applied to the first scan driving circuit in inverse proportion to the second operating frequency.

7. The display device according to claim 3, wherein: The first scanning driving circuit comprises: a first node controller connected to a first node and a second node, and configured to receive a first high voltage, a first low voltage, a first start signal, a first clock signal, and a second clock signal, and control a voltage level of the first node and a voltage level of the second node, the first low voltage having a level lower than that of the first high voltage, and the second clock signal having a phase opposite to that of the first clock signal; a first output buffer section connected to the first node and the second node, and configured to receive the first high voltage and the second clock signal and output the write scan signal according to the voltage level of the first node and the voltage level of the second node; and a first setting portion connected to the first node and the second node, and the first setting portion is configured to receive the first setting signal, and The first output buffer part outputs the first high voltage or the second clock signal according to the voltage level of the first node and the voltage level of the second node.

8. The display device according to claim 7, wherein: The first setting part receives the first high voltage and the first low voltage, and sets the voltage level of the first node to the first low voltage and the voltage level of the second node to the first high voltage in response to the first setting signal, so that the first output buffer part outputs the disabled write scan signal.

9. The display device according to claim 7, wherein: The first setting part receives a second high voltage and a second low voltage, sets the voltage level of the first node to the second low voltage and sets the voltage level of the second node to the second high voltage in response to the first setting signal, so that the first output buffer part outputs the disabled write scan signal, and The second high voltage has a level different from that of the first high voltage, and the second low voltage has a level different from that of the first low voltage and has a level lower than that of the second high voltage.

10. The display device according to claim 3, wherein: The display device further includes: a second scanning driving circuit configured to apply an initialization scanning signal to the pixel in response to an initialization clock signal, and The second scan driving circuit outputs the disabled initialization scan signal in response to a second setting signal received in the blanking period of the first frame.

Images