Gate signal masking circuit, gate driver and display device

Abstract

The invention provides a gate signal masking circuit, a gate driver and a display device. The gate signal masking circuit includes a connection transistor connecting a first control node and a first transistor based on a connection signal, the first transistor connected to a masking node, the connection transistor, and a second control node, the first transistor including a control electrode receiving a carry signal, a second transistor receiving a first electrode of a masking signal and a second electrode connected to the first node, a third transistor including a control electrode receiving an enable signal, a first electrode connected to the first node, and a second electrode connected to the masking node, a third transistor including a control electrode receiving a second enable signal, a fourth transistor connected to a first electrode of the mask node and to a second electrode of the second node; and a fifth transistor including a control electrode receiving a carry signal, a first electrode connected to the second node, and a second electrode receiving a power voltage.

Description

Technical Field

[0001] Embodiments of the present invention relate to a gate signal masking circuit, a gate driver including the gate signal masking circuit, and a display device including the gate driver. More specifically, embodiments of the present invention relate to a gate signal masking circuit that reduces power consumption, a gate driver including the gate signal masking circuit, and a display device including the gate driver. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes a gate driver, a data driver, an emission driver, and a drive controller. The gate driver outputs a gate signal to the gate line. The data driver outputs a data voltage to the data line. The emission driver outputs an emission signal to the emission line. The drive controller controls the gate driver, the data driver, and the emission driver.

[0003] When the image displayed on the display panel is a static image or the display panel operates in a screen-off mode, the driving frequency of the display panel may be reduced to reduce power consumption.

[0004] When part of the image displayed on the display panel is a static image and part of the image displayed on the display panel is a moving image, it is necessary to reduce the driving frequency of the part of the display panel corresponding to the static image to further reduce power consumption.

[0005] However, one stage of the gate driver receives an output of a previous stage as a carry signal to output a gate signal, so that it may not be possible to reduce the driving frequency of only a portion of the display panel.

[0006] Furthermore, when a first gate signal generator for generating a data initialization gate signal and a second gate signal generator for generating a compensation gate signal are commonly formed, waveforms of the data initialization gate signal and the compensation gate signal may not be differently generated. Summary of the invention

[0007] Embodiments of the present invention provide a gate signal masking circuit that supports multiple divisions of a driving frequency to reduce power consumption of a display device and is capable of differently generating waveforms of a data initialization gate signal and a compensation gate signal.

[0008] Embodiments of the present invention also provide a gate driver including a gate signal masking circuit.

[0009] Embodiments of the present invention also provide a display device including a gate driver.

[0010] In an embodiment of a gate signal masking circuit according to the present invention, the gate signal masking circuit includes a connection control switch element, a first switch element, a second switch element, a third switch element, a fourth switch element and a fifth switch element. The connection control switch element is configured to connect the first control node and the first switch element based on the connection control signal. The first switch element includes a control electrode connected to the masking control node, a first electrode connected to the connection control switch element and a second electrode connected to the second control node. The second switch element includes a control electrode configured to receive a carry signal, a first electrode configured to receive a masking power signal and a second electrode connected to the first intermediate node. The third switch element includes a control electrode configured to receive a first enable signal, a first electrode connected to the first intermediate node and a second electrode connected to the masking control node. The fourth switch element includes a control electrode configured to receive a second enable signal, a first electrode connected to the masking control node and a second electrode connected to the second intermediate node. The fifth switch element includes a control electrode configured to receive a carry signal, a first electrode connected to the second intermediate node and a second electrode configured to receive a low power voltage.

[0011] In an embodiment, the gate signal masking circuit may further include: a sixth switching element including a control electrode connected to the second control node, a first electrode configured to receive a first clock signal, and a second electrode connected to the gate output node, a seventh switching element including a control electrode configured to receive a carry signal, a first electrode connected to the gate output node, and a second electrode configured to receive a low power voltage, and an eighth switching element including a control electrode configured to receive a carry signal, a first electrode configured to receive the first clock signal, and a second electrode connected to the second control node.

[0012] In an embodiment, the gate signal masking circuit may further include a first masking capacitor and a second masking capacitor, the first masking capacitor including a first electrode configured to receive a first clock signal and a second electrode connected to a second control node, the second masking capacitor including a first electrode connected to a masking control node and a second electrode configured to receive a low power voltage.

[0013] In an embodiment, the masked power signal may be a first clock signal.The first electrode of the second switching element may be connected to the first electrode of the sixth switching element.

[0014] In an embodiment, the gate signal masking circuit may be configured to output the gate pulse when the first enable signal has an inactive level in all periods in which the carry signal has an active level.

[0015] In an embodiment, the gate signal masking circuit may be configured not to output the gate pulse when the first enable signal has a valid level in all periods in which the carry signal has a valid level.

[0016] In an embodiment, the gate signal masking circuit may be configured to output the gate pulse when the first enable signal changes from an inactive level to an active level during a period in which the carry signal has an active level.

[0017] In an embodiment, the gate signal masking circuit may be configured not to output the gate pulse when the first enable signal changes from the active level to the inactive level during a period in which the carry signal has the active level.

[0018] In an embodiment, the connection control signal may be one of a plurality of previous carry signals. The connection control switch element may be a P-type transistor.

[0019] In an embodiment, the connection control signal may be an inverted signal of one of a plurality of previous carry signals. The connection control switch element may be an N-type transistor.

[0020] In an embodiment of the gate driver according to the present invention, the gate driver includes a carry generator, a first masking circuit and a second masking circuit. The carry generator is configured to generate a carry signal based on a previous carry signal. The first masking circuit is connected to the carry generator and configured to output a first gate signal. The second masking circuit is connected to the carry generator and configured to output a second gate signal. The first masking circuit includes a connection control switch element connecting a first control node of the carry generator and a first switch element of the first masking circuit.

[0021] In an embodiment, the first control node of the carry generator may be directly connected to the ninth switching element of the second masking circuit.

[0022] In an embodiment, the first masking circuit may include: a control electrode connected to a first masking control node, a first switch element connected to a first electrode of a control switch element and a second electrode connected to a second control node, a control electrode configured to receive a carry signal, a first electrode configured to receive a masking power signal and a second electrode connected to a first intermediate node, a control electrode configured to receive a first enable signal, a first electrode connected to the first intermediate node and a second electrode connected to the first masking control node, a control electrode configured to receive a second enable signal, a first electrode connected to the first masking control node and a second electrode connected to the second intermediate node, and a third switch element configured to receive a second enable signal, a first electrode connected to the first masking control node and a second electrode connected to the second intermediate node. electrode, a fourth switching element including a control electrode configured to receive a carry signal, a first electrode connected to the second intermediate node and a second electrode configured to receive a low power voltage, a sixth switching element including a control electrode connected to the second control node, a first electrode configured to receive a first clock signal and a second electrode connected to the first gate output node, a seventh switching element including a control electrode configured to receive a carry signal, a first electrode connected to the first gate output node and a second electrode configured to receive a low power voltage, and an eighth switching element including a control electrode configured to receive a carry signal, a first electrode configured to receive the first clock signal and a second electrode connected to the second control node.

[0023] In an embodiment, the second masking circuit may include: a ninth switching element including a control electrode connected to the second masking control node, a first electrode connected to the first control node, and a second electrode connected to the third control node; a tenth switching element including a control electrode configured to receive a carry signal, a first electrode configured to receive a masking power signal, and a second electrode connected to the third intermediate node; an eleventh switching element including a control electrode configured to receive a first enable signal, a first electrode connected to the third intermediate node, and a second electrode connected to the second masking control node; a control electrode configured to receive a second enable signal, a first electrode connected to the second masking control node, and a second electrode connected to the fourth intermediate node. A twelfth switching element, including a control electrode configured to receive a carry signal, a first electrode connected to a fourth intermediate node, and a second electrode configured to receive a low power voltage; a fourteenth switching element including a control electrode connected to a third control node, a first electrode configured to receive a first clock signal, and a second electrode connected to a second gate output node; a fifteenth switching element including a control electrode configured to receive a carry signal, a first electrode connected to the second gate output node, and a second electrode configured to receive a low power voltage; and a sixteenth switching element including a control electrode configured to receive a carry signal, a first electrode configured to receive a first clock signal, and a second electrode connected to the third control node.

[0024] In an embodiment, the carry generator may include: a first carry switch element including a control electrode configured to receive a second carry clock signal, a first electrode configured to receive a previous carry signal, and a second electrode connected to a first carry node, a second carry switch element including a first control electrode configured to receive the first carry clock signal, a first electrode configured to receive a previous carry signal, and a second electrode connected to the first carry node, a fourth carry switch element including a control electrode connected to the first carry node, a first electrode configured to receive a high power voltage, and a second electrode connected to the second carry node, a fifth carry switch element including a first control electrode connected to the first carry node, a first electrode configured to receive a low power voltage, and a second electrode connected to the second carry node, a seventh carry switch element including a control electrode connected to the second carry node, a first electrode configured to receive a high power voltage, and a second electrode connected to a carry output node, and an eighth carry switch element including a first control electrode connected to the second carry node, a first electrode configured to receive a low power voltage, and a second electrode connected to the carry output node.

[0025] In an embodiment, the carry generator may further include: a third carry switch element including a control electrode connected to ground, a first electrode connected to ground, and a second electrode connected to the second control electrode of the second carry switch element, a sixth carry switch element including a control electrode connected to ground, a first electrode connected to ground, and a second electrode connected to the second control electrode of the fifth carry switch element, and a ninth carry switch element including a control electrode connected to ground, a first electrode connected to ground, and a second electrode connected to the second control electrode of the eighth carry switch element.

[0026] In an embodiment, the first gate signal may be configured to output a single pulse in one frame. The second gate signal may be configured to output two pulses in the one frame.

[0027] In an embodiment of a display device according to the present invention, the display device includes a display panel, a gate driver and a data driver. The display panel includes pixels, and the pixels include a first type of switching element and a second type of switching element different from the first type. The gate driver is configured to output a first gate signal and a second gate signal to the display panel. The data driver is configured to output a data voltage to the display panel. The gate driver includes a carry generator configured to generate a carry signal based on a previous carry signal, a first masking circuit connected to the carry generator and configured to output the first gate signal, and a second masking circuit connected to the carry generator and configured to output the second gate signal. The first masking circuit includes a connection control switch element connecting a first control node of the carry generator and a first switching element of the first masking circuit.

[0028] In an embodiment, the first control node of the carry generator may be directly connected to the ninth switching element of the second masking circuit.

[0029] In an embodiment, a pixel may include: a first pixel switching element including a control electrode connected to a first pixel node, a first electrode connected to a second pixel node, and a second electrode connected to a third pixel node, a second pixel switching element including a control electrode configured to receive a data write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the second pixel node, a third pixel switching element including a control electrode configured to receive a compensation gate signal, a first electrode connected to the first pixel node, and a second electrode connected to the third pixel node, a fourth pixel switching element including a control electrode configured to receive a data initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the first pixel node, a fifth pixel switching element including a control electrode configured to receive an emission signal, a first electrode configured to receive a pixel high power voltage, and a second electrode connected to the second pixel node, a sixth pixel switching element including a control electrode configured to receive an emission signal, a first electrode connected to the third pixel node, and a second electrode connected to an anode of a light emitting element, a seventh pixel switching element including a control electrode configured to receive a light emitting element initialization gate signal, a first electrode configured to receive a light emitting element initialization voltage, and a second electrode connected to the anode of the light emitting element, and a light emitting element including an anode and a cathode configured to receive a pixel low power voltage. The waveform of the first gate signal output from the first masking circuit may be different from the waveform of the second gate signal output from the second masking circuit. The first gate signal may be a data initialization gate signal. The second gate signal may be a compensation gate signal.

[0030] In an embodiment, a pixel may include: a first pixel switching element including a control electrode connected to a first pixel node, a first electrode connected to a second pixel node, and a second electrode connected to a third pixel node, a second pixel switching element including a control electrode configured to receive a data write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the second pixel node, a third pixel switching element including a control electrode configured to receive a compensation gate signal, a first electrode connected to the first pixel node, and a second electrode connected to the third pixel node, a fourth pixel switching element including a control electrode configured to receive a data initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the first pixel node, a fifth pixel switching element including a control electrode configured to receive an emission signal, a first electrode configured to receive a pixel high power voltage, and a second electrode connected to the second pixel node, a sixth pixel switching element including a control electrode configured to receive an emission signal, a first electrode connected to the third pixel node, and a second electrode connected to an anode of a light emitting element, a seventh pixel switching element including a control electrode configured to receive a light emitting element initialization gate signal, a first electrode configured to receive a light emitting element initialization voltage, and a second electrode connected to the anode of the light emitting element, and a light emitting element including an anode and a cathode configured to receive a pixel low power voltage. The light emitting element initialization gate signal may be a data write gate signal of a previous stage. The waveform of the first gate signal output from the first masking circuit may be different from the waveform of the second gate signal output from the second masking circuit. The first gate signal may be a data initialization gate signal. The second gate signal may be a compensation gate signal.

[0031] In an embodiment, a pixel may include: a first pixel switching element including a control electrode connected to a first pixel node, a first electrode connected to a second pixel node, and a second electrode connected to a third pixel node; a second pixel switching element including a control electrode configured to receive a data write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the second pixel node; a third pixel switching element including a control electrode configured to receive a compensation gate signal, a first electrode connected to the first pixel node, and a second electrode connected to the third pixel node; a fourth pixel switching element including a control electrode configured to receive a data initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the first pixel node; and a A control electrode of a first pixel node, a first electrode configured to receive a pixel high power voltage and a second electrode connected to a second pixel node, a sixth pixel switching element including a control electrode configured to receive an emission signal, a first electrode connected to a third pixel node and a second electrode connected to an anode of a light emitting element, a seventh pixel switching element including a control electrode configured to receive a light emitting element initialization gate signal, a first electrode configured to receive a light emitting element initialization voltage and a second electrode connected to an anode of a light emitting element, an eighth pixel switching element including a control electrode configured to receive a bias gate signal, a first electrode configured to receive a bias voltage and a second electrode connected to a second pixel node, and a light emitting element including an anode and a cathode configured to receive a pixel low power voltage. The waveform of the first gate signal output from the first masking circuit may be different from the waveform of the second gate signal output from the second masking circuit. The first gate signal may be a data initialization gate signal. The second gate signal may be a compensation gate signal.

[0032] According to the gate signal masking circuit, the gate driver and the display device, the output of the gate signal can be controlled based on the carry signal, the first enable signal and the second enable signal, so that multiple divisions of the driving frequency can be supported. Through the multiple divisions of the driving frequency, the power consumption of the display device can be effectively reduced.

[0033] In addition, when the first gate signal generator for generating the data initialization gate signal and the second gate signal generator for generating the compensation gate signal are commonly formed, the first masking circuit for outputting the data initialization gate signal further includes a control switch element, but the second masking circuit for outputting the compensation gate signal does not further include a control switch element, so that the waveforms of the data initialization gate signal and the compensation gate signal can be generated differently. The data initialization gate signal and the compensation gate signal are generated differently, so that the display quality of the display panel can be effectively enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other features and advantages of the present invention will become more apparent by describing in detail embodiments of the present invention with reference to the accompanying drawings, in which:

[0035] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention;

[0036] Figure 2 It is shown Figure 1 A circuit diagram of an example of a pixel of a display panel;

[0037] Figure 3 It is shown Figure 1 A circuit diagram of another example of a pixel of a display panel;

[0038] Figure 4 It is shown Figure 1 A circuit diagram of another example of a pixel of a display panel;

[0039] Figure 5 It is shown Figure 1 Conceptual diagram of the gate driver;

[0040] Figure 6 It shows that according to Figure 1 The driving frequencies of various parts of the display panel are applied to Figure 1 A conceptual diagram of a first enable signal and a second enable signal of a gate driver;

[0041] Fig. 7A It is shown Figure 1 A block diagram of an example of a carry generator, a first masking circuit, and a second masking circuit of a gate driver;

[0042] Figure 7B It is shown Figure 1 block diagram of other examples of a carry generator, a first masking circuit, and a second masking circuit of a gate driver;

[0043] Figure 8 is shown in Figure 1. Figure 2 A timing diagram of an input signal of a pixel;

[0044] Fig. 9 is shown in the self-scan period applied to Figure 2 A timing diagram of an input signal of a pixel;

[0045] Fig.10 It is shown Figure 1 A circuit diagram of a carry generator, a first masking circuit and a second masking circuit of a gate driver;

[0046] Fig.11 It is shown Fig.10A timing diagram of input signals, node signals and output signals of a carry generator, a first masking circuit and a second masking circuit;

[0047] Fig.12 is shown in the first case Fig.10 A timing diagram of input signals, node signals and output signals of a carry generator, a first masking circuit and a second masking circuit;

[0048] Fig.13 is shown in the second case Fig.10 A timing diagram of input signals, node signals and output signals of a carry generator, a first masking circuit and a second masking circuit;

[0049] Fig.14 It is shown that in the third case Fig.10 A timing diagram of input signals, node signals and output signals of a carry generator, a first masking circuit and a second masking circuit;

[0050] Fig.15 It is shown that in the fourth case Fig.10 A timing diagram of input signals, node signals and output signals of a carry generator, a first masking circuit and a second masking circuit;

[0051] Fig.16 It is shown Figure 1 A block diagram of an example of a carry generator, a first masking circuit, and a second masking circuit of a gate driver;

[0052] Fig.17 is a block diagram showing an electronic device according to an embodiment of the present invention; and

[0053] Fig.18 It is shown Fig.17 FIG. 4 is a diagram of an example in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0054] The terms used herein are only for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, "a", "an", "the", and "at least one" as used herein do not represent a limit to quantity and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one" should not be interpreted as limiting "a" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that when the terms “comprises” and / or “comprising” or “includes” and / or “including” are used in the present specification, it specifies the presence of stated features, regions, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or clusters thereof.

[0055] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "first component", "first region", "first layer" or "first part" discussed below can be referred to as the second element, second component, second region, second layer or second part without departing from the teachings herein. Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings.

[0056] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0057] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0058] The display panel 100 has a display area displaying an image and a peripheral area adjacent to the display area.

[0059] The display panel 100 includes a plurality of gate lines GWL, GCL, GIL, and GBL, a plurality of data lines DL, a plurality of emission lines EML, and a plurality of pixels electrically connected to the gate lines GWL, GCL, GIL, and GBL, the data lines DL, and the emission lines EML. The gate lines GWL, GCL, GIL, and GBL may extend in a first direction D1, the data lines DL may extend in a second direction D2 crossing the first direction D1, and the emission lines EML may extend in the first direction D1.

[0060] The driving controller 200 receives input image data IMG and an input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0061] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0062] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0063] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0064] The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0065] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0066] The driving controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600 .

[0067] The gate driver 300 generates a gate signal for driving the gate lines GWL, GCL, GIL, and GBL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may sequentially output the gate signal to the gate lines GWL, GCL, GIL, and GBL. Herein, the gate signal transmitted by the gate line GWL may be referred to as a data writing gate signal GW, the gate signal transmitted by the gate line GCL may be referred to as a compensation gate signal GC or a second gate signal GC, and the gate signal transmitted by the gate line GIL may be referred to as a data initialization gate signal GI or a first gate signal GI, as shown in FIG. Figure 8 and Fig. 9 as shown in .

[0068] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0069] In an implementation, the gamma reference voltage generator 400 may be disposed in the driving controller 200 or in the data driver 500 .

[0070] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200 and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into an analog type data voltage using the gamma reference voltage VGREF and outputs the data voltage to the data line DL.

[0071] The emission driver 600 generates an emission signal to drive the emission line EML in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission line EML. Herein, the emission signal transmitted by the emission line EML may be referred to as the emission signal EM. Figure 8 and Fig. 9 as shown in .

[0072] Although for the convenience of explanation, Figure 1The gate driver 300 in the embodiment is arranged at a first side of the display panel 100, and the emission driver 600 is arranged at a second side of the display panel 100 opposite to the first side, but the present invention may not be limited thereto. For example, both the gate driver 300 and the emission driver 600 may be arranged at a first side of the display panel 100. For example, the gate driver 300 and the emission driver 600 may be arranged at both sides of the display panel 100. For example, the gate driver 300 and the emission driver 600 may be formed integrally.

[0073] Figure 2 It is shown Figure 1 FIG. 1 is a circuit diagram of an example of a pixel of the display panel 100 .

[0074] Reference Figure 1 and Figure 2 , the display panel 100 includes a plurality of pixels. Each of the pixels includes a light emitting element EE.

[0075] The pixel receives the data write gate signal GW[n], the compensation gate signal GC[n], the data initialization gate signal GI[n], the light emitting element initialization gate signal GB[n], the data voltage VDATA and the emission signal EM[n], and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0076] In this embodiment, the pixel may include a first type of switching element and a second type of switching element different from the first type. For example, the first type of switching element may be a polysilicon thin film transistor. For example, the first type of switching element may be a low temperature polysilicon (LTPS) thin film transistor. For example, the second type of switching element may be an oxide thin film transistor. For example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor.

[0077] At least one of the pixels may include first to seventh pixel switching elements PT1 to PT7 and a light emitting element EE.

[0078] The pixel may include a first pixel switching element PT1, a second pixel switching element PT2, a third pixel switching element PT3, a fourth pixel switching element PT4, a fifth pixel switching element PT5, a sixth pixel switching element PT6, a seventh pixel switching element PT7 and a light emitting element EE, the first pixel switching element PT1 includes a control electrode connected to the first pixel node N1, a first electrode connected to the second pixel node N2 and a second electrode connected to the third pixel node N3, the second pixel switching element PT2 includes a control electrode for receiving a data write gate signal GW[n], a first electrode for receiving a data voltage VDATA and a second electrode connected to the second pixel node N2, the third pixel switching element PT3 includes a control electrode for receiving a compensation gate signal GC[n], a first electrode connected to the first pixel node N1 and a second electrode connected to the third pixel node N3, and the fourth pixel switching element PT4 includes a control electrode for receiving a compensation gate signal GC[n], a first electrode connected to the first pixel node N1 and a second electrode connected to the third pixel node N3. The pixel switching element PT5 includes a control electrode for receiving a data initialization gate signal GI[n], a first electrode for receiving an initialization voltage VINIT, and a second electrode connected to the first pixel node N1. The pixel switching element PT5 includes a control electrode for receiving an emission signal EM[n], a first electrode for receiving a pixel high power voltage ELVDD, and a second electrode connected to the second pixel node N2. The pixel switching element PT6 includes a control electrode for receiving an emission signal EM[n], a first electrode connected to the third pixel node N3, and a second electrode connected to the anode of the light-emitting element EE. The pixel switching element PT7 includes a control electrode for receiving a light-emitting element initialization gate signal GB[n], a first electrode for receiving a light-emitting element initialization voltage VAINIT, and a second electrode connected to the anode of the light-emitting element EE. The light-emitting element EE includes an anode and a cathode for receiving a pixel low power voltage ELVSS.

[0079] The pixel may further include a storage capacitor CST and a boost capacitor CBOOST, the storage capacitor CST including a first electrode for receiving a pixel high power voltage ELVDD and a second electrode connected to the first pixel node N1, and the boost capacitor CBOOST including a first electrode for receiving a data write gate signal GW[n] and a second electrode connected to the first pixel node N1.

[0080] The driving current may flow through the fifth pixel switching element PT5, the first pixel switching element PT1 and the sixth pixel switching element PT6 to drive the light emitting element EE. The intensity of the driving current may be determined by the level of the data voltage VDATA. The brightness of the light emitting element EE may be determined by the intensity of the driving current.

[0081] In the present embodiment, when the image displayed on the display panel 100 is a static image or the display panel is operated in the screen-off mode, the driving frequency of the display panel 100 can be reduced to reduce power consumption. When all of the switching elements of the pixels of the display panel 100 are polysilicon thin film transistors, flickering may be generated due to leakage current of the pixel switching elements in the low-frequency driving mode. Therefore, some of the pixel switching elements may be designed using oxide thin film transistors. In the present exemplary embodiment, the third pixel switching element PT3 and the fourth pixel switching element PT4 may be oxide thin film transistors. The first pixel switching element PT1, the second pixel switching element PT2, the fifth pixel switching element PT5, the sixth pixel switching element PT6, and the seventh pixel switching element PT7 may be polysilicon thin film transistors.

[0082] Although in the present embodiment, some of the pixel switching elements are oxide thin film transistors and other pixel switching elements are polysilicon thin film transistors, the present invention may not be limited to this. The present invention may be applied to pixels including only oxide thin film transistors. Although in the present embodiment, some of the pixel switching elements are N-type transistors and other pixel switching elements are P-type transistors, the present invention may not be limited to this. The present invention may be applied to pixels including only N-type transistors.

[0083] Figure 3 It is shown Figure 1 FIG. 1 is a circuit diagram of another example of a pixel of the display panel 100 .

[0084] Reference Figure 1 and Figure 3 , the display panel 100 includes a plurality of pixels. Each of the pixels includes a light emitting element EE.

[0085] The pixel receives the data write gate signal GW[n], the compensation gate signal GC[n], the data initialization gate signal GI[n], the light emitting element initialization gate signal GB[n], the data voltage VDATA and the emission signal EM[n], and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0086] In this embodiment, the pixel may include a first type of switching element and a second type of switching element different from the first type. For example, the first type of switching element may be a polysilicon thin film transistor. For example, the first type of switching element may be a low temperature polysilicon (LTPS) thin film transistor. For example, the second type of switching element may be an oxide thin film transistor. For example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor.

[0087] At least one of the pixels may include first to seventh pixel switching elements PT1 to PT7 and a light emitting element EE.

[0088] The pixel may include a first pixel switching element PT1, a second pixel switching element PT2, a third pixel switching element PT3, a fourth pixel switching element PT4, a fifth pixel switching element PT5, a sixth pixel switching element PT6, a seventh pixel switching element PT7 and a light emitting element EE, the first pixel switching element PT1 includes a control electrode connected to the first pixel node N1, a first electrode connected to the second pixel node N2 and a second electrode connected to the third pixel node N3, the second pixel switching element PT2 includes a control electrode for receiving a data write gate signal GW[n], a first electrode for receiving a data voltage VDATA and a second electrode connected to the second pixel node N2, the third pixel switching element PT3 includes a control electrode for receiving a compensation gate signal GC[n], a first electrode connected to the first pixel node N1 and a second electrode connected to the third pixel node N3, and the fourth pixel switching element PT4 includes a control electrode for receiving a compensation gate signal GC[n], a first electrode connected to the first pixel node N1 and a second electrode connected to the third pixel node N3. The pixel switching element PT5 includes a control electrode for receiving a data initialization gate signal GI[n], a first electrode for receiving an initialization voltage VINIT, and a second electrode connected to the first pixel node N1. The pixel switching element PT5 includes a control electrode for receiving an emission signal EM[n], a first electrode for receiving a pixel high power voltage ELVDD, and a second electrode connected to the second pixel node N2. The pixel switching element PT6 includes a control electrode for receiving an emission signal EM[n], a first electrode connected to the third pixel node N3, and a second electrode connected to the anode of the light-emitting element EE. The pixel switching element PT7 includes a control electrode for receiving a light-emitting element initialization gate signal GB[n], a first electrode for receiving a light-emitting element initialization voltage VAINIT, and a second electrode connected to the anode of the light-emitting element EE. The light-emitting element EE includes an anode and a cathode for receiving a pixel low power voltage ELVSS.

[0089] The pixel may further include a storage capacitor CST and a boost capacitor CBOOST, the storage capacitor CST including a first electrode for receiving a pixel high power voltage ELVDD and a second electrode connected to the first pixel node N1, and the boost capacitor CBOOST including a first electrode for receiving a data write gate signal GW[n] and a second electrode connected to the first pixel node N1.

[0090] In this embodiment, the light emitting element initialization gate signal GB[n] may be the data writing gate signal GW[n-1] of the previous stage (see Figure 3). When the data write gate signal GW[n-1] of the previous stage is used as the light emitting element initialization gate signal GB[n] of the current stage, part of the gate signal generating circuit of the gate driver 300 can be omitted. Therefore, the manufacturing cost of the display device can be reduced, and the dead zone of the display device can be reduced.

[0091] In the present embodiment, when the image displayed on the display panel 100 is a static image or the display panel is operated in the screen-off mode, the driving frequency of the display panel 100 can be reduced to reduce power consumption. When all of the switching elements of the pixels of the display panel 100 are polysilicon thin film transistors, flickering may be generated due to leakage current of the pixel switching elements in the low-frequency driving mode. Therefore, some of the pixel switching elements may be designed using oxide thin film transistors. In the present exemplary embodiment, the third pixel switching element PT3 and the fourth pixel switching element PT4 may be oxide thin film transistors. The first pixel switching element PT1, the second pixel switching element PT2, the fifth pixel switching element PT5, the sixth pixel switching element PT6, and the seventh pixel switching element PT7 may be polysilicon thin film transistors.

[0092] Although in the present embodiment, some of the pixel switching elements are oxide thin film transistors and other pixel switching elements are polysilicon thin film transistors, the present invention may not be limited to this. The present invention may be applied to pixels including only oxide thin film transistors. Although in the present embodiment, some of the pixel switching elements are N-type transistors and other pixel switching elements are P-type transistors, the present invention may not be limited to this. The present invention may be applied to pixels including only N-type transistors.

[0093] Figure 4 It is shown Figure 1 FIG. 1 is a circuit diagram of another example of a pixel of the display panel 100 .

[0094] Reference Figure 1 and Figure 4 , the display panel 100 includes a plurality of pixels. Each of the pixels includes a light emitting element EE.

[0095] The pixel receives a data write gate signal GW[n], a compensation gate signal GC[n], a data initialization gate signal GI[n], a light emitting element initialization gate signal GB[n], a bias gate signal GBI[n], a data voltage VDATA and an emission signal EM[n], and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0096] In this embodiment, the pixel may include a first type of switching element and a second type of switching element different from the first type. For example, the first type of switching element may be a polysilicon thin film transistor. For example, the first type of switching element may be a low temperature polysilicon (LTPS) thin film transistor. For example, the second type of switching element may be an oxide thin film transistor. For example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor.

[0097] At least one of the pixels may include first to eighth pixel switching elements PT1 to PT8 and a light emitting element EE.

[0098] The pixel may include a first pixel switching element PT1, a second pixel switching element PT2, a third pixel switching element PT3, a fourth pixel switching element PT4, a fifth pixel switching element PT5, a sixth pixel switching element PT6, a seventh pixel switching element PT7, an eighth pixel switching element PT8 and a light emitting element EE, the first pixel switching element PT1 includes a control electrode connected to the first pixel node N1, a first electrode connected to the second pixel node N2 and a second electrode connected to the third pixel node N3, the second pixel switching element PT2 includes a control electrode for receiving a data write gate signal GW[n], a first electrode for receiving a data voltage VDATA and a second electrode connected to the second pixel node N2, the third pixel switching element PT3 includes a control electrode for receiving a compensation gate signal GC[n], a first electrode connected to the first pixel node N1 and a second electrode connected to the third pixel node N3, the fourth pixel switching element PT4 includes a control electrode for receiving a data initialization gate signal GI[n], a first electrode for receiving a data voltage VDATA The first electrode of the initialization voltage VINIT and the second electrode connected to the first pixel node N1, the fifth pixel switching element PT5 includes a control electrode for receiving the emission signal EM[n], a first electrode for receiving the pixel high power voltage ELVDD and a second electrode connected to the second pixel node N2, the sixth pixel switching element PT6 includes a control electrode for receiving the emission signal EM[n], a first electrode connected to the third pixel node N3 and a second electrode connected to the anode of the light-emitting element EE, the seventh pixel switching element PT7 includes a control electrode for receiving the light-emitting element initialization gate signal GB[n], a first electrode for receiving the light-emitting element initialization voltage VAINIT and a second electrode connected to the anode of the light-emitting element EE, the eighth pixel switching element PT8 includes a control electrode for receiving the bias gate signal GBI[n], a first electrode for receiving the bias voltage VBIAS and a second electrode connected to the second pixel node N2, and the light-emitting element EE includes an anode and a cathode for receiving the pixel low power voltage ELVSS.

[0099] The pixel may further include a storage capacitor CST and a boost capacitor CBOOST, the storage capacitor CST including a first electrode for receiving a pixel high power voltage ELVDD and a second electrode connected to the first pixel node N1, and the boost capacitor CBOOST including a first electrode for receiving a data write gate signal GW[n] and a second electrode connected to the first pixel node N1.

[0100] In the present embodiment, when the image displayed on the display panel 100 is a static image or the display panel is operated in the screen-off mode, the driving frequency of the display panel 100 can be reduced to reduce power consumption. When all of the switching elements of the pixels of the display panel 100 are polysilicon thin film transistors, flickering may be generated due to leakage current of the pixel switching elements in the low-frequency driving mode. Therefore, some of the pixel switching elements may be designed using oxide thin film transistors. In the present exemplary embodiment, the third pixel switching element PT3 and the fourth pixel switching element PT4 may be oxide thin film transistors. The first pixel switching element PT1, the second pixel switching element PT2, the fifth pixel switching element PT5, the sixth pixel switching element PT6, the seventh pixel switching element PT7, and the eighth pixel switching element PT8 may be polysilicon thin film transistors.

[0101] Although in the present embodiment, some of the pixel switching elements are oxide thin film transistors and other pixel switching elements are polysilicon thin film transistors, the present invention may not be limited to this. The present invention may be applied to pixels including only oxide thin film transistors. Although in the present embodiment, some of the pixel switching elements are N-type transistors and other pixel switching elements are P-type transistors, the present invention may not be limited to this. The present invention may be applied to pixels including only N-type transistors.

[0102] Figure 5 It is shown Figure 1 A conceptual diagram of a gate driver 300 is shown. Figure 6 It shows that according to Figure 1 The driving frequencies of the various parts of the display panel 100 are applied to Figure 1 1 and 2. Conceptual diagram of a first enable signal EN and a second enable signal ENB of a gate driver 300.

[0103] Reference Figures 1 to 6 , the gate driver 300 may include a carry generator ST for generating a carry signal based on a previous carry signal and a gate signal masking circuit MC connected to the carry generator ST.

[0104] The gate signal masking circuit MC may output or not output a gate pulse according to the carry signal, the first enable signal EN, and the second enable signal ENB.

[0105] For example, when the first enable signal EN has a high level H and the second enable signal ENB has a low level L, the gate signal masking circuit MC may output a gate pulse.

[0106] For example, when the first enable signal EN has a low level L and the second enable signal ENB has a high level H, the gate signal masking circuit MC may not output a gate pulse.

[0107] like Figure 6 As shown in , according to the first enable signal EN and the second enable signal ENB, the gate driver 300 can output a high-frequency (e.g., 120 Hz) gate pulse for a portion of the display panel 100 that requires high-frequency drive, and can output a low-frequency (e.g., 1 Hz) gate pulse for a portion of the display panel 100 that requires low-frequency drive.

[0108] The gate signal masking circuit MC can mask the output of the gate pulse to output a gate pulse of a low frequency (e.g., 1 Hz). The carry generator ST transmits the carry signal to the subsequent stage regardless of the operation of the gate signal masking circuit MC that masks the output of the gate pulse, so that the gate driver 300 can support multiple divisions of the driving frequency (i.e., provide different frequencies according to the region).

[0109] Fig. 7A It is shown Figure 1 A block diagram of an example of carry generators CRG(n), CRG(n-1), CRG(n-2) and CRG(n-3), first masking circuits GIC(n), GIC(n-1), GIC(n-2) and GIC(n-3), and second masking circuits GCC(n), GCC(n-1), GCC(n-2) and GCC(n-3) of a gate driver 300. Figure 7B It is shown Figure 1 Block diagram of other instances of carry generators CRG(n), CRG(n-1), CRG(n-2) and CRG(n-3), first masking circuits GIC(n), GIC(n-1), GIC(n-2) and GIC(n-3) and second masking circuits GCC(n), GCC(n-1), GCC(n-2) and GCC(n-3) of the gate driver 300. Figure 8 is shown in Figure 1. Figure 2 Timing diagram of the pixel input signal. Fig. 9 is shown in the self-scan period applied to Figure 2 Timing diagram of the pixel input signal. Fig.10 It is shown Figure 1 1 is a circuit diagram of a carry generator CRG(n), a first masking circuit GIC(n), and a second masking circuit GCC(n) of a gate driver 300. Fig.11 It is shown Fig.10 A timing diagram of input signals, node signals and output signals of the carry generator CRG(n), the first masking circuit GIC(n) and the second masking circuit GCC(n).

[0110] Reference Figures 1 to 11 For example, the gate driver 300 includes a carry generator CRG(n), a first masking circuit GIC(n), and a second masking circuit GCC(n). Herein, the description of the carry generator CRG(n) is applicable to the carry generators CRG(n-1), CRG(n-2), and CRG(n-3), the description of the first masking circuit GIC(n) is applicable to the first masking circuits GIC(n-1), GIC(n-2), and GIC(n-3), and the description of the second masking circuit GCC(n) is applicable to the second masking circuits GCC(n-1), GCC(n-2), and GCC(n-3). In addition, as Fig. 7A and Figure 7B As shown in , each of the carry signals CR(n), CR(n-1), CR(n-2), and CR(n-3) may be simply shown as a carry signal CR. Fig. 7A and Figure 7B Each of the connection control switch elements S9(n), S9(n-1), S9(n-2) and S9(n-3) shown in FIG. 1 can be briefly shown as the connection control switch element S9, as shown in FIG. Fig.10 as shown in .

[0111] The carry generator CRG(n) generates the carry signal CR(n) based on the previous carry signal CR(n-1). Fig.10 The previous carry signal CR(n-1) is a carry signal of the previous stage, but the present invention is not limited thereto. The previous carry signal may be one of the carry signals of a plurality of previous stages relative to the current stage. When the carry generator CRG(n) is in the first stage of the gate driver 300, the carry generator CRG(n) may be based on Figures 12 to 15 The vertical start signal FLM shown in generates the carry signal CR(n).

[0112] The first masking circuit GIC(n) is connected to the carry generator CRG(n) and outputs a first gate signal GI(n). The second masking circuit GCC(n) is connected to the carry generator CRG(n) and outputs a second gate signal GC(n).

[0113] For example, the first gate signal GI(n) may be Figure 2 , Figure 3 and Figure 4 For example, the second gate signal GC(n) may be Figure 2 , Figure 3 and Figure 4 The "compensation gate signal" of

[0114] The first masking circuit GIC(n) includes a connection control switching element S9 that connects the first control node QB of the carry generator CRG(n) and the first switching element SI1 of the first masking circuit GIC(n) based on a connection control signal (eg, connection control signal CR(nm)).

[0115] In contrast, the second masking circuit GCC(n) does not include a connection control switching element that connects the first control node QB of the carry generator CRG(n) and the ninth switching element SC1 of the second masking circuit GCC(n) based on a connection control signal (eg, connection control signal CR(nm)).

[0116] For example, the first control node QB of the carry generator CRG(n) may be connected to the first switch element SI1 of the first masking circuit GIC(n) through the connection control switch element S9. Conversely, the first control node QB of the carry generator CRG(n) may be directly connected to the ninth switch element SC1 of the second masking circuit GCC(n).

[0117] For example, the connection control signal applied to the control electrode of the connection control switch element S9 may be as follows: Fig. 7A , the carry signal CR(n-1) of the previous stage (specifically, the carry generator CRG(n-1)) shown in .

[0118] For example, the connection control signal applied to the control electrode of the connection control switch element S9 may be as follows: Figure 7B , the carry signal CR(n-2) of the first two stages (specifically, the carry generator CRG(n-2)) shown in .

[0119] The present invention is not limited to Fig. 7A and Figure 7B The connection control signal applied to the control electrode of the connection control switch element S9 may be one previous carry signal CR(nm) of the previous carry signals of the previous stages. In addition, for example, the connection control switch element S9 may be a P-type transistor.

[0120] Fig. 7A and Figure 7BA single gate driver in may generate both a first gate signal GI and a second gate signal GC. For example, a first gate signal GI(n) generated by a first masking circuit GIC(n) of the nth level may be applied to a pixel PX(n-2) in the (n-2)th pixel row. For example, a second gate signal GC(n) generated by a second masking circuit GCC(n) of the nth level may be applied to a pixel PX(n) in the nth pixel row. Similarly, a first gate signal GI(n-1) generated by a first masking circuit GIC(n-1) of the (n-1)th level may be applied to a pixel PX(n-3) in the (n-3)th pixel row. For example, a second gate signal GC(n-1) generated by a second masking circuit GCC(n-1) of the (n-1)th level may be applied to a pixel PX(n-1) in the (n-1)th pixel row.

[0121] The first masking circuit GIC(n) may include a first switching element SI1, a second switching element SI2, a third switching element SI3, a fourth switching element SI4 and a fifth switching element SI5, the first switching element SI1 including a control electrode connected to the first masking control node S-nodeI, a first electrode connected to the connection control switching element S9 and a second electrode connected to the second control node SQB_GI, the second switching element SI2 including a control electrode for receiving a carry signal CR(n), a first electrode for receiving a masking power signal (for example, a first clock signal NCK1) and a second electrode connected to the first intermediate node IN1, the third switching element SI3 including a control electrode for receiving a first enable signal EN, a first electrode connected to the first intermediate node IN1 and a second electrode connected to the first masking control node S-nodeI, the fourth switching element SI4 including a control electrode for receiving a second enable signal ENB, a first electrode connected to the first masking control node S-nodeI and a second electrode connected to the second intermediate node IN2, and the fifth switching element SI5 including a control electrode for receiving a carry signal CR(n), a first electrode connected to the second intermediate node IN2 and a second electrode for receiving the low power voltage VGL.

[0122] The first masking circuit GIC(n) may further include a sixth switching element SI6, a seventh switching element SI7 and an eighth switching element SI8, the sixth switching element SI6 including a control electrode connected to the second control node SQB_GI, a first electrode for receiving the first clock signal NCK1 and a second electrode connected to the first gate output node for outputting the first gate signal GI(n), the seventh switching element SI7 including a control electrode for receiving a carry signal CR(n), a first electrode connected to the first gate output node for outputting the first gate signal GI(n) and a second electrode for receiving the low power voltage VGL, the eighth switching element SI8 including a control electrode for receiving the carry signal CR(n), a first electrode for receiving the first clock signal NCK1 and a second electrode connected to the second control node SQB_GI.

[0123] The first masking circuit GIC(n) may further include a first masking capacitor CI1 and a second masking capacitor CI2, the first masking capacitor CI1 including a first electrode for receiving the first clock signal NCK1 and a second electrode connected to the second control node SQB_GI, the second masking capacitor CI2 including a first electrode connected to the first masking control node S-nodeI and a second electrode for receiving the low power voltage VGL.

[0124] The mask power signal may be the first clock signal NCK1. The first electrode of the second switching element SI2 may be connected to the first electrode of the sixth switching element SI6. Alternatively, the mask power signal may be the high power voltage VGH.

[0125] The second masking circuit GCC(n) may include a ninth switching element SC1, a tenth switching element SC2, an eleventh switching element SC3, a twelfth switching element SC4 and a thirteenth switching element SC5, the ninth switching element SC1 including a control electrode connected to the second masking control node S-nodeC, a first electrode connected to the first control node QB and a second electrode connected to the third control node SQB_GC, the tenth switching element SC2 including a control electrode for receiving a carry signal CR(n), a first electrode for receiving a masking power signal (e.g., a first clock signal NCK1) and a second electrode connected to the third intermediate node IN3, the eleventh switching element SC3 including a control electrode for receiving a first enable signal EN, a first electrode connected to the third intermediate node IN3 and a second electrode connected to the second masking control node S-nodeC, the twelfth switching element SC4 including a control electrode for receiving a second enable signal ENB, a first electrode connected to the second masking control node S-nodeC and a second electrode connected to the fourth intermediate node IN4, and the thirteenth switching element SC5 including a control electrode for receiving a carry signal CR(n), a first electrode connected to the fourth intermediate node IN4 and a second electrode for receiving the low power voltage VGL.

[0126] The second masking circuit GCC(n) may further include a fourteenth switching element SC6, a fifteenth switching element SC7 and a sixteenth switching element SC8, the fourteenth switching element SC6 including a control electrode connected to the third control node SQB_GC, a first electrode for receiving the first clock signal NCK1 and a second electrode connected to the second gate output node for outputting the second gate signal GC(n), the fifteenth switching element SC7 including a control electrode for receiving the carry signal CR(n), a first electrode connected to the second gate output node for outputting the second gate signal GC(n) and a second electrode for receiving the low power voltage VGL, and the sixteenth switching element SC8 including a control electrode for receiving the carry signal CR(n), a first electrode for receiving the first clock signal NCK1 and a second electrode connected to the third control node SQB_GC.

[0127] The second masking circuit GCC(n) may further include a third masking capacitor CC1 and a fourth masking capacitor CC2, wherein the third masking capacitor CC1 includes a first electrode for receiving the first clock signal NCK1 and a second electrode connected to the third control node SQB_GC, and the fourth masking capacitor CC2 includes a first electrode connected to the second masking control node S-nodeC and a second electrode for receiving the low power voltage VGL.

[0128] For example, the carry generator CRG(n) may include an input circuit (e.g., a first carry switch element T1, a second carry switch element T2, and a third carry switch element T3), a first inverter (e.g., a fourth carry switch element T4, a fifth carry switch element T5, and a sixth carry switch element T6), and a second inverter (e.g., a seventh carry switch element T7, an eighth carry switch element T8, and a ninth carry switch element T9).

[0129] The carry generator CRG(n) may include a first carry switch element T1, a second carry switch element T2, a fourth carry switch element T4, a fifth carry switch element T5, a seventh carry switch element T7 and an eighth carry switch element T8, the first carry switch element T1 including a control electrode for receiving a second carry clock signal CKB, a first electrode for receiving a previous carry signal CR(n-1) and a second electrode connected to a first carry node A(n), the second carry switch element T2 including a first control electrode for receiving a first carry clock signal CK, a first electrode for receiving a previous carry signal CR(n-1) and a second electrode connected to the first carry node A(n), the fourth carry switch element T4 including a first electrode connected to the first carry node A(n) a control electrode connected to the first carry node A(n), a first electrode for receiving the high power voltage VGH and a second electrode connected to the second carry node B(n); a fifth carry switch element T5 includes a first control electrode connected to the first carry node A(n), a first electrode for receiving the low power voltage VGL and a second electrode connected to the second carry node B(n); a seventh carry switch element T7 includes a control electrode connected to the second carry node B(n), a first electrode for receiving the high power voltage VGH and a second electrode connected to a carry output node for outputting a carry signal CR(n); an eighth carry switch element T8 includes a first control electrode connected to the second carry node B(n), a first electrode for receiving the low power voltage VGL and a second electrode connected to the carry output node.

[0130] The first carry switch element T1 may output the previous carry signal CR(n-1) to the first carry node A(n) in response to the second carry clock signal CKB. The second carry switch element T2 may output the previous carry signal CR(n-1) to the first carry node A(n) in response to the first carry clock signal CK. For example, the first carry switch element T1 may be a P-type transistor, and the second carry switch element T2 may be an N-type dual-gate transistor.

[0131] The fourth carry switch element T4 may be a P-type transistor, and the fifth carry switch element T5 may be an N-type dual-gate transistor. The fourth carry switch element T4 and the fifth carry switch element T5 may invert the signal of the first carry node A(n), and output the inverted signal of the first carry node A(n) to the second carry node B(n). Here, the second carry node B(n) may be the first control node QB.

[0132] The seventh carry switch element T7 may be a P-type transistor, and the eighth carry switch element T8 may be an N-type dual-gate transistor. The seventh carry switch element T7 and the eighth carry switch element T8 may invert the signal of the second carry node B(n) and output the inverted signal of the second carry node B(n) to the carry output node.

[0133] The carry generator CRG(n) may further include a third carry switch element T3, a sixth carry switch element T6, and a ninth carry switch element T9, wherein the third carry switch element T3 includes a control electrode connected to the ground GND, a first electrode connected to the ground GND, and a second electrode connected to the second control electrode (or node CKL(n)) of the second carry switch element T2, the sixth carry switch element T6 includes a control electrode connected to the ground GND, a first electrode connected to the ground GND, and a second electrode connected to the second control electrode (or node AL(n)) of the fifth carry switch element T5, and the ninth carry switch element T9 includes a control electrode connected to the ground GND, a first electrode connected to the ground GND, and a second electrode connected to the second control electrode (or node BL(n)) of the eighth carry switch element T8. The third carry switch element T3 may enhance the stability and reliability of the second carry switch element T2. The sixth carry switch element T6 may enhance the stability and reliability of the fifth carry switch element T5. The ninth carry switch element T9 may enhance the stability and reliability of the eighth carry switch element T8.

[0134] The carry generator CRG(n) may further include a holding capacitor C0, a first capacitor C1, a second capacitor C2 and a third capacitor C3, the holding capacitor C0 including a first electrode connected to the first carry node A(n) and a second electrode for receiving a holding voltage VDC, the first capacitor C1 connected between a first control electrode of the second carry switch element T2 and a second control electrode of the second carry switch element T2, the second capacitor C2 connected between a first control electrode of the fifth carry switch element T5 and a second control electrode of the fifth carry switch element T5, and the third capacitor C3 connected between a first control electrode of the eighth carry switch element T8 and a second control electrode of the eighth carry switch element T8.

[0135] exist Fig.11In the period DU2, the connection control switch element S9 can be turned off by the high-level connection control signal CR (nm). When the connection control switch element S9 is turned off, the first control node QB and the second control node SQB_GI (which may correspond to Fig.11 The second control node SQB_GI(n) in the period DU1 is disconnected. Therefore, in the period DU2, the signal of the second control node SQB_GI remains at the high level of the previous level. Accordingly, the output of the first gate signal GI(n) remains at a low level during the period DU1.

[0136] For example, in Fig.11 , the connection control signal CR(nm) may be a carry signal of the first three stages. In the first three stages outputting the second gate signal GC(n-3), the control electrode of the fourteenth switch element SC6 may be controlled by the third control node SQB_GC(n-3). In addition, in the present embodiment, the first gate signal GI(n) of the current stage and the second gate signal GC(n-3) of the first three stages may have the same timing (i.e., when the first gate signal GI(n) of the current stage changes, the second gate signal GC(n-3) of the first three stages also changes).

[0137] When there is no connection control switch element S9, the first gate signal GI(n) of the current stage and the second gate signal GC(n-3) of the previous three stages may have the same waveform. Fig.11 In the present embodiment shown in , during the period DU1, the output of the first gate signal GI(n) is maintained at a low level due to the connection control switch element S9 controlled by the connection control signal CR(nm), so that the first gate signal GI(n) of the current stage and the second gate signal GC(n-3) of the previous three stages have different waveforms (for example, there is a duration in which the first gate signal GI(n) of the current stage does not change while the second gate signal GC(n-3) of the previous three stages changes).

[0138] In the low frequency driving mode, the driving timing of the display panel 100 includes a data writing period in which a data voltage is written to a pixel and the pixel emits light and a self scanning period in which a data voltage is not written to the pixel and the pixel emits light.

[0139] During the data writing period Figure 8 In the first frame P1, the data initialization gate signal GI, the compensation gate signal GC, and the data write gate signal GW may have an activation pulse. Figure 8 The second frame P2 to the fourth frame P4 may be a self-scan period.

[0140] like Figure 8 As shown in the first frame P1 of FIG. 1 , the first gate signal GI may output a single pulse in the frame. Figure 8As shown in the first frame P1 of FIG. 8 , the second gate signal GC may output two pulses in the frame.

[0141] On the contrary, during the self-scan period Fig. 9 In the first frame P1, the data initialization gate signal GI, the compensation gate signal GC, and the data write gate signal GW may not have any activation pulse. Fig. 9 The second frame P2 to the fourth frame P4 may be a self-scan period.

[0142] Fig.12 is shown in the first case Fig.10 A timing diagram of input signals, node signals and output signals of the carry generator CRG(n), the first masking circuit GIC(n) and the second masking circuit GCC(n). Fig.13 is shown in the second case Fig.10 A timing diagram of input signals, node signals and output signals of the carry generator CRG(n), the first masking circuit GIC(n) and the second masking circuit GCC(n). Fig.14 It is shown that in the third case Fig.10 A timing diagram of input signals, node signals and output signals of the carry generator CRG(n), the first masking circuit GIC(n) and the second masking circuit GCC(n). Fig.15 It is shown that in the fourth case Fig.10 A timing diagram of input signals, node signals and output signals of the carry generator CRG(n), the first masking circuit GIC(n) and the second masking circuit GCC(n).

[0143] In the following, reference is made to Figures 12 to 15 The operations of the first masking circuit and the second masking circuit are explained in detail.

[0144] Reference Figures 1 to 15 , the signal of the first masking control node S-nodeI is determined by the operation of the second switching element SI2 to the fifth switching element SI5, and the signal of the second masking control node S-nodeC is determined by the operation of the tenth switching element SC2 to the thirteenth switching element SC5.

[0145] Hereinafter, the operation of the first masking circuit GIC(n) is described, and the operation of the second masking circuit GCC(n) is substantially the same as the operation of the first masking circuit GIC(n).

[0146] For example, when the carry signal CR(n) has a low level and the first enable signal EN has a low level, the second switch element SI2 and the third switch element SI3 are turned on so that the masking power signal (eg, the first clock signal NCK1) can be applied to the first masking control node S-nodeI. In addition, Fig.11The clock signals NCK2, NCK3, NCK4, NCK5 and NCK6 in may be masked power signals of other stages.

[0147] The second enable signal ENB may be an inverted signal of the first enable signal EN. Therefore, when the third switch element SI3 is turned on in response to the first enable signal EN, the fourth switch element SI4 may be turned off in response to the second enable signal ENB.

[0148] For example, when the carry signal CR(n) has a low level and the second enable signal ENB has a low level, the fourth switching element SI4 and the fifth switching element SI5 are turned on so that the low power voltage VGL can be applied to the first masking control node S-nodeI.

[0149] The second enable signal ENB may be an inverted signal of the first enable signal EN. Therefore, when the fourth switch element SI4 is turned on in response to the second enable signal ENB, the third switch element SI3 may be turned off in response to the first enable signal EN.

[0150] When the carry signal CR(n) has a high level, the second switch element SI2 and the fifth switch element SI5 are turned off so that the first masking control node S-node1 can maintain the previous state regardless of the state of the first enable signal EN and the state of the second enable signal ENB. Figures 12 to 15 In each of the first to fourth cases, Fig.10 The type of at least one of the switch elements shown in the figure may be changed so that the following description holds true. For example, at least one P-type transistor may be changed to an N-type transistor.

[0151] Fig.12 A case is shown in which the first enable signal EN has an inactive level (eg, a high level) in all periods in which the carry signal CR(n) has an active level (eg, a high level).

[0152] When the first enable signal EN has an inactive level in all periods in which the carry signal CR(n) has an active level, the first masking circuit GIC(n) may output a gate pulse of the first gate signal GI(n).

[0153] Fig.13 The first enable signal EN has an effective level (e.g., a low level) in all periods in which the carry signal CR(n) has an effective level (e.g., a high level). As used herein, an "effective level" is defined as a signal level that turns on a corresponding switching element, and an "ineffective level" is defined as a signal level that turns off a corresponding switching element.

[0154] When the first enable signal EN has a valid level in all periods in which the carry signal CR(n) has a valid level, the first masking circuit GIC(n) may not output a gate pulse.

[0155] Fig.14 A case is shown where the first enable signal EN changes from an inactive level (eg, a high level) to an active level (eg, a low level) during a period in which the carry signal CR(n) has an active level (eg, a high level).

[0156] When the first enable signal EN changes from an inactive level to an active level during a period in which the carry signal CR(n) has an active level, the first masking circuit GIC(n) may output a gate pulse.

[0157] Fig.15 A case is shown where the first enable signal EN changes from an active level (eg, a low level) to an inactive level (eg, a high level) during a period in which the carry signal CR(n) has an active level (eg, a high level).

[0158] When the first enable signal EN changes from the active level to the inactive level during a period in which the carry signal CR(n) has the active level, the first masking circuit GIC(n) may not output the gate pulse.

[0159] Refer again Figures 12 to 15 When the first enable signal EN has an inactive level (eg, a high level) at a rising edge of the carry signal CR(n), the first masking circuit GIC(n) may output a gate pulse (eg, Fig.12 and Fig.14 On the contrary, when the first enable signal EN has a valid level (eg, a low level) at the rising edge of the carry signal CR(n), the first masking circuit GIC(n) may not output a gate pulse (eg, Fig.13 and Fig.15 ).

[0160] According to this embodiment, the output of the gate signal can be controlled based on the carry signal CR(n), the first enable signal EN and the second enable signal ENB, so that multiple divisions of the driving frequency can be supported. By multiple divisions of the driving frequency, the power consumption of the display device can be effectively reduced.

[0161] In addition, when the first gate signal generator for generating the data initialization gate signal GI(n) and the second gate signal generator for generating the compensation gate signal GC(n) are commonly formed, the first masking circuit GIC(n) for outputting the data initialization gate signal GI(n) further includes the connection control switch element S9, but the second masking circuit GCC(n) for outputting the compensation gate signal GC(n) does not further include the connection control switch element S9, so that the waveforms of the data initialization gate signal GI(n) and the compensation gate signal GC(n) can be generated differently. The data initialization gate signal GI(n) and the compensation gate signal GC(n) are generated differently, so that the display quality of the display panel 100 can be enhanced.

[0162] Fig.16 It is shown Figure 1 A block diagram of an example of carry generators CRG(n), CRG(n-1), CRG(n-2) and CRG(n-3), first masking circuits GIC(n), GIC(n-1), GIC(n-2) and GIC(n-3), and second masking circuits GCC(n), GCC(n-1), GCC(n-2) and GCC(n-3) of a gate driver 300.

[0163] The gate signal masking circuit, the gate driver, and the display device according to the present embodiment are substantially the same as those of the reference 1 except for the connection control signal applied to the connection control switch element. Figures 1 to 15 The gate signal masking circuit, gate driver and display device of the previous embodiment explained are the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 15 The same or similar parts as those described in the previous embodiments are described herein, and any repeated explanation regarding the above elements will be omitted.

[0164] Reference Figures 1 to 6 and Figures 8 to 16 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0165] The gate driver 300 includes a carry generator CRG(n), a first masking circuit GIC(n), and a second masking circuit GCC(n).

[0166] The first masking circuit GIC(n) is connected to the carry generator CRG(n) and outputs a first gate signal GI(n). The second masking circuit GCC(n) is connected to the carry generator CRG(n) and outputs a second gate signal GC(n).

[0167] The first masking circuit GIC(n) includes a connection control switching element S9 that connects the first control node QB of the carry generator CRG(n) and the first switching element SI1 of the first masking circuit GIC(n) based on a connection control signal (eg, connection control signal CR(nm)).

[0168] In contrast, the second masking circuit GCC(n) does not include a connection control switching element that connects the first control node QB of the carry generator CRG(n) and the ninth switching element SC1 of the second masking circuit GCC(n) based on a connection control signal (eg, connection control signal CR(nm)).

[0169] For example, the first control node QB of the carry generator CRG(n) may be connected to the first switch element SI1 of the first masking circuit GIC(n) through the connection control switch element S9. Conversely, the first control node QB of the carry generator CRG(n) may be directly connected to the ninth switch element SC1 of the second masking circuit GCC(n).

[0170] For example, the connection control signal applied to the control electrode of the connection control switch element S9 may be as follows: Fig.16 In addition, for example, the connection control switch element S9 may be Fig.16 The N-type transistor in.

[0171] The present invention is not limited to Fig.16 The connection control signal applied to the control electrode of the connection control switch element S9 may be an inverted signal CRB(nm) of a carry signal CR(nm) of a plurality of previous stages. Fig.16 As shown in , each of the inversion signals CRB(n), CRB(n-1), CRB(n-2), and CRB(n-3) may be simply illustrated as the inversion signal CRB.

[0172] According to this embodiment, the output of the gate signal can be controlled based on the carry signal CR(n), the first enable signal EN and the second enable signal ENB, so that multiple divisions of the driving frequency can be supported. By multiple divisions of the driving frequency, the power consumption of the display device can be effectively reduced.

[0173] In addition, when the first gate signal generator for generating the data initialization gate signal GI(n) and the second gate signal generator for generating the compensation gate signal GC(n) are commonly formed, the first masking circuit GIC(n) for outputting the data initialization gate signal GI(n) further includes the connection control switch element S9, but the second masking circuit GCC(n) for outputting the compensation gate signal GC(n) does not further include the connection control switch element S9, so that the waveforms of the data initialization gate signal GI(n) and the compensation gate signal GC(n) can be generated differently. The data initialization gate signal GI(n) and the compensation gate signal GC(n) are generated differently, so that the display quality of the display panel 100 can be enhanced.

[0174] Fig.17 is a block diagram showing an electronic device 1000 according to an embodiment of the present invention. Fig.18 It is shown Fig.17 The electronic device 1000 is implemented as an example of a smart phone.

[0175] Reference Fig.17 and Fig.18 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0176] In an embodiment, if Fig.18 As shown in , the electronic device 1000 may be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart board, a smart watch, a tablet PC, a car navigation system, a computer monitor, a notebook computer, a head mounted display (HMD) device, and the like.

[0177] The processor 1010 may perform various computing functions or various tasks. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), and the like. The processor 1010 may be connected to other components via an address bus, a control bus, a data bus, and the like. In addition, the processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0178] The processor 1010 can output the input image data IMG and the input control signal CONT to Figure 1 A drive controller 200 is provided.

[0179] The memory device 1020 may store data used for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and the like, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, and the like.

[0180] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, and the like. The I / O device 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, and the like, and output devices such as a printer, a speaker, and the like. In some embodiments, a display device 1060 may be included in the I / O device 1040. The power supply 1050 may provide power for the operation of the electronic device 1000. The display device 1060 may be connected to other components via a bus or other communication link.

[0181] According to embodiments of a gate signal masking circuit, a gate driver, and a display device, power consumption of the display device can be reduced, and display quality can be improved.

[0182] The foregoing is an illustration of the present invention and should not be construed as limiting it. Although some embodiments of the present invention have been described, it will be readily appreciated by those skilled in the art that many modifications are possible in the embodiments without substantially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined in the claims. In the claims, the device-plus-function clause is intended to cover the structure described herein as performing the function, and not only structural equivalents, but also equivalent structures. Therefore, it should be understood that the foregoing is an illustration of the present invention and should not be construed as being limited to the specific embodiments disclosed, and it should be understood that modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present invention is defined by the appended claims, and the equivalents of the claims are included therein.

Claims

1. A gate signal masking circuit, comprising: a connection control switch element configured to connect the first control node and the first switch element based on a connection control signal; the first switch element, the first switch element comprising a control electrode connected to a masking control node, a first electrode connected to the connection control switch element, and a second electrode connected to a second control node; a second switch element, the second switch element comprising a control electrode configured to receive a carry signal, a first electrode configured to receive a mask power signal, and a second electrode connected to the first intermediate node; a third switch element, the third switch element comprising a control electrode configured to receive a first enable signal, a first electrode connected to the first intermediate node, and a second electrode connected to the masking control node; a fourth switch element, the fourth switch element comprising a control electrode configured to receive a second enable signal, a first electrode connected to the masking control node, and a second electrode connected to a second intermediate node; as well as A fifth switching element includes a control electrode configured to receive the carry signal, a first electrode connected to the second intermediate node, and a second electrode configured to receive a low power voltage.

2. The gate signal masking circuit according to claim 1, further comprising: a sixth switching element, the sixth switching element comprising a control electrode connected to the second control node, a first electrode configured to receive a first clock signal, and a second electrode connected to a gate output node; a seventh switching element, the seventh switching element comprising a control electrode configured to receive the carry signal, a first electrode connected to the gate output node, and a second electrode configured to receive the low power voltage; as well as An eighth switching element includes a control electrode configured to receive the carry signal, a first electrode configured to receive the first clock signal, and a second electrode connected to the second control node.

3. The gate signal masking circuit according to claim 2, further comprising: a first masked capacitor comprising a first electrode configured to receive the first clock signal and a second electrode connected to the second control node; as well as A second masking capacitor includes a first electrode connected to the masking control node and a second electrode configured to receive the low power voltage.

4. The gate signal masking circuit according to claim 2, wherein: The masked power signal is the first clock signal, and The first electrode of the second switching element is connected to the first electrode of the sixth switching element.

5. The gate signal masking circuit according to claim 1, wherein: The gate signal masking circuit is configured to output a gate pulse when the first enable signal has an inactive level in all periods in which the carry signal has an active level.

6. The gate signal masking circuit according to claim 1, wherein: The gate signal masking circuit is configured not to output a gate pulse when the first enable signal has a valid level in all periods in which the carry signal has a valid level.

7. The gate signal masking circuit according to claim 1, wherein: The gate signal masking circuit is configured to output a gate pulse when the first enable signal changes from an inactive level to an active level during a period in which the carry signal has an active level.

8. The gate signal masking circuit according to claim 1, wherein: The gate signal masking circuit is configured not to output a gate pulse when the first enable signal changes from a valid level to an invalid level during a period in which the carry signal has a valid level.

9. The gate signal masking circuit according to claim 1, wherein: The connection control signal is one of a plurality of previous carry signals, and Wherein, the connection control switch element is a P-type transistor.

10. The gate signal masking circuit according to claim 1, wherein: The connection control signal is an inverted signal of one of a plurality of previous carry signals, and Wherein, the connection control switch element is an N-type transistor.

11. A gate driver comprising: a carry generator configured to generate a carry signal based on a previous carry signal; a first masking circuit connected to the carry generator and configured to output a first gate signal; as well as a second masking circuit connected to the carry generator and configured to output a second gate signal, The first masking circuit includes a connection control switch element connecting a first control node of the carry generator and a first switch element of the first masking circuit.

12. The gate driver according to claim 11, wherein: The first control node of the carry generator is directly connected to a ninth switching element of the second masking circuit.

13. The gate driver according to claim 11, wherein: The first masking circuit comprises: the first switch element, the first switch element comprising a control electrode connected to a first masking control node, a first electrode connected to the connection control switch element, and a second electrode connected to a second control node; a second switch element, the second switch element comprising a control electrode configured to receive the carry signal, a first electrode configured to receive the mask power signal, and a second electrode connected to the first intermediate node; a third switch element, the third switch element comprising a control electrode configured to receive a first enable signal, a first electrode connected to the first intermediate node, and a second electrode connected to the first masked control node; a fourth switch element, the fourth switch element comprising a control electrode configured to receive a second enable signal, a first electrode connected to the first masking control node, and a second electrode connected to a second intermediate node; a fifth switching element, the fifth switching element comprising a control electrode configured to receive the carry signal, a first electrode connected to the second intermediate node, and a second electrode configured to receive a low power voltage; a sixth switching element, the sixth switching element comprising a control electrode connected to the second control node, a first electrode configured to receive the first clock signal, and a second electrode connected to the first gate output node; a seventh switching element including a control electrode configured to receive the carry signal, a first electrode connected to the first gate output node, and a second electrode configured to receive the low power voltage; and An eighth switching element includes a control electrode configured to receive the carry signal, a first electrode configured to receive the first clock signal, and a second electrode connected to the second control node.

14. The gate driver according to claim 13, wherein: The second masking circuit comprises: a ninth switch element, the ninth switch element comprising a control electrode connected to the second masked control node, a first electrode connected to the first control node, and a second electrode connected to a third control node; a tenth switch element, the tenth switch element comprising a control electrode configured to receive the carry signal, a first electrode configured to receive the mask power signal, and a second electrode connected to a third intermediate node; an eleventh switch element, the eleventh switch element comprising a control electrode configured to receive the first enable signal, a first electrode connected to the third intermediate node, and a second electrode connected to the second masking control node; a twelfth switch element, the twelfth switch element comprising a control electrode configured to receive the second enable signal, a first electrode connected to the second masking control node, and a second electrode connected to a fourth intermediate node; a thirteenth switching element, the thirteenth switching element comprising a control electrode configured to receive the carry signal, a first electrode connected to the fourth intermediate node, and a second electrode configured to receive the low power voltage; a fourteenth switching element, the fourteenth switching element comprising a control electrode connected to the third control node, a first electrode configured to receive the first clock signal, and a second electrode connected to a second gate output node; a fifteenth switching element, the fifteenth switching element including a control electrode configured to receive the carry signal, a first electrode connected to the second gate output node, and a second electrode configured to receive the low power voltage; and A sixteenth switching element includes a control electrode configured to receive the carry signal, a first electrode configured to receive the first clock signal, and a second electrode connected to the third control node.

15. The gate driver according to claim 11, wherein: The carry generator comprises: a first carry switch element, the first carry switch element comprising a control electrode configured to receive a second carry clock signal, a first electrode configured to receive the previous carry signal, and a second electrode connected to a first carry node; a second carry switch element, the second carry switch element comprising a first control electrode configured to receive a first carry clock signal, a first electrode configured to receive the previous carry signal, and a second electrode connected to the first carry node; a fourth carry switch element, the fourth carry switch element comprising a control electrode connected to the first carry node, a first electrode configured to receive a high power voltage, and a second electrode connected to a second carry node; a fifth carry switch element, the fifth carry switch element comprising a first control electrode connected to the first carry node, a first electrode configured to receive a low power voltage, and a second electrode connected to the second carry node; a seventh carry switch element including a control electrode connected to the second carry node, a first electrode configured to receive the high power voltage, and a second electrode connected to a carry output node; and An eighth carry switch element includes a first control electrode connected to the second carry node, a first electrode configured to receive the low power voltage, and a second electrode connected to the carry output node.

16. The gate driver according to claim 15, wherein: The carry generator further comprises: a third carry switch element, the third carry switch element comprising a control electrode connected to ground, a first electrode connected to the ground, and a second electrode connected to the second control electrode of the second carry switch element; a sixth carry switch element including a control electrode connected to the ground, a first electrode connected to the ground, and a second electrode connected to the second control electrode of the fifth carry switch element; and A ninth carry switch element includes a control electrode connected to the ground, a first electrode connected to the ground, and a second electrode connected to the second control electrode of the eighth carry switch element.

17. The gate driver according to claim 11, wherein: The first gate signal is configured to output a single pulse in one frame, and Wherein, the second gate signal is configured to output two pulses in the one frame.

18. A display device comprising: a display panel comprising pixels, the pixels comprising switching elements of a first type and switching elements of a second type different from the first type; a gate driver configured to output a first gate signal and a second gate signal to the display panel; as well as a data driver configured to output a data voltage to the display panel, Wherein, the gate driver comprises: a carry generator configured to generate a carry signal based on a previous carry signal; a first masking circuit connected to the carry generator and configured to output the first gate signal; and a second masking circuit connected to the carry generator and configured to output the second gate signal, The first masking circuit includes a connection control switch element connecting a first control node of the carry generator and a first switch element of the first masking circuit.

19. The display device according to claim 18, wherein: The first control node of the carry generator is directly connected to a ninth switching element of the second masking circuit.

20. The display device according to claim 18, wherein: The pixels include: a first pixel switching element, the first pixel switching element comprising a control electrode connected to the first pixel node, a first electrode connected to the second pixel node, and a second electrode connected to the third pixel node; a second pixel switching element, the second pixel switching element comprising a control electrode configured to receive a data write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second pixel node; a third pixel switching element, the third pixel switching element comprising a control electrode configured to receive a compensation gate signal, a first electrode connected to the first pixel node, and a second electrode connected to the third pixel node; a fourth pixel switching element, the fourth pixel switching element comprising a control electrode configured to receive a data initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the first pixel node; a fifth pixel switching element, the fifth pixel switching element comprising a control electrode configured to receive an emission signal, a first electrode configured to receive a pixel high power voltage, and a second electrode connected to the second pixel node; a sixth pixel switch element, the sixth pixel switch element comprising a control electrode configured to receive the emission signal, a first electrode connected to the third pixel node, and a second electrode connected to an anode of a light emitting element; a seventh pixel switching element, the seventh pixel switching element comprising a control electrode configured to receive a light emitting element initialization gate signal, a first electrode configured to receive a light emitting element initialization voltage, and a second electrode connected to the anode of the light emitting element; and the light emitting element, the light emitting element comprising the anode and a cathode configured to receive a pixel low power voltage, wherein a waveform of the first gate signal output from the first masking circuit is different from a waveform of the second gate signal output from the second masking circuit, Wherein, the first gate signal is the data initialization gate signal, and Wherein, the second gate signal is the compensation gate signal.

21. The display device according to claim 18, wherein: The pixels include: a first pixel switching element, the first pixel switching element comprising a control electrode connected to the first pixel node, a first electrode connected to the second pixel node, and a second electrode connected to the third pixel node; a second pixel switching element, the second pixel switching element comprising a control electrode configured to receive a data write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second pixel node; a third pixel switching element, the third pixel switching element comprising a control electrode configured to receive a compensation gate signal, a first electrode connected to the first pixel node, and a second electrode connected to the third pixel node; a fourth pixel switching element, the fourth pixel switching element comprising a control electrode configured to receive a data initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the first pixel node; a fifth pixel switching element, the fifth pixel switching element comprising a control electrode configured to receive an emission signal, a first electrode configured to receive a pixel high power voltage, and a second electrode connected to the second pixel node; a sixth pixel switch element, the sixth pixel switch element comprising a control electrode configured to receive the emission signal, a first electrode connected to the third pixel node, and a second electrode connected to an anode of a light emitting element; a seventh pixel switching element, the seventh pixel switching element comprising a control electrode configured to receive a light emitting element initialization gate signal, a first electrode configured to receive a light emitting element initialization voltage, and a second electrode connected to the anode of the light emitting element; and the light emitting element, the light emitting element comprising the anode and a cathode configured to receive a pixel low power voltage, The initialization gate signal of the light emitting element is the data writing gate signal of the previous stage. wherein a waveform of the first gate signal output from the first masking circuit is different from a waveform of the second gate signal output from the second masking circuit, Wherein, the first gate signal is the data initialization gate signal, and Wherein, the second gate signal is the compensation gate signal.

22. The display device according to claim 18, wherein: The pixels include: a first pixel switching element, the first pixel switching element comprising a control electrode connected to the first pixel node, a first electrode connected to the second pixel node, and a second electrode connected to the third pixel node; a second pixel switching element, the second pixel switching element comprising a control electrode configured to receive a data write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second pixel node; a third pixel switching element, the third pixel switching element comprising a control electrode configured to receive a compensation gate signal, a first electrode connected to the first pixel node, and a second electrode connected to the third pixel node; a fourth pixel switching element, the fourth pixel switching element comprising a control electrode configured to receive a data initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the first pixel node; a fifth pixel switching element, the fifth pixel switching element comprising a control electrode configured to receive an emission signal, a first electrode configured to receive a pixel high power voltage, and a second electrode connected to the second pixel node; a sixth pixel switch element, the sixth pixel switch element comprising a control electrode configured to receive the emission signal, a first electrode connected to the third pixel node, and a second electrode connected to an anode of a light emitting element; a seventh pixel switch element, the seventh pixel switch element comprising a control electrode configured to receive a light emitting element initialization gate signal, a first electrode configured to receive a light emitting element initialization voltage, and a second electrode connected to the anode of the light emitting element; an eighth pixel switching element, the eighth pixel switching element comprising a control electrode configured to receive a bias gate signal, a first electrode configured to receive a bias voltage, and a second electrode connected to the second pixel node; and the light emitting element, the light emitting element comprising the anode and a cathode configured to receive a pixel low power voltage, wherein a waveform of the first gate signal output from the first masking circuit is different from a waveform of the second gate signal output from the second masking circuit, Wherein, the first gate signal is the data initialization gate signal, and Wherein, the second gate signal is the compensation gate signal.

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