Current limiting circuit, chip and electronic equipment

Abstract

The invention provides a current limiting circuit, a chip and electronic equipment. The circuit comprises a current mode control circuit and a superposed circuit, the current mode control circuit comprises a ramp voltage end and a clamping voltage end, the input end of the superposed circuit is electrically connected with the ramp voltage end, the output end of the superposed circuit is electrically connected with the clamping voltage end, and the ramp voltage end is electrically connected with ramp voltage; the superposed circuit comprises a sampling hold circuit, a limiting reference circuit and a summing circuit; the sampling hold circuit is used for sampling the ramp voltage to obtain a sampling voltage and converting the sampling voltage into a sampling current; the limiting reference circuit is used for generating a preset limiting current; and the summing circuit is used for adding the sampling current and the preset limiting current to obtain a target current-limiting voltage and outputting the target current-limiting voltage to the clamping voltage end. The slope voltage is sampled through the sampling and holding circuit and is superposed to the clamping voltage end, so that the magnitude of the output current of the current limiting circuit is not influenced by the slope voltage.

Description

Technical Field

[0001] The present application relates to the field of power management technology, and in particular to a current limiting circuit, a chip, and an electronic device. Background Art

[0002] In the application of current mode control converter, in order to improve the subharmonic oscillation problem, a ramp voltage is usually used for compensation. In practical applications, a ramp voltage generation circuit is used to generate a ramp voltage, but the ramp voltage will change with the input voltage and output voltage of the current mode control converter. Generally, the lower the input voltage and the higher the output voltage, the larger the corresponding ramp voltage will be. When the ramp voltage increases, the peak current of the current mode control converter will decrease. The decrease in peak current will affect the load carrying capacity of the converter, thereby limiting the application of the current mode control converter.

[0003] Therefore, the existing current limiting circuit is not suitable for wide input and output application scenarios because the output current is affected by the ramp voltage. Summary of the invention

[0004] The present application provides a current limiting circuit, a chip and an electronic device, so that the output current of a current mode control converter is not affected by a ramp voltage and is suitable for application scenarios with wide input and output.

[0005] In a first aspect, the present application provides a current limiting circuit, which includes: a current mode control circuit and a superposition circuit, the current mode control circuit includes a ramp voltage terminal and a clamp voltage terminal, the input terminal of the superposition circuit is electrically connected to the ramp voltage terminal, the output terminal of the superposition circuit is electrically connected to the clamp voltage terminal, and the ramp voltage terminal is electrically connected to the ramp voltage; the superposition circuit includes a sampling and holding circuit, a limiting reference circuit and an adding circuit, the output terminal of the sampling and holding circuit is electrically connected to a first input terminal of the adding circuit, the output terminal of the limiting reference circuit is electrically connected to a second input terminal of the adding circuit, the input terminal of the sampling and holding circuit is electrically connected to an input terminal of the superposition circuit, and the output terminal of the adding circuit is electrically connected to the clamp voltage terminal;

[0006] A sampling and holding circuit is used to sample the ramp voltage to obtain a sampling voltage and convert the sampling voltage into a sampling current;

[0007] A limiting reference circuit for generating a preset limiting current;

[0008] The adding circuit is used to add the sampled current and the preset limiting current to obtain a target current limiting voltage, and output the target current limiting voltage to the clamping voltage terminal.

[0009] The present application samples the ramp voltage through the sampling and holding circuit in the superposition circuit and superimposes it to the clamping voltage terminal, which is equivalent to the loop balance relationship V in the related art.ILIMIT_REF =V RAMP +I PEAK× R SNS The left side of the equation also adds a ramp voltage V RAMP , thereby eliminating the slope voltage at both ends of the equation, so that the output current of the current limiting circuit is not affected by the slope voltage.

[0010] In a possible design, the sample-and-hold circuit includes: a switch, a first capacitor, a first operational amplifier, a first switch tube, a second switch tube, a third switch tube, and a first resistor;

[0011] The first end of the switch is electrically connected to the input end of the sample-and-hold circuit, and the second end of the switch is electrically connected to the first end of the first capacitor and the positive end of the first operational amplifier respectively;

[0012] The second terminal of the first capacitor is grounded;

[0013] The reverse end of the first operational amplifier is electrically connected to the first end of the first resistor and the second end of the first switch tube respectively, and the output end of the first operational amplifier is electrically connected to the control end of the first switch tube;

[0014] The first end of the first switch tube is electrically connected to the first end of the second switch tube, the control end of the second switch tube, and the control end of the third switch tube respectively;

[0015] The second end of the second switch tube is electrically connected to the second end of the third switch tube;

[0016] The first end of the third switch tube is electrically connected to the output end of the sample and hold circuit.

[0017] In one possible design, the current mode control circuit includes a first comparison circuit, the first comparison circuit includes: a second resistor, a third resistor and a second operational amplifier;

[0018] The first end of the second resistor is electrically connected to the output voltage, and the second end of the second resistor is electrically connected to the positive end of the second operational amplifier and the first end of the third resistor respectively;

[0019] A second end of the third resistor is grounded;

[0020] The inverting end of the second operational amplifier is electrically connected to the reference voltage, and the output end of the second operational amplifier is electrically connected to the clamping voltage end and the output end of the first comparison circuit respectively.

[0021] In a possible design, the current mode control circuit further includes a second comparison circuit, the second comparison circuit including: an adder, a fourth resistor, a second capacitor, a third capacitor, and a third operational amplifier;

[0022] A first input terminal of the adder is electrically connected to the ramp voltage terminal, a second input terminal of the adder is electrically connected to an input terminal of the second comparison circuit, and an output terminal of the adder is electrically connected to a positive terminal of the third operational amplifier;

[0023] The reverse end of the third operational amplifier is electrically connected to the first end of the fourth resistor, the first end of the second capacitor and the output end of the second operational amplifier respectively, and the output end of the third operational amplifier is electrically connected to the output end of the second comparison circuit;

[0024] The second end of the fourth resistor is electrically connected to the first end of the third capacitor;

[0025] The second end of the second capacitor and the second end of the third capacitor are both grounded.

[0026] In one possible design, the current mode control circuit further includes a latch circuit, the latch circuit including a first NAND gate and a second NAND gate;

[0027] The first input terminal of the first NAND gate is electrically connected to the output terminal of the third operational amplifier, the second input terminal of the first NAND gate is electrically connected to the output terminal of the second NAND gate, and the output terminal of the first NAND gate is electrically connected to the first input terminal of the second NAND gate and the output terminal of the latch circuit;

[0028] The second input terminal of the second NAND gate is electrically connected to the input terminal of the latch circuit.

[0029] In one possible design, the current mode control circuit further includes an oscillator, wherein an output terminal of the oscillator is electrically connected to an input terminal of the latch circuit.

[0030] In a possible design, the current mode control circuit further includes a driving circuit, and the driving circuit includes a driver, a fourth switch tube, a fifth switch tube, a fifth resistor, and a buffer;

[0031] The input end of the driver is electrically connected to the output end of the latch circuit, the first output end of the driver is electrically connected to the control end of the fourth switch tube, and the second output end of the driver is electrically connected to the control end of the fifth switch tube;

[0032] The first end of the fourth switch tube is electrically connected to the input voltage, and the second end of the fourth switch tube is electrically connected to the first end of the fifth resistor and the positive input end of the buffer respectively;

[0033] The second end of the fifth resistor is electrically connected to the reverse input end of the buffer, the first end of the fifth switch tube and the output end of the driving circuit respectively;

[0034] The second end of the fifth switch tube is electrically connected to the output voltage;

[0035] The output terminal of the buffer is electrically connected to the second input terminal of the adder.

[0036] In one possible design, the current mode control circuit further includes an output circuit, the output circuit including an energy storage element, a sixth resistor, and a fourth capacitor;

[0037] The first end of the energy storage element is electrically connected to the output end of the driving circuit, and the second end of the energy storage element is grounded;

[0038] The first end of the sixth resistor and the first end of the fourth capacitor are both grounded;

[0039] The second end of the sixth resistor and the second end of the fourth capacitor are electrically connected to the output voltage.

[0040] In a second aspect, the present application provides a chip, comprising a current limiting circuit in each possible design in the above-mentioned first aspect.

[0041] The beneficial effects provided in the above-mentioned second aspect and various possible designs of the above-mentioned second aspect can refer to the beneficial effects brought about by the above-mentioned first aspect and various possible implementation methods of the first aspect, and will not be repeated here.

[0042] In a third aspect, the present application provides an electronic device, which includes the chip in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of the structure of a current limiting circuit provided in the related art;

[0044] Figure 2 A schematic diagram of the structure of a current limiting circuit provided in one embodiment of the present application;

[0045] Figure 3 A schematic diagram of the structure of a sample-and-hold circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0046] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0047] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0048] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0049] In the related art, see Figure 1 In the current limiting circuit of the current mode control converter, V COMP The clamping method is used to limit the current. COMP The clamp voltage value is set to V ILIMIT_REF , limiting the output current.

[0050] When the output load of the circuit becomes larger or the output is short-circuited, V COMP The voltage increases, when V COMP When the voltage rises to the clamping voltage, V COMP =V ILIMIT_REF When the current is limited. Figure 1 The loop balance relationship in V COMP =V ILIMIT_REF =V RAMP +I PEAK× R SNS , we can get: PEAK =(V ILIMIT_REF -V RAMP ) / R SNS , where the peak current I PEAK is the current flowing through the inductor L, V RAMP is the ramp voltage.

[0051] In the application of wide input-output current mode control converter, the ramp voltage compensation method is usually used to improve the subharmonic oscillation problem. The ramp voltage generation circuit is used to generate the ramp voltage. The ramp voltage is not a fixed voltage value, but will change with the input voltage and output voltage. In general, the lower the input voltage and the higher the output voltage, the larger the corresponding ramp voltage will be. See formula I PEAK =(V ILIMIT_REF -V RAMP ) / R SNS It can be seen that when the ramp voltage V RAMP When the peak current I PEAK The reduction of peak current will affect the load capacity of the circuit, thereby limiting the application of current mode control converter.

[0052] Therefore, the existing current limiting circuit is not suitable for wide input and output application scenarios because the output current is affected by the ramp voltage.

[0053] In order to solve the problem in the prior art that the magnitude of the output current of the current limiting circuit is affected by the ramp voltage, the present application provides a current limiting circuit, a chip and an electronic device.

[0054] The current limiting circuit may be a chip or a circuit module.

[0055] Among them, the current limiting circuit can be integrated in the same chip or in different chips, and the embodiments of the present application do not make specific limitations on this.

[0056] In this application, electronic devices may include, but are not limited to: chargers, tablet computers, smart home devices, vehicles, and wearable devices.

[0057] See also Figure 2The embodiment of the present application provides a current limiting circuit 1000, which may include: a current mode control circuit 100 and a superposition circuit 200, wherein the current mode control circuit 100 includes a ramp voltage terminal RAMP and a clamp voltage terminal CLAMP_MAX, wherein the input terminal of the superposition circuit 200 is electrically connected to the ramp voltage terminal RAMP, the output terminal of the superposition circuit 200 is electrically connected to the clamp voltage terminal CLAMP_MAX, and the ramp voltage terminal is electrically connected to the ramp voltage V RAMP Electrical connection: The superposition circuit 200 includes a sampling and holding circuit 201, a limiting reference circuit 202 and an adding circuit 203, the output end of the sampling and holding circuit 201 is electrically connected to the first input end of the adding circuit 203, the output end of the limiting reference circuit 202 is electrically connected to the second input end of the adding circuit 203, the input end of the sampling and holding circuit 201 is electrically connected to the input end of the superposition circuit 200, and the output end of the adding circuit 203 is electrically connected to the clamping voltage end CLAMP_MAX.

[0058] The sampling and holding circuit 201 is used to sample and hold the ramp voltage V RAMP Sampling is performed to obtain a sampling voltage, and the sampling voltage is converted into a sampling current IRAMP_SAMPLE.

[0059] The limiting reference circuit 202 is used to generate a preset limiting current.

[0060] The adding circuit 203 is used for adding the sampled current and the preset limiting current to obtain a target current limiting voltage, and outputting the target current limiting voltage to the clamping voltage terminal CLAMP_MAX.

[0061] The limiting reference circuit 202 generates a preset limiting current ILIMIT_REF. The specific current value of the preset limiting current ILIMIT_REF can be set according to user needs.

[0062] The adding circuit 203 is used to add the sampled current to the preset limiting current, and then convert the added current into a voltage to obtain a target current limiting voltage V CLAMP_MAX , and set the target current limit voltage V CLAMP_MAX Output to the clamp voltage terminal CLAMP_MAX.

[0063] See also Figure 2 , according to the loop balance relationship in this application, V COMP =V CLAMP_MAX =V RAMP +I PEAK× R SNS , where V CLAMP_MAX =V RAMP +V ILIMIT_REF , that is, V COMP =V RAMP +V ILIMIT_REF=V RAMP +I PEAK× R SNS , we can get: V ILIMIT_REF =I PEAK× R SNS , peak current I PEAK With V ILIMIT_REF Related to the ramp voltage V RAMP The peak current can be obtained by setting the current value of the preset limit current ILIMIT_REF, thereby eliminating the limitation of the ramp voltage on the output current of the current limiting circuit. ILIMIT_REF It is the voltage value corresponding to the preset limiting current ILIMIT_REF.

[0064] See also Figure 1 , according to the loop balance relationship in the related art, V COMP =V ILIMIT_REF =V RAMP +I PEAK× R SNS Compared with the prior art, the present application samples the ramp voltage through the sampling and holding circuit in the superposition circuit and superimposes it to the clamping voltage terminal CLAMP_MAX, which is equivalent to the loop balance relationship V in the related art. ILIMIT_REF =V RAMP +I PEAK× R SNS The left side of the equation also adds a ramp voltage V RAMP , thereby eliminating the slope voltage at both ends of the equation, so that the output current of the current limiting circuit is not affected by the slope voltage.

[0065] In one possible embodiment, see Figure 3 The sample-and-hold circuit 201 includes: a switch HS_ON, a first capacitor C1, a first operational amplifier A1, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3 and a first resistor R1.

[0066] A first end of the switch HS_ON is electrically connected to the input end of the sample-and-hold circuit, and a second end of the switch HS_ON is electrically connected to the first end of the first capacitor C1 and the positive end of the first operational amplifier A1 , respectively.

[0067] A second terminal of the first capacitor C1 is grounded.

[0068] The reverse end of the first operational amplifier A1 is electrically connected to the first end of the first resistor R1 and the second end of the first switch tube Q1 respectively, and the output end of the first operational amplifier A1 is electrically connected to the control end of the first switch tube Q1.

[0069] The first end of the first switch tube Q1 is electrically connected to the first end of the second switch tube Q2 , the control end of the second switch tube Q2 , and the control end of the third switch tube Q3 , respectively.

[0070] The second end of the second switch tube Q2 is electrically connected to the second end of the third switch tube Q3.

[0071] A first end of the third switch tube Q3 is electrically connected to the output end of the sample and hold circuit.

[0072] In an example, for any switch tube in the sampling and holding circuit of the present application, the switch tube can be an N-type MOS tube or a P-type MOS tube, and the specific selection can be made according to the actual situation; the first end of the MOS tube is the source or the drain, and the second end of the MOS tube is the drain or the source corresponding to the first end.

[0073] Through the sampling and holding circuit, when the switch HS_ON is turned off, the ramp voltage V RAMP The peak value of the ramp voltage is sampled in real time, the peak voltage of the ramp voltage is maintained on the first capacitor C1, a sampling voltage is obtained, and the sampling voltage is converted into a sampling current through the first operational amplifier A1.

[0074] The sample-and-hold circuit can convert the transient ramp voltage into a steady-state sampling current IRAMP_SAMPLE. Therefore, the sampling current is the effect of the ramp voltage change on the output current of the current limiting circuit. The target current limiting voltage is obtained through the subsequent adding circuit, and the target current limiting voltage is output to the clamping voltage terminal, so that the output current of the current limiting circuit in this application is not affected by the ramp voltage.

[0075] In one possible embodiment, see Figure 2 The current mode control circuit 100 includes a first comparison circuit 101, and the first comparison circuit 101 includes: a second resistor R FB1 , the third resistor R FB2 and a second operational amplifier GM.

[0076] The second resistor R FB1 The first end of the second resistor R is electrically connected to the output voltage VOUT. FB1 The second end of the second operational amplifier GM and the third resistor R FB2 The first end is electrically connected to the

[0077] The third resistor R FB2 The second end is grounded.

[0078] The inverting terminal of the second operational amplifier GM is electrically connected to the reference voltage VREF, and the output terminal of the second operational amplifier GM is electrically connected to the clamping voltage terminal CLAMP_MAX and the output terminal of the first comparison circuit respectively.

[0079] In one possible embodiment, see Figure 2 The current mode control circuit 100 further includes a second comparison circuit 102, which includes an adder A2, a fourth resistor R C , the second capacitor C F , the third capacitor C C and a third operational amplifier GM2.

[0080] A first input terminal of the adder A2 is electrically connected to the ramp voltage terminal RAMP, a second input terminal of the adder A2 is electrically connected to an input terminal of the second comparison circuit 102, and an output terminal of the adder A2 is electrically connected to a positive terminal of the third operational amplifier GM2.

[0081] The inverting terminal of the third operational amplifier GM2 is respectively connected to the fourth resistor R C The first end of the second capacitor C F The first end of the operational amplifier GM1 is electrically connected to the output end of the second operational amplifier GM1, and the output end of the third operational amplifier GM2 is electrically connected to the output end of the second comparison circuit 102.

[0082] The fourth resistor R C The second end of the third capacitor C C The first end is electrically connected to the

[0083] The second capacitor C F The second end of the third capacitor C C The second ends of are grounded.

[0084] In one possible embodiment, see Figure 2 The current mode control circuit 100 further includes a latch circuit 103 , and the latch circuit 103 includes a first NAND gate U1 and a second NAND gate U2 .

[0085] The first input terminal of the first NAND gate U1 is electrically connected to the output terminal of the third operational amplifier GM2, the second input terminal of the first NAND gate U1 is electrically connected to the output terminal of the second NAND gate U2, and the output terminal of the first NAND gate U1 is electrically connected to the first input terminal of the second NAND gate U2 and the output terminal of the latch circuit 103.

[0086] The second input terminal of the second NAND gate U2 is electrically connected to the input terminal of the latch circuit 103 .

[0087] In one possible embodiment, see Figure 2 The current mode control circuit 100 further includes an oscillator 104 , and an output end of the oscillator 104 is electrically connected to an input end of the latch circuit 103 .

[0088] The oscillator is used to generate a clock signal. The frequency of the clock signal can be set according to the needs of the user. This application does not make any specific limitations on the frequency of the clock signal.

[0089] In one possible embodiment, see Figure 2 The current mode control circuit 100 further includes a driving circuit 105, which includes a driver LOGIC&DRIVER, a fourth switch tube Q4, a fifth switch tube Q5, a fifth resistor R SNS and a buffer BUF.

[0090] The input end of the driver LOGIC&DRIVER is electrically connected to the output end of the latch circuit 103, the first output end of the driver LOGIC&DRIVER is electrically connected to the control end of the fourth switch tube Q4, and the second output end of the driver LOGIC&DRIVER is electrically connected to the control end of the fifth switch tube Q5.

[0091] The first end of the fourth switch tube Q4 is electrically connected to the input voltage VIN, and the second end of the fourth switch tube Q4 is electrically connected to the fifth resistor R SNS The first end of is electrically connected to the positive input end of the buffer BUF.

[0092] The fifth resistor R SNS The second end of is electrically connected to the inverting input end of the buffer BUF, the first end of the fifth switch tube Q5 and the output end of the driving circuit 105 respectively.

[0093] The second end of the fifth switch tube Q5 is electrically connected to the output voltage VOUT.

[0094] An output terminal of the buffer BUF is electrically connected to a second input terminal of the adder A2.

[0095] In an example, for any switch tube in the driving circuit of the present application, the switch tube can be an N-type MOS tube or a P-type MOS tube, and the specific selection can be made according to the actual situation; the first end of the MOS tube is the source or the drain, and the second end of the MOS tube is the drain or the source corresponding to the first end.

[0096] The buffer is used to collect the fifth resistor R SNS The voltage difference between the two ends is converted into a single-ended voltage.

[0097] In one possible embodiment, see Figure 2 The current mode control circuit 100 further includes an output circuit 106, which includes an energy storage element L, a sixth resistor R LOAD And the fourth capacitor C OUT .

[0098] A first end of the energy storage element L is electrically connected to the output end of the driving circuit 105 , and a second end of the energy storage element L is grounded.

[0099] The sixth resistor R LOAD The first end and the fourth capacitor C OUT The first ends of are grounded.

[0100] The sixth resistor R LOAD The second end of the fourth capacitor C OUT The second end is electrically connected to the output voltage VOUT.

[0101] In one example, the energy storage element in the present application may be an inductor. The output voltage VOUT in the present application is a negative voltage, for example, VOUT is -5V, -12V, etc.

[0102] An embodiment of the present application provides a chip, comprising any of the above-mentioned current limiting circuits.

[0103] An embodiment of the present application also provides an electronic device, comprising the above chip.

[0104] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A current limiting circuit, characterized in that: The current limiting circuit comprises: a current mode control circuit and a superposition circuit, the current mode control circuit comprises a slope voltage terminal and a clamp voltage terminal, the input terminal of the superposition circuit is electrically connected to the slope voltage terminal, the output terminal of the superposition circuit is electrically connected to the clamp voltage terminal, and the slope voltage terminal is electrically connected to the slope voltage; the superposition circuit comprises a sampling and holding circuit, a limiting reference circuit and an adding circuit, the output terminal of the sampling and holding circuit is electrically connected to the first input terminal of the adding circuit, the output terminal of the limiting reference circuit is electrically connected to the second input terminal of the adding circuit, the input terminal of the sampling and holding circuit is electrically connected to the input terminal of the superposition circuit, and the output terminal of the adding circuit is electrically connected to the clamp voltage terminal; The sample-and-hold circuit is used to sample the ramp voltage to obtain a sampled voltage, and convert the sampled voltage into a sampled current; The limiting reference circuit is used to generate a preset limiting current; The adding circuit is used for adding the sampled current and the preset limiting current to obtain a target current limiting voltage, and outputting the target current limiting voltage to the clamping voltage terminal.

2. The current limiting circuit according to claim 1, characterized in that: The sampling and holding circuit includes: a switch, a first capacitor, a first operational amplifier, a first switch tube, a second switch tube, a third switch tube and a first resistor; The first end of the switch is electrically connected to the input end of the sample-and-hold circuit, and the second end of the switch is electrically connected to the first end of the first capacitor and the positive end of the first operational amplifier respectively; The second end of the first capacitor is grounded; The reverse end of the first operational amplifier is electrically connected to the first end of the first resistor and the second end of the first switch tube respectively, and the output end of the first operational amplifier is electrically connected to the control end of the first switch tube; The first end of the first switch tube is electrically connected to the first end of the second switch tube, the control end of the second switch tube and the control end of the third switch tube respectively; The second end of the second switch tube is electrically connected to the second end of the third switch tube; The first end of the third switch tube is electrically connected to the output end of the sample and hold circuit.

3. The current limiting circuit according to claim 1, characterized in that: The current mode control circuit includes a first comparison circuit, and the first comparison circuit includes: a second resistor, a third resistor and a second operational amplifier; The first end of the second resistor is electrically connected to the output voltage, and the second end of the second resistor is electrically connected to the positive end of the second operational amplifier and the first end of the third resistor respectively; The second end of the third resistor is grounded; The inverting terminal of the second operational amplifier is electrically connected to a reference voltage, and the output terminal of the second operational amplifier is electrically connected to the clamping voltage terminal and the output terminal of the first comparison circuit respectively.

4. The current limiting circuit according to claim 3, characterized in that: The current mode control circuit further includes a second comparison circuit, wherein the second comparison circuit includes: an adder, a fourth resistor, a second capacitor, a third capacitor and a third operational amplifier; The first input terminal of the adder is electrically connected to the ramp voltage terminal, the second input terminal of the adder is electrically connected to the input terminal of the second comparison circuit, and the output terminal of the adder is electrically connected to the positive terminal of the third operational amplifier; The reverse end of the third operational amplifier is electrically connected to the first end of the fourth resistor, the first end of the second capacitor and the output end of the second operational amplifier respectively, and the output end of the third operational amplifier is electrically connected to the output end of the second comparison circuit; The second end of the fourth resistor is electrically connected to the first end of the third capacitor; The second end of the second capacitor and the second end of the third capacitor are both grounded.

5. The current limiting circuit according to claim 4, characterized in that: The current mode control circuit further includes a latch circuit, wherein the latch circuit includes a first NAND gate and a second NAND gate; The first input terminal of the first NAND gate is electrically connected to the output terminal of the third operational amplifier, the second input terminal of the first NAND gate is electrically connected to the output terminal of the second NAND gate, and the output terminal of the first NAND gate is electrically connected to the first input terminal of the second NAND gate and the output terminal of the latch circuit; The second input terminal of the second NAND gate is electrically connected to the input terminal of the latch circuit.

6. The current limiting circuit according to claim 5, characterized in that: The current mode control circuit further includes an oscillator, an output end of the oscillator is electrically connected to an input end of the latch circuit.

7. The current limiting circuit according to claim 6, characterized in that: The current mode control circuit further includes a driving circuit, wherein the driving circuit includes a driver, a fourth switch tube, a fifth switch tube, a fifth resistor and a buffer; The input end of the driver is electrically connected to the output end of the latch circuit, the first output end of the driver is electrically connected to the control end of the fourth switch tube, and the second output end of the driver is electrically connected to the control end of the fifth switch tube; The first end of the fourth switch tube is electrically connected to the input voltage, and the second end of the fourth switch tube is electrically connected to the first end of the fifth resistor and the positive input end of the buffer respectively; The second end of the fifth resistor is electrically connected to the reverse input end of the buffer, the first end of the fifth switch tube and the output end of the driving circuit respectively; The second end of the fifth switch tube is electrically connected to the output voltage; The output terminal of the buffer is electrically connected to the second input terminal of the adder.

8. The current limiting circuit according to claim 7, characterized in that: The current mode control circuit further includes an output circuit, wherein the output circuit includes an energy storage element, a sixth resistor and a fourth capacitor; The first end of the energy storage element is electrically connected to the output end of the drive circuit, and the second end of the energy storage element is grounded; The first end of the sixth resistor and the first end of the fourth capacitor are both grounded; The second end of the sixth resistor and the second end of the fourth capacitor are electrically connected to the output voltage.

9. A chip, characterized in that: include: A current limiting circuit as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: include: The chip as claimed in claim 9.

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