A data transmission system based on data stream bit-by-bit backhaul check

Abstract

The application relates to data transmission, in particular to a data transmission system based on bit-by-bit feedback checking of data flow, a data transmission layer, data interaction between a chip internal memory and the layer, reading and writing in a DMA mode, realization of data transmission of different lengths, and data of a current data transmission task is cached to realize data retransmission when data checking error occurs; a data link layer used for data packaging and transmission control, a sending end state machine T_FSM and a receiving end state machine R_FSM are respectively built in a sending end TX and a receiving end RX to control working states; a data conversion layer used for data coding and checking, parallel data is converted into serial data, the serial data is transmitted to the outside through LVDS, and data checking results are fed back to the data link layer; the technical scheme provided by the application can overcome the defect that data retransmission of the whole data packet is needed when data checking error occurs, and data transmission efficiency is greatly reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to data transmission, in particular to a data transmission system based on bit-by-bit feedback check of data stream. BACKGROUND

[0002] Single event upset (SEU) is a phenomenon that when a high-energy particle hits a semiconductor component, it causes the logic to change "0" or "1", and then causes logic error. In an electromagnetic radiation harsh environment such as outer space, the communication between chips is often affected by SEU. Since high-performance chips need to match high-transmission-rate communication interfaces, data errors in communication interfaces will cause functional errors of the entire device.

[0003] When developing high-performance anti-radiation components, the commonly used reinforcement techniques include register multi-mode redundancy, memory data interleaving and pipeline self-refreshing. For data transmission modules, including high-speed transmission devices, data packets are generally used for data transmission. The reinforcement method is only used for reinforcing registers or memories, and the data is more checked. Once the data check is wrong, the entire data packet needs to be retransmitted, which greatly reduces the data transmission efficiency. SUMMARY

[0004] (I) Technical problems to be solved

[0005] In view of the above shortcomings of the prior art, the present application provides a data transmission system based on bit-by-bit feedback check of data stream, which can effectively overcome the defect that the data transmission efficiency is greatly reduced due to the need for data retransmission of the entire data packet when the data check error occurs in the prior art.

[0006] (II) Technical solutions

[0007] In order to achieve the above purpose, the present application is realized by the following technical solutions:

[0008] A data transmission system based on bit-by-bit feedback check of data stream, comprising a data transmission layer, a data link layer and a data conversion layer;

[0009] The data transmission layer is used for data interaction between the internal memory of the chip and the layer, adopts DMA mode for reading and writing, realizes data transmission of different lengths, and buffers the data of the current data transmission task for data retransmission when data check error occurs;

[0010] The data link layer is used for data packaging and transmission control, and the sending end state machine T_FSM and the receiving end state machine R_FSM are respectively built in the sending end TX and the receiving end RX for working state control;

[0011] The data conversion layer is used for encoding and checking of data, converts parallel data into serial data, transmits the serial data to the outside through LVDS, and feeds back the data checking result to the data link layer to determine whether the current transmission data is normally transmitted or retransmitted, and can also synchronize and check the data transmitted back through LVDS.

[0012] Preferably, the data transmission layer comprises a DMA controller, a configuration register CSR and a retransmission register.

[0013] The DMA controller is used for data interaction between the chip and the internal memory, and reads and writes in the DMA mode.

[0014] The configuration register CSR is used for configuring the controller or obtaining the controller state, parsing the value of the control register into a corresponding control signal, outputting after cross-clock domain processing, sampling the input state signal and updating the internal register.

[0015] The retransmission register buffers the data of the current data transmission task for data retransmission when the data checking is wrong.

[0016] Preferably, the data conversion layer comprises a data shifter DATASHIFT, an echo synchronizer ECHO SYNC and an echo checker ECHO COMPARE.

[0017] The data shifter DATASHIFT converts parallel data into serial data.

[0018] The echo synchronizer ECHO SYNC aligns the transmitted back serial data and converts the serial data into parallel data.

[0019] The echo checker ECHO COMPARE compares and checks the transmitted back data with the corresponding transmitted data.

[0020] Preferably, every time the transmitter TX transmits an effective data, the TXS_CTRL signal of the transmitter TX starts to flip, the TXS_DATA signal transmitted by the transmitter TX maintains 4 high levels, and then starts to transmit data, the TXS_CTRL signal remains high after transmitting an effective data, and waits for the transmitted back data of the receiver RX.

[0021] After the transmitter TX receives the transmitted back data, the transmitter TX compares and checks the transmitted back data with the corresponding transmitted data.

[0022] If the transmitted back data is detected to be wrong, the TXS_CTRL signal of the transmitter TX starts to flip, the TXS_DATA signal transmitted by the transmitter TX maintains 4 low levels, and then starts to retransmit data.

[0023] If the back data is correct, the next valid data is transmitted.

[0024] Preferably, the TXR_CTRL signal of the receiving end RX starts to flip after receiving a valid data, and the TXR_DATA signal of the receiving end RX starts to transmit after maintaining a low level for 1 bit.

[0025] Preferably, the sending end state machine T_FSM in the data link layer includes six working states:

[0026] The reset state: after the chip is powered on and reset, the TX channel enters the reset state, and the output signal is maintained as a high level;

[0027] The data sending state: when the data transmission layer starts to work, there is a 32-bit valid data in the buffer of the TX channel, the TX channel enters the data sending state, starts to send the valid data, and the TXS_CTRL signal starts to flip, the rising edge is aligned with each bit of the data, and the output signal is maintained as a high level after the sending is completed;

[0028] The data verification state: after sending a valid data, the TX channel enters the data verification state, starts to collect the back data through the state of the TXR_CTRL signal, and compares and verifies the back data with the corresponding sending data;

[0029] The high level verification state: after N periods, the TX channel enters the high level verification state, starts to detect 4 periods of high level to ensure that the data transmission is completed; if the data verification is correct and 4 periods of high level are detected, the TX channel jumps back to the data sending state to continue to transmit the next valid data; if the data verification is incorrect or 4 periods of high level are not detected, the TX channel jumps into the retransmission waiting state;

[0030] The retransmission waiting state: at this time, the TXS_CTRL signal is maintained as a low level to inform the data transmission layer to retransmit the data;

[0031] The low level verification state: after N periods, the TX channel enters the low level verification state until 4 periods of low level are detected, and then the TX channel jumps back to the data sending state to retransmit the current valid data;

[0032] N is the delay period of the sending end TX and the receiving end RX for transmitting the same group of data.

[0033] Preferably, the receiving end state machine R_FSM in the data link layer includes five working states:

[0034] The reset state: after the chip is powered on and reset, the RX channel enters the reset state, and waits to receive the valid data sent by the opposite end;

[0035] Receiving state, after detecting 3 continuous high levels, detecting rising edge, entering receiving state, starting to receive valid data;

[0036] Observing state, after receiving a valid data, waiting for the peer to compare and check the returned data; if 3 continuous high levels are detected, it indicates that the received data is correct, the data is popped out and jumps into the submission preparation state; if rising edge is detected, it directly jumps into the submission preparation state; if 3 continuous low levels are detected, it indicates that the received data is incorrect, the data is discarded and jumps into the retransmission state;

[0037] Submission preparation state, if 3 rising edges are detected, it indicates that the next round of valid data receiving starts, the current data is popped out and jumps back to the receiving state; if 3 continuous low levels are detected, it indicates that the received data is incorrect, the peer starts to retransmit the data, and jumps into the retransmission state;

[0038] Retransmission state, detecting rising edge, indicating that the retransmission data starts, jumping back to the receiving state.

[0039] (Three) beneficial effects

[0040] Compared with the prior art, the data transmission system based on data stream bit-by-bit return verification provided by the application is based on the idea of data stream bit-by-bit return verification, and a high-speed data transmission protocol resistant to single event upset in a radiation environment is constructed, data stream bit-by-bit return verification is realized, parallel data can be verified bit by bit, only one parallel data needs to be retransmitted when data verification error occurs, the data transmission accuracy is improved, the data retransmission loss is greatly reduced, and the data transmission efficiency is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creating laborious work.

[0042] Figure 1 It is a schematic diagram of the system of the application;

[0043] Figure 2 It is a schematic diagram of single event upset error of the sending end TX in the application before transmission, during transmission and when high level is transmitted;

[0044] Figure 3 It is a schematic diagram of single event upset error of the receiving end RX in the application when data is returned;

[0045] Figure 4 It is a schematic diagram of the sending end state machine T_FSM of the sending end TX in the application;

[0046] Figure 5 A schematic diagram of a receiving end state machine R_FSM of a receiving end RX in the application. DETAILED DESCRIPTION

[0047] In order to make the objects, technical solutions and advantages of the embodiments of the application clearer, the technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are some but not all of the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the application.

[0048] A data transmission system based on data stream bit-by-bit feedback verification, as shown in Figure 1 includes a data transmission layer, a data link layer and a data conversion layer;

[0049] The data transmission layer is used for data interaction between the internal memory of the chip and the layer, reads and writes in the DMA mode, realizes data transmission of different lengths, and buffers data of a current data transmission task for data retransmission when data verification is wrong.

[0050] The data link layer is used for data packaging and transmission control, and a sending end state machine T_FSM and a receiving end state machine R_FSM are respectively built in a sending end TX and a receiving end RX to control working states.

[0051] The data conversion layer is used for data encoding and verification, converts parallel data into serial data, transmits the serial data to the outside through LVDS, feeds back data verification results to the data link layer to determine whether current transmission data is normally transmitted or retransmitted, and can also synchronize and verify data transmitted through LVDS.

[0052] As shown in Figure 1 , the data transmission layer includes a DMA controller, a configuration register CSR and a retransmission register.

[0053] The DMA controller is used for data interaction between the internal memory of the chip and reads and writes in the DMA mode.

[0054] The configuration register CSR is used for configuration and controller state acquisition, parses the value of the control register into a corresponding control signal, outputs after cross-clock domain processing, samples an input state signal and updates an internal register.

[0055] The retransmission register buffers data of a current data transmission task for data retransmission when data verification is wrong.

[0056] As Figure 1 shown, the data conversion layer includes a data shifter DATASHIFT, an echo synchronizer ECHO SYNC and an echo comparator ECHO COMPARE;

[0057] The data shifter DATASHIFT converts parallel data into serial data;

[0058] The echo synchronizer ECHO SYNC aligns the serial data and converts it into parallel data;

[0059] The echo comparator ECHO COMPARE compares the echo data with the corresponding sending data.

[0060] As Figure 2 shown, every time the sending end TX sends a valid data, the TXS_CTRL signal of the sending end TX starts to flip, the TXS_DATA signal transmitted by the sending end TX maintains 4 high levels, and then starts to send data. After sending a valid data, the TXS_CTRL signal remains high, and waits for the echo data from the receiving end RX.

[0061] After receiving the echo data, the sending end TX compares the echo data with the corresponding sending data:

[0062] If the echo data is detected to be incorrect, the TXS_CTRL signal of the sending end TX starts to flip, the TXS_DATA signal transmitted by the sending end TX maintains 4 low levels, and then starts to retransmit data.

[0063] If the echo data is detected to be correct, the next valid data is continuously transmitted.

[0064] As Figure 3 shown, every time the receiving end RX receives a valid data, the TXR_CTRL signal of the receiving end RX starts to flip, the TXR_DATA signal transmitted by the receiving end RX maintains 1 low level, and then starts to transmit echo data.

[0065] As Figure 4 shown, the sending end state machine T_FSM in the data link layer includes six working states:

[0066] The reset state, after the chip is powered on and reset, the TX channel enters the reset state, at this time the output signal remains high;

[0067] The data sending state, when the data transmission layer starts to work, there is a 32-bit valid data in the buffer of the TX channel, enters the data sending state, starts to send the valid data, at the same time the TXS_CTRL signal starts to flip, the rising edge is aligned with every bit of data, and after the sending is completed, the output signal continues to remain high.

[0068] Data check state: After sending a valid data, enter the data check state, start collecting the backhaul data through the TXR_CTRL signal state sent back, and compare and verify it with the corresponding sent data;

[0069] High-level check state: considering the transmission delay, after N periods, enter the high-level check state, start detecting 4 periods of high level to ensure that the data backhaul is complete; if the data check is correct and 4 periods of high level are detected, jump back to the data sending state and continue to transmit the next valid data; if the data check is incorrect / 4 periods of high level are not detected, jump into the retransmission waiting state;

[0070] Re-transmission waiting state: at this time, TXS_CTRL remains low, notifying the data transmission layer to retransmit the data;

[0071] Low-level check state: after N periods, enter the low-level check state, until 4 periods of low level are detected, jump back to the data sending state and retransmit the current valid data;

[0072] Wherein, N is the delay period of the same group of data transmission of the sending end TX and the receiving end RX.

[0073] As shown in Figure 5 The receiving end state machine R_FSM in the data link layer includes five working states:

[0074] Reset state: after the chip is powered on and reset, the RX channel enters the reset state and waits to receive valid data sent by the opposite end;

[0075] Receiving state: after detecting 3 consecutive high levels and detecting the rising edge, enter the receiving state and start receiving valid data;

[0076] Observation state: after receiving a valid data, wait for the opposite end to compare and verify the backhaul data; if 3 consecutive high levels are detected, it means that the received data is correct, the data is popped out and jumps into the submission preparation state; if the rising edge is detected, it directly jumps into the submission preparation state; if 3 consecutive low levels are detected, it means that the received data is incorrect, the data is discarded and jumps into the retransmission state;

[0077] Submission preparation state: if 3 rising edges are detected, it means that the next round of valid data reception starts, the current data is popped out and jumps back to the receiving state; if 3 consecutive low levels are detected, it means that the received data is incorrect, the opposite end starts to retransmit the data, and jumps into the retransmission state;

[0078] Re-transmission state: detecting the rising edge means that the retransmission data starts, and jumps back to the receiving state.

[0079] The above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalent features; and these modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A data transmission system based on bit-by-bit data stream back-transmission verification, characterized in that: It includes the data transmission layer, data link layer, and data conversion layer; The data transfer layer is used for data interaction between the chip's internal memory and this layer. It uses DMA for reading and writing to achieve data transfer of different lengths. At the same time, it caches the data of the current data transfer task so that data can be retransmitted when data verification fails. The data link layer is used for data packaging and transmission control. The transmitting end TX and the receiving end RX have built-in transmitting end state machine T_FSM and receiving end state machine R_FSM respectively to control the working state. The data conversion layer is used for data encoding and verification. It converts parallel data into serial data, transmits it to the outside via LVDS, and feeds back the data verification results to the data link layer to determine whether the currently transmitted data is transmitted normally or retransmitted. At the same time, it can synchronize and verify the data transmitted back through LVDS. Each time a valid data is transmitted in the transmitting end TX, the TXS_CTRL signal of the transmitting end TX starts to toggle. After the TXS_DATA signal transmitted by the transmitting end TX is maintained at a high level for 4 consecutive times, data transmission begins. After transmitting a valid data, the TXS_CTRL signal remains high, waiting for the data to be transmitted back from the receiving end RX. After receiving the returned data, the sending end TX compares and verifies it with the corresponding sent data: If an error is detected in the returned data, the TXS_CTRL signal of the transmitting end TX will start to toggle, and the TXS_DATA signal transmitted by the transmitting end TX will maintain a low level for 4 consecutive times before retransmitting the data. If the returned data is correct, then continue transmitting the next valid data.

2. The data transmission system based on bit-by-bit data stream back-transmission verification according to claim 1, characterized in that: The data transmission layer includes a DMA controller, a configuration register (CSR), and a retransmission register. The DMA controller is used to interact with the chip's internal memory, and performs read and write operations using DMA. The configuration register (CSR) is used to configure the controller or obtain the controller status. It parses the value of the control register into the corresponding control signal, performs cross-clock domain processing, and outputs the signal. At the same time, it samples the input status signal and updates the internal registers. The retransmission register buffers the data for the current data transmission task, allowing for data retransmission in case of data verification errors.

3. The data transmission system based on bit-by-bit data stream back-transmission verification according to claim 2, characterized in that: The data conversion layer includes a data shifter DATASHIFT, a return synchronizer ECHO SYNC, and a return checker ECHOCOMPARE. The DATASHIFT data shifter converts parallel data into serial data. The ECHO SYNC backhaul synchronizer aligns the serial data being returned and converts it into parallel data. The ECHO COMPARE checker compares and verifies the returned data with the corresponding sent data.

4. The data transmission system based on bit-by-bit data stream back-transmission verification according to claim 1, characterized in that: Each time a valid data is received in the receiver RX, the TXR_CTRL signal of the receiver RX starts to flip. After the TXR_DATA signal transmitted by the receiver RX is maintained at a low level for one period, it starts to transmit data back.

5. The data transmission system based on bit-by-bit data stream back-transmission verification according to claim 4, characterized in that: The transmitter state machine T_FSM in the data link layer includes six working states: In the reset state, after the chip is powered on and reset, the TX channel enters the reset state, and the output signals remain at a high level. In the data transmission state, after the data transmission layer starts working, there is 32 bits of valid data in the buffer of the TX channel. Entering the data transmission state, the valid data is sent. At the same time, the TXS_CTRL signal starts to toggle, with the rising edge aligned with the middle of each bit of data. After the transmission is completed, the output signal continues to remain at a high level. Data verification state: After sending a valid data, the system enters the data verification state and begins to collect the returned data by collecting the status of the returned TXR_CTRL signal and comparing and verifying it with the corresponding sent data. In the high-level check state, considering transmission delay, after N cycles, the system enters the high-level check state and begins detecting 4 cycles of high level to ensure that the data has been transmitted back. If the data verification is correct and 4 cycles of high level are detected, the system jumps back to the data transmission state and continues to transmit the next valid data. If the data verification is incorrect or 4 cycles of high level are not detected, the system jumps to the retransmission waiting state. Retransmission wait state: At this time, TXS_CTRL remains low, notifying the data transmission layer to retransmit data; After N cycles of low-level detection, the system enters the low-level detection state again until four cycles of low level are detected. Then, it jumps back to the data transmission state and retransmits the currently valid data. Where N is the delay period for the same set of data transmissions at the transmitting end TX and the receiving end RX.

6. The data transmission system based on bit-by-bit data stream back-transmission verification according to claim 5, characterized in that: The receiver state machine R_FSM in the data link layer includes five working states: In the reset state, after the chip is powered on and reset, the RX channel enters the reset state and waits to receive valid data sent by the other end. In the receive state, after detecting three consecutive high levels and then detecting a rising edge, the system enters the receive state and begins receiving valid data. In the observation state, after receiving a valid data, the system waits for the other end to compare and verify the returned data. If three consecutive high levels are detected, it indicates that the received data is correct, the data is discarded, and the system jumps to the submission preparation state. If a rising edge is detected, the system jumps directly to the submission preparation state. If three consecutive low levels are detected, it indicates that the received data is incorrect, the data is discarded, and the system jumps to the retransmission state. The system submits to the ready state. If three rising edges are detected, it indicates that the next round of valid data reception has begun. The current data is popped and the system jumps back to the receive state. If three consecutive low levels are detected, it indicates that the received data has been corrupted. The other end begins to retransmit the data and the system jumps to the retransmission state. In the retransmission state, a rising edge is detected, indicating the start of retransmission, and the system jumps back to the receive state.

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