A baseband modulation system and method supporting oversampling and variable symbol rate

Abstract

The present invention discloses a baseband modulation system and method supporting oversampling and variable symbol rate, belonging to the field of digital signal transmission technology. The system includes parallel modulation one and modulation two, input signals enter modulation one and modulation two at the same time, modulation one and modulation two are used to modulate signals of different modulation types; through parallel processing of modulation one / modulation two, the sampling rate in the modulation process is a factor of the FPGA user clock frequency. M times, which exceeds the clock frequency. While retaining phase continuity, the transmittable bandwidth increases with the increase of sampling rate. A system structure different from the existing technology is adopted to generate a large-bandwidth, variable-symbol-rate modulated signal that can adapt to the rapidly changing signal propagation environment. After the system structure is designed, the symbol rate can be directly adjusted by the host computer on the PC without modifying the code from the bottom of the design, so that the system has the function of variable symbol rate.

Description

Technical Field

[0001] The invention relates to a baseband modulation system and method supporting oversampling and variable symbol rate, belonging to the technical field of digital signal transmission. Background Art

[0002] As the research on 6G mobile communication technology progresses, it is expected to support extremely high data transmission rates, extreme connection density, and lower latency, which will pose higher challenges to baseband signal processing, including the need to support wider spectrum resources, higher sampling rates, and more complex modulation and demodulation technologies. In addition, since 6G will integrate resources from different frequency bands to achieve full spectrum access, this will require baseband modulation and demodulation technology to be able to flexibly adapt to the characteristics of different frequency bands and optimize the spectrum utilization efficiency of signals.

[0003] The following introduces the background of the invention from two aspects: digital logic structure and variable symbol rate signal processing method:

[0004] In the prior art, there are mainly the following designs for baseband modulation systems with high sampling rates higher than the clock frequency:

[0005] (1) The design on the host computer software can be executed in program sequence according to the generation principle of the modulation signal. The logic is simple and the operation is easy. However, due to the limitations of CPU calculation speed and transmission bandwidth, the real-time performance of the signal is not high.

[0006] (2) The digital logic structure design on the FPGA (field programmable gate array) adopts a multi-channel parallel approach and is often designed for a specific modulation type. For example, when mapping only QPSK (quadrature phase shift keying) modulation, the signal is converted from serial to parallel and then output in a parallel filtering manner. The signals before and after filtering are parallel. Or when mapping only FSK (frequency-shift keying) modulation, multiple parallel DDS (direct digital frequency synthesizers) are used to generate IQ signals. It is impossible to flexibly change the modulation mode in real time and achieve a flexible and variable symbol rate.

[0007] (3) In space high-speed optical communication, a fast frequency hopping signal generator based on multi-channel parallel DDS is used to achieve continuous phase, thereby meeting the requirement of strict continuity of the carrier phase of the frequency hopping signal in the coherent fast frequency hopping system. This technology can improve the anti-interference ability of the wireless communication system while ensuring signal quality, but the system is heavily dependent on the accuracy of phase synchronization and has a complex design structure.

[0008] There are two main methods for processing variable symbol rate signals in existing baseband modulation systems:

[0009] (1) Controlling the rate of symbol generation by externally changing the external system clock frequency requires a dedicated clock chip, and the frequency change is complex and lacks flexibility;

[0010] (2) Changing the interpolation factor (or interpolation multiple) to change the symbol rate. This method needs to be designed in conjunction with the filter. In order to reduce code distortion, the coefficient length is often controlled by a fixed truncation length, which will result in the coefficient length not being fixed when the symbol rate is variable. The filter IP core cannot be directly used for implementation, and the filter needs to be designed by itself. The complexity is high. When the symbol rate is too low, the coefficient length is too large. The BRAM (block random access memory) and DSP (digital signal processor) resources occupied during implementation are too large, resulting in excessive use of FPGA resources. It is not very practical. If the filter coefficient length is fixed, the bit rate cannot be higher than the clock frequency when the serial bit signal is generated. At the same bit rate, the symbol rates of different modulation types are different. Therefore, the filter coefficient design needs to be designed in combination with the symbol rate, bit rate, and modulation type, which is relatively complicated.

[0011] In summary, the prior art still has the following defects: complex system structure, immutable symbol rate, and small bandwidth. Summary of the invention

[0012] The purpose of the present invention is to provide a baseband modulation system and method supporting oversampling and variable symbol rate, so as to solve the defects of complex system structure, invariable symbol rate and small bandwidth in the baseband modulation process in the prior art.

[0013] To achieve the above objectives, the present invention is implemented by adopting the following technical solutions:

[0014] In a first aspect, the present invention provides a baseband modulation system supporting oversampling and variable symbol rate, comprising a parallel modulation one and a modulation two, wherein an input signal enters the modulation one and the modulation two at the same time, and the modulation one and the modulation two are used to modulate signals of different modulation types;

[0015] Modulation The modulation performed on a pair of input signals includes: converting the input signal into an IQ signal with an average energy of 1, performing interpolation upsampling on the IQ signal, performing parallel filtering on the IQ signal to obtain a first parallel IQ signal, converting the first parallel IQ signal into a first serial IQ signal and outputting it;

[0016] The modulation performed on the input signal by the modulation second includes: converting the input signal into an I signal, performing interpolation upsampling on the I signal, performing serial filtering on the I signal, generating a second parallel IQ signal with a different frequency based on the frequency deviation of the input signal and the I signal, converting the second parallel IQ signal into a second serial IQ signal, performing conjugation processing on the second serial IQ signal, and selecting one of the conjugation results for output;

[0017] Based on the modulation type of the input signal acquired in advance, an output signal that is consistent with the modulation type of the input signal is selected from the output signals of modulation one and modulation two as the output signal of the baseband modulation system and output.

[0018] Furthermore, the input signal is obtained by the following method:

[0019] Get m sequence, the m The sequence is input into the linear feedback shift register, and the linear feedback shift register is shifted in one clock cycle. N Get N bit register, so that the adder m registers and d The output of the register is N The calculation is repeated and the result of each calculation is assigned to the first register. After the calculation is completed, the registers output in parallel. N bits of PN sequence, the PN sequence being an input signal;

[0020] N is the number of bits contained in a symbol in the modulation type of the input signal, N ≥1 and is an integer, m is the number of linear feedback shift registers, d for m The corresponding polynomial taps;

[0021] Wherein, within one clock cycle, assigning the result of each calculation to the first register is completed by the following formula:

[0022] r ( N : m -1) = r (0: m - N -1);

[0023] a ( N -1- n ) = r ( d -1- n ) ^ r ( m -1- n ), N ≤ d ≤ m ;

[0024] r ( N -1- n) = a ( N -1- n );

[0025] in, r ( N : m -1) indicates the N +1 register output value r ( N ) to m The output value of the register r ( m -1), r (0: m - N -1) indicates the output value of the first register r ( 0 ) to mN The output value of the register r ( m - N -1), a ( N -1- n )express r ( d -1- n )and r ( m -1- n ), r ( d -1- n ) indicates the d - n The output value of the register, r ( m -1- n ) indicates the m - n The output value of the register, ^ represents binary addition operation, r ( N -1- n ) indicates the N - n The output value of the register, n =0~ N -1, n is a count that increases by 1;

[0026] Among them, in one clock cycle, the output contains N The PN sequence of bits is:

[0027] y = r ( m -1- n );

[0028] in, y Represents PN sequence.

[0029] Further, the conversion of the input signal into an IQ signal with an average energy of 1 is completed by a symbol mapping and normalization module, and the symbol mapping and normalization module includes a parallel 2ASK conversion module, a BPSK conversion module, a QPSK conversion module, an 8PSK conversion module, a 16QAM conversion module and a 32QAM conversion module, and a first signal selector connected after all the conversion modules;

[0030] The 2ASK conversion module includes 2ASK symbol mapping and 2ASK bit width consistency, which are used to perform symbol mapping and normalization on the input signal of the modulation type 2ASK. The BPSK conversion module includes BPSK symbol mapping and BPSK energy normalization, which are used to perform symbol mapping and normalization on the input signal of the modulation type BPSK. The QPSK conversion module includes QPSK symbol mapping and QPSK energy normalization, which are used to perform symbol mapping and normalization on the input signal of the modulation type QPSK. The 8PSK conversion module includes 8PSK symbol mapping and 8PSK energy normalization, which are used to perform symbol mapping and normalization on the input signal of the modulation type 8PSK. The 16QAM conversion module includes 16QAM symbol mapping and 16QAM energy normalization, which are used to perform symbol mapping and normalization on the input signal of the modulation type 16QAM. The 32QAM conversion module includes 32QAM symbol mapping and 32QAM energy normalization, which are used to perform symbol mapping and normalization on the input signal of the modulation type 32QAM.

[0031] The operations performed by the first signal selector in modulation one include: the first signal selector selects a signal having the same modulation type as the input signal from the signals input thereto and outputs the signal, thereby obtaining an IQ signal with an average energy of 1.

[0032] Further, the conversion of the input signal into the I signal is implemented by a symbol mapping module, and the symbol mapping module includes a parallel 2FSK conversion module and a 4FSK conversion module, and a second signal selector connected after all the conversion modules;

[0033] The 2FSK conversion module includes a 2FSK symbol mapping for performing symbol mapping on an input signal whose modulation type is 2FSK, and the 4FSK conversion module includes a 4FSK symbol mapping for performing symbol mapping on an input signal whose modulation type is 4FSK;

[0034] The operation performed by the second signal selector in modulation 2 includes: the second signal selector selects a signal having the same modulation type as the input signal from the signals input thereto and outputs the signal to obtain an I signal.

[0035] Further, the parallel filtering of the IQ signal to obtain the first parallel IQ signal is implemented by a parallel filtering module, and the parallel filtering module includes a serial-to-parallel conversion module, a raised cosine shaping filter, a root raised cosine shaping filter, a Gaussian shaping filter and a third signal selector;

[0036] The raised cosine shaping filter, the root raised cosine shaping filter and the Gaussian shaping filter are in parallel, and are respectively connected to the serial-to-parallel conversion module and the third signal selector, and the serial-to-parallel conversion module also has an interface directly connected to the third signal selector;

[0037] The operation performed by the third signal selector in modulation one includes: the third signal selector selects a signal having the same filtering type as the input signal from the signal input thereto and outputs the signal to obtain a first parallel IQ signal.

[0038] Further, the serial filtering of the I signal is implemented by a serial filtering module, and the serial filtering module includes a raised cosine shaping filter, a root raised cosine shaping filter, a Gaussian shaping filter and a fourth signal selector;

[0039] The raised cosine shaping filter, the root raised cosine shaping filter and the Gaussian shaping filter are in parallel and are all connected to the fourth signal selector, and the fourth signal selector also has an input end for receiving the I signal after interpolation upsampling;

[0040] The operation performed by the fourth signal selector in modulation 2 includes: the fourth signal selector selects a signal having the same filtering type as the input signal from the signals input thereto and outputs the signal.

[0041] Further, the generating of second parallel IQ signals with different frequencies based on the frequency deviation of the input signal and the I signal includes:

[0042] Multiplying the I signal and the frequency deviation of the input signal to generate an output frequency, generating a phase increment value, calculating a frequency control word according to the absolute value of the output frequency, inputting the phase increment value and the frequency control word into a phase accumulation counter to generate a multi-channel phase corresponding to a second parallel IQ signal, setting a coordinate rotation digital computer based on the output frequency and the phase, and generating a multi-channel parallel second parallel IQ signal through the set coordinate rotation digital computer;

[0043] The selecting one of the conjugated results to output comprises: selecting a corresponding serial signal output according to the positive or negative of the output frequency.

[0044] Furthermore, the bit rate of the input signal is expressed as:

[0045] f b = Nf B ;

[0046] in, f b is the bit rate of the input signal, N is the number of bits per symbol in the modulation type of the input signal, f B is the symbol rate;

[0047] The symbol rate has a value range of:

[0048] If no filter is used for filtering, the symbol rate range is f B ≤ f clk / 2, f clk is the clock frequency;

[0049] If a filter is used for filtering, the symbol rate range is , R is the interpolation factor during the interpolation upsampling process, L is the value obtained by subtracting one from the coefficient length of the filter, [·] means rounding down, P f Indicates the amount of parallel data output when the signal is filtered. In modulation 2, P f = 1.

[0050] Furthermore, the expressions of coefficient group addresses of the filters used in the parallel filtering and the serial filtering are:

[0051] A e = C 2 C 3 m f + C 3 m s + m r ;

[0052] in, Ae It is e Group filter coefficient group address, C 2 is the symbol rate quantity, C 3 is the roll-off factor number, m f Indicates that there are filters available to select C 1 filter types, in steps of 1, m f = 0~ C 1-1, m s Indicates that there is a filter that can be selected C 2 symbol rates, step size 1, m s = 0~ C 2-1, m r Indicates that there is a filter that can be selected C 3 roll-off factors, step size 1, m r = 0~ C 3-1;

[0053] All filter coefficient group addresses are stored in a filter IP core, with a total of C 1 C 2 C There are three coefficient group addresses, and the total length of the filter coefficients is C 1 C 2 C 3( L +1).

[0054] In a second aspect, the present invention provides a baseband modulation method supporting supersampling and variable symbol rate, which is implemented by the system described in any one of the first aspects, including:

[0055] Get input signal;

[0056] Inputting the input signal into modulation 1 and modulation 2 respectively;

[0057] Modulation The modulation performed on a pair of input signals includes: converting the input signal into an IQ signal with an average energy of 1, performing interpolation upsampling on the IQ signal, performing parallel filtering on the IQ signal to obtain a first parallel IQ signal, converting the first parallel IQ signal into a first serial IQ signal and outputting it;

[0058] The modulation performed on the input signal by the modulation second includes: converting the input signal into an I signal, performing interpolation upsampling on the I signal, performing serial filtering on the I signal, generating a second parallel IQ signal with a different frequency based on the frequency deviation of the input signal and the I signal, converting the second parallel IQ signal into a second serial IQ signal, performing conjugation processing on the second serial IQ signal, and selecting one of the conjugation results for output;

[0059] Based on the modulation type of the input signal acquired in advance, an output signal that is consistent with the modulation type of the input signal is selected from the output signals of modulation one and modulation two as the output signal of the baseband modulation system and output.

[0060] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0061] The present invention provides a baseband modulation system and method supporting oversampling and variable symbol rate, which realizes that the sampling rate in the modulation process is a factor of the FPGA user clock frequency through parallel processing of modulation 1 / modulation 2. M times, M The amount of parallel data exceeds the clock frequency. While maintaining phase continuity, the transmittable bandwidth increases with the increase of sampling rate. M It can change with the design requirements and has great flexibility; it adopts a system structure different from the existing technology to generate a modulation signal with large bandwidth and variable symbol rate, which can adapt to the rapidly changing signal propagation environment; two modulation paths, modulation 1 and modulation 2, are designed, which can be applicable to various modulation types such as nASK (n-ary amplitude shift keying), nPSK (n-ary phase shift keying), nQAM (n-ary quadrature amplitude modulation), and nFSK (n-ary frequency shift keying); after the system structure is designed, the symbol rate can be directly adjusted through the host computer on the PC side, without modifying the code from the bottom of the design, so that the system has the function of variable symbol rate.

[0062] By parallel N The PN sequence of 10 bits and the specific numerical range of the calculated symbol rate together support the variable symbol rate function of the system.

[0063] It can be seen from the expression of the bit rate that when the symbol rate is large, the bit rate may be higher than the clock frequency, which supports the consistency of the symbol rate range while supporting variable modulation type. It also supports the calculation of the symbol rate range without considering the influence of the bit rate, and supports the design of the filter coefficient group address, which only needs to consider the influence of the symbol rate, filter type, and roll-off factor, without additionally considering conditions such as modulation type and bit rate, thereby reducing the structural complexity of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1is a schematic diagram of a baseband modulation system supporting oversampling and variable symbol rate corresponding to Embodiment 1 of the present invention;

[0065] Figure 2 is a schematic diagram of a baseband modulation system supporting oversampling and variable symbol rate corresponding to Embodiment 2 of the present invention;

[0066] Figure 3 It is a principle block diagram of multi-channel parallel PN sequence generation provided by the present invention;

[0067] Figure 4 It is a MATLAB main function design flow chart of the signal modulation provided by the present invention;

[0068] Figure 5 A MATLAB sub-function floating-point design flow chart of the signal modulation provided by the present invention;

[0069] Figure 6 A MATLAB sub-function fixed-point design flow chart for the signal modulation provided by the present invention;

[0070] Figure 7 The 16QAM mapping constellation diagram provided by the present invention;

[0071] Figure 8 A comparison diagram of the floating-point and fixed-point time domain errors of 16QAM at a symbol rate of 62.5 MHz provided by the present invention;

[0072] Fig. 9 The present invention provides a 16QAM fixed-point simulation vector diagram when the symbol rate is 62.5MHz;

[0073] Fig.10 The 16QAM fixed-point simulation power spectrum diagram provided by the present invention at a symbol rate of 62.5MHz;

[0074] Fig.11 A comparison diagram of the time domain errors of 4FSK floating point and fixed point provided by the present invention when the symbol rate is 25MHz and the frequency deviation is 150MHz;

[0075] Fig.12 The 4FSK fixed-point simulation power spectrum diagram provided by the present invention when the symbol rate is 25MHz and the frequency deviation is 150MHz;

[0076] Fig.13 The module control block diagram based on FPGA design provided by the present invention;

[0077] Fig.14 The fixed-point baseband modulation joint simulation design block diagram of the MATLAB and VIVADO platforms provided by the present invention;

[0078] Fig.15This is a measured diagram of a 16QAM vector analyzer provided by the present invention when the symbol rate is 62.5MHz;

[0079] Fig.16 The present invention provides a measured diagram of the 4FSK power spectrum when the symbol rate is 25MHz and the frequency offset is 150MHz. DETAILED DESCRIPTION

[0080] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the protection scope of the present invention.

[0081] Example 1.

[0082] like Figure 1 As shown, the present invention provides a baseband modulation system supporting oversampling and variable symbol rate, including parallel modulation one and modulation two, input signals enter modulation one and modulation two at the same time, modulation one and modulation two are used to modulate signals of different modulation types;

[0083] Modulation The modulation performed on a pair of input signals includes: converting the input signal into an IQ signal with an average energy of 1, interpolating and upsampling the IQ signal, parallel filtering the IQ signal to obtain a first parallel IQ signal, converting the first parallel IQ signal into a first serial IQ signal and outputting it;

[0084] The modulation performed on the input signal by the modulation second includes: converting the input signal into an I signal, performing interpolation upsampling on the I signal, performing serial filtering on the I signal, generating a second parallel IQ signal with a different frequency based on the frequency deviation of the input signal and the I signal, converting the second parallel IQ signal into a second serial IQ signal, performing conjugation processing on the second serial IQ signal, and selecting one of the conjugation results for output;

[0085] Based on the modulation type of the input signal acquired in advance, an output signal that is consistent with the modulation type of the input signal is selected from the output signals of modulation one and modulation two as the output signal of the baseband modulation system and output.

[0086] The sampling rate in the modulation process is a factor of the FPGA user clock frequency through parallel processing of modulation one and modulation two. M times, M The amount of parallel data exceeds the clock frequency. While maintaining phase continuity, the transmittable bandwidth increases with the increase of sampling rate. MIt can change with the design requirements and has great flexibility; it adopts a system structure different from the existing technology to generate a modulation signal with large bandwidth and variable symbol rate, which can adapt to the rapidly changing signal propagation environment; two modulation paths, modulation one and modulation two, are designed, which can be applicable to various modulation types such as nASK (n-ary amplitude shift keying), nPSK (n-ary phase shift keying), nQAM (n-ary quadrature amplitude modulation), and nFSK (n-ary frequency shift keying); after the system structure is designed, the symbol rate can be directly adjusted through the host computer on the PC side, without modifying the code from the bottom of the design, so that the system has the function of variable symbol rate.

[0087] Example 2.

[0088] The model of the FPGA chip selected in this embodiment is xcvu13p-fhgb2104-2-i, which contains extremely rich DSP and BRAM resources. The selected data transmission hardware interface model is JESD204C, and the total bit width is 128 bits. The interface sends data to the RF chip part for mixing to generate a RF signal.

[0089] The requirements of this embodiment are that the baseband modulation part includes four types: ASK, PSK, QAM, and FSK, and the maximum transmission bandwidth of the modulated signal is ≥ 600MHz, and when modulating, the signal bandwidth is ≥ 100MHz.

[0090] Based on the above requirements, the principle block diagram of the designed baseband modulation system is as follows: Figure 2 As shown, TX_I and TX_Q represent the transmitted vector signals. The real-time baseband modulation system includes 2ASK, BPSK, QPSK, 8PSK, 16QAM, 32QAM, 2FSK, and 4FSK. The number of bits contained in the symbol is N = 2~5 range, system clock f clk = 250MHz, sampling rate f s = 4 f clk = 1GHz, the number of parallel signals is M = 4 groups of IQ vector signals, each group of I or Q path signals is 16 bits wide, and the symbol rate range is 0.5MHz~62.5MHz.

[0091] Before designing FPGA, we first conduct floating-point and fixed-point simulation verification on MATLAB (matrix laboratory, a programming software) to check whether the errors of the two meet the sign requirements and whether the solution is feasible. Figure 4 , Figure 5 and Figure 6 shown.

[0092] like Figure 5 and Figure 6 As shown, in the floating-point modulation and fixed-point modulation sub-functions, both parts are based on the number of LFSR (Linear Feedback Shift Register) m , choose its polynomial taps d (Tap: A bit that affects the next state of a linear feedback shift register), and then according to its characteristic polynomial (the polynomial represents the feedback function of the LFSR, x represents the independent variable of the feedback function), generating a cycle length of 2 m -1 and the same set of PN sequences used for floating-point modulation and fixed-point modulation are used as the binary data source of the modulation signal. The several sets of selectable PN sequence characteristic polynomials and reference marks used are shown in Table 1.

[0093] Table 1- Correspondence table of polynomials of PN sequences of different lengths

[0094]

[0095] The taps of each polynomial in Table 1 satisfy 5 ≤ d < m , symbol constraints, generation method reference Figure 3 , in terms of the number of bits of QPSK or 4FSK N = 2, for example, m = 7 o'clock, d = 6, in one clock cycle, the register needs to be shifted right by 2 bits, expressed as:

[0096] r (2:6) = r (0:4);

[0097] a (1) = r (5) + r (6) a (0) = r (4) + r (5);

[0098] r (1) = a (1) r (0) = a (0);

[0099] in, r (2:6) indicates the output value of the third register r (2) Output value to the 7th register r (6) r(0:4) indicates the output value of the first register r (0) Output value to the 5th register r (4) r (5) indicates the output value of the sixth register, r (1) indicates the output value of the second register, a (1) Indicates r (5) and r The addition result of (6) is a (0) means r (4) and r The addition result of (5) is Figure 3 middle, r 0 to r 6 respectively correspond to r (0) to r (6), are the output values ​​of the 1st to 7th registers, respectively. The 1st register corresponds to Figure 3 Register 0 in , and so on, the 7th register corresponds to Figure 3 Register 6 in .

[0100] In one clock cycle, the two bits of the PN sequence output in parallel are:

[0101] y = r (6) r (5);

[0102] Its bit rate f b It is expressed as:

[0103] f b = 2f B .

[0104] In the design of the baseband modulation system, if the filter is not used in the filtering method, select the symbol rate mode m s = 0~248 (step 1) as input, the interpolation factor value is R = 4 + 2 m s = 4~500, then its symbol rate is , satisfying the conditions f B ≤ 125MHz.

[0105] In the design process of baseband modulation system, if a filter is used for filtering, the filter coefficient length of modulation one is set to L1+1 = 251, the coefficient width is 20 bits (fix20_19, fixb_c means 1 sign bit, bc-1 integer bit, c decimal bit, ufixb_c means 0 sign bit, bc integer bit, c decimal bit, and so on). The filter coefficient length of modulation 2 is L 2+1 = 81, the coefficient width is 31 bits (fix31_30). Select the symbol rate mode m s =0~7 (step 1) as the condition for using three filters: raised cosine, root raised cosine, and Gaussian. At this time, the symbol rate is f B =13.889MHz~62.5MHz, when modulation 1 is satisfied M f =4 symbol rate range 8.065MHz ≤ f B ≤ 125MHz, and modulation 2 M f =1 symbol rate range 6.25MHz ≤ f B ≤ 125MHz.

[0106] It is necessary to perform symbol mapping and energy normalization according to the mapping principles in modulation 1 and modulation 2. i The bits of the PN sequence in a clock cycle are b ( i ), i Indicates the serial number of the clock cycle, the bit is b(i) , 2ASK symbol mapping is as follows:

[0107] D 2ASK = b(i) ;

[0108] in, D 2ASK Indicates the IQ value after 2ASK symbol mapping and energy normalization.

[0109] Bit is b(i) , BPSK symbol mapping and energy normalization are as follows:

[0110] ;

[0111] in, D BPSK (i) Represents the IQ value after BPSK symbol mapping and energy normalization, j Represents the imaginary part.

[0112] Bit isb (2 i ), b (2 i +1), b (2 i ) indicates the second i The bits of the PN sequence in clock cycles, b (2 i +1) indicates the second i The bits of the PN sequence under +1 clock cycle, QPSK symbol mapping and energy normalization are as follows:

[0113] ;

[0114] in, D QPSK (i) Indicates the IQ value after QPSK symbol mapping and energy normalization.

[0115] Bit is b (3 i ), b (3 i +1), b (3 i +2), b (3 i ) indicates the third i The bits of the PN sequence in clock cycles, b (3 i +1) indicates the 3rd i +1 bit of the PN sequence in a clock cycle, b (3 i +2) indicates the 3rd i The bit of the PN sequence under +2 clock cycles, 8PSK symbol mapping and energy normalization are as follows:

[0116] ;

[0117] in, D 8PSK Indicates the IQ value after 8PSK symbol mapping and energy normalization, e is a natural constant, p For phase.

[0118] Phase p The mapping phase corresponding to the bit position is shown in Table 2:

[0119] Table 2 - Phase and bit mapping table

[0120]

[0121] Bit is b (4i ), b (4 i +1), b (4 i +2), b (4 i +3), b (4 i ) indicates the 4th i The bits of the PN sequence in clock cycles, b (4 i +1) indicates the 4th i +1 bit of the PN sequence in a clock cycle, b (4 i +2) indicates the 4th i +2 clock cycles of the PN sequence bits, b (4 i +3) indicates the 4th i The bit, 16QAM symbol mapping and energy normalization of the PN sequence under +3 clock cycles are as follows:

[0122] ;

[0123] in, D 16QAM (i) Indicates the IQ value after 16QAM symbol mapping and energy normalization. The constellation diagram is shown as follows Figure 7 As shown, it serves as the main reference diagram for subsequent tests.

[0124] Bit is b (5 i ), b (5 i +1), b (5 i +2), b (5 i +3), b (5 i +4), b (5 i ) indicates the 5th i The bits of the PN sequence in clock cycles, b (5 i +1) indicates the 5th i +1 bit of the PN sequence in a clock cycle, b (5 i +2) indicates the 5th i +2 clock cycles of the PN sequence bits, b (5 i +3) indicates the 5th i +3 clock cycles of the PN sequence bits, b (5i +4) means the 5th i The bit, 16QAM symbol mapping and energy normalization of the PN sequence under +4 clock cycles are as follows:

[0125] ;

[0126] in, D 32QAM (i) Indicates the IQ value after 32QAM symbol mapping and energy normalization.

[0127] Bit is b ( i ), the 2FSK symbol mapping is as follows:

[0128] D 2FSK =2 b ( i )-1;

[0129] in, D 2FSK Indicates the I value after 2FSK symbol mapping.

[0130] Bit is b (2 i ), b (2 i +1), the 4FSK symbol mapping is as follows:

[0131] ;

[0132] in, D 4FSK Indicates the I value after 2FSK symbol mapping.

[0133] During the mapping process, the expansion multiples of floating point and fixed point are kept the same. Fixed point also needs to be truncated to facilitate subsequent error comparison. The same is true for subsequent process stages. The data bit width after truncation at each stage of the process is as follows Figure 6 shown.

[0134] The baseband modulation system designed by the present invention adopts four filtering modes: none, raised cosine, root raised cosine and Gaussian. The first one has no filter, and the latter three have filters. The roll-off factor is β = 0.1 ~ 1.0 (step 0.1) ten kinds, the following are the process descriptions of modulation 1 and modulation 2 respectively.

[0135] There are two ways to perform the three parts of serial-to-parallel conversion, interpolation upsampling and filtering of the signal.

[0136] First, convert the symbols from serial to MRoad parallel, then proceed M The interpolation upsampling of the path, if the clock period is f clk When there is no filter, copy interpolation is used, and when there is a filter, zero interpolation is used. The sampling rate of the signal after interpolation is f s = Mf clk , according to the coefficient group address in the IP core of the FIR filter under FPGA, the filter coefficients are extracted and filtered with the interpolated signal. In this case, the number of parallel input and output signals of the filter is M The sampling rate is Mf clk .

[0137] Second, keep the single-channel serial mode. When there is no filter, copy interpolation is used. When there is a filter, zero interpolation is used. The sampling rate after interpolation is f clk When the IP core of the FIR filter under FPGA is set, the interpolation mode is used (Interpolation is selected), and the interpolation interval is M (Integer value, that is, the value of the interpolation interval is selected M ), after configuration is completed, filter coefficients are extracted according to the coefficient group address and filtered with the interpolated signal. In this case, the filter input signal is serial and the sampling rate is f clk , output signal M The sampling rate is Mf clk .

[0138] Modulate a signal from 1 channel to multiple channels, upsample and filter by interpolation. Since the filter function of the MATLAB system itself can only perform single-channel filtering, method 1 is used. In the actual FPGA design, method 2 is used. The output values ​​of the two methods are the same and the filtering effects are consistent.

[0139] Convert the symbols from serial to 4-way parallel. When there is no filter, copy interpolation is used. When there is a filter, zero interpolation is used. The sampling rate of the interpolated signal is f s = 4 f clk = 1GHz, directly configure the filter coefficients in the simulation stage, and then filter with the interpolated signal. Then select the signal output in this case according to the filtering method.

[0140] When the filter mode is None, no filter is needed, and the output can be directly converted from 1 channel to 4 channels for copying and interpolation. When there is a filter, 1 channel is converted to 4 channels and then zero interpolation is performed. Then, according to the filter coefficient order 251 and 81 for modulation 1 or modulation 2, the bit width is 20 and 31 bits, and the corresponding coefficients are generated and filtered with the input function. The filtered data is output with a total sampling rate of 1GHz under 4 parallel channels. Thus, the real-time baseband modulation signal of modulation 1 is generated.

[0141] The modulation signal is directly interpolated, upsampled and filtered in the serial state, and the sampling rate after interpolation is f clk =250MHz. Then select the signal output according to the filtering method.

[0142] When configuring the Cordic IP core of the FPGA, the input signal bit width is assigned to fix32_29, and the actual range is [-1, 1], which represents the angle [-π, π]. There are two integer bits that are not used. The actual phase increment value and phase accumulator bit width are W =30, the output signal bit width is allocated to fix16_14, indicating the amplitude [-1, 1]. To simulate its input and output, according to the filtered signal and frequency interval f d The nFSK output frequency obtained by multiplication f o , the generated phase increment Δ θ for:

[0143] ;

[0144] Right now ;

[0145] The generated M= The 4 parallel phases are generated as:

[0146] ;

[0147] in, θ t Indicates t Phases, t = 2 ~ M， Indicates the phase number.

[0148] The parallel phase increment value is used as the real-time phase to generate a real-time IQ vector signal according to the Cordic (Coordinate Rotation Digital Computer) principle.

[0149] According to f o The sign of the conjugate is selected and output. f o≥0, directly output IQ signal, f o <0, the positive value of the I-path signal and the negative value of the Q-path signal are output, thereby generating a real-time baseband modulation signal of modulation 2.

[0150] After the sub-functions of floating-point and fixed-point modulation are simulated, two parts of modulation signals are generated, such as Figure 4 As shown, it is known M =4, it is necessary to merge the 4 parallel signals into 1 serial signal, then extract the difference, draw a graph for observation, and compare the error range.

[0151] The system has a sampling rate of f s When FFT (Fast Fourier Transform) is performed, the transmittable bandwidth is B s The range is:

[0152] ;

[0153] in, f clk is the clock frequency, f c is the carrier of the RF signal, in baseband f c =0.

[0154] The transmission bandwidth of the designed baseband modulation signal occupies B m for:

[0155] ;

[0156] Among them, the first row corresponds to modulation 1 when there is no filter, the second row corresponds to modulation 2 when there is no filter, the third row corresponds to modulation 1 when there is a filter, and the fourth row corresponds to modulation 2 when there is a filter. f B is the symbol rate, f d is the frequency offset value (or frequency interval), N is the number of bits in a single symbol of the input modulation type, β is the roll-off factor of the filter, and 0< β ≤ 1.

[0157] When the modulation type is set to 16QAM of modulation 1, N =4, the drawing comparison error is as follows Figure 8 As shown, the symbol rate mode is set to 0 (symbol rate f B = 62.5MHz, bit rate f b= 250MHz), the filter mode is root raised cosine, the roll-off factor β Set to 0.8, the floating point and fixed point error is about 10 -5 The accuracy is high and the solution is feasible. The vector diagram and power spectrum of the fixed-point simulation are as follows: Fig. 9 and Fig.10 As shown, we can see that the bandwidth occupied by the signal is approximately:

[0158] .

[0159] The bandwidth occupied by modulation 1 is greater than 100 MHz, which meets the preset requirements.

[0160] When the modulation type is set to 4FSK of modulation 2, N =2, the drawing comparison error is as follows Fig.11 As shown, the symbol rate mode is set to 3 (symbol rate f B = 25MHz, bit rate f b = 100MHz), filter mode is none, frequency offset (frequency deviation) f d The floating point and fixed point errors are about 10 -5 The accuracy is high and the solution is feasible. Fig.12 As shown in the figure, since both ends are infinitely extended when there is no filter, the energy is mainly concentrated in the main lobe, so the bandwidth occupied by the main lobe is:

[0161] .

[0162] The occupied bandwidth is greater than 600MHz, which meets the preset requirements and the simulation is successful.

[0163] After MATLAB simulation verification is completed, according to its Figure 6 The fixed-point modulation design process is designed according to the bit width design and interception of each process module. The FPGA modules under the VIVADO platform are designed. The interface of the real-time baseband modulation signal generation system is shown in Table 3 below.

[0164] Table 3 - Digital signal interface table of FPGA baseband modulation system

[0165]

[0166] According to the interface, design the control relationship of each functional module from the top layer to the bottom layer, such as Fig.13 As shown, the functions that need to be implemented by each module are shown in Table 4 below.

[0167] Table 4 FPGA baseband modulation module functions

[0168]

[0169] It should be noted that all the coefficients needed for the filter are generated offline using MATLAB.coe files, and then the files are imported into the FIR filter IP core of the VIVADO platform (an integrated design kit released by an FPGA manufacturer in 2012). When using it, each group of filter coefficients can be read according to the coefficient group address. According to the filtering method of the input signal during the design in Table 3 F ir = 0~3, step 1, representing four filtering modes: none, raised cosine, root raised cosine, Gaussian, symbol rate mode m s = 0~248, step 1, the corresponding interpolation factor is R = 4 + 2 m s = 4 ~ 500, symbol rate range is f B = f clk / R = 0.5 ~62.5MHz, roll-off type α = 1~10, step 1, respectively represents the roll-off factor β = 0.1~1.0, that is α = 10 β .

[0170] When the signal modulation system has a filter, the limit range of the above input signal is F ir = 1~3, m s = 0~7, β =1~10, the access of coefficient group address is generated according to the following formula:

[0171] ;

[0172] in, A e It is e Group filter coefficient group address.

[0173] There are 240 coefficient group addresses in total, and the corresponding symbol rates, filter types, and roll-off factors are shown in Table 5 below.

[0174] Table 5 - Filter coefficient group address table

[0175]

[0176] After the functional design of each FPGA module is completed, a joint simulation is established with the fixed-point modulation in MATLAB to verify whether the output results of the designed real-time baseband modulated IQ vector signal are the same. The specific simulation process is as follows: Fig.14 shown.

[0177] The input parameters in Table 1 are set on the MATLAB platform, and the intercepted output IQ signal data quantity parameters are imported into the MATLAB fixed-point function and FPGA fixed-point read-write function designed on the platform.

[0178] MATLAB fixed-point function directly Figure 6 After the simulation, the simulation results are output. The FPGA fixed-point read and write function needs to convert the parameters into the input format under the FPGA first. After the processing is completed, it is saved in a .txt file and read through the test bench simulation module designed by the VIVADO platform to realize the real-time baseband modulation system designed by FPGA. After the simulation, the intercepted IQ signal is saved in a .txt file.

[0179] On the MATLAB platform, the FPGA fixed-point read and write function reads the .txt file results output by the FPGA and compares them with the MATLAB fixed-point function after converting 4 channels to 1 channel. If it is found that the IQ signal results of the two are exactly the same, the joint simulation is completed and the FPGA design is completed.

[0180] In the actual test, the FPGA chip used is xcvu13p-fhgb2104-2-i, and the transmission interface model is JESD204C. f c =3GHz carrier frequency mixing, it is transmitted through the RF port and connected to the vector signal analyzer through the RF line to observe its power spectrum and constellation diagram analysis.

[0181] In Modulation 1, select 16QAM signal measurement, set the symbol rate to 62.5MHz, set the filter mode to root raised cosine, and set the roll-off factor to 0.8. The vector analysis diagram is as follows: Fig.15 As shown, Fig.15 The first picture shows the spectrum (power spectrum) of the received signal. The center frequency corresponds to the RF frequency of 1 GHz and the display bandwidth is 200 MHz. The second picture shows the signal vector change diagram, which contains the trajectory changes of each digital signal. The third picture shows the constellation diagram. The points with concentrated energy in the vector diagram are extracted as the constellation diagram obtained by analysis. The 16 constellation points under 16QAM can be viewed. Fig. 9 The simulation results are consistent, and the transmission bandwidth is about 112.5MHz, which is consistent with Fig.10 The simulation results are consistent, and the constellation diagram is parsed to 16 points, which is consistent with Figure 7 The constellation points of 16QAM are consistent, and its EVM (vector amplitude error) measurement shows that the average value is about 0.46, which is within 1, and the measurement accuracy is relatively high.

[0182] In Modulation 2, select 4FSK signal measurement, set the symbol rate to 25MHz, and set the filter mode to none. The power spectrum is as follows: Fig.16 As shown in the figure, there are four energy concentration points at 2.55GHz, 2.85GHz, 3.15GHz, and 3.45GHz, and the corresponding baseband signal powers are -450MHz, -150MHz, 150MHz, and 450MHz, respectively. The intervals between them are twice the frequency deviation, and the main lobe of the transmission signal occupies a bandwidth of 950MHz, which is the same as Fig.12 The simulation results are consistent.

[0183] In summary, the actual measurement part is basically consistent with the simulation part, and the baseband error range is within 10 -5 Within 30 days, the FPGA-based baseband modulation system has been tested and verified, and it can achieve the results analyzed in the practical application.

[0184] Example 3.

[0185] The present invention provides a baseband modulation method supporting oversampling and variable symbol rate, which is implemented by the system provided in Embodiment 1, including:

[0186] Get input signal;

[0187] Inputting the input signal into modulation 1 and modulation 2 respectively;

[0188] Modulation The modulation performed on a pair of input signals includes: converting the input signal into an IQ signal with an average energy of 1, interpolating and upsampling the IQ signal, parallel filtering the IQ signal to obtain a first parallel IQ signal, converting the first parallel IQ signal into a first serial IQ signal and outputting it;

[0189] The modulation performed on the input signal by the modulation second includes: converting the input signal into an I signal, performing interpolation upsampling on the I signal, performing serial filtering on the I signal, generating a second parallel IQ signal with a different frequency based on the frequency deviation of the input signal and the I signal, converting the second parallel IQ signal into a second serial IQ signal, performing conjugation processing on the second serial IQ signal, and selecting one of the conjugation results for output;

[0190] Based on the modulation type of the input signal acquired in advance, an output signal that is consistent with the modulation type of the input signal is selected from the output signals of modulation one and modulation two as the output signal of the baseband modulation system and output.

[0191] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0192] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0193] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0194] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0195] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A baseband modulation system supporting supersampling and variable symbol rate, characterized in that: It includes parallel modulation one and modulation two, the input signal enters modulation one and modulation two at the same time, and modulation one and modulation two are used to modulate signals of different modulation types; Modulation The modulation performed on an input signal includes: converting the input signal into an IQ signal with an average energy of 1, performing interpolation upsampling on the IQ signal, performing parallel filtering on the interpolation upsampling IQ signal to obtain a first parallel IQ signal, converting the first parallel IQ signal into a first serial IQ signal and outputting the signal; The modulation performed on the input signal by the modulation second includes: converting the input signal into an I signal, performing interpolation upsampling on the I signal, performing serial filtering on the interpolation upsampling I signal, generating a second parallel IQ signal of a different frequency based on the frequency deviation of the input signal and the I signal after serial filtering, converting the second parallel IQ signal into a second serial IQ signal, performing conjugation processing on the second serial IQ signal, and selecting one of the conjugation results for output; Based on the modulation type of the input signal acquired in advance, an output signal consistent with the modulation type of the input signal is selected from the output signals of modulation one and modulation two as the output signal of the baseband modulation system and outputted; The interpolation up-sampled IQ signal is subjected to parallel filtering to obtain a first parallel IQ signal, which is implemented by a parallel filtering module, wherein the parallel filtering module includes a serial-to-parallel conversion module, a raised cosine shaping filter, a root raised cosine shaping filter, a Gaussian shaping filter and a third signal selector; The raised cosine shaping filter, the root raised cosine shaping filter and the Gaussian shaping filter are in parallel, and are respectively connected to the serial-to-parallel conversion module and the third signal selector, and the serial-to-parallel conversion module also has an interface directly connected to the third signal selector; The operations performed by the third signal selector in modulation 1 include: the third signal selector selects a signal having the same filtering type as the input signal from the signal input thereto and outputs the signal to obtain a first parallel IQ signal; The serial filtering of the I signal after interpolation upsampling is implemented by a serial filtering module, wherein the serial filtering module includes a raised cosine shaping filter, a root raised cosine shaping filter, a Gaussian shaping filter and a fourth signal selector; The raised cosine shaping filter, the root raised cosine shaping filter and the Gaussian shaping filter are in parallel and are all connected to the fourth signal selector, and the fourth signal selector also has an input end for receiving the I signal after interpolation upsampling; The operation performed by the fourth signal selector in modulation 2 includes: the fourth signal selector selects a signal having the same filtering type as the input signal from the signals input thereto and outputs the signal.

2. The baseband modulation system supporting supersampling and variable symbol rate according to claim 1, characterized in that: The input signal is obtained by the following method: Get m sequence, the m The sequence is input into the linear feedback shift register, and the linear feedback shift register is shifted in one clock cycle. N Get N bit register, so that the adder m registers and d The output of the register is N The calculation is repeated and the result of each calculation is assigned to the first register. After the calculation is completed, the registers output in parallel. N bits of PN sequence, the PN sequence being an input signal; N is the number of bits contained in a symbol in the modulation type of the input signal, N ≥1 and is an integer, m is the number of linear feedback shift registers, d for m The corresponding polynomial taps; Wherein, within one clock cycle, assigning the result of each calculation to the first register is completed by the following formula: r ( N : m -1) = r (0: m - N -1)； a ( N -1- n ) = r ( d -1- n ) ^ r ( m -1- n )， N ≤ d ≤ m ； r ( N -1- n ) = a ( N -1- n )； in, r ( N : m -1) indicates the N +1 register output value r ( N ) to m The output value of the register r ( m -1), r (0: m - N -1) indicates the output value of the first register r ( 0 ) to mN The output value of the register r ( m - N -1), a ( N -1- n )express r ( d -1- n )and r ( m -1- n ), r ( d -1- n ) indicates the d - n The output value of the register, r ( m -1- n ) indicates the m - n The output value of the register, ^ represents binary addition operation, r ( N -1- n ) indicates the N - n The output value of the register, n =0~ N -1, n is a count that increases by 1; Among them, in one clock cycle, the output contains N The PN sequence of bits is: y = r ( m -1- n )； in, y Represents PN sequence.

3. The baseband modulation system supporting supersampling and variable symbol rate according to claim 1, characterized in that: The conversion of the input signal into an IQ signal with an average energy of 1 is completed by a symbol mapping and normalization module, wherein the symbol mapping and normalization module includes a parallel 2ASK conversion module, a BPSK conversion module, a QPSK conversion module, an 8PSK conversion module, a 16QAM conversion module and a 32QAM conversion module, and a first signal selector connected after all the conversion modules; The 2ASK conversion module includes 2ASK symbol mapping and 2ASK bit width consistency, which are used to perform symbol mapping and normalization on the input signal of the modulation type 2ASK. The BPSK conversion module includes BPSK symbol mapping and BPSK energy normalization, which are used to perform symbol mapping and normalization on the input signal of the modulation type BPSK. The QPSK conversion module includes QPSK symbol mapping and QPSK energy normalization, which are used to perform symbol mapping and normalization on the input signal of the modulation type QPSK. The 8PSK conversion module includes 8PSK symbol mapping and 8PSK energy normalization, which are used to perform symbol mapping and normalization on the input signal of the modulation type 8PSK. The 16QAM conversion module includes 16QAM symbol mapping and 16QAM energy normalization, which are used to perform symbol mapping and normalization on the input signal of the modulation type 16QAM. The 32QAM conversion module includes 32QAM symbol mapping and 32QAM energy normalization, which are used to perform symbol mapping and normalization on the input signal of the modulation type 32QAM. The operations performed by the first signal selector in modulation one include: the first signal selector selects a signal having the same modulation type as the input signal from the signals input thereto and outputs the signal, thereby obtaining an IQ signal with an average energy of 1.

4. The baseband modulation system supporting supersampling and variable symbol rate according to claim 1, characterized in that: The conversion of the input signal into the I signal is implemented by a symbol mapping module, wherein the symbol mapping module includes a parallel 2FSK conversion module and a 4FSK conversion module, and a second signal selector connected after all the conversion modules; The 2FSK conversion module includes a 2FSK symbol mapping for performing symbol mapping on an input signal whose modulation type is 2FSK, and the 4FSK conversion module includes a 4FSK symbol mapping for performing symbol mapping on an input signal whose modulation type is 4FSK; The operation performed by the second signal selector in modulation 2 includes: the second signal selector selects a signal having the same modulation type as the input signal from the signals input thereto and outputs the signal to obtain an I signal.

5. The baseband modulation system supporting supersampling and variable symbol rate according to claim 1, characterized in that: The generating of second parallel IQ signals with different frequencies based on the frequency deviation of the input signal and the I signal after serial filtering comprises: Multiplying the I signal after serial filtering and the frequency deviation of the input signal to generate an output frequency, generating a phase increment value, calculating a frequency control word according to the absolute value of the output frequency, inputting the phase increment value and the frequency control word into a phase accumulation counter to generate a multi-channel phase corresponding to a second parallel IQ signal, setting a coordinate rotation digital computer based on the output frequency and the phase, and generating a multi-channel parallel second parallel IQ signal through the set coordinate rotation digital computer; The selecting one of the conjugated results to output comprises: selecting a corresponding serial signal output according to the positive or negative of the output frequency.

6. The baseband modulation system supporting supersampling and variable symbol rate according to claim 1, characterized in that: The bit rate of the input signal is expressed as: f b = Nf B ； in, f b is the bit rate of the input signal, N is the number of bits per symbol in the modulation type of the input signal, f B is the symbol rate; The symbol rate has a value range of: If no filter is used for filtering, the symbol rate range is f B ≤ f clk / 2, f clk is the clock frequency; If a filter is used for filtering, the symbol rate range is , R is the interpolation factor during the interpolation upsampling process, L is the value obtained by subtracting one from the coefficient length of the filter, [·] means rounding down, P f Indicates the amount of parallel data output when the signal is filtered. In modulation 2, P f = 1.

7. The baseband modulation system supporting supersampling and variable symbol rate according to claim 1, characterized in that: The expression of the coefficient group address of the filter used for the parallel filtering and the serial filtering is: A e = C 2 C 3 m f + C 3 m s + m r ； in, A e It is e Group filter coefficient group address, C 2 is the symbol rate quantity, C 3 is the roll-off factor number, m f Indicates that there are filters available to select C 1 filter types, in steps of 1, m f = 0~ C 1-1, m s Indicates that there is a filter that can be selected C 2 symbol rates, step size 1, m s = 0~ C 2-1, m r Indicates that there is a filter that can be selected C 3 roll-off factors, step size 1, m r = 0~ C 3-1; All filter coefficient group addresses are stored in a filter IP core, with a total of C 1 C 2 C There are three coefficient group addresses, and the total length of the filter coefficients is C 1 C 2 C 3( L +1).

8. A baseband modulation method supporting supersampling and variable symbol rate, characterized in that: The method is implemented by the system according to any one of claims 1 to 7, comprising: Get input signal; Inputting the input signal into modulation 1 and modulation 2 respectively; Modulation The modulation performed on an input signal includes: converting the input signal into an IQ signal with an average energy of 1, performing interpolation upsampling on the IQ signal, performing parallel filtering on the interpolation upsampling IQ signal to obtain a first parallel IQ signal, converting the first parallel IQ signal into a first serial IQ signal and outputting the signal; The modulation performed on the input signal by the modulation second includes: converting the input signal into an I signal, performing interpolation upsampling on the I signal, performing serial filtering on the interpolation upsampling I signal, generating a second parallel IQ signal of a different frequency based on the frequency deviation of the input signal and the I signal after serial filtering, converting the second parallel IQ signal into a second serial IQ signal, performing conjugation processing on the second serial IQ signal, and selecting one of the conjugation results for output; Based on the modulation type of the input signal acquired in advance, an output signal that is consistent with the modulation type of the input signal is selected from the output signals of modulation one and modulation two as the output signal of the baseband modulation system and output.

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