TTE analyzer and data analysis method

Abstract

The invention provides a TTE analyzer and a data analysis method. The method comprises the following steps: S1, initializing a main controller; s2, the upper computer data analysis software platform sends a communication link heartbeat command to the main controller, and the main controller sends an ACK message to the upper computer data analysis software platform after receiving the command; s3, the upper computer data analysis software platform sends a TTE data card port Link state query command to the main controller to obtain a Link state, and sends a TTE data card port Link state message to the upper computer data analysis software platform; s4, the upper computer data analysis software platform sends a command of starting to capture TTE data to the main controller, and the main controller analyzes the port number; s5, the upper computer data analysis software platform sends a TTE data uploading command to the main controller, and the main controller analyzes the port number; and S6, after the upper computer data analysis software platform receives the data, analyzing and analyzing TTE network data. According to the invention, monitoring, diagnosis and troubleshooting can be carried out on TTE network equipment, and protocol verification and real-time traffic capture are supported.

Description

Technical Field

[0001] The present invention relates to the field of TTE analysis and detection, and in particular to a TTE analyzer and a data analysis method. Background Art

[0002] Time-triggered Ethernet (TTE) is an advanced network communication technology that implements fault-tolerant distributed network synchronization by complying with the SAE AS6802 protocol. This technology enables traditional Ethernet to not only handle high-real-time data transmission, but also support mixed service triggering, greatly improving the reliability and performance of the network. TTE networks are particularly suitable for building open, highly reliable, and high-performance critical systems.

[0003] Although TTE technology has significant advantages in network real-time and reliability, in practical applications, there are still some technical challenges when using TTE analyzers for network behavior analysis, especially in circuit design and data capture. Therefore, it is of great practical significance to develop a TTE analyzer that can monitor, diagnose and troubleshoot TTE network equipment and support protocol verification and real-time traffic capture. Summary of the invention

[0004] The present invention aims to at least solve the technical problems existing in the prior art, and in particular innovatively proposes a TTE analyzer and a data analysis method.

[0005] In order to achieve the above-mentioned object of the present invention, the present invention provides a TTE analyzer and a data analysis method, comprising the following steps:

[0006] S1, main controller initialization;

[0007] S2, the host computer data analysis software platform sends a communication link heartbeat command to the main controller every 1 second. After receiving the command, the main controller sends an ACK message to the host computer data analysis software platform to determine whether the communication link is normal and display the communication link status on the software platform interface;

[0008] S3, the host computer data analysis software platform sends a TTE data card port Link status query command to the main controller every 1 second. After receiving the command, the main controller reads the port register 8-11 bits, obtains the Link status, and sends the TTE data card port Link status message to the host computer data analysis software platform. The host computer data analysis software platform interface displays the TTE data card port Link status;

[0009] S4, the host computer data analysis software platform sends a command to start capturing TTE data to the main controller. After receiving the command, the main controller parses out the port number;

[0010] S5, the host computer data analysis software platform sends a TTE data upload command to the main controller. After receiving the command, the main controller parses out the port number;

[0011] S6, after receiving the data, the host computer data analysis software platform analyzes and interprets the TTE network data.

[0012] Further, the determination of whether the communication link is normal is obtained by:

[0013] S201, determining the response speed of the communication link:

[0014] First, collect relevant parameters of the wireless communication link, including signal strength, bit error rate, and delay;

[0015] Then, it is determined whether the delay is higher than the set first delay threshold; if the delay is higher than the set first delay threshold, it is determined to be at the third level response speed;

[0016] If the delay is lower than the set first delay threshold but higher than the set second delay threshold, where the value of the first delay threshold is greater than the second delay threshold; then determine whether the signal strength is higher than the first signal strength threshold, if the signal strength is higher than the first signal strength threshold and the bit error rate is lower than the bit error rate threshold, it is determined to be a second-level response speed; if the signal strength is lower than the first signal strength threshold but higher than the second signal strength threshold, it is determined to be a third-level response speed; where the first signal strength threshold is greater than the second signal strength threshold;

[0017] If the delay is lower than the set second delay threshold, and the signal strength is lower than the first signal strength threshold but higher than the second signal strength threshold, and the bit error rate is lower than the bit error rate threshold, it is determined to be a secondary response speed; if the delay is lower than the set second delay threshold, and the signal strength is higher than the first signal strength threshold, and the bit error rate is lower than the bit error rate threshold, it is determined to be a primary response speed;

[0018] The above method uses latency as the main indicator of response speed. When the signal strength and bit error rate are within an acceptable range, a lower latency means a faster response speed. The above method is used to evaluate the response speed of the link, thereby evaluating the link performance.

[0019] Since step S2 has the following 4 delays, there are 4 response speeds for each execution;

[0020] Sending delay: The time point when the host computer sends the heartbeat command.

[0021] Transmission delay: The time required for the heartbeat command to be transmitted from the host computer to the main controller.

[0022] Processing delay: The time it takes for the master controller to process the heartbeat command and generate an ACK message after receiving it.

[0023] ACK sending delay: the time point when the main controller sends an ACK message back to the host computer.

[0024] ACK transmission delay: the time required for the ACK message to be transmitted from the main controller back to the host computer;

[0025] S202, determine the monitoring communication cycle:

[0026] S202-1, record the timestamp of each time the upper computer data analysis software platform sends the communication link heartbeat command to the main controller in step S2; record it as the sending time; and the timestamp of the TTE network data analyzed and parsed in S6; record it as the corresponding time; the difference between these two timestamps is the communication cycle;

[0027] S202-2, determine whether the command at the N-1th sending time is the same as the command at the Nth sending time. If they are the same, record the timestamp of the Nth analysis and parsing of the TTE network data. At this time, the communication cycle is the timestamp from the N-1th sending time to the Nth analysis and parsing of the TTE network data.

[0028] S203, recording the number of response speeds at each level in each cycle, and using this to determine whether the communication link is normal: if there is no third-level response speed within a monitoring communication cycle, and the number of second-level response speeds does not exceed the second-level response speed number threshold, then the communication link is normal.

[0029] Further, step S4 includes:

[0030] S4-1, write the port number to Bit0-1 of the port register, write 01 to Bit4-5 to start the port data capture function, the TTE data card starts to capture TTE network data, and stores the captured data in the FPGA DDR;

[0031] S4-2, the main controller sends a command ACK message to start capturing TTE data to the host computer data analysis software platform;

[0032] S4-3, the host computer data analysis software platform sends a stop capturing TTE data command to the main controller. After receiving the command, the main controller writes the port register Bit4-5 to 00, and the TTE data card stops data capturing;

[0033] S4-4, the main controller sends a partial stop ACK message to the host computer data analysis software platform.

[0034] Further, step S5 includes:

[0035] S5-1, write the port number to Bit0-1 of the port register, write 01 to Bit6-7 to start the port data upload function, and the TTE data card writes the data stored in the FPGADDR into the shared memory;

[0036] S5-2, the main controller sends a TTE data upload start command ACK message to the host computer data analysis software platform;

[0037] S5-3, after the TTE data card uploads the captured data, the port register Bit6-7 is written with 00, and an interrupt is sent to the main controller;

[0038] S5-4, after receiving the interrupt, the main controller reads the status register bit3 1, which is 1, indicating that the data FPGA TTE data card FPGA writes the collected TTE data into the shared memory area, and the main controller starts uploading the data in the shared memory to the host computer data analysis software platform. After receiving the data, the host computer data analysis software platform sends an ACK message to the main controller;

[0039] S5-5, after uploading the data, the main controller sets the status register bit31 to 0;

[0040] S5-6, the main controller records the data in the shared memory to the SATA disk.

[0041] Furthermore, the TTE analyzer and data analysis method are implemented based on the TTE analyzer, and the TTE analyzer includes:

[0042] Data processing circuit board, including T1042 data processing module, PEX8648 switching module, DB9 serial port, RJ45 Ethernet interface, VPX connector, clock management module and power management module;

[0043] Data acquisition circuit board, including FPGA module, LVDS switch, SFP network transmission interface, VPX connector, DDR3, clock management module and power management module;

[0044] Back panel;

[0045] Power board;

[0046] The data processing circuit board, data acquisition circuit board and power board are connected to the backplane through the VPX connector, and data exchange is carried out on the backplane. The external network data enters the FPGA module of the data acquisition circuit board through the SFP interface, and then the FPGA module transmits the network data to the VPX connector through the PCIE X4 interface. Then the network data enters the PEX8648 switching module of the data processing circuit board from the VPX connector. The PEX8648 switching module transmits the network data to the T1042 data processing module, and the T1042 data processing module transmits the network data to the RJ45 network port. Finally, the RJ45 network port transmits the network data to the host computer.

[0047] The data processing circuit board includes a PEX8648 switching module connected to the VPX connector via a 4-way PCIE X4 interface, the PEX8648 switching module connected to the T1042 data processing module via a 1-way PCIE X4 interface, the T1042 data processing module connected to the host computer via an RJ45 Ethernet interface, and receiving control and debugging signals via a DB9 serial port;

[0048] Among them, the data acquisition circuit board, the power management module is connected to the processor D4 and the FPGA, the clock management module is connected to the FPGA module, the FPGA module is connected to the DDR3 memory, the FPGA module is connected to the VPX connector through the PCIE X4 interface, the FPGA module is connected to the VPX connector through three sets of LVDS X3 switches, the FPGA module is connected to the indicator module and the button module through the GPIO interface, the FPGA module is connected to the JTAG interface, the FPGA module is connected to the SFP interface module through the LVDS X4 switch, and the SFP X4 interface is connected to the external network;

[0049] The power management module converts the voltage provided by the power board into the voltage required by each module.

[0050] Furthermore, the data processing circuit board and the data acquisition circuit board include a power management module, wherein the power management module includes:

[0051] Multiple input power interfaces and capacitor filtering networks to provide stable voltage input;

[0052] Buck regulator chip for voltage regulation and clock synchronization;

[0053] A power good indication circuit is used to monitor the power status;

[0054] The voltage output pin VOUT10 of the buck regulator chip D12, the voltage output pin VOUT11 of the buck regulator chip D12 and the voltage output pin VOUT12 of the buck regulator chip D12 output the power supply voltage VCC1.8V and are connected to the first end of the capacitor C279 and the first end of the capacitor C282, the second end of the capacitor C279 and the second end of the capacitor C282 are grounded, the feedback pin FB1 of the buck regulator chip D12 is connected to the first end of the resistor R144, the second end of the resistor R144 is grounded, the voltage tracking and soft start pin TRACK|SS1 of the buck regulator chip D12 is connected to the first end of the capacitor C276, the second end of the capacitor C276 is grounded, the power good indication pin PGOOD1 of the buck regulator chip D12 is connected to the first end of the resistor R139, and the second end of the resistor R139 is connected to the internal power pin 1NTVCC1 of the buck regulator chip D12;

[0055] The voltage output pin VOUT20 of the buck regulator chip D12, the voltage output pin VOUT21 of the buck regulator chip D12 and the voltage output pin VOUT22 of the buck regulator chip D12 output the power supply voltage VCC1.5V and are connected to the first end of the capacitor C280 and the first end of the capacitor C283, the second end of the capacitor C280 and the second end of the capacitor C283 are grounded, the feedback pin FB2 of the buck regulator chip D12 is connected to the first end of the resistor R145, the second end of the resistor R145 is grounded, the voltage tracking and soft start pin TRACK|SS2 of the buck regulator chip D12 is connected to the first end of the capacitor C277, the second end of the capacitor C277 is grounded, the power good indication terminal PGOOD2 of the buck regulator chip D12 is connected to the first end of the resistor R140, and the second end of the resistor R140 is connected to the internal power pin INTVCC2 of the buck regulator chip D12;

[0056] The power good indication terminal PGOOD1 of the buck voltage regulator chip D12 is connected to the enable terminal RUN2 of the buck voltage regulator chip D12;

[0057] The voltage input pin VIN10 of the buck voltage regulator chip D12, the voltage input pin VIN11 of the buck voltage regulator chip D12, and the voltage input pin SVIN1 of the buck voltage regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C272, the second end of the capacitor C272 is grounded, and the power good indication terminal PGOOD3 of the buck voltage regulator chip D12 and the power good indication terminal PGOOD4 of the buck voltage regulator chip D12 are connected to the enable terminal RUN1 of the buck voltage regulator chip D12;

[0058] The voltage input pin VIN20 of the buck voltage regulator chip D12, the voltage input pin VIN21 of the buck voltage regulator chip D12, and the voltage input pin SVIN2 of the buck voltage regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C273, and the second end of the capacitor C273 is grounded;

[0059] An internal power pin INTVCC1 of the buck regulator chip D12 is connected to an operation mode configuration pin MODE1 of the buck regulator chip D12, and an internal power pin INTVCC2 of the buck regulator chip D12 is connected to an operation mode configuration pin MODE2 of the buck regulator chip D12.

[0060] The voltage output pin VOUT30 of the buck regulator chip D12, the voltage output pin VOUT31 of the buck regulator chip D12, the voltage output pin VOUT32 of the buck regulator chip D12, the voltage output pin VOUT40 of the buck regulator chip D12, the voltage output pin VOUT41 of the buck regulator chip D12 and the voltage output pin VOUT42 of the buck regulator chip D12 output the power supply voltage VCC1V VINT and are connected to the first end of the capacitor C281 and the first end of the capacitor C284, the second end of the capacitor C281 and the second end of the capacitor C284 are grounded, the feedback pin FB3 of the buck regulator chip D12 and the feedback pin FB4 of the buck regulator chip D12 are connected to the first end of the resistor R143 and the first end of the resistor R146, the second end of the resistor R143 and the second end of the resistor R146 are grounded, the voltage tracking and soft start pin TRACK|SS3 of the buck regulator chip D12 and the voltage tracking and soft start pin TRACK|SS3 of the buck regulator chip D12 The start pin TRACK|SS4 is connected to the first end of the capacitor C278, the second end of the capacitor C278 is grounded, the power good indication terminal PGOOD3 of the buck voltage regulator chip D12 is connected to the first end of the resistor R141, the second end of the resistor R141 is connected to the internal power pin INTVCC3 of the buck voltage regulator chip D12, the power good indication terminal PGOOD4 of the buck voltage regulator chip D12 is connected to the first end of the resistor R142, and the second end of the resistor R142 is connected to the internal power pin INTVCC4 of the buck voltage regulator chip D12;

[0061] The voltage input pin VIN30 of the buck regulator chip D12, the voltage input pin VIN31 of the buck regulator chip D12, the voltage input pin SVIN3 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, the voltage input pin VIN40 of the buck regulator chip D12, and the voltage input pin VIN41 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, and the voltage input pin VIN40 of the buck regulator chip D12 and the voltage input pin VIN42 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274. 1. The voltage input pin SVIN4 of the buck regulator chip D12 and the enable pin RUN4 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C275, the second end of the capacitor C275 is grounded, the internal power pin INTVCC3 of the buck regulator chip D12 is connected to the working mode configuration pin MODE3 of the buck regulator chip D12, and the internal power pin 1NTVCC4 of the buck regulator chip D12 is connected to the working mode configuration pin MODE4 of the buck regulator chip D12;

[0062] Ground pin SGND of buck regulator chip D12, ground pin GND 0 of buck regulator chip D12, ground pin GND 1 of buck regulator chip D12, ground pin GND 2 of buck regulator chip D12, ground pin GND 3 of buck regulator chip D12, ground pin GND 4 of buck regulator chip D12, ground pin GND 5 of buck regulator chip D12, ground pin GND 6 of buck regulator chip D12, ground pin GND 7 of buck regulator chip D12, ground pin GND 8 of buck regulator chip D12, ground pin GND-9 of buck regulator chip D12, ground pin GND 10 of buck regulator chip D12, ground pin GND 11 of buck regulator chip D12, ground pin GND 12 of buck regulator chip D12 13. Ground pin GND 14. Ground pin GND15. Ground pin GND 16. Ground pin GND 17. Ground pin GND 18. Ground pin GND 19. Ground pin GND 20. of buck voltage regulator chip D12 are all grounded.

[0063] Further, the data processing circuit board includes a clock management module;

[0064] The control pin OE of the clock generator U3 is connected to the first end of the resistor R102, the second end of the resistor R102 is connected to the second end of the inductor L1, the first end of the capacitor C53 and the voltage input pin VDD of the clock generator U3, the first end of the inductor L1 is connected to the input voltage VCC3.3V, the second end of the capacitor C53 is grounded, the clock signal output pin CLK of the clock generator U3 is connected to the first end of the capacitor C58, the second end of the capacitor C58 is connected to the clock input pin CLK0 of the clock distribution chip D1, the clock signal output pin CLK* of the clock generator U3 is connected to the first end of the capacitor C95, the second end of the capacitor C95 is connected to the clock input pin CLK0* of the clock distribution chip D1, and the ground pin GND of the clock generator U3 is grounded;

[0065] The clock input pin CLK0 of the clock distribution chip D1 and the clock input pin CLK0* of the clock distribution chip D1 are connected to the clock signal output pin CLK of the clock generator U3 and the clock signal output pin CLK* of the clock generator U3 to receive the synchronous differential signal from the clock generator U3, the first end of the resistor R86 is connected to the input voltage VCC3.3V, the second end of the resistor R86 is connected to the first end of the resistor R87 and the clock input pin CLK0 of the clock distribution chip D1, the second end of the resistor R87 is grounded, the first end of the resistor R88 is connected to the input voltage VCC3.3V, the second end of the resistor R88 is connected to the first end of the resistor R89 ​​and the clock input pin CLK0* of the clock distribution chip D1, and the second end of the resistor R89 ​​is grounded;

[0066] The first end of the resistor R90 is connected to the clock input pin CLK1 of the clock distribution chip D1, and the second end of the resistor R90 is grounded. The first end of the resistor R101 is connected to the clock input pin CLK1* of the clock distribution chip D1, and the second end of the resistor R101 is grounded. The first end of the resistor R62 is connected to the clock selection pin CLK SET of the clock distribution chip D1, and the second end of the resistor R62 is grounded. The clock selection pin CLK SET of the clock distribution chip D1 is connected to the clock input pin CLK SET of the clock distribution chip D1. SET is connected to the clock selection signal, the first end of the capacitor C54, the first end of the capacitor C55, and the first end of the capacitor C56 are all connected to the input voltage VCC3.3V, the second end of the capacitor C54, the second end of the capacitor C55, and the second end of the capacitor C56 are all grounded, the first end of the capacitor C54 is also connected to the voltage input pin VCC0 of the clock distribution chip D1, the voltage input pin VCC1 of the clock distribution chip D1, the voltage input pin VCC2 of the clock distribution chip D1, the voltage input pin VCC3 of the clock distribution chip D1, and the voltage input pin VCC4 of the clock distribution chip D1, and the voltage pin VEE of the clock distribution chip D1 is grounded;

[0067] A first end of the resistor R103 is connected to a signal output pin Q0 of the clock distribution chip D1 and a first end of the capacitor C18, a second end of the resistor R103 is grounded, and a second end of the capacitor C18 is connected to a VPX connector, a first end of the resistor R104 is connected to a signal output pin Q0* of the clock distribution chip D1 and a first end of the capacitor C60, a second end of the resistor R104 is grounded, and a second end of the capacitor C60 is connected to a VPX connector, a first end of the resistor R1 is connected to a signal output pin Q1 of the clock distribution chip D1 and a first end of the capacitor C21, a second end of the resistor R1 is grounded, and a second end of the capacitor C21 is connected to the VPX connector, a first end of the resistor R8 is connected to a signal output pin Q1* of the clock distribution chip D1 and a first end of the capacitor C61, a second end of the resistor R8 is grounded, and a second end of the capacitor C61 is connected to the VPX connector, A first end of the resistor R21 is connected to a signal output pin Q2 of the clock distribution chip D1 and a first end of the capacitor C38, a second end of the resistor R21 is grounded, and a second end of the capacitor C38 is connected to a VPX connector, a first end of the resistor R35 is connected to a signal output pin Q2* of the clock distribution chip D1 and a first end of the capacitor C62, a second end of the resistor R35 is grounded, and a second end of the capacitor C62 is connected to the VPX connector, a first end of the resistor R36 is connected to a signal output pin Q3 of the clock distribution chip D1 and a first end of the capacitor C44, a second end of the resistor R36 is grounded, and a second end of the capacitor C44 is connected to the VPX connector, a first end of the resistor R57 is connected to a signal output pin Q3* of the clock distribution chip D1 and a first end of the capacitor C17, a second end of the resistor R57 is grounded, and a second end of the capacitor C17 is connected to the VPX connector;

[0068] The second end of the capacitor C18 is connected to the first end of the resistor R58 and the first end of the resistor R59, the second end of the resistor R58 is connected to the input voltage VCC3.3V, and the second end of the resistor R59 is grounded. The second end of the capacitor C60 is connected to the first end of the resistor R60 and the first end of the resistor R61, the second end of the resistor R60 is connected to the input voltage VCC3.3V, and the second end of the resistor R61 is grounded. The second end of the capacitor C21 is connected to the first end of the resistor R63 and the first end of the resistor R64, the second end of the resistor R63 is connected to the input voltage VCC3.3V, and the second end of the resistor R64 is grounded. The second end of the capacitor C61 is connected to the first end of the resistor R66 and the first end of the resistor R67, the second end of the resistor R66 is connected to the input voltage VCC3.3V, and the second end of the resistor R67 is grounded. The second end of capacitor C38 is connected to the first end of resistor R68 and the first end of resistor R69, the second end of resistor R68 is connected to the input voltage VCC3.3V, and the second end of resistor R69 is grounded. The second end of capacitor C62 is connected to the first end of resistor R70 and the first end of resistor R72, the second end of resistor R70 is connected to the input voltage VCC3.3V, and the second end of resistor R72 is grounded. The second end of capacitor C44 is connected to the first end of resistor R73 and the first end of resistor R74, the second end of resistor R73 is connected to the input voltage VCC3.3V, and the second end of resistor R74 is grounded. The second end of capacitor C17 is connected to the first end of resistor R75 and the first end of resistor R76, the second end of resistor R75 is connected to the input voltage VCC3.3V, and the second end of resistor R76 is grounded.

[0069] Furthermore, the data processing circuit board includes a T1042 data processing module,

[0070] In the above-mentioned T1042 data processing module, the first end of capacitor C88, the first end of capacitor C89, the first end of capacitor C96, the first end of capacitor C98, the first end of capacitor C100, the first end of capacitor C102, the first end of capacitor C105, the first end of capacitor C108 and the first end of capacitor C111 are connected to the input voltage VCC3.3V and the voltage input pin VCC of processor IC1, the second end of capacitor C88, the second end of capacitor C89, the second end of capacitor C96, the second end of capacitor C98, the second end of capacitor C100, the second end of capacitor C102, the second end of capacitor C105, the second end of capacitor C108 and the second end of capacitor C111 are grounded and connected to the voltage input pin VCC of processor IC1, the first end of capacitor C106, the first end of capacitor C109 and the first end of capacitor C112 are connected to the input voltage VCC1 .8V is connected to the voltage input pin VCCQ of the processor IC1, the second end of the capacitor C106, the second end of the capacitor C109 and the second end of the capacitor C112 are grounded, the first end of the resistor R152 is connected to the input voltage VCC1.2V, the second end is connected to the first end of the capacitor C90, the first end of the capacitor C97, the first end of the capacitor C99, the first end of the capacitor C101, the first end of the capacitor C103, the first end of the capacitor C107, the first end of the capacitor C110, the first end of the capacitor C113, the voltage input pin VDDC of the processor IC1 and the voltage input pin VDD of the processor IC1, the second end of the capacitor C90, the second end of the capacitor C97, the second end of the capacitor C99, the second end of the capacitor C101, the second end of the capacitor C103, the second end of the capacitor C107, the second end of the capacitor C110 and the second end of the capacitor C113 are grounded;

[0071] A first SATA power supply pin SATA VDD of the processor IC1 is connected to a first end of a capacitor C120, a first end of a capacitor C122, a first end of a capacitor C124, and a first end of an inductor L11, a second end of the capacitor C120, a second end of the capacitor C122, and a second end of the capacitor C124 are grounded, and a second end of the inductor L11 is connected to an input voltage VCC1.2V;

[0072] The second SATA power supply pin SATA VDD of the processor IC1 is connected to the first end of the capacitor C121, the first end of the capacitor C123, the first end of the capacitor C125 and the first end of the inductor L12, the second end of the capacitor C121, the second end of the capacitor C123 and the second end of the capacitor C125 are all grounded, and the second end of the inductor L12 is connected to the input voltage VCC1.2V;

[0073] The SATA voltage pin SATA VSS of the processor IC1 is grounded, the sleep signal pin DEVSLP of the processor IC1 is connected to the first end of the resistor R155, the second end of the resistor R155 is grounded, when the pin receives the sleep signal, the device will enter the low power mode, the crystal oscillator output pin XTAL OUT of the processor IC1 and the crystal oscillator input pin XTAL IN of the processor IC1 are connected to the external crystal oscillator circuit, the power reset pin PWR RESETN of the processor IC1 is connected to the first end of the resistor R158, the second end of the resistor R158 is connected to the external reset signal, and the power reset pin PWR RESETN of the processor IC1 is connected to the external SATA power reset signal;

[0074] The spare pin NC34 of the processor IC1 is connected to the LED indicator light, and the spare pin NC37 of the processor IC1 and the spare pin NC38 of the processor IC1 are connected to the SATA device for receiving and sending control commands and data of the SATA device. The processor IC1 is the main controller.

[0075] Further, the data processing circuit board includes a PEX8648 switching module, and the PEX8648 switching module includes: a switching chip, a multi-channel PCIE X4 interface;

[0076] The PEX8648 switching module includes a switching chip U2, 4 PCIE X4 interfaces and a single PCIE X4 interface, wherein a first end of the 4 PCIE X4 interface is connected to the VPX connector, a second end of the 4 PCIE X4 interface is connected to the switching chip U2, a first end of the single PCIE X4 interface is connected to the switching chip, and a second end of the single PCIE interface is connected to the T1042 data processing module;

[0077] The above-mentioned PEX8648 switching module includes a network transmission indication pin of the switching chip U2 connected to an LED lamp holder to indicate the network transmission status.

[0078] Furthermore, the data processing circuit board includes an RJ45 network port module, and the RJ45 network port module includes an Ethernet interface, a network transmission indicator light, and a capacitor filter network;

[0079] The RJ45 network port module includes network signal transmission pins 1 to 8 of the Ethernet interface ETH0 for Gigabit Ethernet data transmission, an indicator light pin 9 of the Ethernet interface ETH0 receives a network activity signal GBE0ACT N, and when data is transmitted, the LED light is on, the indicator light pin 9 of the Ethernet interface ETH0 is connected to the first end of the capacitor C6, the second end of the capacitor C6 is grounded, the indicator light pin 10 of the Ethernet interface ETH0 is connected to the first end of the resistor R9, and the second end of the resistor R9 is connected to the input voltage LED 2V5;

[0080] The indicator light pin 11 of the Ethernet interface ETH0 receives the network connection signal LINK1000N. When the link is successful, the LED lights up. The indicator light pin 11 of the Ethernet interface ETH0 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is grounded. The indicator light pin 12 of the Ethernet interface ETH0 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the input voltage LED 2V5.

[0081] Further, the data processing circuit board includes a VPX connector module;

[0082] The first end of the above-mentioned VPX connector module is connected to the PEX8648 switching module of the data processing circuit board through a 4-way PCIE X4 interface, the second end of the VPX connector module is connected to the four data acquisition circuit boards through four single-way PCIE X4 interfaces, and the power transmission end of the VPX connector module is connected to the power board.

[0083] Furthermore, the data processing circuit board is connected to the host computer through the RJ45 network port, and is connected to the backplane through the VPX connector. The backplane interacts with the data acquisition circuit board, and the data acquisition circuit board is connected to the TTE network through the SFP network transmission interface.

[0084] Furthermore, the data acquisition circuit board includes a clock management module, the clock management module includes an enable pin OE of a clock generator U1 connected to a first end of a resistor R114, a second end of the resistor R114 connected to an input voltage VCC3.3V, a voltage input pin VDD of the clock generator U1 connected to a first end of a capacitor C244 and a second end of an inductor L5, the second end of the capacitor C244 is grounded, a first end of the inductor L5 is connected to the input voltage VCC3.3V, a clock output pin CLK of the clock generator U1 is connected to an FPGA module and a first end of a capacitor C255, a second end of the capacitor C255 is connected to a first end of a resistor R126, The first end of resistor R127, the first end of resistor R171 and the FPGA module are connected, the second end of resistor R126 is connected to the input voltage VCC1.5V, the second end of resistor R127 is grounded, the second end of resistor R171 is connected to the second end of capacitor C317, the clock output pin CLK* of clock generator U1 is connected to the first end of capacitor C317, the second end of capacitor C137 is connected to the first end of resistor R130, the first end of resistor R155 and the FPGA module, the second end of resistor R130 is connected to the input voltage VCC1.5V, the second end of resistor R155 is grounded, and the ground pin GND of clock generator U1 is grounded.

[0085] Furthermore, the data acquisition circuit board includes an FPGA module, the FPGA module includes a processor chip D4, wherein the GPIO pin of the processor chip D4 is connected to the LED indicator light, the GTX pin of the processor chip D4 is connected to the SFP interface through an LVDS switch, the PCIE X4 interface of the processor chip D4 is connected to the data processing circuit board through a VPX connector, the processor chip D4 is connected to the VPX connector through the LVDS switch, and is connected to other data acquisition circuit boards through the VPX connector.

[0086] Furthermore, the data acquisition circuit board includes two 2GB DDR3 and two 256Mb FLASH, one FLASH is used as the program storage of FPGA, and the other is used to store network parameters.

[0087] Furthermore, the data acquisition circuit board includes an SFP module interface connected to the LVD X4 switch via an Ethernet transmission line, the LVD X4 switch is connected to the FPGA module, and the SFP module is connected to the external network to collect TTE network signals.

[0088] Furthermore, the data acquisition circuit board includes a VPX connector, the FPGA module is connected to the VPX connector via a PCIE X4 interface, and data is exchanged with the data processing circuit board via the VPX connector to achieve high-speed data communication with the host system.

[0089] Furthermore, the data acquisition circuit board includes an indicator light module and a button module, both of which are connected to the FPGA module through a GPIO port, wherein the indicator light and button module include an LED indicator light and a button to display system status and user input control.

[0090] In summary, due to the adoption of the above technical solution, the present invention can monitor, diagnose and troubleshoot TTE network equipment, and support protocol verification and real-time traffic capture.

[0091] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0093] Figure 1 It is a schematic flow diagram of the method of the present invention.

[0094] Figure 2 It is a schematic diagram of the circuit system of the present invention.

[0095] Figure 3 It is a hardware block diagram of the present invention.

[0096] Figure 4 It is a schematic diagram of the data processing circuit board.

[0097] Figure 5 Figure 1 is a schematic diagram of the data acquisition circuit board.

[0098] Figure 6 This is a partial interface circuit diagram of the backplane.

[0099] Figure 7 This is the circuit diagram of the PEX8648 switching module.

[0100] Figure 8 This is the circuit diagram of the T1042 data processing module.

[0101] Fig. 9 Here is a schematic diagram of the VPX connector.

[0102] Fig.10 This is the circuit diagram of the RJ45 network port.

[0103] Fig.11 This is the circuit diagram of the DB9 serial port.

[0104] Fig.12 This is the circuit diagram of the processor chip in the FPGA module.

[0105] Fig.13It is the circuit diagram of LVDS switch.

[0106] Fig.14 It is the circuit diagram of the SFP network transmission interface.

[0107] Fig.15 This is the circuit diagram of the clock management module.

[0108] Fig.16 This is the circuit diagram of the power management module.

[0109] Fig.17 is the circuit diagram of the clock generator U3. DETAILED DESCRIPTION

[0110] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0111] The present invention provides a TTE analyzer and a data analysis method, such as Figure 1 As shown:

[0112] S1, the main controller (processor IC1) is initialized, corresponding to step 1 of the flowchart;

[0113] S2, the host computer data analysis software platform sends a communication link heartbeat command to the main controller every 1 second. After receiving the command, the main controller sends an ACK message to the host computer data analysis software platform to determine whether the communication link is normal and display the communication link status on the software platform interface, corresponding to step 2 of the flowchart;

[0114] S3, the host computer data analysis software platform sends a TTE data card port Link status query command to the main controller every 1 second. After receiving the command, the main controller reads the port register 8-11 bits, obtains the Link status, and sends the TTE data card port Link status message to the host computer data analysis software platform. The host computer data analysis software platform interface displays the TTE data card port Link status, corresponding to step 3 of the flowchart;

[0115] S4, the host computer data analysis software platform sends a command to start capturing TTE data to the main controller. After receiving the command, the main controller parses out the port number; corresponding to step 4 of the flowchart.

[0116] S4-1, write the port number to Bit0-1 of the port register, write 01 to Bit4-5 to start the port data capture function, the TTE data card starts to capture TTE network data, and stores the captured data in the FPGA DDR, corresponding to step 4-1 of the flowchart;

[0117] S4-2, the main controller sends a command ACK message to start capturing TTE data to the host computer data analysis software platform, corresponding to step 4-2 of the flowchart;

[0118] S4-3, the host computer data analysis software platform sends a stop capturing TTE data command to the main controller. After receiving the command, the main controller writes the port register Bit4-5 to 00, and the TTE data card stops capturing data. The corresponding process Figure 4-3 , 4-4;

[0119] S4-4, the main controller sends a partial stop ACK message to the host computer data analysis software platform, corresponding to step 4-5 of the flowchart;

[0120] S5, the host computer data analysis software platform sends a TTE data upload command to the main controller. After receiving the command, the main controller parses the port number, corresponding to step 5 of the flowchart;

[0121] S5-1, write the port number to Bit0-1 of the port register, write 01 to Bit6-7 to start the port data upload function, and the TTE data card writes the data stored in the FPGADDR into the shared memory, corresponding to step 5-1 of the flowchart;

[0122] S5-2, the main controller sends a start TTE data upload command ACK message to the host computer data analysis software platform, corresponding to step 5-2 of the flowchart;

[0123] S5-3, after the TTE data card uploads the captured data, the port register Bit6-7 is written with 00, and an interrupt is sent to the main controller, corresponding to step 5-3 of the flowchart;

[0124] S5-4, after receiving the interrupt, the main controller reads the status register bit31, which is 1, indicating that the data FPGA TTE data card FPGA writes the collected TTE data into the shared memory area, and the main controller starts uploading the data in the shared memory to the host computer data analysis software platform. After receiving the data, the host computer data analysis software platform sends an ACK message to the main controller, corresponding to steps 5-4 and 5-5 of the flowchart;

[0125] S5-5, after uploading the data, the main controller sets the status register bit31 to 0;

[0126] S5-6, the main controller records the data in the shared memory to the SATA disk, corresponding to step 5-6 of the flowchart.

[0127] S6, after receiving the data, the host computer data analysis software platform analyzes and parses the TTE network data. Figure 6 .

[0128] The TTE data card FPGA register design is shown in Table 1:

[0129] Table 1

[0130]

[0131] Wherein, judging whether the communication link is normal in step S2 includes:

[0132] S201, determining the response speed of the communication link:

[0133] First, collect relevant parameters of the wireless communication link, including signal strength, bit error rate, and delay;

[0134] Then, it is determined whether the delay is higher than the set first delay threshold; if the delay is higher than the set first delay threshold, it is determined to be at the third level of response speed. This may be caused by poor channel conditions, interference or equipment failure. It is necessary to conduct in-depth analysis of the link to find out the cause of the high bit error rate.

[0135] If the delay is lower than the set first delay threshold but higher than the set second delay threshold, where the value of the first delay threshold is greater than the second delay threshold; then determine whether the signal strength is higher than the first signal strength threshold, if the signal strength is higher than the first signal strength threshold and the bit error rate is lower than the bit error rate threshold, it is determined to be a second-level response speed; if the signal strength is lower than the first signal strength threshold but higher than the second signal strength threshold, it is determined to be a third-level response speed; where the first signal strength threshold is greater than the second signal strength threshold;

[0136] If the delay is lower than the set second delay threshold, and the signal strength is lower than the first signal strength threshold but higher than the second signal strength threshold, and the bit error rate is lower than the bit error rate threshold, it is determined to be a secondary response speed; if the delay is lower than the set second delay threshold, and the signal strength is higher than the first signal strength threshold, and the bit error rate is lower than the bit error rate threshold, it is determined to be a primary response speed;

[0137] The above method uses latency as the main indicator of response speed. When the signal strength and bit error rate are within an acceptable range, a lower latency means a faster response speed. The above method is used to evaluate the response speed of the link, thereby evaluating the link performance.

[0138] Since step S2 has the following 4 delays, there are 4 response speeds for each execution;

[0139] Sending delay: The time point when the host computer sends the heartbeat command.

[0140] Transmission delay: The time required for the heartbeat command to be transmitted from the host computer to the main controller.

[0141] Processing delay: The time it takes for the master controller to process the heartbeat command and generate an ACK message after receiving it.

[0142] ACK sending delay: the time point when the main controller sends an ACK message back to the host computer.

[0143] ACK transmission delay: The time required for the ACK message to be transmitted from the main controller back to the host computer.

[0144] Among them, the first delay threshold, the second delay threshold, the first signal strength threshold, the second signal strength threshold, and the bit error rate threshold are set initially, and are dynamically adjusted during the response speed analysis process to adapt to changes in the link status.

[0145] S202, determine the monitoring communication cycle:

[0146] The communication cycle is the entire process starting from heartbeat detection (step S2), status query (step S3), start of data capture (step S4), data upload (step S5), until data analysis is completed (step S6).

[0147] S202-1, record the timestamp of each time the upper computer data analysis software platform sends the communication link heartbeat command to the main controller in step S2; record it as the sending time; and the timestamp of the TTE network data analyzed and parsed in S6; record it as the corresponding time; the difference between these two timestamps is the communication cycle;

[0148] S202-2, determine whether the command at the N-1th sending time is the same as the command at the Nth sending time. If they are the same, record the timestamp of the Nth analysis and parsing of the TTE network data. At this time, the communication cycle is the timestamp from the N-1th sending time to the Nth analysis and parsing of the TTE network data.

[0149] S203, record the number of response speeds at each level in each cycle, and use this to determine whether the communication link is normal: if there is no third-level response speed within a monitoring communication cycle, and the number of second-level response speeds does not exceed the second-level response speed number threshold, it means that the communication link is normal.

[0150] With this approach, we can effectively monitor and analyze the status of wireless communication links while optimizing parameter settings to improve communication efficiency and security.

[0151] The method of the present invention is implemented based on a TTE analyzer. The working circuit of the TTE analysis is as follows: Figure 2 to Figure 17 As shown, it includes a data processing circuit board, a data acquisition circuit board, a backplane, a power board, a PEX8648 switching module, a T1042 data processing module, a VPX connector, an RJ45 network port, a DB9 serial port, an FPGA module, an LVDS switch module, an SFP network transmission interface, a data processing circuit board, a data acquisition circuit board, and a power board are all connected to the backplane through a VPX connector, wherein the network port end of the data processing circuit board is connected to the host computer through the RJ45 network port, the VPX connector end of the data processing circuit board is connected to the backplane, and data is exchanged with the data acquisition circuit board on the backplane, the data acquisition circuit board is connected to the TTE network through the SFP network transmission interface, the data acquisition circuit board is connected to the backplane through the VPX interface and exchanges data with the data processing circuit board on the backplane, and the power board is connected to the backplane to supply power to the data acquisition circuit board and the data processing circuit board.

[0152] In the above scheme: the data processing circuit board includes a T1042 data processing module, a PEX8648 switching module, a DB9 serial port, an RJ54 Ethernet interface, a VPX connector, and a power management module. The PEX8648 switching module is connected to the VPX connector through a 4-way PCIE X4 interface to receive network data transmitted from the 4-way data acquisition circuit board. The PEX8648 switching module is connected to the VPX connector through a 1-way PCIE The X4 interface is connected to the T1042 data processing module, and forwards the data transmitted by the bus to the PEX8648 switching module to the T1042 data processing module. The T1042 data processing module is connected to the Ethernet interface RJ45 and sends the Ethernet signal to the host computer through the RJ45 Ethernet interface. The T1042 data processing module is connected to the DB9 serial port and can accept serial port signals for control and debugging. The PEX8648 is connected to the lamp holder and serves as an indicator for the normal operation of the module. The power management module is connected to the power board through the VPX connector, obtains the 12V power supply voltage from the power board and converts the 12V voltage into 1V, 1.8V or 3.3V voltages to power the entire data processing circuit board. The power management module is connected to the lamp holder and serves as an indicator for normal power supply.

[0153] In the above scheme, the data acquisition circuit board includes an FPGA module, an LVDS switch, an SFP network transmission interface, a VPX connector, two 2GB DDR3s, two FLASHs (256Mb) and a power management module. The FPGA module interacts with the data processing circuit board through the PCIE X4 interface and interacts with the other three data acquisition circuit boards through the PCIEX4 interface. One of the two FLASHs is used as the program storage of the FPGA, and the other is used to store network parameters. The FPGA module is connected to the SFP network transmission interface through the LVDS switch and interacts with the TTE network environment. The FPGA module is connected to the indicator light through the GPIO port to indicate the working status. The power management module converts the 12V voltage of the power board into multiple voltages such as 1.8V, 1.5V or 1V for powering the data acquisition circuit board.

[0154] In the above scheme, the data acquisition circuit board includes a power management module. As shown in the figure, the voltage output pin VOUT30 of the buck regulator chip D12, the voltage output pin VOUT31 of the buck regulator chip D12, the voltage output pin VOUT32 of the buck regulator chip D12, the voltage output pin VOUT40 of the buck regulator chip D12, the voltage output pin VOUT41 of the buck regulator chip D12 and the voltage output pin VOUT42 of the buck regulator chip D12 output the power supply voltage VCC1V VINT and connected to the first end of capacitor C281 and the first end of capacitor C284, the second end of capacitor C281 and the second end of capacitor C284 are grounded, the feedback pin FB3 of the buck regulator chip D12 and the feedback pin FB4 of the buck regulator chip D12 are connected to the first end of resistor R143 and the first end of resistor R146, the second end of resistor R143 and the second end of resistor R146 are grounded, the voltage tracking and soft start pin TRACK|SS3 of the buck regulator chip D12 and the voltage tracking and soft start pin TRACK|SS4 of the buck regulator chip D12 The start pin TRACK|SS4 is connected to the first end of the capacitor C278, the second end of the capacitor C278 is grounded, the power good indication terminal PGOOD3 of the buck voltage regulator chip D12 is connected to the first end of the resistor R141, the second end of the resistor R141 is connected to the internal power pin INTVCC3 of the buck voltage regulator chip D12, the power good indication terminal PGOOD4 of the buck voltage regulator chip D12 is connected to the first end of the resistor R142, and the second end of the resistor R142 is connected to the internal power pin INTVCC4 of the buck voltage regulator chip D12;

[0155] The voltage input pin VIN30 of the buck regulator chip D12, the voltage input pin VIN31 of the buck regulator chip D12, the voltage input pin SVIN3 of the buck regulator chip D12, and the enable pin RUN3 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, the voltage input pin VIN40 of the buck regulator chip D12, and the voltage input pin VIN41 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, the second end of the capacitor C274 is grounded, and the voltage input pin VIN40 of the buck regulator chip D12 and the voltage input pin VIN42 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274. 1. The voltage input pin SVIN4 of the buck regulator chip D12 and the enable pin RUN4 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C275, the second end of the capacitor C275 is grounded, the internal power pin INTVCC3 of the buck regulator chip D12 is connected to the working mode configuration pin MODE3 of the buck regulator chip D12, and the internal power pin 1NTVCC4 of the buck regulator chip D12 is connected to the working mode configuration pin MODE4 of the buck regulator chip D12;

[0156] Ground pin SGND of buck regulator chip D12, ground pin GND 0 of buck regulator chip D12, ground pin GND 1 of buck regulator chip D12, ground pin GND 2 of buck regulator chip D12, ground pin GND 3 of buck regulator chip D12, ground pin GND 4 of buck regulator chip D12, ground pin GND 5 of buck regulator chip D12, ground pin GND 6 of buck regulator chip D12, ground pin GND 7 of buck regulator chip D12, ground pin GND 8 of buck regulator chip D12, ground pin GND-9 of buck regulator chip D12, ground pin GND 10 of buck regulator chip D12, ground pin GND 11 of buck regulator chip D12, ground pin GND 12 of buck regulator chip D12 13. Ground pin GND 14 of buck regulator chip D12. Ground pin GND 15 of buck regulator chip D12. Ground pin GND 16 of buck regulator chip D12. Ground pin GND 17 of buck regulator chip D12. Ground pin GND 18 of buck regulator chip D12. Ground pin GND 19 of buck regulator chip D12. Ground pin GND 20 of buck regulator chip D12 are all grounded. The input power supply voltage VCC5V is converted into a stable power supply voltage VCC1V for output through the buck regulator chip D12.

[0157] The voltage output pin VOUT10 of the buck regulator chip D12, the voltage output pin VOUT11 of the buck regulator chip D12 and the voltage output pin VOUT12 of the buck regulator chip D12 output the power supply voltage VCC1.8V and are connected to the first end of the capacitor C279 and the first end of the capacitor C282, the second end of the capacitor C279 and the second end of the capacitor C282 are grounded, the feedback pin FB1 of the buck regulator chip D12 is connected to the first end of the resistor R144, the second end of the resistor R144 is grounded, the voltage tracking and soft start pin TRACK|SS1 of the buck regulator chip D12 is connected to the first end of the capacitor C276, the second end of the capacitor C276 is grounded, the power good indication pin PGOOD1 of the buck regulator chip D12 is connected to the first end of the resistor R139, and the second end of the resistor R139 is connected to the internal power pin 1NTVCC1 of the buck regulator chip D12;

[0158] The voltage output pin VOUT20 of the buck regulator chip D12, the voltage output pin VOUT21 of the buck regulator chip D12 and the voltage output pin VOUT22 of the buck regulator chip D12 output the power supply voltage VCC1.5V and are connected to the first end of the capacitor C280 and the first end of the capacitor C283, the second end of the capacitor C280 and the second end of the capacitor C283 are grounded, the feedback pin FB2 of the buck regulator chip D12 is connected to the first end of the resistor R145, the second end of the resistor R145 is grounded, the voltage tracking and soft start pin TRACK|SS2 of the buck regulator chip D12 is connected to the first end of the capacitor C277, the second end of the capacitor C277 is grounded, the power good indication terminal PGOOD2 of the buck regulator chip D12 is connected to the first end of the resistor R140, and the second end of the resistor R140 is connected to the internal power pin INTVCC2 of the buck regulator chip D12;

[0159] The power good indication terminal PGOOD1 of the buck voltage regulator chip D12 is connected to the enable terminal RUN2 of the buck voltage regulator chip D12;

[0160] The voltage input pin VIN10 of the buck voltage regulator chip D12, the voltage input pin VIN11 of the buck voltage regulator chip D12, and the voltage input pin SVIN1 of the buck voltage regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C272, the second end of the capacitor C272 is grounded, and the power good indication terminal PGOOD3 of the buck voltage regulator chip D12 and the power good indication terminal PGOOD4 of the buck voltage regulator chip D12 are connected to the enable terminal RUN1 of the buck voltage regulator chip D12;

[0161] The voltage input pin V1N20 of the buck regulator chip D12, the voltage input pin VIN21 of the buck regulator chip D12, and the voltage input pin SVIN2 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C273, and the second end of the capacitor C273 is grounded;

[0162] The internal power pin INTVCC1 of the buck regulator chip D12 is connected to the working mode configuration pin MODE1 of the buck regulator chip D12, and the internal power pin 1NTVCC2 of the buck regulator chip D12 is connected to the working mode configuration pin MODE2 of the buck regulator chip D12. The input power supply voltage VCC5V is converted into a stable power supply voltage VCC1.8V and VCC1.5V for output through the buck regulator chip D12.

[0163] In a preferred embodiment of the present invention, the power management module also includes capacitors C272, C273, C274 and C275, each with a capacitance of 22uF, capacitors C276, C277 and C278 with a capacitance of 0.1uF, capacitors C279, C280, C281, C282, C283 and C284.

[0164] In a preferred embodiment of the present invention, the power management module also includes resistors R139, R140, R141 and R142, each having a resistance of 10 kΩ, resistors R143 and R146 having a resistance of 90.9 kΩ, resistor R145 having a resistance of 40.2 kΩ, and resistor R144 having a resistance of 30.1 kΩ.

[0165] The above-mentioned data acquisition circuit board includes a PEX8648 switching module, including a switching chip U2, a 4-way PCIE X4 interface and a single-way PCIE X4 interface, the first end of the 4-way PCIE X4 interface is connected to the VPX connector, the second end of the 4-way PCIE X4 interface is connected to the switching chip U2, the first end of the single-way PCIE X4 interface is connected to the switching chip, and the second end of the single-way PCIE X4 interface is connected to the T1042 data processing module.

[0166] The above-mentioned PEX8648 switching module includes a network transmission indication pin of a U2 switching chip connected to an LED lamp holder to indicate the network transmission status.

[0167] The data processing circuit board includes a T1042 data processing module. The first end of capacitor C88, the first end of capacitor C89, the first end of capacitor C96, the first end of capacitor C98, the first end of capacitor C100, the first end of capacitor C102, the first end of capacitor C105, the first end of capacitor C108 and the first end of capacitor C111 are connected to the input voltage VCC3.3V and the voltage input pin VCC of the processor IC1. The second end of capacitor C88, the second end of capacitor C89, the second end of capacitor C96, the second end of capacitor C98, the second end of capacitor C100, the second end of capacitor C102, the second end of capacitor C105, the second end of capacitor C108 and the second end of capacitor C111 are grounded and connected to the voltage input pin VCC of the processor IC1. The first end of capacitor C106, the first end of capacitor C109 and the first end of capacitor C112 are connected to the input voltage VCC3.3V. VCC1.8V is connected to the voltage input pin VCCQ of the processor IC1, the second end of the capacitor C106, the second end of the capacitor C109 and the second end of the capacitor C112 are grounded, the first end of the resistor R152 is connected to the input voltage VCC1.2V, the second end is connected to the first end of the capacitor C90, the first end of the capacitor C97, the first end of the capacitor C99, the first end of the capacitor C101, the first end of the capacitor C103, the first end of the capacitor C107, the first end of the capacitor C110, the first end of the capacitor C113, the voltage input pin VDDC of the processor IC1 and the voltage input pin VDD of the processor IC1, the second end of the capacitor C90, the second end of the capacitor C97, the second end of the capacitor C99, the second end of the capacitor C101, the second end of the capacitor C103, the second end of the capacitor C107, the second end of the capacitor C110 and the second end of the capacitor C113 are grounded;

[0168] A first SATA power supply pin SATA VDD of the processor IC1 is connected to a first end of a capacitor C120, a first end of a capacitor C122, a first end of a capacitor C124, and a first end of an inductor L11, a second end of the capacitor C120, a second end of the capacitor C122, and a second end of the capacitor C124 are grounded, and a second end of the inductor L11 is connected to an input voltage VCC1.2V;

[0169] The second SATA power supply pin SATA VDD of the processor IC1 is connected to the first end of the capacitor C121, the first end of the capacitor C123, the first end of the capacitor C125 and the first end of the inductor L12, the second end of the capacitor C121, the second end of the capacitor C123 and the second end of the capacitor C125 are all grounded, and the second end of the inductor L12 is connected to the input voltage VCC1.2V;

[0170] The SATA voltage pin SATA VSS of the processor IC1 is grounded, the sleep signal pin DEVSLP of the processor IC1 is connected to the first end of the resistor R155, the second end of the resistor R155 is grounded, when the pin receives the sleep signal, the device will enter the low power mode, the crystal oscillator output pin XTAL OUT of the processor IC1 and the crystal oscillator input pin XTAL IN of the processor IC1 are connected to the external crystal oscillator circuit, the power reset pin PWR RESETN of the processor IC1 is connected to the first end of the resistor R158, the second end of the resistor R158 is connected to the external reset signal, and the power reset pin PWR RESETN of the processor IC1 is connected to the external SATA power reset signal;

[0171] The spare pin NC34 of the processor IC1 is connected to the LED indicator light, and the spare pin NC37 of the processor IC1 and the spare pin NC38 of the processor IC1 are connected to the SATA device for receiving and sending control commands and data of the SATA device. The processor IC1 is the main controller.

[0172] In a preferred embodiment of the present invention, the processor module also includes: the capacitance of capacitor C88, capacitor C89 and capacitor C96 is 1uF, the capacitance of capacitor C98, capacitor C100, capacitor C102, capacitor C105, capacitor C10 and capacitor C111 is 0.1uF, the capacitance of capacitor C106 is 1uF, the capacitance of capacitor C109 and capacitor C112 is 1uF, the capacitance of capacitor C90, capacitor C99 and capacitor C101 is 10uF, the capacitance of capacitor C101, capacitor C103, capacitor C107, capacitor C110 and capacitor C113 is 4.7uF, the capacitance of capacitor C120, capacitor C121, capacitor C122, and capacitor C123 is 0.1uF, the capacitance of capacitor C124 and capacitor C125 is 10uF, the inductance of inductor L11 and inductor L12 is 22uH, and the resistance of resistor R155 is 1k Ω.

[0173] The first end of the above-mentioned VPX connector module is connected to the PEX8648 switching module of the data processing circuit board through a 4-way PCIE X4 interface, the second end of the VPX connector module is connected to the four data acquisition circuit boards through four single-way PCIE X4 interfaces, and the power transmission end of the VPX connector module is connected to the power board.

[0174] The above RJ45 network port module includes an Ethernet interface ETH0, a network transmission indicator light and a capacitor filter network. The network signal transmission pins 1 to 8 of the Ethernet interface ETH0 are used for Gigabit Ethernet data transmission. The indicator light pin 9 of the Ethernet interface ETH0 receives a network activity signal GBE0ACT N. When data is transmitted, the LED light is on. The indicator light pin 9 of the Ethernet interface ETH0 is connected to the first end of the capacitor C6, and the second end of the capacitor C6 is grounded. The indicator light pin 10 of the Ethernet interface ETH0 is connected to the first end of the resistor R9, and the second end of the resistor R9 is connected to the input voltage LED 2V5.

[0175] The indicator light pin 11 of the Ethernet interface ETH0 receives the network connection signal L1NK1000N. When the link is successful, the LED light is on. The indicator light pin 11 of the Ethernet interface ETH0 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is grounded. The indicator light pin 12 of the Ethernet interface ETH0 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the input voltage LED 2V5;

[0176] In a preferred embodiment of the present invention, the RJ45 network port module further includes: the capacitance of capacitor C4 and capacitor C6 is 4700pF, and the resistance of capacitor R9 and capacitor R10 is 330Ω.

[0177] The above-mentioned clock management module includes the MC100LVE111FA clock distribution chip D1, the clock generator U3, the decoupling capacitor for reducing power supply noise, and the resistor network for impedance matching and the resistor network for voltage division. These three parts together constitute the clock management module for ensuring the signal integrity and stability of the clock signal.

[0178] The control pin OE of the clock generator U3 is connected to the first end of the resistor R102, the second end of the resistor R102 is connected to the second end of the inductor L1, the first end of the capacitor C53 and the voltage input pin VDD of the clock generator U3, the first end of the inductor L1 is connected to the input voltage VCC3.3V, the second end of the capacitor C53 is grounded, the clock signal output pin CLK of the clock generator U3 is connected to the first end of the capacitor C58, the second end of the capacitor C58 is connected to the clock input pin CLK0 of the clock distribution chip D1, the clock signal output pin CLK* of the clock generator U3 is connected to the first end of the capacitor C95, the second end of the capacitor C95 is connected to the clock input pin CLK0* of the clock distribution chip D1, and the ground pin GND of the clock generator U3 is grounded.

[0179] The clock input pin CLK0 of the clock distribution chip D1 and the clock input pin CLK0* of the clock distribution chip D1 are connected to the clock signal output pin CLK of the clock generator U3 and the clock signal output pin CLK* of the clock generator U3 to receive the synchronous differential signal from the clock generator U3, the first end of the resistor R86 is connected to the input voltage VCC3.3V, the second end of the resistor R86 is connected to the first end of the resistor R87 and the clock input pin CLK0 of the clock distribution chip D1, the second end of the resistor R87 is grounded, the first end of the resistor R88 is connected to the input voltage VCC3.3V, the second end of the resistor R88 is connected to the first end of the resistor R89 ​​and the clock input pin CLK0* of the clock distribution chip D1, and the second end of the resistor R89 ​​is grounded;

[0180] The first end of the resistor R90 is connected to the clock input pin CLK1 of the clock distribution chip D1, and the second end of the resistor R90 is grounded. The first end of the resistor R101 is connected to the clock input pin CLK1* of the clock distribution chip D1, and the second end of the resistor R101 is grounded. The first end of the resistor R62 is connected to the clock selection pin CLK SET of the clock distribution chip D1, and the second end of the resistor R62 is grounded. The clock selection pin CLK SET of the clock distribution chip D1 is connected to the clock input pin CLK SET of the clock distribution chip D1. SET is connected to the clock selection signal, the first end of the capacitor C54, the first end of the capacitor C55, and the first end of the capacitor C56 are all connected to the input voltage VCC3.3V, the second end of the capacitor C54, the second end of the capacitor C55, and the second end of the capacitor C56 are all grounded, the first end of the capacitor C54 is also connected to the voltage input pin VCC0 of the clock distribution chip D1, the voltage input pin VCC1 of the clock distribution chip D1, the voltage input pin VCC2 of the clock distribution chip D1, the voltage input pin VCC3 of the clock distribution chip D1, and the voltage input pin VCC4 of the clock distribution chip D1, and the voltage pin VEE of the clock distribution chip D1 is grounded;

[0181] A first end of the resistor R103 is connected to a signal output pin Q0 of the clock distribution chip D1 and a first end of the capacitor C18, a second end of the resistor R103 is grounded, and a second end of the capacitor C18 is connected to a VPX connector, a first end of the resistor R104 is connected to a signal output pin Q0* of the clock distribution chip D1 and a first end of the capacitor C60, a second end of the resistor R104 is grounded, and a second end of the capacitor C60 is connected to a VPX connector, a first end of the resistor R1 is connected to a signal output pin Q1 of the clock distribution chip D1 and a first end of the capacitor C21, a second end of the resistor R1 is grounded, and a second end of the capacitor C21 is connected to the VPX connector, a first end of the resistor R8 is connected to a signal output pin Q1* of the clock distribution chip D1 and a first end of the capacitor C61, a second end of the resistor R8 is grounded, and a second end of the capacitor C61 is connected to the VPX connector, A first end of the resistor R21 is connected to a signal output pin Q2 of the clock distribution chip D1 and a first end of the capacitor C38, a second end of the resistor R21 is grounded, and a second end of the capacitor C38 is connected to a VPX connector, a first end of the resistor R35 is connected to a signal output pin Q2* of the clock distribution chip D1 and a first end of the capacitor C62, a second end of the resistor R35 is grounded, and a second end of the capacitor C62 is connected to the VPX connector, a first end of the resistor R36 is connected to a signal output pin Q3 of the clock distribution chip D1 and a first end of the capacitor C44, a second end of the resistor R36 is grounded, and a second end of the capacitor C44 is connected to the VPX connector, a first end of the resistor R57 is connected to a signal output pin Q3* of the clock distribution chip D1 and a first end of the capacitor C17, a second end of the resistor R57 is grounded, and a second end of the capacitor C17 is connected to the VPX connector;

[0182] The second end of the capacitor C18 is connected to the first end of the resistor R58 and the first end of the resistor R59, the second end of the resistor R58 is connected to the input voltage VCC3.3V, and the second end of the resistor R59 is grounded. The second end of the capacitor C60 is connected to the first end of the resistor R60 and the first end of the resistor R61, the second end of the resistor R60 is connected to the input voltage VCC3.3V, and the second end of the resistor R61 is grounded. The second end of the capacitor C21 is connected to the first end of the resistor R63 and the first end of the resistor R64, the second end of the resistor R63 is connected to the input voltage VCC3.3V, and the second end of the resistor R64 is grounded. The second end of the capacitor C61 is connected to the first end of the resistor R66 and the first end of the resistor R67, the second end of the resistor R66 is connected to the input voltage VCC3.3V, and the second end of the resistor R67 is grounded. The second end of capacitor C38 is connected to the first end of resistor R68 and the first end of resistor R69, the second end of resistor R68 is connected to the input voltage VCC3.3V, and the second end of resistor R69 is grounded. The second end of capacitor C62 is connected to the first end of resistor R70 and the first end of resistor R72, the second end of resistor R70 is connected to the input voltage VCC3.3V, and the second end of resistor R72 is grounded. The second end of capacitor C44 is connected to the first end of resistor R73 and the first end of resistor R74, the second end of resistor R73 is connected to the input voltage VCC3.3V, and the second end of resistor R74 is grounded. The second end of capacitor C17 is connected to the first end of resistor R75 and the first end of resistor R76, the second end of resistor R75 is connected to the input voltage VCC3.3V, and the second end of resistor R76 is grounded.

[0183] In a preferred embodiment of the present invention, the clock management module includes: the inductance value of the inductor L1 is 22uH, the capacitance value of the capacitor C53 is 0.1uF, the resistance value of the resistor R102 is 4.7kΩ, the capacitance value of the capacitor C58 and the capacitor C95 is 0.1uF, the resistance value of the resistor R86 and the resistor R87 is 7.5kΩ, the resistance value of the resistor R87, the resistor R89, the resistor R90, the resistor R101 and the resistor R62 is 10k Ω, the capacitance value of the capacitor C54 is 10uF, the resistance value of the capacitor C55 and the capacitor C56 is 0.1uF, the resistance value of the resistor R103, the resistor R104, the resistor R1, the resistor R8, the resistor R21, the resistor R35, the resistor R36 and the resistor R57 is 120Ω, the resistance value of the resistor R59, the resistor R61, the resistor R64, the resistor R67, the resistor R69, the resistor R72, the resistor R74 and the resistor R76 is 1k Ω, and the resistance values ​​of resistors R58, R60, R63, R66, R68, R70, R73 and R75 are 10k Ω.

[0184] The above-mentioned FPGA module adopts the processor chip D4 of the XC7K325T-2FFG900I model to manage various interface signals such as LVDS, PCIe, and JTAG. The LVDS interface is used for high-speed data transmission, the PCIE X4 interface realizes high-speed data communication with the host system, and the JTAG interface is used for programming and debugging.

[0185] The above-mentioned SFP interface module includes an SFP module interface connected to the LVD switch X4 through an Ethernet transmission line, and the LVD switch is connected to the FPGA module.

[0186] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A TTE analyzer and data analysis method, characterized in that: The following steps are involved: S1, main controller initialization; S2, the host computer data analysis software platform sends a communication link heartbeat command to the main controller every 1 second. After receiving the command, the main controller sends an ACK message to the host computer data analysis software platform to determine whether the communication link is normal and display the communication link status on the software platform interface; S3, the host computer data analysis software platform sends a TTE data card port Link status query command to the main controller every 1 second. After receiving the command, the main controller reads the port register 8-11 bits, obtains the Link status, and sends the TTE data card port Link status message to the host computer data analysis software platform. The host computer data analysis software platform interface displays the TTE data card port Link status; S4, the host computer data analysis software platform sends a command to start capturing TTE data to the main controller. After receiving the command, the main controller parses out the port number; S5, the host computer data analysis software platform sends a TTE data upload command to the main controller. After receiving the command, the main controller parses out the port number; S6, after receiving the data, the host computer data analysis software platform analyzes and interprets the TTE network data.

2. A TTE analyzer and data analysis method according to claim 1, characterized in that: The determination of whether the communication link is normal is obtained by: S201, determining the response speed of the communication link: First, collect relevant parameters of the wireless communication link, including signal strength, bit error rate, and delay; Then, it is determined whether the delay is higher than the set first delay threshold; if the delay is higher than the set first delay threshold, it is determined to be at the third level response speed; If the delay is lower than the set first delay threshold but higher than the set second delay threshold, where the value of the first delay threshold is greater than the second delay threshold; then determine whether the signal strength is higher than the first signal strength threshold. If the signal strength is higher than the first signal strength threshold and the bit error rate is lower than the bit error rate threshold, it is determined to be a second-level response speed; if the signal strength is lower than the first signal strength threshold but higher than the second signal strength threshold, it is determined to be a third-level response speed; wherein the first signal strength threshold is greater than the second signal strength threshold; If the delay is lower than the set second delay threshold, and the signal strength is lower than the first signal strength threshold but higher than the second signal strength threshold, and the bit error rate is lower than the bit error rate threshold, it is determined to be a secondary response speed; if the delay is lower than the set second delay threshold, and the signal strength is higher than the first signal strength threshold, and the bit error rate is lower than the bit error rate threshold, it is determined to be a primary response speed; Since step S2 has the following 4 delays, there are 4 response speeds for each execution; Sending delay: the time when the host computer sends the heartbeat command; Transmission delay: the time required for the heartbeat command to be transmitted from the host computer to the main controller; Processing delay: the time it takes for the master controller to process the heartbeat command and generate an ACK message after receiving it; ACK sending delay: the time point when the main controller sends the ACK message back to the host computer; ACK transmission delay: the time required for the ACK message to be transmitted from the main controller back to the host computer; S202, determine the monitoring communication cycle: S202-1, record the timestamp of each time the upper computer data analysis software platform sends the communication link heartbeat command to the main controller in step S2; record it as the sending time; and the timestamp of the TTE network data analyzed and parsed in S6; record it as the corresponding time; the difference between these two timestamps is the communication cycle; S202-2, determine whether the command at the N-1th sending time is the same as the command at the Nth sending time. If they are the same, record the timestamp of the Nth analysis and parsing of the TTE network data. At this time, the communication cycle is the timestamp from the N-1th sending time to the Nth analysis and parsing of the TTE network data. S203, recording the number of response speeds at each level in each cycle, and using this to determine whether the communication link is normal: if there is no third-level response speed within a monitoring communication cycle, and the number of second-level response speeds does not exceed the second-level response speed number threshold, then the communication link is normal.

3. A TTE analyzer and data analysis method according to claim 1, characterized in that: Step S4 includes: S4-1, write the port number to Bit0-1 of the port register, write 01 to Bit4-5 to start the port data capture function, the TTE data card starts to capture TTE network data, and stores the captured data in the FPGA DDR; S4-2, the main controller sends a command ACK message to start capturing TTE data to the host computer data analysis software platform; S4-3, the host computer data analysis software platform sends a stop capturing TTE data command to the main controller. After receiving the command, the main controller writes the port register Bit4-5 to 00, and the TTE data card stops data capturing; S4-4, the main controller sends a partial stop ACK message to the host computer data analysis software platform.

4. A TTE analyzer and data analysis method according to claim 1, characterized in that: Step S5 includes: S5-1, write the port number to Bit0-1 of the port register, write 01 to Bit6-7 to start the port data upload function, and the TTE data card writes the data stored in the FPGA DDR into the shared memory; S5-2, the main controller sends a TTE data upload start command ACK message to the host computer data analysis software platform; S5-3, after the TTE data card uploads the captured data, the port register Bit6-7 is written with 00, and an interrupt is sent to the main controller; S5-4, after receiving the interrupt, the main controller reads the status register bit31, which is 1, indicating that the data FPGA TTE data card FPGA writes the collected TTE data into the shared memory area, and the main controller starts uploading the data in the shared memory to the host computer data analysis software platform. After receiving the data, the host computer data analysis software platform sends an ACK message to the main controller; S5-5, after uploading the data, the main controller sets the status register bit31 to 0; S5-6, the main controller records the data in the shared memory to the SATA disk.

5. A TTE analyzer and data analysis method according to claim 1, characterized in that: The TTE analyzer and data analysis method are implemented based on the TTE analyzer, and the TTE analyzer includes: Data processing circuit board, including T1042 data processing module, PEX8648 switching module, DB9 serial port, RJ45 Ethernet interface, VPX connector, clock management module and power management module; Data acquisition circuit board, including FPGA module, LVDS switch, SFP network transmission interface, VPX connector, DDR3, clock management module and power management module; Back panel; Power board; The data processing circuit board, data acquisition circuit board and power board are connected to the backplane through the VPX connector, and data exchange is carried out on the backplane. The external network data enters the FPGA module of the data acquisition circuit board through the SFP interface, and then the FPGA module transmits the network data to the VPX connector through the PCIE X4 interface. Then the network data enters the PEX8648 switching module of the data processing circuit board from the VPX connector. The PEX8648 switching module transmits the network data to the T1042 data processing module, and the T1042 data processing module transmits the network data to the RJ45 network port. Finally, the RJ45 network port transmits the network data to the host computer. The data processing circuit board includes a PEX8648 switching module connected to the VPX connector via a 4-way PCIE X4 interface, the PEX8648 switching module connected to the T1042 data processing module via a 1-way PCIE X4 interface, the T1042 data processing module connected to the host computer via an RJ45 Ethernet interface, and receiving control and debugging signals via a DB9 serial port; Among them, the data acquisition circuit board, the power management module is connected to the processor D4 and the FPGA, the clock management module is connected to the FPGA module, the FPGA module is connected to the DDR3 memory, the FPGA module is connected to the VPX connector through the PCIE X4 interface, the FPGA module is connected to the VPX connector through three sets of LVDS X3 switches, the FPGA module is connected to the indicator module and the button module through the GPIO interface, the FPGA module is connected to the JTAG interface, the FPGA module is connected to the SFP interface module through the LVDS X4 switch, and the SFP X4 interface is connected to the external network; The power management module converts the voltage provided by the power board into the voltage required by each module.

6. A TTE analyzer and data analysis method according to claim 5, characterized in that: The data processing circuit board and the data acquisition circuit board include a power management module, wherein the power management module includes: Multiple input power interfaces and capacitor filtering networks to provide stable voltage input; Buck regulator chip for voltage regulation and clock synchronization; Power good indication circuit for monitoring power status; The voltage output pin VOUT10 of the buck regulator chip D12, the voltage output pin VOUT11 of the buck regulator chip D12 and the voltage output pin VOUT12 of the buck regulator chip D12 output the power supply voltage VCC1.8V and are connected to the first end of the capacitor C279 and the first end of the capacitor C282, the second end of the capacitor C279 and the second end of the capacitor C282 are grounded, the feedback pin FB1 of the buck regulator chip D12 is connected to the first end of the resistor R144, the second end of the resistor R144 is grounded, the voltage tracking and soft start pin TRACK|SS1 of the buck regulator chip D12 is connected to the first end of the capacitor C276, the second end of the capacitor C276 is grounded, the power good indication pin PGOOD1 of the buck regulator chip D12 is connected to the first end of the resistor R139, and the second end of the resistor R139 is connected to the internal power pin INTVCC1 of the buck regulator chip D12; The voltage output pin VOUT20 of the buck regulator chip D12, the voltage output pin VOUT21 of the buck regulator chip D12 and the voltage output pin VOUT22 of the buck regulator chip D12 output the power supply voltage VCC1.5V and are connected to the first end of the capacitor C280 and the first end of the capacitor C283, the second end of the capacitor C280 and the second end of the capacitor C283 are grounded, the feedback pin FB2 of the buck regulator chip D12 is connected to the first end of the resistor R145, the second end of the resistor R145 is grounded, the voltage tracking and soft start pin TRACK|SS2 of the buck regulator chip D12 is connected to the first end of the capacitor C277, the second end of the capacitor C277 is grounded, the power good indication terminal PGOOD2 of the buck regulator chip D12 is connected to the first end of the resistor R140, and the second end of the resistor R140 is connected to the internal power pin INTVCC2 of the buck regulator chip D12; The power good indication terminal PGOOD1 of the buck voltage regulator chip D12 is connected to the enable terminal RUN2 of the buck voltage regulator chip D12; The voltage input pin VIN1 0 of the buck voltage regulator chip D12, the voltage input pin VIN1 1 of the buck voltage regulator chip D12, and the voltage input pin SVIN1 of the buck voltage regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C272, the second end of the capacitor C272 is grounded, and the power good indication terminal PGOOD3 of the buck voltage regulator chip D12 and the power good indication terminal PGOOD4 of the buck voltage regulator chip D12 are connected to the enable terminal RUN1 of the buck voltage regulator chip D12; The voltage input pin VIN20 of the buck regulator chip D12, the voltage input pin VIN21 of the buck regulator chip D12, and the voltage input pin SVIN2 of the buck regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C273, and the second end of the capacitor C273 is grounded; The internal power supply pin INTVCC1 of the buck voltage regulator chip D12 is connected to the working mode configuration pin MODE1 of the buck voltage regulator chip D12, and the internal power supply pin INTVCC2 of the buck voltage regulator chip D12 is connected to the working mode configuration pin MODE2 of the buck voltage regulator chip D12; The voltage output pin VOUT30 of the buck regulator chip D12, the voltage output pin VOUT31 of the buck regulator chip D12, the voltage output pin VOUT32 of the buck regulator chip D12, the voltage output pin VOUT40 of the buck regulator chip D12, the voltage output pin VOUT41 of the buck regulator chip D12 and the voltage output pin VOUT42 of the buck regulator chip D12 output the power supply voltage VCC1V VINT and are connected to the first end of the capacitor C281 and the first end of the capacitor C284, the second end of the capacitor C281 and the second end of the capacitor C284 are grounded, the feedback pin FB3 of the buck regulator chip D12 and the feedback pin FB4 of the buck regulator chip D12 are connected to the first end of the resistor R143 and the first end of the resistor R146, the second end of the resistor R143 and the second end of the resistor R146 are grounded, the voltage tracking and soft start pin TRACK|SS3 of the buck regulator chip D12 and the voltage tracking and soft start pin TRACK|SS3 of the buck regulator chip D12 The start pin TRACK|SS4 is connected to the first end of the capacitor C278, the second end of the capacitor C278 is grounded, the power good indication terminal PGOOD3 of the buck voltage regulator chip D12 is connected to the first end of the resistor R141, the second end of the resistor R141 is connected to the internal power pin INTVCC3 of the buck voltage regulator chip D12, the power good indication terminal PGOOD4 of the buck voltage regulator chip D12 is connected to the first end of the resistor R142, and the second end of the resistor R142 is connected to the internal power pin INTVCC4 of the buck voltage regulator chip D12; The voltage input pin VIN3 of the step-down voltage regulator chip D12 0. The voltage input pin VIN31 of the buck voltage regulator chip D12, the voltage input pin SVIN3 of the buck voltage regulator chip D12, and the enable pin RUN3 of the buck voltage regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C274, and the second end of the capacitor C274 is grounded. The voltage input pin VIN40 of the buck voltage regulator chip D12, the voltage input pin VIN41 of the buck voltage regulator chip D12, the voltage input pin SVIN4 of the buck voltage regulator chip D12, and the enable pin RUN4 of the buck voltage regulator chip D12 are connected to the power supply voltage VCC5V and the first end of the capacitor C275, and the second end of the capacitor C275 is grounded. The internal power supply pin INTVCC3 of the buck voltage regulator chip D12 is connected to the working mode configuration pin MODE3 of the buck voltage regulator chip D12, and the internal power supply pin INTVCC4 of the buck voltage regulator chip D12 is connected to the working mode configuration pin MODE4 of the buck voltage regulator chip D12; Ground pin SGND of buck regulator chip D12, ground pin GND 0 of buck regulator chip D12, ground pin GND 1 of buck regulator chip D12, ground pin GND 2 of buck regulator chip D12, ground pin GND 3 of buck regulator chip D12, ground pin GND 4 of buck regulator chip D12, ground pin GND 5 of buck regulator chip D12, ground pin GND 6 of buck regulator chip D12, ground pin GND 7 of buck regulator chip D12, ground pin GND 8 of buck regulator chip D12, ground pin GND 9 of buck regulator chip D12, ground pin GND 10 of buck regulator chip D12, ground pin GND 11 of buck regulator chip D12, ground pin GND 12 of buck regulator chip D12 13. Ground pin GND of buck voltage regulator chip D12 14. Ground pin GND of buck voltage regulator chip D12 15. Ground pin GND of buck voltage regulator chip D12 16. Ground pin GND of buck voltage regulator chip D12 17. Ground pin GND of buck voltage regulator chip D12 18. Ground pin GND of buck voltage regulator chip D12 19. Ground pin GND 20 of buck voltage regulator chip D12 are all grounded.

7. A TTE analyzer and data analysis method according to claim 5, characterized in that: The data processing circuit board includes a clock management module; The control pin OE of the clock generator U3 is connected to the first end of the resistor R102, the second end of the resistor R102 is connected to the second end of the inductor L1, the first end of the capacitor C53 and the voltage input pin VDD of the clock generator U3, the first end of the inductor L1 is connected to the input voltage VCC3.3V, the second end of the capacitor C53 is grounded, the clock signal output pin CLK of the clock generator U3 is connected to the first end of the capacitor C58, the second end of the capacitor C58 is connected to the clock input pin CLK0 of the clock distribution chip D1, the clock signal output pin CLK* of the clock generator U3 is connected to the first end of the capacitor C95, the second end of the capacitor C95 is connected to the clock input pin CLK0* of the clock distribution chip D1, and the ground pin GND of the clock generator U3 is grounded; The clock input pin CLK0 of the clock distribution chip D1 and the clock input pin CLK0* of the clock distribution chip D1 are connected to the clock signal output pin CLK of the clock generator U3 and the clock signal output pin CLK* of the clock generator U3 to receive the synchronous differential signal from the clock generator U3, the first end of the resistor R86 is connected to the input voltage VCC3.3V, the second end of the resistor R86 is connected to the first end of the resistor R87 and the clock input pin CLK0 of the clock distribution chip D1, the second end of the resistor R87 is grounded, the first end of the resistor R88 is connected to the input voltage VCC3.3V, the second end of the resistor R88 is connected to the first end of the resistor R89 ​​and the clock input pin CLK0* of the clock distribution chip D1, and the second end of the resistor R89 ​​is grounded; The first end of the resistor R90 is connected to the clock input pin CLK1 of the clock distribution chip D1, and the second end of the resistor R90 is grounded. The first end of the resistor R101 is connected to the clock input pin CLK1* of the clock distribution chip D1, and the second end of the resistor R101 is grounded. The first end of the resistor R62 is connected to the clock selection pin CLK SET of the clock distribution chip D1, and the second end of the resistor R62 is grounded. The clock selection pin CLK SET of the clock distribution chip D1 is connected to the clock input pin CLK SET of the clock distribution chip D1. SET is connected to the clock selection signal, the first end of the capacitor C54, the first end of the capacitor C55, and the first end of the capacitor C56 are all connected to the input voltage VCC3.3V, the second end of the capacitor C54, the second end of the capacitor C55, and the second end of the capacitor C56 are all grounded, the first end of the capacitor C54 is also connected to the voltage input pin VCC0 of the clock distribution chip D1, the voltage input pin VCC1 of the clock distribution chip D1, the voltage input pin VCC2 of the clock distribution chip D1, the voltage input pin VCC3 of the clock distribution chip D1, and the voltage input pin VCC4 of the clock distribution chip D1, and the voltage pin VEE of the clock distribution chip D1 is grounded; A first end of the resistor R103 is connected to a signal output pin Q0 of the clock distribution chip D1 and a first end of the capacitor C18, a second end of the resistor R103 is grounded, and a second end of the capacitor C18 is connected to a VPX connector, a first end of the resistor R104 is connected to a signal output pin Q0* of the clock distribution chip D1 and a first end of the capacitor C60, a second end of the resistor R104 is grounded, and a second end of the capacitor C60 is connected to a VPX connector, a first end of the resistor R1 is connected to a signal output pin Q1 of the clock distribution chip D1 and a first end of the capacitor C21, a second end of the resistor R1 is grounded, and a second end of the capacitor C21 is connected to the VPX connector, a first end of the resistor R8 is connected to a signal output pin Q1* of the clock distribution chip D1 and a first end of the capacitor C61, a second end of the resistor R8 is grounded, and a second end of the capacitor C61 is connected to the VPX connector, A first end of the resistor R21 is connected to a signal output pin Q2 of the clock distribution chip D1 and a first end of the capacitor C38, a second end of the resistor R21 is grounded, and a second end of the capacitor C38 is connected to a VPX connector, a first end of the resistor R35 is connected to a signal output pin Q2* of the clock distribution chip D1 and a first end of the capacitor C62, a second end of the resistor R35 is grounded, and a second end of the capacitor C62 is connected to the VPX connector, a first end of the resistor R36 is connected to a signal output pin Q3 of the clock distribution chip D1 and a first end of the capacitor C44, a second end of the resistor R36 is grounded, and a second end of the capacitor C44 is connected to the VPX connector, a first end of the resistor R57 is connected to a signal output pin Q3* of the clock distribution chip D1 and a first end of the capacitor C17, a second end of the resistor R57 is grounded, and a second end of the capacitor C17 is connected to the VPX connector; The second end of the capacitor C18 is connected to the first end of the resistor R58 and the first end of the resistor R59, the second end of the resistor R58 is connected to the input voltage VCC3.3V, and the second end of the resistor R59 is grounded. The second end of the capacitor C60 is connected to the first end of the resistor R60 and the first end of the resistor R61, the second end of the resistor R60 is connected to the input voltage VCC3.3V, and the second end of the resistor R61 is grounded. The second end of the capacitor C21 is connected to the first end of the resistor R63 and the first end of the resistor R64, the second end of the resistor R63 is connected to the input voltage VCC3.3V, and the second end of the resistor R64 is grounded. The second end of the capacitor C61 is connected to the first end of the resistor R66 and the first end of the resistor R67, the second end of the resistor R66 is connected to the input voltage VCC3.3V, and the second end of the resistor R67 is grounded. The second end of capacitor C38 is connected to the first end of resistor R68 and the first end of resistor R69, the second end of resistor R68 is connected to the input voltage VCC3.3V, and the second end of resistor R69 is grounded. The second end of capacitor C62 is connected to the first end of resistor R70 and the first end of resistor R72, the second end of resistor R70 is connected to the input voltage VCC3.3V, and the second end of resistor R72 is grounded. The second end of capacitor C44 is connected to the first end of resistor R73 and the first end of resistor R74, the second end of resistor R73 is connected to the input voltage VCC3.3V, and the second end of resistor R74 is grounded. The second end of capacitor C17 is connected to the first end of resistor R75 and the first end of resistor R76, the second end of resistor R75 is connected to the input voltage VCC3.3V, and the second end of resistor R76 is grounded.

8. A TTE analyzer and data analysis method according to claim 5, characterized in that: The data processing circuit board includes a T1042 data processing module, In the above-mentioned T1042 data processing module, the first end of capacitor C88, the first end of capacitor C89, the first end of capacitor C96, the first end of capacitor C98, the first end of capacitor C100, the first end of capacitor C102, the first end of capacitor C105, the first end of capacitor C108 and the first end of capacitor C111 are connected to the input voltage VCC3.3V and the voltage input pin VCC of processor IC1, the second end of capacitor C88, the second end of capacitor C89, the second end of capacitor C96, the second end of capacitor C98, the second end of capacitor C100, the second end of capacitor C102, the second end of capacitor C105, the second end of capacitor C108 and the second end of capacitor C111 are grounded and connected to the voltage input pin VCC of processor IC1, the first end of capacitor C106, the first end of capacitor C109 and the first end of capacitor C112 are connected to the input voltage VCC1 .8V is connected to the voltage input pin VCCQ of the processor IC1, the second end of the capacitor C106, the second end of the capacitor C109 and the second end of the capacitor C112 are grounded, the first end of the resistor R152 is connected to the input voltage VCC1.2V, the second end is connected to the first end of the capacitor C90, the first end of the capacitor C97, the first end of the capacitor C99, the first end of the capacitor C101, the first end of the capacitor C103, the first end of the capacitor C107, the first end of the capacitor C110, the first end of the capacitor C113, the voltage input pin VDDC of the processor IC1 and the voltage input pin VDD of the processor IC1, the second end of the capacitor C90, the second end of the capacitor C97, the second end of the capacitor C99, the second end of the capacitor C101, the second end of the capacitor C103, the second end of the capacitor C107, the second end of the capacitor C110 and the second end of the capacitor C113 are grounded; A first SATA power supply pin SATA VDD of the processor IC1 is connected to a first end of a capacitor C120, a first end of a capacitor C122, a first end of a capacitor C124, and a first end of an inductor L11, a second end of the capacitor C120, a second end of the capacitor C122, and a second end of the capacitor C124 are grounded, and a second end of the inductor L11 is connected to an input voltage VCC1.2V; The second SATA power supply pin SATA VDD of the processor IC1 is connected to the first end of the capacitor C121, the first end of the capacitor C123, the first end of the capacitor C125 and the first end of the inductor L12, the second end of the capacitor C121, the second end of the capacitor C123 and the second end of the capacitor C125 are all grounded, and the second end of the inductor L12 is connected to the input voltage VCC1.2V; The SATA voltage pin SATA VSS of the processor IC1 is grounded, the sleep signal pin DEVSLP of the processor IC1 is connected to the first end of the resistor R155, the second end of the resistor R155 is grounded, when the pin receives the sleep signal, the device will enter the low power mode, the crystal oscillator output pin XTAL OUT of the processor IC1 and the crystal oscillator input pin XTAL IN of the processor IC1 are connected to the external crystal oscillator circuit, the power reset pin PWR RESETN of the processor IC1 is connected to the first end of the resistor R158, the second end of the resistor R158 is connected to the external reset signal, and the power reset pin PWR RESETN of the processor IC1 is connected to the external SATA power reset signal; The spare pin NC34 of the processor IC1 is connected to the LED indicator light, and the spare pin NC37 of the processor IC1 and the spare pin NC38 of the processor IC1 are connected to the SATA device for receiving and sending control commands and data of the SATA device. The processor IC1 is the main controller.

9. A TTE analyzer and data analysis method according to claim 5, characterized in that: The data processing circuit board includes a PEX8648 switching module, and the PEX8648 switching module includes: a switching chip, a multi-channel PCIE X4 interface; The PEX8648 switching module includes a switching chip U2, 4 PCIE X4 interfaces and a single PCIE X4 interface, wherein a first end of the 4 PCIE X4 interface is connected to the VPX connector, a second end of the 4 PCIE X4 interface is connected to the switching chip U2, a first end of the single PCIE X4 interface is connected to the switching chip, and a second end of the single PCIE interface is connected to the T1042 data processing module; The above-mentioned PEX8648 switching module includes a network transmission indication pin of the switching chip U2 connected to an LED lamp holder to indicate the network transmission status.

10. A TTE analyzer and data analysis method according to claim 5, characterized in that: The data processing circuit board includes an RJ45 network port module, and the RJ45 network port module includes an Ethernet interface, a network transmission indicator light, and a capacitor filter network; The RJ45 network port module includes network signal transmission pins 1 to 8 of the Ethernet interface ETH0 for Gigabit Ethernet data transmission, an indicator light pin 9 of the Ethernet interface ETH0 receives a network activity signal GBE0 ACT N, and when data is transmitted, the LED light is on, the indicator light pin 9 of the Ethernet interface ETH0 is connected to the first end of the capacitor C6, the second end of the capacitor C6 is grounded, the indicator light pin 10 of the Ethernet interface ETH0 is connected to the first end of the resistor R9, and the second end of the resistor R9 is connected to the input voltage LED 2V5; The indicator light pin 11 of the Ethernet interface ETH0 receives the network connection signal LINK1000 N. When the link is successful, the LED lights up. The indicator light pin 11 of the Ethernet interface ETH0 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is grounded. The indicator light pin 12 of the Ethernet interface ETH0 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the input voltage LED2V5.

Images