Memory device based on ferroelectric field effect transistor and manufacturing method thereof

Abstract

The invention discloses a memory device based on a ferroelectric field effect transistor and a manufacturing method thereof. The memory device comprises a semiconductor substrate; the bottom gating transistor is positioned on one side of the semiconductor substrate; the control gate stack structure is located on one side, far away from the semiconductor substrate, of the bottom gate transistor, the control gate stack structure comprises a plurality of gate isolation layers and gate electrode layers, the gate isolation layers and the gate electrode layers are arranged in a staggered mode, and a first channel hole penetrating through the control gate stack structure is formed in the control gate stack structure; the gate stack layer is located on the side wall of the first channel hole and comprises a dielectric insertion layer, a ferroelectric layer and a bottom interface layer which are stacked in the direction from the control gate stack structure to the first channel hole; the first channel layer and the first channel isolation layer are located on the side, away from the control gate stack structure, of the gate stack layer; and the top gating transistor is positioned on one side, far away from the bottom gating transistor, of the control gate stack structure. The storage device has a larger storage window.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage device based on a ferroelectric field effect transistor and a manufacturing method thereof. Background Art

[0002] With the rapid development of information technology, the Internet and mobile devices have become more popular than ever before, leading to an explosive growth of information. Big data, cloud computing, high-definition video, the Internet of Things and other fields have put forward higher requirements for data storage. Among them, large-capacity storage has become a necessary requirement to meet the efficient storage, fast access and long-term retention of massive data, thereby supporting business continuity and innovative development, and ensuring the smooth operation and continuous progress of the information age.

[0003] At present, in order to meet the demand for large-capacity storage, existing companies usually increase the number of layers of storage cells to meet the demand for large-capacity storage of traditional charge-trapping-based 3D NAND flash memory. However, this approach has multiple challenges: first, as the number of 3D NAND layers increases, its manufacturing process becomes more complex and costly; second, the increase in the number of storage cell layers will increase the inter-layer interference, thereby affecting the reliability and performance of data; and, as the number of storage cell layers increases, the thermal management problem also increases, making it more difficult to dissipate heat for chips including the 3D NAND memory; and, further reducing the cell size also faces the challenge of physical limits, which limits further increases in storage density.

[0004] Ferroelectric field effect transistor (FeFET) is an emerging technology that has attracted widespread attention for its fast read and write speed, ultra-low power consumption and good CMOS compatibility, and is considered to be one of the strong candidates for high-performance memory. However, the storage window of the current hafnium-based ferroelectric transistor storage device is too small, which seriously restricts its application potential. Summary of the invention

[0005] In view of the above problems, the present application provides a storage device based on ferroelectric field effect transistors and a method for manufacturing the same, so as to increase the storage window of the storage device based on ferroelectric field effect transistors, thereby realizing high-density storage by adopting a multi-value storage method. The specific scheme is as follows:

[0006] A storage device based on a ferroelectric field effect transistor, the storage device comprising:

[0007] Semiconductor substrate;

[0008] a bottom gate transistor located on one side of the semiconductor substrate;

[0009] A control gate stack structure located on a side of the bottom gate transistor away from the semiconductor substrate, the control gate stack structure comprising: a plurality of staggered gate isolation layers and gate electrode layers, and a first channel hole penetrating the control gate stack structure;

[0010] A gate stack located on a sidewall of the first channel hole, the gate stack comprising a dielectric insertion layer, a ferroelectric layer and a bottom interface layer stacked along a direction from the control gate stack structure to the first channel hole;

[0011] A first channel layer and a first channel isolation layer located on a side of the gate stack away from the control gate stack structure;

[0012] A top gate transistor is located on a side of the control gate stack structure away from the bottom gate transistor.

[0013] Optionally, the dielectric intercalation layer is an Al2O3 layer, a SiO2 layer, a HfO2 layer, a ZrO2 layer or a TiO2 layer and any combination thereof.

[0014] Optionally, the thickness of the dielectric intercalation layer ranges from 1 nm to 15 nm.

[0015] Optionally, the dielectric intercalation layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

[0016] Optionally, the bottom interface layer is a SiO2 layer, an Al2O3 layer, a HfO2 layer, a TiO2 layer or a ZrO2 layer.

[0017] Optionally, the ferroelectric layer is a HfZrO layer or a HfSiO2 layer.

[0018] A method for manufacturing a storage device based on a ferroelectric field effect transistor, comprising:

[0019] forming a bottom gate transistor on one side of the semiconductor substrate;

[0020] A control gate stack structure is formed on a side of the bottom gate transistor away from the semiconductor substrate, the control gate stack structure comprising: a plurality of gate isolation layers and gate electrode layers arranged in an alternating manner, and a first channel hole penetrating the control gate stack structure is provided in the control gate stack structure;

[0021] forming a gate stack on the sidewall of the first channel hole, wherein the gate stack comprises a dielectric intercalation layer, a ferroelectric layer and a bottom interface layer stacked along the direction from the control gate stack structure to the first channel hole;

[0022] forming a first channel layer and a first channel isolation layer on a side of the gate stack away from the control gate stack structure;

[0023] A top gate transistor is formed on a side of the control gate stack structure away from the bottom gate transistor.

[0024] Optionally, the dielectric intercalation layer is an Al2O3 layer, a SiO2 layer, a HfO2 layer, a ZrO2 layer or a TiO2 layer and any combination thereof; the formation process of the dielectric intercalation layer is an atomic layer deposition process or a chemical vapor deposition process.

[0025] Optionally, the bottom interface layer is a SiO2 layer, an Al2O3 layer, a HfO2 layer, a TiO2 layer or a ZrO2 layer.

[0026] Optionally, the manufacturing method further includes: after the top gating transistor is formed, annealing the structure after the top gating transistor is formed to form a ferroelectric phase; wherein the annealing temperature ranges from 300°C to 900°C, and the annealing time ranges from 10S to 300S.

[0027] The multi-value storage device based on ferroelectric field effect transistor provided in the embodiment of the present application has an additional top dielectric intercalation layer between the ferroelectric layer and the control gate stack structure, and the top dielectric intercalation layer is located between the gate electrode layer in the control gate stack structure and the ferroelectric layer in the gate stack, so that the existence of the spontaneous polarization Ps of the ferroelectric layer can be used to induce the gate electrode layer to inject charges into the interface between the top dielectric intercalation layer and the ferroelectric layer and the defect sites inside the dielectric intercalation layer. This part of the charge has the opposite polarity to the charge injected by the first channel layer to the interface between the bottom interface layer and the ferroelectric layer, which is beneficial to the formation of a larger storage window for the storage device based on the ferroelectric field effect transistor, thereby realizing high-density storage of the storage device based on the ferroelectric field effect transistor through multi-value storage and reducing the cost per bit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0029] Figure 1 A schematic diagram of the structure of a storage device based on a ferroelectric field effect transistor provided in the present application;

[0030] Figure 2-Figure 11 A schematic diagram of some structures involved in a method for manufacturing a storage device based on a ferroelectric field effect transistor provided in the present application. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0032] It is obvious to those skilled in the art that various modifications and changes can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and changes of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0033] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0034] As mentioned in the background technology section, the storage window of the current hafnium-based ferroelectric transistor storage device is too small, which seriously restricts its application potential.

[0035] In view of this, an embodiment of the present application provides a storage device based on a ferroelectric field effect transistor. Optionally, the storage device may be a NAND memory or a NOR memory, but the present application does not limit this, and it depends on the specific circumstances. The following takes the storage device as an example of a NAND memory to describe the storage device provided in the embodiment of the present application. It should be noted that NAND memory is a non-volatile memory (NVM) that can maintain stored data even after the power is turned off. It is a type of flash memory and is widely used in storage devices such as solid-state drives (SSDs), USB flash drives, and SD cards. NAND memory is known for its high capacity, low cost, and long life. It is an important storage solution in technical fields such as big data, cloud computing, high-definition video, and the Internet of Things.

[0036] like Figure 1 As shown, the storage device based on ferroelectric field effect transistor provided in the embodiment of the present application includes:

[0037] The semiconductor substrate 10 may be a silicon substrate, a germanium substrate, or a third-generation semiconductor substrate, etc. The present application does not limit this, and the specific situation may vary.

[0038] A bottom gate transistor 20 located at one side of the semiconductor substrate 10;

[0039] A control gate stack structure 30 located at a side of the bottom gate transistor 20 away from the semiconductor substrate 10, the control gate stack structure comprising: a plurality of staggered gate isolation layers 31 and gate electrode layers 32, and a first channel hole penetrating the control gate stack structure 30;

[0040] A gate stack 33 located on the sidewall of the first channel hole, the gate stack 33 comprising a top dielectric insertion layer 331, a ferroelectric layer 332 and a bottom interface layer 333 stacked along the direction from the control gate stack structure to the first channel hole;

[0041] A first channel layer 34 and a first channel isolation layer 35 located on a side of the gate stack 33 away from the control gate stack structure 30;

[0042] A top gate transistor 40 is located at a side of the control gate stack structure 30 away from the bottom gate transistor 20 .

[0043] On the basis of any of the above embodiments, in one embodiment of the present application, the gate isolation layer may be a SiO2 layer or a low-k dielectric material layer. The thickness of the gate isolation layer ranges from 20 nm to 40 nm. Optionally, in one embodiment of the present application, the formation process of the gate isolation layer is ALD or CVD; wherein atomic layer deposition (ALD, atomic layer deposition) is a high-precision thin film deposition technology that deposits a single atomic layer of material on the substrate surface layer by layer through chemical vapor deposition. Chemical vapor deposition (CVD, Chemical Vapor Deposition) is a thin film preparation technology that deposits a solid film on the surface of a substrate through a chemical reaction of a gaseous precursor, but the present application does not limit this, and it depends on the specific circumstances. It should be noted that in this embodiment, the thickness of the gate isolation layer refers to the size of the gate isolation layer along the first direction, and the first direction is perpendicular to the plane where the semiconductor substrate is located.

[0044] On the basis of any of the above embodiments, in one embodiment of the present application, the material of the gate electrode layer is a conductive material such as TiN, W or polysilicon, and the thickness of the gate electrode layer ranges from 10nm to 40nm; optionally, in one embodiment of the present application, the formation process of the gate electrode layer is CVD (chemical vapor deposition) or PCD (physical vapor deposition), but the present application does not limit this, depending on the specific circumstances. It should be noted that in this embodiment, the thickness of the gate electrode layer is the size of the gate electrode layer along the first direction.

[0045] On the basis of any of the above embodiments, in one embodiment of the present application, the top dielectric intercalation layer (i.e., dielectric intercalation layer) is an Al2O3 layer, a SiO2 layer, a HfO2 layer, a ZrO2 layer, or a TiO2 layer, and any combination thereof, and the thickness of the top dielectric intercalation layer ranges from 1nm to 15nm, and can be optionally 1nm to 8nm; specifically, the formation process of the top dielectric intercalation layer can be ALD or CVD; wherein, atomic layer deposition (ALD, atomic layer deposition) is a high-precision thin film deposition technology that deposits a single atomic layer of material on the substrate surface layer by layer through chemical vapor deposition. Chemical vapor deposition (CVD, Chemical Vapor Deposition) is a thin film preparation technology that deposits a solid film on the substrate surface through a chemical reaction of a gaseous precursor, but the present application does not limit this, and it depends on the specific situation.

[0046] It should be noted that, in this embodiment, the thickness of the top dielectric intercalation layer is the dimension of the top dielectric intercalation layer along a second direction, the second direction is parallel to the plane where the semiconductor substrate is located, and points from the control gate stack structure to the first channel layer.

[0047] Based on any of the above embodiments, in one embodiment of the present application, the ferroelectric layer is Hf x Zr 1-x O2 layer or Hf x Si 1-x O2 layer and other ferroelectric material layers, the thickness of the ferroelectric layer ranges from 5nm to 10nm; optionally, in one embodiment of the present application, the ferroelectric layer is formed by ALD, i.e. atomic layer deposition, but the present application does not limit this, depending on the specific circumstances. It should be noted that in this embodiment, the thickness of the ferroelectric layer is the size of the ferroelectric layer along the second direction.

[0048] On the basis of any of the above embodiments, in one embodiment of the present application, the bottom interface layer is a high-k dielectric material layer such as a SiO2 layer, an Al2O3 layer, an HfO2 layer, a TiO2 layer or a ZrO2 layer, and the thickness of the bottom interface layer ranges from 5Å to 10Å. Optionally, the formation process of the bottom interface layer is ALD, i.e. atomic layer deposition, but the present application does not limit this, depending on the specific circumstances. It should be noted that in this embodiment, the thickness of the bottom interface layer is the size of the bottom interface layer along the second direction.

[0049] Optionally, in one embodiment of the present application, the thickness of the gate stack is not greater than 20nm, so that the storage device can achieve higher density storage, but the present application does not limit this. In other embodiments of the present application, the thickness of the gate stack may also be greater than 20nm, depending on the specific situation. It should be noted that in this embodiment, under the premise that the thickness of the gate stack is not greater than 20nm, the greater the thickness of the top dielectric intercalation layer, the more storage information the storage device can bear, but the present application does not limit this, depending on the specific situation.

[0050] It should be noted that, due to the existence of the large spontaneous polarization Ps of the ferroelectric layer, the ferroelectric field effect transistor causes the charge injection from the first channel layer to the bottom interface layer and the ferroelectric layer interface in the ferroelectric field effect transistor, which makes the storage window of the storage device based on the ferroelectric field effect transistor sharply reduced, close to the storage window of 1V. This brings severe challenges to the realization of high-density storage of the storage device based on the ferroelectric field effect transistor.

[0051] It should be noted that the large spontaneous polarization Ps of the ferroelectric layer in the ferroelectric field effect transistor refers to the large intrinsic dipole moment generated in each unit volume of the ferroelectric material due to the asymmetry of the crystal structure. It refers to the large dipole moment formed inside the material due to the structural characteristics in the absence of an external electric field. This inherent dipole moment has a direct impact on the charge storage capacity and switching speed of the ferroelectric field effect transistor. The ferroelectric layer with a high dielectric constant can enhance the current driving capability of the transistor and increase its operating speed. The main function of the ferroelectric layer in the ferroelectric field effect transistor is to serve as a gate material. Its large spontaneous polarization Ps can effectively regulate the threshold voltage of the transistor and maintain the state of the device after power failure, thereby realizing a non-volatile storage function.

[0052] The storage device based on ferroelectric field effect transistor provided in the embodiment of the present application has an additional top dielectric intercalation layer between the ferroelectric layer and the control gate stack structure, and the top dielectric intercalation layer is located between the gate electrode layer in the control gate stack structure and the ferroelectric layer in the gate stack, so that the existence of the spontaneous polarization Ps of the ferroelectric layer can be used to induce the gate electrode layer to inject charges into the interface between the top dielectric intercalation layer and the ferroelectric layer and the defect sites inside the dielectric intercalation layer. This part of the charge has the opposite polarity to the charge injected by the first channel layer to the interface between the bottom interface layer and the ferroelectric layer, which is beneficial to the formation of a larger storage window for the storage device based on the ferroelectric field effect transistor, thereby realizing high-density storage of the storage device based on the ferroelectric field effect transistor through multi-value storage, realizing high-density storage, and reducing the cost per bit.

[0053] In addition, in the storage device based on ferroelectric field effect transistor provided in the embodiment of the present application, the bottom interface layer adopts a higher dielectric constant material (such as Al2O3) or a high-k material (such as HfO2, ZrO2) or a dielectric material such as SiO2, TiO2, etc., which can reduce the electric field of the interface layer, and at the same time, it can also suppress the charge injection from the first channel layer to the bottom interface layer and the ferroelectric layer interface, further increase the storage window of the storage device, realize high-density storage, and reduce the cost per bit.

[0054] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Figure 1 As shown, the bottom gating transistor 20 includes a first selection isolation layer 21 and a first selection gate electrode layer 22 located on the first side of the semiconductor substrate 10, the first selection isolation layer 21 and the first selection gate electrode layer 22 form a first stacked structure with a second channel hole penetrating the first stacked structure, and a first gate dielectric layer 23, a second channel layer 24, and a second channel isolation layer 25 arranged in a direction away from the first stacked structure are formed on the sidewall of the second channel hole. Optionally, the bottom gating transistor 20 includes two first selection isolation layers 21 and one first selection gate electrode layer 22 located on the first side of the semiconductor substrate 10, and the first selection gate electrode layer 22 is located between the two first selection isolation layers 21.

[0055] Optionally, in one embodiment of the present application, in the first direction, the first gate dielectric layer is located between the gate stack and the semiconductor substrate, and the first gate dielectric layer and the gate stack meet an alignment condition; the second channel layer is located between the first channel layer and the semiconductor substrate, and meets an alignment condition with the first channel layer; the second channel isolation layer is located between the first channel isolation layer and the semiconductor substrate, and meets an alignment condition with the first channel isolation layer. It should be noted that in this embodiment, the alignment condition includes alignment and basic alignment (such as alignment within the allowable error range), which is not limited in this application and depends on the specific situation.

[0056] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Figure 1As shown, the top gating transistor 40 includes a second selection gate electrode layer 41 and a second selection isolation layer 42 located on a side of the control gate stack structure 30 away from the bottom gating transistor 20, and the second selection isolation layer 42 and the second selection gate electrode layer 41 form a second stacking structure with a third channel hole penetrating the second stacking structure, and a second gate dielectric layer 43, a third channel layer 44 and a third channel isolation layer 45 arranged in a direction away from the second stacking structure are formed on the sidewall of the third channel hole. Optionally, the gating transistor 40 includes a second selection gate electrode layer 41 and two second selection isolation layers 42 located on a side of the control gate stack structure 30 away from the bottom gating transistor 20, and the second selection gate electrode layer is located between the two second selection isolation layers 42.

[0057] Optionally, in one embodiment of the present application, in the first direction, the second gate dielectric layer is located on the side of the gate stack away from the first gate dielectric layer, and the second gate dielectric layer and the gate stack meet the alignment condition; the third channel layer is located on the side of the first channel layer away from the second channel layer, and meets the alignment condition with the first channel layer; the third channel isolation layer is located on the side of the first channel isolation layer away from the second channel isolation layer, and meets the alignment condition with the first channel isolation layer. It should be noted that in this embodiment, the alignment condition includes alignment and basic alignment (such as alignment within the allowable error range), which is not limited in this application and depends on the specific situation.

[0058] In the above embodiment, the first channel layer, the second channel layer and the third channel layer together constitute the channel layer of the storage device, and the first channel isolation layer, the second channel isolation layer and the third channel isolation layer together constitute the channel isolation layer of the storage device.

[0059] Optionally, in one embodiment of the present application, the channel layer of the storage device is a polysilicon layer, and the thickness of the storage device ranges from 100nm to 300nm; Optionally, in one embodiment of the present application, the formation process of the channel layer includes LPCVD (Low Pressure Chemical Vapor Deposition). Compared with chemical vapor deposition under normal pressure, LPCVD reduces the collision and scattering of gas molecules by reducing the pressure, thereby improving the deposition rate and uniformity of the film. This technology has better step coverage capability, good film quality, and can control the composition and structure of the film. Among them, the thickness of the channel layer of the storage device is the size of the channel layer of the storage device along the second direction.

[0060] On the basis of the above embodiments, in one embodiment of the present application, the channel isolation layer of the storage device is a low-k dielectric material layer such as a SiO2 layer, and the thickness of the channel isolation layer of the storage device ranges from 300 nm to 500 nm; optionally, in one embodiment of the present application, the formation process of the channel isolation layer of the storage device is CVD, i.e., chemical vapor deposition, but the present application does not limit this, and it depends on the specific circumstances. Among them, the thickness of the channel isolation layer of the storage device refers to the size of the channel isolation layer of the storage device along the second direction.

[0061] On the basis of any of the above embodiments, in one embodiment of the present application, the storage device further comprises: a bit line 50 located on a side of the channel layer of the storage device away from the semiconductor substrate. It should be noted that in other embodiments of the present application, the storage device may further comprise other structures such as a word line, a source, and a drain, which are already well known to those skilled in the art and will not be described in detail in the present application.

[0062] In summary, the storage device based on ferroelectric field effect transistor provided in the embodiment of the present application has an additional top dielectric intercalation layer between the ferroelectric layer and the control gate stack structure, and the top dielectric intercalation layer is located between the gate electrode layer in the control gate stack structure and the ferroelectric layer in the gate stack, so that the existence of the spontaneous polarization Ps of the ferroelectric layer can be used to induce the gate electrode layer to inject charges into the interface between the top dielectric intercalation layer and the ferroelectric layer and the defect sites inside the dielectric intercalation layer. This part of the charge has an opposite polarity to the charge injected by the first channel layer to the interface between the bottom interface layer and the ferroelectric layer, which is beneficial to the formation of a larger storage window for the storage device based on the ferroelectric field effect transistor, thereby realizing high-density storage of the storage device based on the ferroelectric field effect transistor through multi-value storage.

[0063] In addition, the present application also provides a method for manufacturing a storage device based on a ferroelectric field effect transistor, which is used to manufacture the storage device based on a ferroelectric field effect transistor provided in any of the above embodiments. Specifically, the manufacturing method includes:

[0064] S1: Figure 2 As shown, a bottom selection transistor 20 is formed on one side of the semiconductor substrate 10. Optionally, the semiconductor substrate 10 can be a silicon substrate, a germanium substrate, or a third-generation semiconductor substrate, etc. This application does not limit this, and it depends on the specific situation.

[0065] Optionally, in one embodiment of the present application, in one embodiment of the present application, continue as Figure 2As shown, the bottom gating transistor 20 includes a first selection isolation layer 21 and a first selection gate electrode layer 22 located on the first side of the semiconductor substrate 10, and the first selection isolation layer 21 and the first selection gate electrode layer 22 form a first stacked structure with a second channel hole penetrating the first stacked structure, and a first gate dielectric layer 23, a second channel layer 24, and a second channel isolation layer 25 arranged in a direction away from the first stacked structure are formed on the sidewall of the second channel hole. Specifically, the bottom gating transistor 20 includes two first selection isolation layers 21 and a first selection gate electrode layer 22 located on the first side of the semiconductor substrate 10, and the first selection gate electrode layer 22 is located between the two first selection isolation layers 21.

[0066] S2: forming a control gate stack structure on a side of the bottom selection transistor away from the semiconductor substrate, the control gate stack structure comprising: a plurality of staggered gate isolation layers and gate electrode layers, and a first channel hole penetrating the control gate stack structure.

[0067] Specifically, in one embodiment of the present application, a control gate stack structure is formed on the side of the bottom gate transistor away from the semiconductor substrate, the control gate stack structure comprising: a plurality of gate isolation layers and gate electrode layers arranged in an alternating manner, and a first channel hole penetrating the control gate stack structure in the control gate stack structure comprises:

[0068] like Figure 3 As shown, a control gate stack structure 30 is formed on the side of the bottom selection transistor 20 away from the semiconductor substrate 10, and the control gate stack structure 30 includes: a plurality of gate isolation layers 31 and a gate electrode layer 32 arranged in an alternating manner; wherein the gate isolation layer 31 and the first selection isolation layer 21 may be made of the same material;

[0069] like Figure 4 As shown, the control gate stack structure 30 is etched to form a first channel hole in the control gate stack structure 30 , and the first channel hole penetrates the control gate stack structure 30 .

[0070] Optionally, in one embodiment of the present application, the gate isolation layer may be a SiO2 layer or a low-k dielectric material layer. The thickness of the isolation layer ranges from 20 nm to 40 nm, but the present application does not limit this, depending on the specific circumstances. It should be noted that in this embodiment, the thickness of the gate isolation layer refers to the size of the gate isolation layer along the first direction, and the first direction is perpendicular to the plane where the semiconductor substrate is located.

[0071] Specifically, in one embodiment of the present application, forming a control gate stack structure 30 on the side of the bottom selection transistor 20 away from the semiconductor substrate 10 includes: alternately growing gate isolation layers 31 and gate electrode layers 32 on the side of the bottom selection transistor 20 away from the semiconductor substrate 10, with multiple layers of staggered gate isolation layers 31 and gate electrode layers 32.

[0072] Optionally, in one embodiment of the present application, the gate isolation layer is formed by ALD or CVD. Atomic layer deposition (ALD) is a high-precision thin film deposition technology that deposits a single atomic layer of material on the substrate surface layer by layer through chemical vapor deposition. Chemical vapor deposition (CVD) is a thin film preparation technology that deposits a solid film on the substrate surface through a chemical reaction of a gaseous precursor, but the present application does not limit this, and it depends on the specific situation.

[0073] Optionally, in one embodiment of the present application, the gate electrode layer is formed by CVD or PVD, ie, chemical vapor deposition or physical vapor deposition, but the present application does not limit this and it depends on the specific circumstances.

[0074] On the basis of the above embodiments, in one embodiment of the present application, the material of the gate electrode layer is a conductive material such as TiN, W or polysilicon, and the thickness of the gate electrode layer ranges from 10nm to 40nm; however, the present application does not limit this, and the specific situation depends on the specific situation. It should be noted that in this embodiment, the thickness of the gate electrode layer is the size of the gate electrode layer along the first direction.

[0075] S3: forming a gate stack on the sidewall of the first channel hole, wherein the gate stack includes a top dielectric insertion layer, a ferroelectric layer and a bottom interface layer stacked along a direction from the control gate stack structure to the first channel hole.

[0076] Specifically, in one embodiment of the present application, a gate stack is formed on the sidewall of the first channel hole, and the gate stack includes a top dielectric intercalation layer, a ferroelectric layer, and a bottom interface layer stacked along the direction from the control gate stack structure to the first channel hole, including:

[0077] like Figure 5 As shown, a gate stack 33 is formed on the surface of the first channel hole and the surface of the control gate stack structure 30, and the gate stack 33 includes a top dielectric insertion layer 331, a ferroelectric layer 332 and a bottom interface layer 333 stacked along the direction from the control gate stack structure to the first channel hole.

[0078] like Figure 6As shown, the gate stack 33 is etched to remove the portion of the gate stack 33 located on the upper surface of the control gate stack structure 30 and the portion located at the bottom of the first channel hole, and a gate stack 33 is formed on the sidewall of the first channel hole. The gate stack 33 includes a top dielectric insertion layer 331, a ferroelectric layer 332 and a bottom interface layer 333 stacked along the direction from the control gate stack structure to the first channel hole, and the area where the first channel hole is located between the bottom interface layer 333 is a first channel hole.

[0079] It should be noted that, in the above-mentioned embodiment, the gate stack is formed by sequentially forming a top dielectric intercalation layer, a ferroelectric layer and a bottom interface layer and then etching them uniformly to remove the portion of the gate stack located on the upper surface of the control gate stack structure and the portion located at the bottom of the first channel hole, but the present application does not limit this. In other embodiments of the present application, the gate stack can also be formed by forming one layer and etching one layer, such as including: forming a top dielectric intercalation layer, removing the portion of the top dielectric intercalation layer located on the upper surface of the control gate stack structure and the portion located at the bottom of the first channel hole, and retaining the portion of the top dielectric intercalation layer located on the side wall of the first channel hole; forming a ferroelectric layer, removing the portion of the ferroelectric layer located on the upper surface of the control gate stack structure and the portion located at the bottom of the first channel hole, and retaining the portion of the ferroelectric layer located on the side wall surface of the top dielectric intercalation layer; forming a bottom interface layer, removing the portion of the bottom interface layer located on the upper surface of the control gate stack structure and the portion located at the bottom of the first channel hole, and retaining the portion of the bottom interface layer located on the side wall surface of the ferroelectric layer. The present application does not limit this and it depends on the specific circumstances.

[0080] Optionally, in one embodiment of the present application, the top dielectric intercalation layer is a SiO2 layer, an Al2O3 layer, an HfO2 layer, a ZrO2 layer or a TiO2 layer and any combination thereof, and the thickness of the top dielectric intercalation layer ranges from 1nm to 15nm, specifically 1nm to 8nm; Optionally, the formation process of the top dielectric intercalation layer is ALD or CVD; wherein, atomic layer deposition (ALD, atomic layer deposition) is a high-precision thin film deposition technology that deposits a single atomic layer of material on the substrate surface layer by layer through chemical vapor deposition. Chemical vapor deposition (CVD, Chemical VaporDeposition) is a thin film preparation technology that deposits a solid film on the substrate surface through a chemical reaction of a gaseous precursor, but this application does not limit this, and it depends on the specific situation.

[0081] It should be noted that, in this embodiment, the thickness of the top dielectric intercalation layer is the dimension of the top dielectric intercalation layer along a second direction, the second direction is parallel to the plane where the semiconductor substrate is located, and points from the control gate stack structure to the first channel layer.

[0082] Based on any of the above embodiments, in one embodiment of the present application, the ferroelectric layer is Hf x Zr 1-x O2 layer or Hf x Si 1-x O2 layer and other material layers with ferroelectric properties, the thickness of the ferroelectric layer ranges from 5nm to 10nm; optionally, in one embodiment of the present application, the formation process of the ferroelectric layer is ALD, i.e. atomic layer deposition, and the deposition temperature ranges from 300°C, but the present application does not limit this, depending on the specific situation. It should be noted that in this embodiment, the thickness of the ferroelectric layer is the size of the ferroelectric layer along the second direction.

[0083] On the basis of any of the above embodiments, in one embodiment of the present application, the bottom interface layer is a high-k dielectric material layer such as a SiO2 layer, an Al2O3 layer, an HfO2 layer, a TiO2 layer or a ZrO2 layer, and the thickness of the bottom interface layer ranges from 5Å to 10Å. Optionally, the formation process of the bottom interface layer is ALD, i.e. atomic layer deposition, but the present application does not limit this, depending on the specific circumstances. It should be noted that in this embodiment, the thickness of the bottom interface layer is the size of the bottom interface layer along the second direction.

[0084] Optionally, in one embodiment of the present application, the thickness of the gate stack is not greater than 20nm, so that the storage device can achieve higher density storage, but the present application does not limit this. In other embodiments of the present application, the thickness of the gate stack may also be greater than 20nm, depending on the specific situation. It should be noted that in this embodiment, under the premise that the thickness of the gate stack is not greater than 20nm, the greater the thickness of the top dielectric intercalation layer, the more storage information the storage device can bear, but the present application does not limit this, depending on the specific situation.

[0085] It should be noted that, due to the existence of the large spontaneous polarization Ps of the ferroelectric layer, the ferroelectric field effect transistor causes the charge injection from the first channel layer to the bottom interface layer and the ferroelectric layer interface in the ferroelectric field effect transistor, which makes the storage window of the storage device based on the ferroelectric field effect transistor sharply reduced, close to the storage window of 1V. This brings severe challenges to the realization of high-density storage of the storage device based on the ferroelectric field effect transistor.

[0086] It should also be noted that the large spontaneous polarization Ps of the ferroelectric layer in the ferroelectric field effect transistor refers to the large intrinsic dipole moment generated in each unit volume of the ferroelectric material due to the asymmetry of the crystal structure. It refers to the large dipole moment formed inside the material due to the structural characteristics in the absence of an external electric field. This inherent dipole moment has a direct impact on the charge storage capacity and switching speed of the ferroelectric field effect transistor. The ferroelectric layer with a high dielectric constant can enhance the current driving capability of the transistor and increase its operating speed. The main function of the ferroelectric layer in the ferroelectric field effect transistor is to serve as a gate material. Its large spontaneous polarization Ps can effectively regulate the threshold voltage of the transistor and maintain the state of the device after power failure, thereby realizing a non-volatile storage function.

[0087] In the manufacturing method of the storage device based on ferroelectric field effect transistor provided in the embodiment of the present application, a top dielectric intercalation layer is added between the ferroelectric layer and the control gate stack structure, and the top dielectric intercalation layer is located between the gate electrode layer in the control gate stack structure and the ferroelectric layer in the gate stack, so that the existence of the spontaneous polarization Ps of the ferroelectric layer can be used to induce the gate electrode layer to inject charges into the interface between the top dielectric intercalation layer and the ferroelectric layer and the defect sites inside the dielectric intercalation layer. This part of the charge has the opposite polarity to the charge injected by the first channel layer to the interface between the bottom interface layer and the ferroelectric layer, which is beneficial to the formation of a larger storage window for the storage device based on the ferroelectric field effect transistor, thereby realizing high-density storage of the storage device based on the ferroelectric field effect transistor through multi-value storage.

[0088] In addition, in the method for manufacturing a storage device based on a ferroelectric field effect transistor provided in an embodiment of the present application, the bottom interface layer uses a higher dielectric constant material (such as Al2O3) or a high-k material (such as HfO2, ZrO2) or a dielectric material such as SiO2, TiO2, etc., which can reduce the electric field of the interface layer, and at the same time, it can also suppress the charge injection from the first channel layer to the bottom interface layer and the ferroelectric layer interface, further increasing the storage window of the storage device.

[0089] S4: forming a first channel layer and a first channel isolation layer on a side of the gate stack away from the control gate stack structure.

[0090] Optionally, in one embodiment of the present application, in the first direction, the first gate dielectric layer is located between the gate stack and the semiconductor substrate, and the first gate dielectric layer and the gate stack meet an alignment condition; the second channel layer is located between the first channel layer and the semiconductor substrate, and meets an alignment condition with the first channel layer; the second channel isolation layer is located between the first channel isolation layer and the semiconductor substrate, and meets an alignment condition with the first channel isolation layer. It should be noted that in this embodiment, the alignment condition includes alignment and basic alignment (such as alignment within the allowable error range), which is not limited in this application and depends on the specific situation.

[0091] Specifically, in one embodiment of the present application, forming a first channel layer and a first channel isolation layer on a side of the gate stack away from the control gate stack structure includes:

[0092] like Figure 7 As shown, a first channel layer 34 is deposited in the first channel hole, and the first channel layer 34 covers the surface of the first channel hole and the surface of the control gate stack structure 30 away from the bottom gate transistor 20;

[0093] like Figure 8 As shown, the first channel layer 35 is etched to remove the portion of the first channel layer 34 located on the surface of the control gate stack structure 30 away from the bottom gate transistor 20 and the bottom of the first channel hole, and only the portion of the first channel layer located on the side wall of the first channel hole is retained. The area where the first channel hole is located in the middle of the first channel layer is the second channel hole. Fig. 9 As shown, a first channel isolation layer 35 is deposited in the second channel hole.

[0094] It should be noted that when forming the first channel isolation layer, the first channel isolation layer that fills the second channel hole and covers the surface of the control gate stack structure away from the bottom enable transistor is first formed, and then the portion of the first channel isolation layer located on the surface of the control gate stack structure away from the bottom enable transistor is removed, leaving only the portion of the first channel isolation layer located in the second channel hole.

[0095] S5: Fig.10 As shown, a top gate transistor 40 is formed on a side of the control gate stack structure 30 away from the bottom gate transistor 20 .

[0096] Specifically, in one embodiment of the present application, continue as follows Fig.10As shown, the top gating transistor 40 includes a second selection gate electrode layer 41 and a second selection isolation layer 42 located on the side of the control gate stack structure 30 away from the bottom gating transistor 20, and the second selection isolation layer 42 and the second selection gate electrode layer 41 form a second stacking structure with a third channel hole penetrating the second stacking structure, and the sidewalls of the third channel hole are formed with a second gate dielectric layer 43, a third channel layer 44 and a third channel isolation layer 45 arranged in a direction away from the second stacking structure. Optionally, the gating transistor 40 includes a second selection gate electrode layer 41 and two second selection isolation layers 42 located on the side of the control gate stack structure 30 away from the bottom gating transistor 20, and the second selection gate electrode layer is located between the two second selection isolation layers 42. The second selection isolation layer 42 and the gate electrode isolation layer 31 may be made of the same material.

[0097] Optionally, in one embodiment of the present application, in the first direction, the second gate dielectric layer is located on the side of the gate stack away from the first gate dielectric layer, and the second gate dielectric layer and the gate stack meet the alignment condition; the third channel layer is located on the side of the first channel layer away from the second channel layer, and meets the alignment condition with the first channel layer; the third channel isolation layer is located on the side of the first channel isolation layer away from the second channel isolation layer, and meets the alignment condition with the first channel isolation layer. It should be noted that in this embodiment, the alignment condition includes alignment and basic alignment (such as alignment within the allowable error range), which is not limited in this application and depends on the specific situation.

[0098] In the above embodiment, the first channel layer, the second channel layer and the third channel layer together constitute the channel layer of the storage device, and the first channel isolation layer, the second channel isolation layer and the third channel isolation layer together constitute the channel isolation layer of the storage device.

[0099] Optionally, in one embodiment of the present application, the channel layer of the storage device is a polysilicon layer, and the thickness of the storage device ranges from 100nm to 300nm; Optionally, in one embodiment of the present application, the formation process of the channel layer includes LPCVD (Low Pressure Chemical Vapor Deposition), and the deposition temperature ranges from 400℃ to 700℃, but the present application does not limit this, and it depends on the specific situation. Compared with chemical vapor deposition under normal pressure, LPCVD reduces the collision and scattering of gas molecules by reducing the pressure, thereby improving the deposition rate and uniformity of the film. This technology has better step coverage capability, good film quality, and can control the composition and structure of the film. Among them, the thickness of the channel layer of the storage device is the size of the channel layer of the storage device along the second direction.

[0100] On the basis of the above embodiments, in one embodiment of the present application, the channel isolation layer of the storage device is a low-k dielectric material layer such as a SiO2 layer, and the thickness of the channel isolation layer of the storage device ranges from 300 nm to 500 nm; optionally, in one embodiment of the present application, the formation process of the channel isolation layer of the storage device is CVD, i.e., chemical vapor deposition, but the present application does not limit this, and it depends on the specific circumstances. Among them, the thickness of the channel isolation layer of the storage device refers to the size of the channel isolation layer of the storage device along the second direction.

[0101] On the basis of any of the above embodiments, in one embodiment of the present application, the manufacturing method further comprises: after the top gating transistor is formed, annealing is performed to form a ferroelectric phase. Optionally, in one embodiment of the present application, the structure after the top gating transistor is formed is annealed in a gas atmosphere such as N2, NH3 or O2, the annealing temperature ranges from 300°C to 900°C, further optionally 500°C to 800°C, and the annealing time ranges from 10S to 300S, further optionally 10S to 60S, but the present application does not limit this, and it depends on the specific situation.

[0102] Based on any of the above embodiments, in one embodiment of the present application, Fig.11 As shown, the manufacturing method further includes: forming a bit line 50 on the side of the channel layer of the memory device away from the semiconductor substrate. It should be noted that in other embodiments of the present application, the memory device may also include other structures such as word lines, source electrodes, and drain electrodes, which are well known to those skilled in the art and will not be described in detail in the present application.

[0103] In summary, in the manufacturing method of the storage device based on ferroelectric field effect transistor provided in the embodiment of the present application, a top dielectric intercalation layer is added between the ferroelectric layer and the control gate stack structure, and the top dielectric intercalation layer is located between the gate electrode layer in the control gate stack structure and the ferroelectric layer in the gate stack, so that the existence of the spontaneous polarization Ps of the ferroelectric layer can be used to induce the gate electrode layer to inject charges into the interface between the top dielectric intercalation layer and the ferroelectric layer and the defect sites inside the dielectric intercalation layer. This part of the charge has an opposite polarity to the charge injected by the first channel layer to the interface between the bottom interface layer and the ferroelectric layer, which is beneficial to the formation of a larger storage window for the storage device based on the ferroelectric field effect transistor, thereby realizing high-density storage of the storage device based on the ferroelectric field effect transistor through multi-value storage.

[0104] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0105] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0106] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0107] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A storage device based on a ferroelectric field effect transistor, characterized in that: The storage device comprises: Semiconductor substrate; a bottom gate transistor located on one side of the semiconductor substrate; A control gate stack structure located on a side of the bottom gate transistor away from the semiconductor substrate, the control gate stack structure comprising: a plurality of staggered gate isolation layers and gate electrode layers, and a first channel hole penetrating the control gate stack structure; A gate stack located on the sidewall of the first channel hole, the gate stack comprising a dielectric insertion layer, a ferroelectric layer and a bottom interface layer stacked along the direction from the control gate stack structure to the first channel hole; A first channel layer and a first channel isolation layer located on a side of the gate stack away from the control gate stack structure; A top gate transistor is located on a side of the control gate stack structure away from the bottom gate transistor.

2. The storage device according to claim 1, characterized in that The dielectric intercalation layer is an Al2O3 layer, a SiO2 layer, a HfO2 layer, a ZrO2 layer or a TiO2 layer and any combination thereof.

3. The storage device according to claim 2, characterized in that: The thickness of the dielectric intercalation layer ranges from 1 nm to 15 nm.

4. The storage device according to claim 1, characterized in that: The dielectric intercalation layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

5. The storage device according to claim 1, characterized in that: The bottom interface layer is a SiO2 layer, an Al2O3 layer, a HfO2 layer, a TiO2 layer or a ZrO2 layer.

6. The storage device according to claim 1, characterized in that: The ferroelectric layer is Hf x Zr 1-x O2 layer or Hf x Si 1-x O2 layer.

7. A method for manufacturing a storage device based on a ferroelectric field effect transistor, characterized in that: include: forming a bottom gate transistor on one side of the semiconductor substrate; A control gate stack structure is formed on a side of the bottom gate transistor away from the semiconductor substrate, the control gate stack structure comprising: a plurality of gate isolation layers and gate electrode layers arranged in an alternating manner, and a first channel hole penetrating the control gate stack structure is provided in the control gate stack structure; forming a gate stack on the sidewall of the first channel hole, wherein the gate stack comprises a dielectric intercalation layer, a ferroelectric layer and a bottom interface layer stacked along the direction from the control gate stack structure to the first channel hole; forming a first channel layer and a first channel isolation layer on a side of the gate stack away from the control gate stack structure; A top gate transistor is formed on a side of the control gate stack structure away from the bottom gate transistor.

8. The method according to claim 7, characterized in that: The dielectric intercalation layer is an Al2O3 layer, a SiO2 layer, a HfO2 layer, a ZrO2 layer or a TiO2 layer and any combination thereof; the formation process of the dielectric intercalation layer is an atomic layer deposition process or a chemical vapor deposition process.

9. The manufacturing method according to claim 7, characterized in that: The bottom interface layer is a SiO2 layer, an Al2O3 layer, a HfO2 layer, a TiO2 layer or a ZrO2 layer.

10. The manufacturing method according to claim 7, characterized in that: The manufacturing method also includes: after the top gating transistor is formed, annealing the structure after the top gating transistor is formed to form a ferroelectric phase; wherein the annealing temperature ranges from 300°C to 900°C, and the annealing time ranges from 10S to 300S.

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