Display device

Abstract

A display device includes: a substrate including a display area and a non-display area surrounding a through hole; a bank structure on the display area of the substrate and defining an opening; a light emitting element overlapping the opening; and a pattern structure on the non-display area and between the bank structure and the through hole. The pattern structure includes a first pattern dam and a second pattern dam spaced apart from each other, and a recessed portion is defined between the first pattern dam and the second pattern dam, the recessed portion is recessed toward the substrate, the first pattern dam includes a first pattern layer and a second pattern layer, and the second pattern layer includes a second pattern layer. The first pattern layer and the second pattern layer include their respective conductive materials different from each other, and a side portion of the second pattern layer toward the recessed portion protrudes more toward the recessed portion than a side portion of the first pattern layer toward the recessed portion.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0082304, filed on June 27, 2023, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] With the development of the information age, the demand for display devices for displaying images has increased in various forms. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigators, and smart TVs. The display device may be a flat panel display device, such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among the flat panel display devices, the light emitting display device includes a light emitting element, wherein each pixel of the display panel can emit light by itself, so that an image can be displayed even without a backlight unit that provides light for the display panel. Summary of the invention

[0004] An aspect of the present disclosure is to provide a display device that solves a film gap defect near a through hole.

[0005] Aspects of the present disclosure are not limited to those mentioned above, and additional aspects of the present disclosure not mentioned herein will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0006] In one embodiment of the present disclosure, a display device includes: a substrate including a display area and a non-display area surrounding a through hole; a dam structure located on the display area of ​​the substrate and defining an opening in the dam structure; a light-emitting element overlapping the opening in a plan view; and a pattern structure located on the non-display area of ​​the substrate and between the dam structure and the through hole, wherein the pattern structure includes a first pattern dam and a second pattern dam spaced apart from the first pattern dam, and a recessed portion is defined between the first pattern dam and the second pattern dam, the recessed portion being recessed toward the substrate, the first pattern dam including a first pattern layer and a second pattern layer, the first pattern layer and the second pattern layer containing their respective conductive materials different from each other, and a side of the second pattern layer facing the recessed portion protrudes more toward the recessed portion than at least a portion of a side of the first pattern layer facing the recessed portion.

[0007] In one embodiment, the dam structure may include a first dam layer and a second dam layer including their respective conductive materials different from each other, and a side of the second dam layer may include an end protruding more toward the opening than a side of the first dam layer.

[0008] In one embodiment, the first pattern layer may include the same material as that of the first bank layer, and the second pattern layer may include the same material as that of the second bank layer.

[0009] In one embodiment, the thickness of the first pattern layer in a direction perpendicular to the main surface of the substrate may be greater than the thickness of the second pattern layer in the direction.

[0010] In one embodiment, the first pattern layer and the first bank layer may include aluminum (Al), and the second pattern layer and the second bank layer may include titanium (Ti).

[0011] In one embodiment, the display device may further include: a first encapsulation layer located on the bank structure and the pattern structure and comprising an inorganic material; and a second encapsulation layer located on the first encapsulation layer and comprising an organic material, wherein the first encapsulation layer covers the entire pattern structure.

[0012] In one embodiment, the second encapsulation layer may partially contact the bank structure, and the second encapsulation layer does not overlap the pattern structure in a plan view.

[0013] In an embodiment, the display device may further include a third encapsulation layer overlapping the non-display area and located on the first encapsulation layer, wherein the third encapsulation layer covers the entirety of a portion of the first encapsulation layer inside the recessed portion.

[0014] In an embodiment, the display device may further include a main dam between the pattern structure and the bank structure, wherein the main dam includes a first dam layer and a second dam layer, the first dam layer and the second dam layer including their respective conductive materials different from each other.

[0015] In an embodiment, the first dam layer may include the same material as that of the first bank layer, and the second dam layer may include the same material as that of the second bank layer.

[0016] In one embodiment, the light emitting element may include: a first electrode overlapping the opening in a plan view; a light emitting layer on the first electrode; and a second electrode on the light emitting layer, and the second electrode may contact a side of the first bank layer.

[0017] In one embodiment, the second electrode may overlap with a protruding end of the second bank layer in a plan view.

[0018] In one embodiment, the display device may further include: an organic pattern located on the second bank layer and including the same material as that of the light emitting layer; and an electrode pattern located on the organic pattern and including the same material as that of the second electrode.

[0019] In one embodiment, the organic pattern may be spaced apart from the light emitting layer, and the electrode pattern may be spaced apart from the second electrode.

[0020] In an embodiment, the substrate may include an inclined surface in a direction toward the through hole.

[0021] In one embodiment, the display device may further include an optical device inside the through hole.

[0022] In one embodiment, the second pattern dam may include a third pattern layer and a fourth pattern layer, the third pattern layer and the fourth pattern layer contain their respective conductive materials different from each other, and a side of the fourth pattern layer facing the recessed portion protrudes more toward the recessed portion than at least a portion of the side of the third pattern layer facing the recessed portion.

[0023] In one embodiment of the present disclosure, a display device includes: a substrate including a display area and a non-display area surrounding a through hole; a dam structure located on the display area of ​​the substrate and defining an opening in the dam structure; a light-emitting element overlapping the opening in a plan view; and a pattern structure located on the non-display area of ​​the substrate and between the dam structure and the through hole, wherein the pattern structure includes a first pattern dam that completely surrounds the through hole in a plan view, the first pattern dam includes a first pattern layer and a second pattern layer, the width of the lower surface of the second pattern layer in a direction parallel to the main surface of the substrate is greater than the width of the upper surface of the first pattern layer in the direction, and the opposite sides of the second pattern layer are respectively more protruding than at least a portion of the opposite sides of the first pattern layer.

[0024] In one embodiment, the display device may further include a second pattern dam completely surrounding the through hole and the first pattern dam in a plan view, wherein the second pattern dam may be spaced apart from the first pattern dam and define a recessed portion between the second pattern dam and the first pattern dam, the recessed portion being recessed toward the substrate.

[0025] In one embodiment, the display device may further include a main dam completely surrounding the first pattern dam and the second pattern dam in a plan view, wherein the main dam may include a first dam layer and a second dam layer, a first side portion of the second dam layer facing the dam structure may protrude more toward the dam structure than at least a portion of the first side portion of the first dam layer facing the dam structure, and a second side portion of the second dam layer facing the pattern structure may protrude more toward the pattern structure than at least a portion of the second side portion of the first dam layer facing the pattern structure.

[0026] The display device according to one embodiment includes a pattern dam near the through hole, so that a film gap defect near the through hole can be effectively solved.

[0027] The effects according to the embodiments of the present disclosure are not limited to those mentioned above, and more various effects are included in the following description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0029] Figure 1 is a perspective view illustrating a display device according to an embodiment;

[0030] Figure 2 is a plan view illustrating a display panel according to an embodiment;

[0031] Figure 3 As an example, follow Figure 1 A cross-sectional view of an example of a display device taken along line II';

[0032] Figure 4 is a cross-sectional view illustrating an example of a display device, wherein Figure 3 The circuit board is bent;

[0033] Figure 5 A plan view illustrating an arrangement of light emitting areas in a display area of ​​a display device according to an embodiment;

[0034] Figure 6 As an example, follow Figure 5 A cross-sectional view of an example of a display device taken along line X1-X1';

[0035] Figure 7 As an example Figure 6 An enlarged cross-sectional view of a first light emitting region;

[0036] Figure 8 As an example Figure 2 an enlarged plan view of area "H";

[0037] Fig. 9 As an example, follow Figure 8 A cross-sectional view of an example of a display panel taken along line H1-H1';

[0038] Fig.10 is a cross-sectional view illustrating a display panel, wherein Fig. 9 The area "J" is enlarged;

[0039] Fig.11 is a cross-sectional view illustrating a display panel, wherein Fig.10 The area "K" is enlarged;

[0040] Fig.12 As an example Figure 2 an enlarged plan view of area "Q"; and

[0041] Fig.13 As an example, follow Fig.12 A cross-sectional view of the display device taken along line YY'. DETAILED DESCRIPTION

[0042] Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings.

[0043] It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings herein.

[0044] The terms used in this article are only used for the purpose of describing specific embodiments and are not intended to be limiting. As used in this article, the singular forms "one" and "said" are intended to include plural forms, including "at least one", unless the content clearly indicates otherwise. "Or" means "and / or". As used in this article, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It will be further understood that the terms "include" and / or "comprise" when used in this specification specify the presence of the described features, regions, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, parts and / or groups thereof.

[0045] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as illustrated in the figure. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the figure. For example, if the device in one of the figures in the figure is turned over, the element described as being on the "lower" side of the other element will then be oriented on the "upper" side of the other element. Therefore, depending on the specific orientation of the figure, the term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device in one of the figures in the figure is turned over, the element described as being "below" or "below" the other element will then be oriented "above" the other element. The term "below" or "below" therefore can cover both upper and lower orientations.

[0046] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation of a particular value determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, a term such as "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0048] Figure 1 is a perspective view illustrating a display device according to an embodiment. Figure 2 is a plan view illustrating a display panel according to an embodiment. As used herein, a "plan view" refers to a substrate 110 (see, e.g., Figure 3 ) in the thickness direction (Z-axis direction).

[0049] refer to Figure 1 According to one embodiment, the display device 10 is a device for displaying moving images or still images, and can be used as a display screen for various products, such as televisions, laptop computers, monitors, billboards, and Internet of Things (“IoT”) devices, as well as portable electronic devices, such as mobile phones, smart phones, tablet personal computers (“PCs”), smart watches, watch phones, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (“PMPs”), navigators, and ultra mobile personal computers (“UMPCs”).

[0050] The display device 10 according to one embodiment may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro (or nano) light-emitting display device using a micro (or nano) light-emitting diode (micro LED or nano LED). The following description will be based on the display device 10 being an organic light-emitting display device, but the present disclosure is not limited thereto.

[0051] The display device 10 according to one embodiment may include a display panel 100 , a display driver 200 , and a circuit board 300 .

[0052] The display panel 100 may be formed as a plane having a rectangular shape having a long side in a first direction (X-axis direction) and a short side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). A corner where the long side in the first direction (X-axis direction) and the short side in the second direction (Y-axis direction) intersect may be formed at a right angle or be rounded to have a curvature. The plane shape of the display panel 100 is not limited to a rectangular shape, and may be formed in another polygonal shape, a circular shape, or an elliptical shape.

[0053] The display panel 100 may be formed to be flat, but is not limited thereto. For another example, the display panel 100 may include curved portions having a constant curvature or a variable curvature formed at the left and right ends. In addition, the display panel 100 may be flexibly formed to be curved, bent, folded, or rolled.

[0054] The display panel 100 may include a display area DA for displaying an image and a non-display area NDA which is not used to display an image.

[0055] The display area DA may occupy most of the area of ​​the display panel 100. The display area DA may be disposed at the center of the display panel 100. Pixels each including a plurality of light emitting areas may be disposed in the display area DA to display an image.

[0056] The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2. The first non-display area NDA1 may be disposed at one side of the display area DA. The first non-display area NDA1 may be disposed to surround the through hole TH. The through hole TH is a hole through which light may be transmitted and may be an optical device ( Figure 3 500) is set in the area therein.

[0057] The second non-display area NDA2 may be disposed adjacent to the display area DA. The second non-display area NDA2 may be an outer area of ​​the display area DA. The second non-display area NDA2 may be disposed to surround the display area DA. The second non-display area NDA2 may be an edge area of ​​the display panel 100.

[0058] refer to Figure 1 and Figure 2 , the second non-display area NDA2 may include a display pad PD, a display driver 200 , and a circuit board 300 .

[0059] The display pad PD may be disposed on one edge of the display panel 100. For example, the display pad PD may be disposed at a lower edge of the display panel 100. The display pad PD may be connected to the display driver 200 and the circuit board 300.

[0060] The display driver 200 may generate and output signals and voltages for driving the display panel 100. In detail, the display driver 200 may generate and output data voltages, power voltages, scan timing signals, etc. The display driver 200 may supply power voltages to power lines, and may provide gate control signals to the gate driver.

[0061] The display driver 200 may be disposed in the second non-display area NDA2 between the display pad PD and the display area DA. The display driver 200 may be attached to the second non-display area NDA2 of the display panel 100 in a chip on glass (“COG”) manner. Alternatively, the display driver 200 may be attached to the circuit board 300 in a chip on plastic (“COP”) manner.

[0062] The circuit board 300 may be disposed at one edge of the display panel 100 and may be disposed on the display pad PD. The circuit board 300 may be attached to the display pad PD by using a conductive adhesive member such as an anisotropic conductive film and an anisotropic conductive adhesive. Thus, the circuit board 300 may be electrically connected to a signal line of the display panel 100. The circuit board 300 may be a flexible printed circuit board or a flexible film such as a chip on film.

[0063] Although not shown, a bending area may be disposed between the display driver 200 and the display area DA in the second non-display area NDA2. The bending area may be an area that is bent so that the display driver 200 and the circuit board 300 are disposed below the display panel 100. The display driver 200 and the circuit board 300 bent by the bending area may overlap the display area DA in the third direction (Z-axis direction).

[0064] Figure 3 As an example, follow Figure 1 A cross-sectional view of an example of a display device taken along line II'. Figure 4 is a cross-sectional view illustrating an example of a display device, wherein Figure 3 The circuit board in the circuit board is bent.

[0065] refer to Figure 3 According to an embodiment, the display device 10 may include a display panel 100, a polarizing film 190, a cover window CW, and a panel cover 400. The display panel 100 may include a substrate 110, a thin film transistor layer 130, a display element layer 150, a thin film encapsulation layer 170, and a touch sensor layer 180.

[0066] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate capable of being bent, folded, curled, etc. For example, the substrate 110 may include a polymer resin such as polyimide ("PI"), but is not limited thereto. In another embodiment, the substrate 110 may include a glass material or a metal material.

[0067] The thin film transistor layer 130 may be disposed on the substrate 110. The thin film transistor layer 130 may include a plurality of thin film transistors. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode.

[0068] The display element layer 150 may be disposed on the thin film transistor layer 130. The display element layer 150 may include a plurality of light emitting elements and a pixel defining layer for defining pixels, the light emitting elements including a pixel electrode, a common electrode and a light emitting layer to emit light. The plurality of light emitting elements may be disposed in the display area DA.

[0069] The thin film encapsulation layer 170 may be located on the display element layer 150. The thin film encapsulation layer 170 may cover the upper surface and the side of the display element layer 150 to prevent oxygen or moisture from penetrating into the display element layer 150. The thin film encapsulation layer 170 may include at least one inorganic layer and at least one organic layer.

[0070] The touch sensor layer 180 may be disposed on the thin film encapsulation layer 170. The touch sensor layer 180 may include sensor electrodes. The touch sensor layer 180 may sense a user's touch by using the sensor electrodes.

[0071] The polarizing film 190 may be disposed on the touch sensor layer 180. The polarizing film 190 may be disposed on the display panel 100 to reduce external light reflection. The polarizing film 190 may include a first substrate member, a linear polarizing plate, a phase retardation film (such as a quarter wave (λ / 4) plate), and a second substrate member. The first substrate member, the phase retardation film, the linear polarizing plate, and the second substrate member may be sequentially stacked on the display panel 100.

[0072] The cover window CW may be disposed on the polarizing film 190. The cover window CW may be attached to the polarizing film 190 by a transparent adhesive member such as an optically clear adhesive ("OCA").

[0073] The panel lower cover 400 may be disposed on the lower surface of the substrate 110. The lower surface of the substrate 110 may be an opposite surface to the upper surface. In other words, the lower surface of the substrate 110 may be an opposite surface to the surface on which the thin film transistor layer 130, the display element layer 150, the thin film encapsulation layer 170, and the touch sensor layer 180 are located. The panel lower cover 400 may be attached to the lower surface of the substrate 110 by an adhesive member. The adhesive member may be a pressure sensitive adhesive ("PSA").

[0074] The panel lower cover 400 may include at least one of a light shielding member for absorbing light incident from the outside, a buffering member for absorbing impact from the outside, and a heat dissipation member for effectively discharging heat.

[0075] In some embodiments, the display device 10 may further include an optical device 500. The optical device 500 may emit or receive infrared light, ultraviolet light, or light in the visible band. For example, the optical device 500 may be an optical sensor for sensing light incident on the display device 10, such as a proximity sensor, an illumination sensor, a camera sensor, or an image sensor.

[0076] The optical device 500 may be disposed in the through hole TH. The through hole TH is a hole capable of transmitting light, and may be a solid hole passing through the panel cover lower 400, the display panel 100, and the polarizing film 190, but the present disclosure is not limited thereto. In another embodiment, the through hole TH may pass through the panel cover lower 400, but may not pass through the display panel 100 and the polarizing film 190. The cover window CW may be disposed to cover the through hole TH.

[0077] refer to Figure 4 , the display driver 200 and the circuit board 300 may be bent toward the lower portion of the display panel 100. The circuit board 300 may be attached to the lower surface of the panel lower cover 400 by an adhesive member 310. The adhesive member 310 may be a pressure sensitive adhesive.

[0078] Figure 5 is a plan view illustrating the arrangement of the light emitting areas EA1 , EA2 , and EA3 in the display area DA of the display device 10 according to one embodiment.

[0079] refer to Figure 5 , the display device 10 may include a plurality of light emitting areas EA1, EA2, and EA3 disposed in the display area DA. The light emitting areas EA1, EA2, and EA3 may include a first light emitting area EA1, a second light emitting area EA2, and a third light emitting area EA3 that emit light of different colors. The first to third light emitting areas EA1, EA2, and EA3 may emit red light, green light, and blue light, respectively, and the color of light emitted from each of the light emitting areas EA1, EA2, and EA3 may depend on the light emitting element ( Figure 6 For example, the first light emitting area EA1 may emit a red first light, the second light emitting area EA2 may emit a green second light, and the third light emitting area EA3 may emit a blue third light, but the present disclosure is not limited thereto.

[0080] Multiple light emitting areas EA1, EA2 and EA3 can Type setting, such as diamond For example, the first light emitting area EA1 and the third light emitting area EA3 may be spaced apart from each other in the first direction (X-axis direction), and may be alternately arranged in the first direction (X-axis direction) and the second direction (Y-axis direction). In the arrangement of the light emitting areas EA1, EA2, and EA3, the first light emitting area EA1 and the third light emitting area EA3 may be alternately arranged in the first direction (X-axis direction) in the first row R1 and the third row R3. The first light emitting area EA1 and the third light emitting area EA3 may be alternately arranged in the second direction (Y-axis direction) in the first column C1 and the third column C3.

[0081] The second light emitting area EA2 may be spaced apart from another second light emitting area EA2 adjacent thereto in the first direction (X-axis direction) and the second direction (Y-axis direction), and may be spaced apart from the first light emitting area EA1 and the third light emitting area EA3 adjacent thereto in the fourth direction DR4 or the fifth direction DR5. A plurality of second light emitting areas EA2 may be repeatedly arranged along the first direction (X-axis direction) and the second direction (Y-axis direction), and the second light emitting area EA2 and the first light emitting area EA1 or the second light emitting area EA2 and the third light emitting area EA3 may be alternately arranged along the fourth direction DR4 or the fifth direction DR5. In the arrangement of the light emitting areas EA1, EA2, and EA3, the second light emitting area EA2 may be repeatedly arranged in the first direction (X-axis direction) in the second row R2 and the fourth row R4, and the second light emitting area EA2 may be repeatedly arranged in the second direction (Y-axis direction) in the second column C2 and the fourth column C4.

[0082] The first to third light emitting areas EA1, EA2, and EA3 may be formed by a pixel defining layer ( Figure 6 The first opening OP1 defined by the 151) and the embankment structure ( Figure 6 The second opening OP2 defined by 160) is defined, which will be described later.

[0083] In the display device 10, one first light emitting area EA1, two second light emitting areas EA2, and one third light emitting area EA3 disposed adjacent to each other may form one pixel group. One pixel group may include light emitting areas EA1, EA2, and EA3 emitting light of different colors, thereby expressing a white grayscale, but the present disclosure is not limited thereto. The combination of light emitting areas EA1, EA2, and EA3 constituting one pixel group may be modified in various ways depending on the arrangement of the light emitting areas EA1, EA2, and EA3 and the color of light emitted from the light emitting areas EA1, EA2, and EA3.

[0084] Figure 6 As an example, follow Figure 5 A cross-sectional view of an example of the display device 10 taken along line X1 - X1 ′. Figure 7 As an example Figure 6 FIG. 1 is an enlarged cross-sectional view of the first light emitting area EA1.

[0085] refer to Figure 6 , the display panel 100 may include a substrate 110 , a thin film transistor layer 130 , a display element layer 150 , a thin film encapsulation layer 170 and a touch sensor layer 180 .

[0086] The substrate 110 has already been mentioned, and thus a description thereof will be omitted.

[0087] The thin film transistor layer 130 may include a first buffer layer 111, a lower metal layer BML, a second buffer layer 113, a thin film transistor TFT, a gate insulating layer 131, a first interlayer insulating layer 133, a capacitor electrode CPE, a second interlayer insulating layer 135, a first connection electrode CNE1, a first passivation layer 137, a second connection electrode CNE2 and a second passivation layer 139.

[0088] The first buffer layer 111 may be disposed on the substrate 110. The first buffer layer 111 may include an inorganic layer capable of preventing air or moisture from penetrating. For example, the first buffer layer 111 may include a plurality of inorganic layers alternately stacked.

[0089] The lower metal layer BML may be disposed on the first buffer layer 111. For example, the lower metal layer BML may be formed of a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0090] The second buffer layer 113 may cover the first buffer layer 111 and the lower metal layer BML. The second buffer layer 113 may include an inorganic layer capable of preventing air or moisture from penetrating. For example, the second buffer layer 113 may include a plurality of inorganic layers alternately stacked.

[0091] The thin film transistor TFT may be disposed on the second buffer layer 113 and may constitute a pixel circuit of each of the plurality of pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0092] The semiconductor layer ACT may be disposed on the second buffer layer 113. The semiconductor layer ACT may overlap the lower metal layer BML and the gate electrode GE in the thickness direction (ie, the Z-axis direction), and may be insulated from the gate electrode GE by the gate insulating layer 131. A portion of the semiconductor layer ACT may be conductorized to form a source electrode SE and a drain electrode DE.

[0093] The gate electrode GE may be disposed on the gate insulating layer 131. In a plan view, the gate electrode GE may overlap the semiconductor layer ACT with the gate insulating layer 131 interposed therebetween.

[0094] The gate insulating layer 131 may be disposed on the semiconductor layer ACT. For example, the gate insulating layer 131 may cover the semiconductor layer ACT and the second buffer layer 113 and may insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer 131 may include a contact hole through which the first connection electrode CNE1 passes.

[0095] The first interlayer insulating layer 133 may cover the gate electrode GE and the gate insulating layer 131. The first interlayer insulating layer 133 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer 133 may be connected to the contact hole of the gate insulating layer 131 and the contact hole of the second interlayer insulating layer 135.

[0096] The capacitor electrode CPE may be disposed on the first interlayer insulating layer 133. The capacitor electrode CPE may overlap the gate electrode GE in the thickness direction (ie, the Z-axis direction). The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0097] The second interlayer insulating layer 135 may cover the capacitor electrode CPE and the first interlayer insulating layer 133. The second interlayer insulating layer 135 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer 135 may be connected to the contact hole of the first interlayer insulating layer 133 and the contact hole of the gate insulating layer 131.

[0098] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer 135. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole formed in the second interlayer insulating layer 135, the first interlayer insulating layer 133, and the gate insulating layer 131 to contact the drain electrode DE of the thin film transistor TFT.

[0099] The first passivation layer 137 may cover the first connection electrode CNE1 and the second interlayer insulating layer 135. The first passivation layer 137 may protect the thin film transistor TFT. The first passivation layer 137 may include a contact hole through which the second connection electrode CNE2 passes.

[0100] The second connection electrode CNE2 may be disposed on the first passivation layer 137. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 with the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer 137 to contact the first connection electrode CNE1.

[0101] The second passivation layer 139 may cover the second connection electrode CNE2 and the first passivation layer 137. The second passivation layer 139 may include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3 pass.

[0102] The display element layer 150 may be disposed on the thin film transistor layer 130. The display element layer 150 may include light emitting elements ED1, ED2, and ED3, an inorganic pixel defining layer 151, and a bank structure 160.

[0103] refer to Figure 6and Figure 7 , the light emitting elements ED1, ED2, and ED3 may be disposed on the second passivation layer 139. The light emitting elements ED1, ED2, and ED3 may include first electrodes (hereinafter, referred to as pixel electrodes) AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and second electrodes (hereinafter, referred to as common electrodes) CE1, CE2, and CE3.

[0104] The pixel electrodes AE1, AE2, and AE3 may be disposed in the plurality of light emitting regions EA1, EA2, and EA3, respectively. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in the first light emitting region EA1, a second pixel electrode AE2 disposed in the second light emitting region EA2, and a third pixel electrode AE3 disposed in the third light emitting region EA3. The pixel electrodes AE1, AE2, and AE3 may be disposed spaced apart from each other on the second passivation layer 139. The pixel electrodes AE1, AE2, and AE3 may be disposed in the light emitting regions EA1, EA2, and EA3, respectively, to emit light of different colors.

[0105] The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2. In one embodiment, the pixel electrodes AE1, AE2, and AE3 may have a stacked layer structure in which a plurality of indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide (ZnO), and indium oxide (In 2 O 3 ) and a reflective material layer containing a material having a high work function such as Ag, Mg, Al, Pt, Pb, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca or a mixture thereof are stacked. The material layer containing the material having a high work function may be disposed above the reflective material layer, and thus may be disposed close to the light emitting layers EL1, EL2 and EL3. For example, the pixel electrodes AE1, AE2 and AE3 may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag and ITO / Ag / ITO, but are not limited thereto.

[0106] The inorganic pixel defining layer 151 may be located on the pixel electrodes AE1, AE2, and AE3. The inorganic pixel defining layer 151 may define a plurality of first openings OP1 for forming the light emitting areas EA1, EA2, and EA3. In a plan view, the light emitting elements ED1, ED2, and ED3 may be disposed to overlap with the first openings OP1. The inorganic pixel defining layer 151 may be disposed entirely on the second passivation layer 139 and may expose a portion of the upper surface of the pixel electrodes AE1, AE2, and AE3 while partially overlapping with the pixel electrodes AE1, AE2, and AE3 in a plan view.

[0107] The inorganic pixel defining layer 151 may include an inorganic insulating material. For example, the inorganic pixel defining layer 151 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0108] The levee structure 160 may be located on the inorganic pixel defining layer 151. The levee structure 160 may define a plurality of second openings OP2 for forming the light emitting areas EA1, EA2, and EA3. The light emitting elements ED1, ED2, and ED3 may be arranged to overlap the second openings OP2 in a plan view. The levee structure 160 may include a first levee layer 161 and a second levee layer 163, and the first levee layer 161 and the second levee layer 163 may include their respective conductive materials different from each other. For example, the first levee layer 161 and the second levee layer 163 include their respective metal materials and structures different from each other to play different functions.

[0109] The first bank layer 161 may be located on the inorganic pixel defining layer 151. The first bank layer 161 may include a metal having high electrical conductivity. For example, the first bank layer 161 may include aluminum (Al) having high electrical conductivity.

[0110] refer to Figure 7 , the first embankment layer 161 may include a side portion 161c positioned toward the first opening OP1. The side portion 161c of the first embankment layer 161 may be positioned at an oblique angle between the first direction (X-axis direction) and the third direction (Z-axis direction). The embankment structure 160 may be formed by a deposition and etching process rather than a mask process, and the first embankment layer 161 may be formed by a wet etching process. Therefore, the side portion 161c of the first embankment layer 161 may be more recessed than the inorganic pixel defining layer 151 in the first direction (X-axis direction), and thus may be positioned based on an inclined surface shape that is inclined in the first direction (X-axis direction) in the third direction (Z-axis direction).

[0111] The second bank layer 163 may be located on the first bank layer 161. The second bank layer 163 may include a material having a lower etching rate than the first bank layer 161, and for example, may include titanium (Ti).

[0112] In some embodiments, the second bank barrier layer 163 may include a side portion 163c facing the first opening OP1. Like the first bank barrier layer 161, the second bank barrier layer 163 may be formed by a wet etching process. Since the second bank barrier layer 163 includes a material that is relatively stable to the wet etching process compared to the first bank barrier layer 161, the side portion 163c of the second bank barrier layer 163 may have a shape that protrudes more toward the first opening OP1 than at least a portion of the side portion 161c of the first bank barrier layer 161. The side portion 161c of the first bank barrier layer 161 may have a shape that is recessed inward from the side portion 163c of the second bank barrier layer 163. Therefore, the second bank barrier layer 163 of the bank barrier structure 160 may include a terminal protruding toward the first opening OP1, and an undercut may be formed between a lower portion of the terminal TIP of the second bank barrier layer 163 and the side portion 161c of the first bank barrier layer 161.

[0113] The light-emitting layers EL1, EL2, and EL3 may be disposed on the pixel electrodes AE1, AE2, and AE3. The light-emitting layers EL1, EL2, and EL3 may be organic light-emitting layers made of an organic material and may be formed on the pixel electrodes AE1, AE2, and AE3 by a deposition process. When the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3 receive a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layers EL1, EL2, and EL3 through the hole transport layer and the electron transport layer, respectively, and may be combined with each other in the light-emitting layers EL1, EL2, and EL3 to emit light.

[0114] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, which are disposed in their respective light-emitting regions EA1, EA2, and EA3 that are different from each other. The first light-emitting layer EL1 may be disposed on the first pixel electrode AE1 in the first light-emitting region EA1, the second light-emitting layer EL2 may be disposed on the second pixel electrode AE2 in the second light-emitting region EA2, and the third light-emitting layer EL3 may be disposed on the third pixel electrode AE3 in the third light-emitting region EA3. For example, the first light-emitting layer EL1 may be a light-emitting layer for emitting red first light, the second light-emitting layer EL2 may be a light-emitting layer emitting green second light, and the third light-emitting layer EL3 may be a light-emitting layer emitting blue third light.

[0115] In some embodiments, the inorganic pixel defining layer 151 may be disposed on the pixel electrodes AE1, AE2, and AE3, and may be spaced apart from the upper surfaces of the pixel electrodes AE1, AE2, and AE3. In the manufacturing process of the display device 10, a temporary protective layer may be disposed between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3, and then may be partially removed. Therefore, in the area where the temporary protective layer is partially removed, the lower surface of the inorganic pixel defining layer 151 may be spaced apart from the pixel electrodes AE1, AE2, and AE3. The light-emitting layers EL1, EL2, and EL3 may be disposed in a portion of the area between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3. The deposition process of the light-emitting layers EL1, EL2, and EL3 may be performed so that the materials of the light-emitting layers EL1, EL2, and EL3 are deposited in an inclined direction, rather than in a direction (i.e., thickness direction) perpendicular to the upper surface (i.e., main surface) of the substrate 110. Therefore, the light emitting layers EL1, EL2, and EL3 may be disposed to fill the space between the pixel electrodes AE1, AE2, and AE3 and the inorganic pixel defining layer 151. The unremoved portion of the temporary protective layer may remain as a residual pattern 157 in the region between the pixel electrodes AE1, AE2, and AE3 and the inorganic pixel defining layer 151. In other words, the region between the pixel electrodes AE1, AE2, and AE3 and the inorganic pixel defining layer 151 may be filled with the residual pattern 157 and the light emitting layers EL1, EL2, and EL3.

[0116] The common electrodes CE1, CE2, and CE3 may be disposed on the light emitting layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 may include a transparent conductive material to emit light generated by the light emitting layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 may receive a common voltage or a low potential voltage. When the pixel electrodes AE1, AE2, and AE3 receive a voltage corresponding to the data voltage and the common electrodes CE1, CE2, and CE3 receive a low potential voltage, a potential difference may be formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3, whereby the light emitting layers EL1, EL2, and EL3 may emit light.

[0117] For example, the common electrodes CE1, CE2 and CE3 may include silver (Ag), but are not limited thereto. The common electrodes CE1, CE2 and CE3 may include all material layers including materials having a low work function such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba or compounds or mixtures thereof (e.g., a mixture of Ag and Mg). The common electrodes CE1, CE2 and CE3 may further include a transparent metal oxide layer disposed on the material layer including the material having a low work function.

[0118] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3, which are disposed in their respective light emitting areas EA1, EA2, and EA3 different from each other. The first common electrode CE1 may be disposed on the first light emitting layer EL1 in the first light emitting area EA1, the second common electrode CE2 may be disposed on the second light emitting layer EL2 in the second light emitting area EA2, and the third common electrode CE3 may be disposed on the third light emitting layer EL3 in the third light emitting area EA3.

[0119] In the display device 10 according to one embodiment of the present disclosure, the common electrodes CE1, CE2, and CE3 disposed in different light emitting areas EA1, EA2, and EA3 may be electrically connected to each other through the first bank layer 161 of the bank structure 160, rather than being directly connected to each other. Therefore, a portion of the common electrodes CE1, CE2, and CE3 may be disposed on a side of the first bank layer 161 of the bank structure 160.

[0120] The capping layer 159 may be disposed on the common electrodes CE1, CE2, and CE3. The capping layer 159 may include an inorganic insulating material and cover the light emitting elements ED1, ED2, and ED3. The capping layer 159 may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air. In one embodiment, the capping layer 159 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0121] refer to Figure 6, a plurality of organic patterns ELP1, ELP2 and ELP3, electrode patterns CEP1, CEP2 and CEP3, and capping patterns 159-1, 159-2 and 159-3 may be located on the second bank barrier layer 163. A plurality of organic patterns ELP1, ELP2 and ELP3, electrode patterns CEP1, CEP2 and CEP3, and capping patterns 159-1, 159-2 and 159-3 may be disposed around the periphery of the light emitting areas EA1, EA2 and EA3 or the first opening OP1. The stacked structure of the plurality of organic patterns ELP1, ELP2 and ELP3, electrode patterns CEP1, CEP2 and CEP3, and capping patterns 159-1, 159-2 and 159-3 disposed around the periphery of the light emitting areas EA1, EA2 and EA3 may be partially etched in the manufacturing process of the display device 10 so that the pattern shape may be changed. Therefore, a portion of the upper surface of the second embankment layer 163 of the embankment structure 160 may not be covered by the multiple organic patterns ELP1, ELP2 and ELP3, the electrode patterns CEP1, CEP2 and CEP3, and the capping patterns 159-1, 159-2 and 159-3, and the groove portion TP may be formed in this portion of the upper surface of the second embankment layer 163 by the pattern.

[0122] A plurality of organic patterns ELP1, ELP2, and ELP3 may be formed on the second dam layer 163 to partially overlap the second dam layer 163 in a plan view. Each of the organic patterns ELP1, ELP2, and ELP3 may include the same material as that of each of the light-emitting layers EL1, EL2, and EL3. The first organic pattern ELP1 may include the same material as that of the first light-emitting layer EL1 of the first light-emitting element ED1, the second organic pattern ELP2 may include the same material as that of the second light-emitting layer EL2 of the second light-emitting element ED2, and the third organic pattern ELP3 may include the same material as that of the third light-emitting layer EL3 of the third light-emitting element ED3. Since the dam structure 160 includes the end TIP, the organic patterns ELP1, ELP2, and ELP3 may be marks formed to be disconnected and not connected to the light-emitting layers EL1, EL2, and EL3.

[0123] A plurality of electrode patterns CEP1, CEP2, and CEP3 may be disposed on a plurality of organic patterns ELP1, ELP2, and ELP3, respectively. The electrode patterns CEP1, CEP2, and CEP3 may include a first electrode pattern CEP1, a second electrode pattern CEP2, and a third electrode pattern CEP3, each of which includes the same material as that of the common electrodes CE1, CE2, and CE3. For example, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be disposed directly on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, respectively. The arrangement relationship of the electrode patterns CEP1, CEP2, and CEP3 with the organic patterns ELP1, ELP2, and ELP3 may be the same as the arrangement relationship of the common electrodes CE1, CE2, and CE3 with the light-emitting layers EL1, EL2, and EL3. Since the dam structure 160 includes the end TIP, the electrode patterns CEP1, CEP2, and CEP3 may be marks formed when the deposition material is disconnected and not connected to the common electrodes CE1, CE2, and CE3. In the display device 10, even in a deposition process without using a mask, the common electrodes CE1, CE2, and CE3 may be separately formed in different regions by the end TIP of the dam structure 160. In one embodiment, in a plan view, the common electrodes CE1, CE2, and CE3 may overlap with the protruding end TIP of the second dam layer 163 of the dam structure 160.

[0124] A plurality of capping patterns 159-1, 159-2, and 159-3 may be located on the plurality of electrode patterns CEP1, CEP2, and CEP3. The plurality of capping patterns 159-1, 159-2, and 159-3 may include the same material as that of the capping layer 159. The arrangement relationship between the capping patterns 159-1, 159-2, and 159-3 and the plurality of electrode patterns CEP1, CEP2, and CEP3 may be the same as the arrangement relationship between the capping layer 159 and the common electrodes CE1, CE2, and CE3. Since the dam structure 160 includes the end TIP, the capping patterns 159-1, 159-2, and 159-3 may be marks formed when the capping layer 159 is disconnected. The capping patterns 159-1, 159-2, and 159-3 may prevent delamination of the plurality of patterns from occurring during the manufacturing process.

[0125] The thin film encapsulation layer 170 may be disposed on the light emitting elements ED1, ED2, and ED3, the dam structure 160, and the plurality of patterns, and may cover the plurality of light emitting elements ED1, ED2, and ED3, the dam structure 160, and the plurality of patterns. The thin film encapsulation layer 170 may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the display element layer 150. The thin film encapsulation layer 170 may include at least one organic layer to protect the display element layer 150 from particles such as dust. In one embodiment, the thin film encapsulation layer 170 may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175 stacked in sequence. The first encapsulation layer 171 and the third encapsulation layer 175 may be inorganic encapsulation layers, and the second encapsulation layer 173 disposed between the first encapsulation layer 171 and the third encapsulation layer 175 may be an organic encapsulation layer.

[0126] Each of the first encapsulation layer 171 and the third encapsulation layer 175 may include one or more inorganic insulating materials. The inorganic insulating materials may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0127] The second encapsulation layer 173 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide and polyethylene. For example, the second encapsulation layer 173 may include an acrylic resin, such as polymethyl methacrylate, polyacrylic acid, etc. The second encapsulation layer 173 may be formed by curing a monomer or coating a polymer.

[0128] The first encapsulation layer 171 may include first to third inorganic layers 171 - 1 , 171 - 2 , and 171 - 3 disposed to correspond to different light emitting areas EA1 , EA2 , and EA3 , respectively.

[0129] The first to third inorganic layers 171-1, 171-2, and 171-3 may be provided to cover the organic patterns ELP1, ELP2, and ELP3, the electrode patterns CEP1, CEP2, and CEP3, and the capping patterns 159-1, 159-2, and 159-3. Since the first to third inorganic layers 171-1, 171-2, and 171-3 may be formed by chemical vapor deposition ("CVD"), the first to third inorganic layers 171-1, 171-2, and 171-3 may be formed to have a uniform thickness along the step difference of the deposited layers. For example, the first to third inorganic layers 171-1, 171-2, and 171-3 may form a thin film even under the undercut caused by the end TIP of the dam structure 160.

[0130] The first inorganic layer 171-1 may be disposed on the first light emitting element ED1 and the first electrode pattern CEP1 to overlap the first light emitting region EA1 in a plan view. The first inorganic layer 171-1 may be disposed to cover the first light emitting element ED1, the sidewall of the dam structure 160, the first organic pattern ELP1, the first electrode pattern CEP1, and the capping pattern 159-1. However, in a plan view, the first inorganic layer 171-1 may be disposed only on the first light emitting region EA1 and the dam structure 160 near the first light emitting region EA1, without overlapping the second light emitting region EA2 and the third light emitting region EA3.

[0131] The second inorganic layer 171-2 may be disposed on the second light emitting element ED2 and the second electrode pattern CEP2 to overlap with the second light emitting region EA2 in a plan view. The second inorganic layer 171-2 may be disposed to cover the second light emitting element ED2, the sidewall of the dam structure 160, the second organic pattern ELP2, the second electrode pattern CEP2, and the capping pattern 159-2. However, in a plan view, the second inorganic layer 171-2 may be disposed only on the dam structure 160 near the second light emitting region EA2 and not overlap with the first light emitting region EA1 and the third light emitting region EA3.

[0132] The third inorganic layer 171-3 may be disposed on the third light emitting element ED3 and the third electrode pattern CEP3 to overlap the third light emitting region EA3 in a plan view. The third inorganic layer 171-3 may be disposed to cover the third light emitting element ED3, the sidewall of the dam structure 160, the third organic pattern ELP3, the third electrode pattern CEP3, and the capping pattern 159-3. However, in a plan view, the third inorganic layer 171-3 may be disposed only on the third light emitting region EA3 and the dam structure 160 near the third light emitting region EA3 without overlapping the first light emitting region EA1 and the second light emitting region EA2.

[0133] In some embodiments, the first inorganic layer 171-1 may be formed after the first common electrode CE1 is formed, the second inorganic layer 171-2 may be formed after the second common electrode CE2 is formed, and the third inorganic layer 171-3 may be formed after the third common electrode CE3 is formed. Therefore, the first to third inorganic layers 171-1, 171-2, and 171-3 may be provided to cover different electrode patterns CEP1, CEP2, and CEP3 and organic patterns ELP1, ELP2, and ELP3, respectively.

[0134] The first to third inorganic layers 171-1, 171-2, and 171-3 may be disposed to be spaced apart from each other on the dam structure 160. Therefore, in a plan view, a portion of the second dam layer 163 of the dam structure 160 may not overlap with the first to third inorganic layers 171-1, 171-2, and 171-3. Therefore, a portion of the upper surface of the second dam layer 163 may be exposed without being covered by the first to third inorganic layers 171-1, 171-2, and 171-3. The exposed portion of the upper surface of the second dam layer 163 may contact the second encapsulation layer 173.

[0135] The touch sensor layer 180 may be disposed on the thin film encapsulation layer 170. The touch sensor layer 180 may include a touch buffer layer 181, a touch insulating layer 183, touch electrodes TE, and a touch passivation layer 185.

[0136] The touch buffer layer 181 may be disposed on the thin film encapsulation layer 170. The touch buffer layer 181 may have insulating and optical functions. The touch buffer layer 181 may include at least one inorganic layer. Optionally, the touch buffer layer 181 may be omitted. Although not shown, a connection electrode electrically connected to the touch electrode TE may be disposed on the touch buffer layer 181. The connection electrode may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be formed of a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag-Pd-Cu ("APC") alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0137] The touch insulating layer 183 may cover the touch buffer layer 181. The touch insulating layer 183 may have an insulating function. For example, the touch insulating layer 183 may be an inorganic layer including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0138] A portion of the touch electrode TE may be disposed on the touch insulating layer 183. In a plan view, each touch electrode TE may not overlap with the first to third light emitting areas EA1, EA2, and EA3. Each touch electrode TE may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be formed of a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0139] The touch passivation layer 185 may cover the touch electrode TE and the touch insulating layer 183 . The touch passivation layer 185 may have insulating and optical functions. The touch passivation layer 185 may be formed of a material as an example of the touch insulating layer 183 .

[0140] The light shielding layer BM may be disposed on the touch sensor layer 180. The light shielding layer BM may be disposed to overlap the inorganic pixel defining layer 151 and the dam structure 160 in a plan view. The light shielding layer BM may include a light absorbing material. For example, the light shielding layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, or aniline black, but is not limited thereto. The light shielding layer BM may prevent color mixing due to penetration of visible light in the first to third light emitting areas EA1, EA2, and EA3, thereby improving the color reproduction rate of the display device 10.

[0141] In a plan view, the color filter layer CF may be disposed on the touch passivation layer 185 and the light blocking layer BM by overlapping the light emitting areas EA1 , EA2 , and EA3 .

[0142] The color filter layer CF may include a first color filter 191, a second color filter 193, and a third color filter 195 that are respectively arranged to correspond to different light emitting areas EA1, EA2, and EA3. The plurality of color filters 191, 193, and 195 may include a colorant such as a dye or a pigment that absorbs light of a wavelength band other than a specific wavelength band, and may be arranged to correspond to the color of light emitted from the light emitting areas EA1, EA2, and EA3. For example, the first color filter 191 may be a red color filter that is arranged to overlap with the first light emitting area EA1, for transmitting only the red first light. The second color filter 193 may be a green color filter that is arranged to overlap with the second light emitting area EA2, for transmitting only the green second light, and the third color filter 195 may be a blue color filter that is arranged to overlap with the third light emitting area EA3, for transmitting only the blue third light.

[0143] Figure 6 The plurality of color filters 191, 193, and 195 are shown to be spaced apart from other color filters 191, 193, and 195 adjacent thereto on the light shielding layer BM, but the present disclosure is not limited thereto. In other words, the plurality of color filters 191, 193, and 195 may be disposed to partially overlap with other color filters 191, 193, and 195 adjacent thereto. That is, in a plan view, different color filters 191, 193, and 195 do not overlap with each other in the light emitting areas EA1, EA2, and EA3, and may overlap with each other on the light shielding layer BM.

[0144] An overcoat layer OC may be disposed on the color filter layer CF and the light shielding layer BM to planarize the upper ends of the plurality of color filters 191, 193, and 195. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0145] Figure 8 As an example Figure 2 An enlarged plan view of area "H".

[0146] refer to Figure 8 , the first non-display area NDA1 may be disposed to surround the outer circumference of the through hole TH. The main dam DM1 and the pattern dam DP may be located in the first non-display area NDA1.

[0147] The main dam DM1 may be a boundary between the display area DA and the first non-display area NDA1. The display device 10 may have a structure in which a plurality of layers are sequentially stacked on one substrate 110. Several layers of the display device 10 are made of organic materials and may be formed by a process of directly coating the organic materials on the substrate 110. For example, the second encapsulation layer 173 of the thin film encapsulation layer 170 may include an organic material and thus may flow while having fluidity. The organic material coated in the display area DA may overflow into the non-display area NDA. Therefore, the main dam DM1 may be located in the first non-display area NDA1 and may prevent the organic material disposed in the display area DA from overflowing into the through hole TH.

[0148] In some embodiments, the main dam DM1 is formed when the dam structure 160 located in the display area DA is extended, and then can be formed into the form of the main dam DM1 shown by an etching process during the manufacturing process. That is, the dam structure 160 and the main dam DM1 are integrated into one body, and then can be separated from each other by an etching process performed in the manufacturing process. Therefore, the main dam DM1 may include the same material and characteristics as those of the dam structure 160.

[0149] The pattern dam DP may be located between the through hole TH and the main dam DM1. The pattern dam DP may be referred to as a "pattern structure". The pattern dam DP may prevent a film gap near the through hole TH. For example, a film gap near the through hole TH may be caused by compressive and tensile stresses contained in the first encapsulation layer 171 and the third encapsulation layer 175 of the thin film encapsulation layer 170. The display device 10 may increase a contact area between the first encapsulation layer 171 and the third encapsulation layer 175 and a lower structure by forming the pattern dam DP. Therefore, a film gap defect near the through hole TH of the display device 10 may be resolved.

[0150] In some embodiments, the pattern dam DP may be formed when the dam structure 160 and the main dam DM1 located in the display area DA are extended, and then may be formed in the form of the pattern dam DP shown by an etching process during a manufacturing process. That is, the pattern dam DP may be integrated with the main dam DM1 and the dam structure 160 located in the first non-display area NDA1, and then may be separated from the main dam DM1 and the dam structure 160 by an etching process performed during a manufacturing process. Therefore, the pattern dam DP may include the same material and characteristics as those of the dam structure 160.

[0151] In some embodiments, the pattern dam DP may include a first pattern dam DP1 and a second pattern dam DP2. The first pattern dam DP1 may be disposed to surround the circumference of the through hole TH in a plan view. The second pattern dam DP2 may be positioned to surround the first pattern dam DP1 and the through hole TH. In one embodiment, at least one of the second pattern dam DP2 and the main dam DM1 may be omitted.

[0152] The display area DA may include a bank structure 160 defining the second opening OP2. The light emitting elements ED1, ED2, and ED3 may be disposed in each of the second openings OP2 to form the light emitting areas EA1, EA2, and EA3.

[0153] Fig. 9 As an example, follow Figure 8 2 is a cross-sectional view of an example of a display panel taken along line H1 - H1 ′.

[0154] refer to Fig. 9 The through hole TH may pass through the substrate 110, the thin film transistor layer 130, the display element layer 150, the thin film encapsulation layer 170, the touch sensor layer 180, and the polarizing film 190 included in the display panel 100. The through hole TH may be covered by the cover window CW. The through hole TH may be formed by a laser processing process. Although not shown in the figure, the optical device 500 (see Figure 3 ) can be arranged inside the through hole TH.

[0155] In a plan view, the substrate 110 may include a first surface 110a, a side portion 110c, and an inclined surface 110s at a portion overlapping the first non-display area NDA1. The inclined surface 110s of the substrate 110 may be a surface connecting the first surface 110a and the side portion 110c of the substrate 110. The inclined surface 110s of the substrate 110 may be formed by a laser processing process for forming the through hole TH. In detail, the inclined surface 110s of the substrate 110 may be formed by spraying an etching solution after irradiating laser. An angle θ1 formed by the first surface 110a of the substrate 110 and the inclined surface 110s and an angle θ2 formed by the side portion 110c of the substrate 110 and the inclined surface 110s may be an obtuse angle.

[0156] Fig.10 is a cross-sectional view illustrating a display panel, wherein Fig. 9 The area "J" is enlarged.

[0157] refer to Fig.10 The main dam DM1 may be disposed on the second passivation layer 139. As described above, the main dam DM1 may prevent the organic material applied to the display area DA from overflowing to the non-display area NDA. Therefore, it is desirable that the main dam DM1 has at least a minimum thickness or height for the above function.

[0158] In some embodiments, the main dam DM1 may include a first dam layer DM11 and a second dam layer DM12. By including the first dam layer DM11 and the second dam layer DM12, the main dam DM1 may have a height capable of preventing the organic material from overflowing. In an embodiment, the first dam layer DM11 and the second dam layer DM12 may include their respective conductive materials different from each other. The first dam layer DM11 included in the main dam DM1 may include the same material and characteristics as the first dam layer 161 of the dam structure 160, and the second dam layer DM12 included in the main dam DM1 may include the same material and characteristics as the second dam layer 163 of the dam structure 160.

[0159] The first dam layer DM11 may include the same material and characteristics as those of the first dam layer 161 of the dam structure 160. For example, the first dam layer DM11 may include aluminum (Al) having high electrical conductivity. The second dam layer DM12 may include the same material and characteristics as those of the second dam layer 163 of the dam structure 160. For example, the second dam layer DM12 may include a material having a low etching rate, and may include titanium (Ti), for example.

[0160] For convenience of description, the main dam DM1 is shown as one, and the first dam layer DM11 and the second dam layer DM12 are shown as being arranged alternately once, but the present disclosure is not limited thereto. That is, in another embodiment, a plurality of main dams DM1 may be arranged, and a plurality of first dam layers DM11 and a plurality of second dam layers DM12 may be alternately stacked several times. That is, the main dam DM1 may have a multilayer structure in which the first dam layer DM11 and the second dam layer DM12 are repeatedly stacked.

[0161] like Fig.10 As shown in FIG. 1 , the first encapsulation layer 171 may be located on the main dam DM1 and may cover the entirety of the main dam DM1. The first encapsulation layer 171 may extend beyond the main dam DM1 to the boundary of the first non-display area NDA1. Therefore, the first encapsulation layer 171 may block oxygen and moisture that penetrate through the through hole TH.

[0162] In a plan view, the second encapsulation layer 173 may be located on the first encapsulation layer 171 by overlapping the display area DA. The second encapsulation layer 173 may be disposed so as not to cover the upper surface of the main dam DM1. The second encapsulation layer 173 may not overflow to the first non-display area NDA1 through the main dam DM1. Therefore, in a plan view, the second encapsulation layer 173 may not overlap the first non-display area NDA1.

[0163] In a plan view, the third encapsulation layer 175 may be disposed on the second encapsulation layer 173 by overlapping the display area DA, and may be disposed on the first encapsulation layer 171 by overlapping the first non-display area NDA1. The third encapsulation layer 175 may extend beyond the main dam DM1 to the boundary of the first non-display area NDA1. Therefore, the first encapsulation layer 171 and the third encapsulation layer 175 may block oxygen and moisture that penetrate through the through hole TH.

[0164] In some embodiments, the pattern dam DP may be located between the main dam DM1 and the through hole TH. The pattern dam DP may be located on the second interlayer insulating layer 135. The pattern dam DP may include a first pattern dam DP1 and a second pattern dam DP2.

[0165] Fig.11 is a cross-sectional view illustrating a display panel, wherein Fig.10 The area "K" is enlarged.

[0166] refer to Fig.11 The first and second pattern dams DP1 and DP2 may be positioned to be spaced apart from each other in the first direction (X-axis direction). A recessed portion R recessed in a direction toward the substrate 110 may be included between the first and second pattern dams DP1 and DP2 spaced apart from each other.

[0167] In some embodiments, the first pattern dam DP1 may include a first pattern layer DP11 and a second pattern layer DP12. The first pattern layer DP11 and the second pattern layer DP12 may include the same structure and characteristics as the first and second dam layers 161 and 163 of the dam structure 160. In one embodiment, the first and second pattern layers DP11 and DP12 may include their respective conductive materials different from each other.

[0168] The first pattern layer DP11 may be located on the second interlayer insulating layer 135. The first pattern layer DP11 may include a metal having high conductivity, and, for example, may include aluminum (Al).

[0169] In some embodiments, the first pattern layer DP11 may include a lower surface DP11a, an upper surface DP11b, and a side DP11c. The lower surface DP11a of the first pattern layer DP11 may be positioned to contact the second interlayer insulating layer 135. The side DP11c of the first pattern layer DP11 may be positioned toward the recessed portion R and may connect the lower surface DP11a with the upper surface DP11b. The side DP11c of the first pattern layer DP11 may be positioned to form an oblique angle between the first direction (X-axis direction) and the third direction (Z-axis direction), but is not limited thereto. The side DP11c of the first pattern layer DP11 may be positioned perpendicular to the first direction (X-axis direction). The upper surface DP11b of the first pattern layer DP11 may contact the second pattern layer DP12.

[0170] The second pattern layer DP12 may be located on the first pattern layer DP11. The thickness of the first pattern layer DP11 in a direction perpendicular to the main surface of the substrate 110 (i.e., the Z-axis direction) may be greater than the thickness of the second pattern layer DP12 in the direction (i.e., the Z-axis direction). The second pattern layer DP12 may include the same material and characteristics as those of the second bank layer 163 of the bank structure 160. For example, the second pattern layer DP12 may include a material having a low etching rate, and may include titanium (Ti), for example.

[0171] In some embodiments, the second pattern layer DP12 may include a lower surface DP12a and a side portion DP12c. The lower surface DP12a of the second pattern layer DP12 may contact the first pattern layer DP11. The width W-DP12 of the lower surface DP12a of the second pattern layer DP12 may be greater than the width W-DP11 of the upper surface DP11b of the first pattern layer DP11. The side portion DP12c of the second pattern layer DP12 may have a shape that protrudes more toward the recessed portion R than at least a portion of the side portion DP11c of the first pattern layer DP11. Therefore, the second pattern layer DP12 may include a protruding end TIP. This may be due to the second pattern layer DP12 including a material that is relatively stable to the wet etching process compared to the first pattern layer DP11. Therefore, an undercut may be formed between the lower portion of the end TIP of the second pattern layer DP12 and the side portion DP11c of the first pattern layer DP11.

[0172] The second pattern dam DP2 may include a first pattern layer DP21 and a second pattern layer DP22. The first pattern layer DP21 and the second pattern layer DP22 may include the same structure and characteristics as the first and second dam layers 161 and 163 of the dam structure 160. In one embodiment, the first pattern layer DP21 and the second pattern layer DP22 may include conductive materials different from each other. In addition, the first pattern layer DP21 of the second pattern dam DP2 may include the same structure and characteristics as the first pattern layer DP11 of the first pattern dam DP1, and the second pattern layer DP22 of the second pattern dam DP2 may include the same structure and characteristics as the second pattern layer DP12 of the first pattern dam DP1.

[0173] In some embodiments, the first pattern layer DP21 of the second pattern dam DP2 may include a lower surface DP21a, an upper surface DP21b, and a side DP21c, and the second pattern layer DP22 may include a lower surface DP22a and a side DP22c. The width of the upper surface DP21b of the first pattern layer DP21 may be smaller than the width of the lower surface DP22a of the second pattern layer DP22. In addition, the side DP22c of the second pattern layer DP22 may be formed to protrude more toward the recessed portion R than at least a portion of the side DP21c of the first pattern layer DP21, whereby the second pattern layer DP22 may include a protruding tip TIP.

[0174] The first encapsulation layer 171 may cover the entirety of the first pattern dam DP1 and the second pattern dam DP2. The first encapsulation layer 171 may cover the curved portion included in the pattern dam DP inside the recessed portion R formed by the pattern dam DP. For example, the first encapsulation layer 171 may cover the undercut below the second pattern layer DP12 of the first pattern dam DP1 and the second pattern layer DP22 of the second pattern dam DP2. As described above, the display device 10 may include the pattern dam DP so that the area in which the first encapsulation layer 171 of the display device 10 contacts the lower structure may be increased. Therefore, the display device 10 may resolve the film gap of the first encapsulation layer 171 during the manufacturing process.

[0175] The third encapsulation layer 175 may be located on the first encapsulation layer 171 by overlapping the first pattern dam DP1 and the second pattern dam DP2 in a plan view. In the display area DA, the second encapsulation layer 173 may be located between the first encapsulation layer 171 and the third encapsulation layer 175, but the first encapsulation layer 171 and the third encapsulation layer 175 may contact each other by overlapping the first non-display area NDA1 in a plan view. In other words, the third encapsulation layer 175 may cover the first encapsulation layer 171 by overlapping the first non-display area NDA1 in a plan view. For example, the third encapsulation layer 175 may cover the undercut under the second pattern layer DP12 of the first pattern dam DP1 and the second pattern layer DP22 of the second pattern dam DP2 along the first encapsulation layer 171. In addition, other descriptions have been mentioned and will therefore be omitted.

[0176] Fig.12 As an example Figure 2 An enlarged plan view of area "Q". Fig.13 As an example, follow Fig.12 A cross-sectional view of the display device taken along line YY'.

[0177] refer to Fig.12 and Fig.13 , a main dam DM1 surrounding the display area DA may be located in the second non-display area NDA2. The main dam DM1 may be located on the second passivation layer 139. As described above, the main dam DM1 may be formed to prevent the organic material in the display area DA from overflowing to the non-display area NDA. For example, in the second non-display area NDA2, the second encapsulation layer 173 may not flow to the second non-display area NDA2 through the main dam DM1.

[0178] In some embodiments, the main dam DM1 located in the second non-display area NDA2 may include a first dam layer DM11 and a second dam layer DM12. The width of the upper surface of the first dam layer DM11 in the first direction (X-axis direction) may be smaller than the width of the lower surface of the second dam layer DM12. In addition, the opposite sides of the second dam layer DM12 may protrude more than the opposite sides of the first dam layer DM11 toward the first direction (X-axis direction). The shapes of the first dam layer DM11 and the second dam layer DM12 may be the same as those of the first dam layer 161 and the second dam layer 163.

[0179] refer to Fig.12, the pattern dam DP may overlap the second non-display area NDA2 in a plan view and may be positioned to surround the main dam DM1. The pattern dam DP may include a first pattern dam DP1 and a second pattern dam DP2. The first pattern dam DP1 may overlap the second non-display area NDA2 in a plan view and may be positioned to surround the main dam DM1. In addition, the second pattern dam DP2 may overlap the second non-display area NDA2 in a plan view and may be positioned to surround the first pattern dam DP1 and the main dam DM1.

[0180] refer to Fig.13 , the pattern dam DP may overlap the second non-display area NDA2 in a plan view, and may be located between the main dam DM1 and the end EG of the substrate 110. The first pattern dam DP1 may be located close to the main dam DM1, and the second pattern dam DP2 may be located close to the end EG of the substrate 110. The pattern dam DP may be located on the first power line VL1. The main dam DM1 and the pattern dam DP located in the second non-display area NDA2 may be electrically connected to the dam structure 160 located in the display area DA through the first power line VL1. As described above, the common electrodes CE1, CE2, and CE3 of the display device 10 may be electrically connected to each other through the dam structure 160.

[0181] In some embodiments, the pattern dam DP located in the second non-display area NDA2 is integrated with the dam structure 160 located in the display area DA and the main dam DM1 located in the second non-display area NDA2, and then may be separated from the dam structure 160 and the main dam DM1 by an etching process performed during a manufacturing process. Fig.13 1 and 2. The first and second pattern dams DP1 and DP2 may be positioned to be spaced apart from each other in the first direction (X-axis direction). A recessed portion R recessed toward the substrate 110 may be included between the first and second pattern dams DP1 and DP2 spaced apart from each other.

[0182] In some embodiments, the first pattern dam DP1 overlapping the second non-display area NDA2 in a plan view may include a first pattern layer DP11 and a second pattern layer DP12. The first pattern layer DP11 and the second pattern layer DP12 may include the same structure and characteristics as those of the first and second bank layers 161 and 163 of the bank structure 160. In detail, the first pattern layer DP11 may include a metal having high conductivity, and, for example, may include aluminum (Al). The second pattern layer DP12 may be located on the first pattern layer DP11. The second pattern layer DP12 may include the same material and characteristics as those of the second bank layer 163 of the bank structure 160. For example, the second pattern layer DP12 may include a material having a low etching rate, and, for example, may include titanium (Ti). Compared with the first pattern layer DP11, the second pattern layer DP12 may include a material that is relatively stable to a wet etching process, and thus may have a shape that protrudes more toward the recessed portion R than at least a portion of the first pattern layer DP11.

[0183] The second pattern dam DP2 overlapping the second non-display area NDA2 in a plan view may include a first pattern layer DP21 and a second pattern layer DP22. The first pattern layer DP21 and the second pattern layer DP22 may include the same structure and characteristics as those of the first and second dam layers 161 and 163 of the dam structure 160. In addition, the first pattern layer DP21 of the second pattern dam DP2 may include the same structure and characteristics as those of the first pattern layer DP11 of the first pattern dam DP1, and the second pattern layer DP22 of the second pattern dam DP2 may include the same structure and characteristics as those of the second pattern layer DP12 of the first pattern dam DP1. The side of the second pattern layer DP22 may be formed to protrude more toward the recessed portion R than at least a portion of the side of the first pattern layer DP21.

[0184] In a plan view, the first encapsulation layer 171 may cover the entirety of the first pattern dam DP1 and the second pattern dam DP2 by overlapping the second non-display area NDA2. The first encapsulation layer 171 may cover the entirety of the first pattern layer DP11 and the second pattern layer DP12 of the first pattern dam DP1 and the first pattern layer DP21 and the second pattern layer DP22 of the second pattern dam DP2. Since the area of ​​the first encapsulation layer 171 in contact with the first pattern dam DP1 and the second pattern dam DP2 increases, a film gap may be resolved.

[0185] In a plan view, the third encapsulation layer 175 may be located on the first encapsulation layer 171 by overlapping the second non-display area NDA2. The third encapsulation layer 175 may cover the first encapsulation layer 171 on the first pattern dam DP1 and the second pattern dam DP2. The third encapsulation layer 175 may cover the entirety of the first encapsulation layer 171 inside the recessed portion R between the first pattern dam DP1 and the second pattern dam DP2. Other descriptions have been mentioned and will therefore be omitted.

[0186] However, the effects of the present disclosure are not limited to the effects stated herein. The above and other effects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the claims.

Claims

1. A display device, comprising: A substrate including a display area and a non-display area surrounding the through hole; a dam structure located on the display area of ​​the substrate and defining an opening in the dam structure; a light emitting element overlapping the opening in a plan view; as well as a pattern structure located on the non-display area of ​​the substrate and between the dam structure and the through hole, wherein the pattern structure includes a first pattern dam and a second pattern dam spaced apart from the first pattern dam, and a recessed portion is defined between the first pattern dam and the second pattern dam, the recessed portion being recessed toward the substrate, The first pattern dam includes a first pattern layer and a second pattern layer, the first pattern layer and the second pattern layer include their respective conductive materials different from each other, and A side of the second pattern layer facing the recessed portion protrudes more toward the recessed portion than at least a portion of a side of the first pattern layer facing the recessed portion.

2. The display device according to claim 1, wherein the bank structure comprises a first bank layer and a second bank layer, the first bank layer and the second bank layer comprise their respective conductive materials different from each other, and The side portion of the second bank layer includes a tip that protrudes further toward the opening than the side portion of the first bank layer.

3. The display device according to claim 2, wherein the first pattern layer comprises the same material as that of the first bank layer, and The second pattern layer includes the same material as that of the second bank layer. 4 . The display device according to claim 3 , wherein a thickness of the first pattern layer in a direction perpendicular to the main surface of the substrate is greater than a thickness of the second pattern layer in the direction.

5. The display device according to claim 3 or 4, wherein the first pattern layer and the first bank layer contain aluminum, and The second pattern layer and the second bank layer include titanium.

6. The display device according to claim 1, further comprising: A first encapsulation layer, located on the bank structure and the pattern structure, and comprising an inorganic material; as well as a second encapsulation layer, located on the first encapsulation layer and comprising an organic material, The first encapsulation layer covers the entire pattern structure.

7. The display device according to claim 6, wherein the second encapsulation layer is partially in contact with the bank structure, and The second encapsulation layer does not overlap the pattern structure in the plan view.

8. The display device according to claim 6 or 7, further comprising a third encapsulation layer overlapping the non-display area and located on the first encapsulation layer, The third encapsulation layer covers the entire portion of the first encapsulation layer inside the recessed portion.

9. The display device according to claim 2, further comprising a main dam located between the pattern structure and the dam structure, The main dam includes a first dam layer and a second dam layer, and the first dam layer and the second dam layer include respective conductive materials different from each other.

10. The display device according to claim 9, wherein the first dam layer comprises the same material as that of the first barrier layer, and The second dam layer includes the same material as that of the second barrier layer.

11. The display device according to claim 2, wherein the light emitting element comprises: a first electrode overlapping the opening in the plan view; A light-emitting layer, located on the first electrode; as well as A second electrode is located on the light-emitting layer. The second electrode contacts the side of the first barrier layer. 12 . The display device according to claim 11 , wherein the second electrode overlaps the protruding end of the second bank layer in the plan view.

13. The display device according to claim 11, further comprising: an organic pattern, located on the second bank layer and comprising the same material as that of the light emitting layer; as well as The electrode pattern is located on the organic pattern and includes the same material as that of the second electrode. 14 . The display device of claim 13 , wherein the organic pattern is spaced apart from the light emitting layer, and the electrode pattern is spaced apart from the second electrode. 15 . The display device according to claim 1 , wherein the substrate includes an inclined surface in a direction toward the through hole.

16. The display device according to claim 1 or 15, further comprising an optical device inside the through hole.

17. The display device according to claim 1, wherein the second pattern dam comprises a third pattern layer and a fourth pattern layer, the third pattern layer and the fourth pattern layer contain their respective conductive materials different from each other, and A side of the fourth pattern layer facing the concave portion protrudes more toward the concave portion than at least a portion of a side of the third pattern layer facing the concave portion.

18. A display device comprising: A substrate including a display area and a non-display area surrounding the through hole; a dam structure located on the display area of ​​the substrate and defining an opening in the dam structure; a light emitting element overlapping the opening in a plan view; as well as a pattern structure located on the non-display area of ​​the substrate and between the dam structure and the through hole, wherein the pattern structure comprises a first pattern dam completely surrounding the through hole in the plan view, The first pattern dam includes a first pattern layer and a second pattern layer, The width of the lower surface of the second pattern layer in a direction parallel to the main surface of the substrate is greater than the width of the upper surface of the first pattern layer in the direction, and The opposite sides of the second pattern layer are respectively more protruding than at least a portion of the opposite sides of the first pattern layer.

19. The display device according to claim 18, further comprising a second pattern dam completely surrounding the through hole and the first pattern dam in the plan view, The second pattern dam is spaced apart from the first pattern dam, and a recessed portion is defined between the second pattern dam and the first pattern dam, and the recessed portion is recessed toward the substrate.

20. The display device of claim 19, further comprising a main dam completely surrounding the first pattern dam and the second pattern dam in the plan view, The main dam includes a first dam layer and a second dam layer. A first side portion of the second dam layer facing the embankment structure protrudes further toward the embankment structure than at least a portion of a first side portion of the first dam layer facing the embankment structure, and A second side portion of the second dam layer facing the pattern structure protrudes further toward the pattern structure than at least a portion of a second side portion of the first dam layer facing the pattern structure.

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