Display device and method of manufacturing same

Abstract

The invention provides a display device and a method of manufacturing the same. The display device includes: a substrate; a first conductive layer on the substrate and including gate electrodes respectively disposed in the pixel circuit regions arranged in the first direction; a second conductive layer disposed on the first conductive layer, the second conductive layer including a first bridge pattern; a third conductive layer disposed on the second conductive layer, the third conductive layer including a voltage supply line for supplying a driving voltage and a second bridge pattern; and a fourth conductive layer disposed on the third conductive layer, the fourth conductive layer including a common electrode line electrically connected to the gate electrode through the first bridge pattern and the second bridge pattern and electrically separated from the voltage supply line. The common electrode lines are arranged in a second direction crossing the first direction, and each of the common electrode lines extends in the first direction to overlap the pixel circuit region.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0082161 filed in the Korean Intellectual Property Office on June 26, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates generally to a display device, and more particularly, to a display device for allowing a storage capacitor to be shared between sub-pixels and a method of manufacturing the display device. Background Art

[0003] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation devices, and game consoles may include display devices for displaying images. Recently, an organic light emitting diode display (OLED), which is one of the display devices, has a self-luminous property and does not require a separate light source, so that its thickness and weight can be reduced. In addition, OLED has high-quality characteristics such as low power consumption, high brightness, and high response speed. Therefore, OLED, which is a next-generation display device for portable electronic devices, has become a focus.

[0004] OLED includes a plurality of pixels emitting light of different colors, and a circuit including a plurality of transistors and a plurality of capacitors for driving the organic light emitting diode is formed in each pixel. Specifically, for the purpose of 4K pixel design, a circuit including a minimum number of transistors and a minimum number of capacitors is formed in a micro organic light emitting display device.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0006] The embodiment provides a display device capable of including an electronic component with ultra-high resolution in a relatively small area and a method for manufacturing the display device. For example, in the display device, a storage capacitor can be shared between sub-pixels, and thus, a design space for various components included in the display device can be ensured. Therefore, an electronic component with ultra-high resolution can be included in a relatively small area.

[0007] According to aspects of the present disclosure, a display device is provided, which includes: a substrate; a first conductive layer, which is on the substrate and includes gate electrodes respectively arranged in pixel circuit areas arranged along a first direction; a second conductive layer, which is arranged on the first conductive layer, and the second conductive layer includes a first bridge pattern; a third conductive layer, which is arranged on the second conductive layer, and the third conductive layer includes a voltage supply line and a second bridge pattern for supplying a driving voltage; and a fourth conductive layer, which is arranged on the third conductive layer, and the fourth conductive layer includes a common electrode line, which is electrically connected to the gate electrode through the first bridge pattern and the second bridge pattern, and is electrically separated from the voltage supply line, wherein the common electrode lines are arranged along a second direction intersecting the first direction, and each of the common electrode lines extends along the first direction to overlap with the pixel circuit area.

[0008] Each of the common electrode lines together with the voltage supply line may form a first storage capacitor.

[0009] Each of the first bridge patterns together with the voltage supply line may form a second storage capacitor.

[0010] The voltage supply line may extend along the first direction to overlap the pixel circuit region.

[0011] Pixel circuits of sub-pixels included in one unit pixel may be provided in the pixel circuit region, and gate electrodes may be respectively included in the pixel circuits of the sub-pixels.

[0012] The number of common electrode lines in one unit pixel may be equal to the number of sub-pixels included in the one unit pixel.

[0013] The first bridge pattern and the second bridge pattern may overlap each other. The common electrode line may be connected to the second bridge pattern through the first contact hole. The second bridge pattern may be connected to the first bridge pattern through the second contact hole.

[0014] The common electrode lines in one unit pixel are connected to the second bridge patterns through the first contact holes, respectively.

[0015] The display device may further include a fifth conductive layer including a data line for supplying a data signal and disposed between the first conductive layer and the second conductive layer.

[0016] The fifth conductive layer may further include a third bridge pattern. The common electrode line may be electrically connected to the gate electrode through the first bridge pattern, the second bridge pattern, and the third bridge pattern.

[0017] The second conductive layer may further include a gate line for supplying a gate signal.

[0018] According to another aspect of the present disclosure, a method for manufacturing a display device is provided, the method comprising: forming a first conductive layer on a substrate, the first conductive layer comprising gate electrodes respectively arranged in pixel circuit areas arranged along a first direction; forming a second conductive layer arranged on the first conductive layer, the second conductive layer comprising a first bridge pattern; forming a third conductive layer arranged on the second conductive layer, the third conductive layer comprising a voltage supply line and a second bridge pattern for supplying a driving voltage; and forming a fourth conductive layer arranged on the third conductive layer, the fourth conductive layer comprising a common electrode line, the common electrode line being electrically connected to the gate electrode through the first bridge pattern and the second bridge pattern, and being electrically separated from the voltage supply line, wherein the common electrode lines are arranged along a second direction intersecting the first direction, and each of the common electrode lines extends along the first direction to overlap with the pixel circuit area.

[0019] Each of the common electrode lines together with the voltage supply line may form a first storage capacitor.

[0020] Each of the first bridge patterns together with the voltage supply line may form a second storage capacitor.

[0021] The voltage supply line may extend along the first direction to overlap the pixel circuit region. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0023] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals always refer to the same elements.

[0024] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0025] Figure 2 It is shown that the Figure 1 A block diagram of an embodiment of a pixel circuit area in at least one unit pixel is shown in FIG.

[0026] Figure 3 It is shown in Figure 2 A circuit diagram of an embodiment of a pixel circuit is shown in FIG.

[0027] Figure 4 It is shown in Figure 2A plan view of an embodiment of a first conductive layer in a pixel circuit is shown in FIG.

[0028] Figure 5 It is shown in Figure 2 A plan view of an embodiment of a fifth conductive layer in a pixel circuit is shown in FIG.

[0029] Figure 6 It is shown in Figure 2 A plan view of an embodiment of a second conductive layer in a pixel circuit is shown in FIG.

[0030] Figure 7 It is shown in Figure 2 A plan view of an embodiment of a third conductive layer in a pixel circuit is shown in FIG.

[0031] Figure 8 It is shown in Figure 2 A plan view of an embodiment of a fourth conductive layer in a pixel circuit is shown in FIG.

[0032] Fig. 9 It is shown along the Figure 4 2 is a cross-sectional view of a pixel circuit including first to fifth conductive layers taken along line II′ shown in FIG.

[0033] Fig.10 It is shown along the Figure 4 2 is a cross-sectional view of a pixel circuit including first to fifth conductive layers taken along line II-II′ shown in FIG.

[0034] Fig.11 is a flowchart illustrating an embodiment of a method of manufacturing a display device. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the following description, only the necessary parts for understanding the operation according to the present disclosure are described, and the description of other parts is omitted so as not to unnecessarily obscure the subject matter of the present disclosure. In addition, the present disclosure is not limited to the exemplary embodiments described herein, but can be embodied in various different forms. On the contrary, the exemplary embodiments described herein are provided to thoroughly and completely describe the disclosed content, and the disclosed concept is fully conveyed to those of ordinary skill in the art.

[0036] Throughout the specification, when an element is referred to as being "connected" or "bound" to another element, the element may be directly connected or directly bound to the other element, or indirectly connected or indirectly bound to the other element when one or more intervening elements are placed therebetween. The technical terms used herein are only used for the purpose of illustrating a specific embodiment and are not intended to limit the embodiment. It will be understood that when a component "includes" an element, unless there is another description to the contrary, it should be understood that the component does not exclude another element, but may further include another element. It will be understood that, for the purpose of this disclosure, "at least one (kind / person) of X, Y, and Z" can be interpreted as any combination of only X, only Y, only Z, or two or more items of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Similarly, for the purpose of this disclosure, "at least one (kind / person) selected from the group consisting of X, Y, and Z" can be interpreted as any combination of only X, only Y, only Z, or two or more items of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ).

[0037] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element.

[0038] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0039] Reference Figure 1 , the display device 100 may include a display panel DP, a controller 110 , a data driver 120 , and a scan driver 130 .

[0040] The controller 110 may control the driving operations of the data driver 120 and the scan driver 130. The controller 110 may receive the image signal RGB and the control signal CTRL. The controller 110 may start scanning according to the timing implemented in each frame, and generate an image data signal DATA obtained by converting the data format of the image signal RGB into an interface specification suitable for the data driver 120. The controller 110 may output a first control signal SCS and a second control signal DCS.

[0041] The controller 110 may be a timing controller used in general display technology or a control device including a timing controller to further perform another control function. The controller 110 may be implemented as a separate component from the data driver 120. The controller 110 and the data driver 120 may be implemented as one integrated circuit.

[0042] The display panel DP may include a plurality of unit pixels PX. The plurality of unit pixels PX may be arranged in the first direction DR1 and the second direction DR2. In addition, a plurality of scan lines SL1 to SLm and a plurality of data lines DL1 to DLn may be provided in the display panel DP. Therefore, the plurality of scan lines SL1 to SLm and the plurality of data lines DL1 to DLn may be provided while crossing each other. In the display panel DP, the plurality of unit pixels PX are electrically connected to the scan lines SL1 to SLm and the data lines DL1 to DLn.

[0043] The display panel DP may include various types of panels such as an organic light emitting diode (OLED). The kind of lines provided in the display panel DP may vary according to a sub-pixel structure, a panel type, and the like.

[0044] The data driver 120 may output a data voltage to a plurality of data lines DL1 to DLn, thereby driving the plurality of data lines DL1 to DLn. For example, the data driver 120 may receive a second control signal DCS and an image data signal DATA from the controller 110. The data driver 120 may convert the image data signal DATA into a data signal, and output the data signal to the data lines DL1 to DLn. The data signal may be an analog voltage value corresponding to a grayscale value of the image data signal DATA. That is, when a specific scan line is selected by the scan driver 130, the data driver 120 may convert the received image data signal DATA into a data voltage in an analog form, and supply the data voltage to the plurality of data lines DL1 to DLn.

[0045] The scan driver 130 may output a scan signal to the plurality of scan lines SL1 to SLm, thereby driving the plurality of scan lines SL1 to SLm. The scan driver 130 may represent a gate driver. The scan driver 130 may sequentially supply a scan signal having an on voltage and an off voltage to the plurality of scan lines SL1 to SLm under the control of the controller 110. For example, the scan driver 130 may receive a first control signal SCS from the controller 110. The first control signal SCS may include a start signal and a clock signal. The scan driver 130 may output a scan signal to the scan lines SL1 to SLm in response to the first control signal SCS.

[0046] Therefore, the unit pixel PX receiving each scan signal may receive an analog voltage of a grayscale value corresponding to the image data signal DATA. Therefore, the unit pixel PX may output light having a brightness corresponding to the analog voltage. Therefore, an image may be displayed on the display panel DP.

[0047] Figure 2 It is shown that the Figure 1A block diagram of an embodiment of a pixel circuit area in at least one unit pixel is shown in FIG.

[0048] Reference Figure 2 , at least one unit pixel PX may include a plurality of sub-pixels.

[0049] According to an embodiment, one unit pixel PX may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. Optionally, one unit pixel PX may further include a white (W) sub-pixel in addition to the red sub-pixel, the green sub-pixel, and the blue sub-pixel. Figure 2 In the figure, for the convenience of description, three pixel circuits PC_R, PC_G and PC_B arranged in sequence are shown. However, the embodiment is not limited thereto. For example, the present disclosure can also be applied to two pixel circuits arranged in sequence.

[0050] Each of the sub-pixels may include a pixel circuit and a light emitting element. For example, a red sub-pixel may include a first pixel circuit PC_R and a light emitting element controlled by the first pixel circuit PC_R to emit light.

[0051] The pixel circuit areas AR1, AR2 and AR3 may have the same area and may be sequentially arranged along the first direction DR1 on the substrate. In addition, the pixel circuits driving the sub-pixels included in one unit pixel may be respectively arranged in the pixel circuit areas AR1, AR2 and AR3. For example, the first pixel circuit PC_R of the red sub-pixel may be arranged in the first pixel circuit area AR1 among the pixel circuit areas arranged along the first direction DR1. The second pixel circuit PC_G of the green sub-pixel may be arranged in the second pixel circuit area AR2 among the pixel circuit areas arranged along the first direction DR1. The third pixel circuit PC_B of the blue sub-pixel may be arranged in the third pixel circuit area AR3 among the pixel circuit areas arranged along the first direction DR1. However, the order of the red sub-pixel, the green sub-pixel and the blue sub-pixel is described as an example, and the present disclosure is not limited thereto.

[0052] Figure 3 It is shown in Figure 2 A circuit diagram of an embodiment of a pixel circuit is shown in FIG.

[0053] Reference Figure 3 , will be described in Figure 1 Pixel circuit of a sub-pixel of one unit pixel PX among a plurality of unit pixels PX shown in FIG.

[0054] The pixel circuit of each of the sub-pixels may have a 2T1C structure including two transistors and one capacitor. Specifically, since the micro organic light-emitting display device needs to have a pixel circuit having a structure including a minimum number of transistors and a minimum number of capacitors for the purpose of 4K pixel design, the micro organic light-emitting display device may be constructed as a pixel circuit having a 2T1C structure. The pixel circuit having a 2T1C structure may include a first transistor, a second transistor, and a capacitor. The first transistor may be a driving transistor T1, the second transistor may be a switching transistor T2, and the capacitor may be a storage capacitor Cst.

[0055] The driving transistor T1 may drive the light emitting element 310 by supplying a driving current. The gate electrode of the driving transistor T1 may be electrically connected to the first node N1. In addition, the drain electrode of the driving transistor T1 may be electrically connected to the second node N2, which is electrically connected to the anode electrode of the light emitting element 310. The source electrode of the driving transistor T1 may be electrically connected to the third node N3, which is connected to the power supply voltage VDD.

[0056] The switching transistor T2 may be connected between the first node N1 and the corresponding data line DLj. The gate electrode of the switching transistor T2 may be electrically connected to the scan line SLi for supplying a scan signal. The drain electrode of the switching transistor T2 may be electrically connected to the data line DLj, and the source electrode of the switching transistor T2 may be electrically connected to the first node N1.

[0057] The on / off of the switching transistor T2 can be controlled by a scan signal applied to the gate electrode through the scan line SLi. When the switching transistor T2 is turned on by the scan signal, the switching transistor T2 can transmit the data voltage Vdata supplied from the corresponding data line DLj to the gate electrode of the driving transistor T1. However, in the present disclosure, the case where each of the driving transistor T1 and the switching transistor T2 is a p-type transistor is described as an example. However, each of the driving transistor T1 and the switching transistor T2 can be an n-type transistor, or the driving transistor T1 and the switching transistor T2 can be different types of transistors.

[0058] The storage capacitor Cst may be used to maintain a constant voltage for a certain time (e.g., one frame time). The storage capacitor Cst may be electrically connected between the first node N1 and the third node N3, or electrically connected between the first node N1 and the second node N2. However, in the present disclosure, a case where the storage capacitor Cst is connected between the first node N1 and the third node N3 is described as an example. However, the present disclosure is not limited thereto.

[0059] The storage capacitor Cst is not a parasitic capacitor (eg, Cgs or Cgd) that is an internal capacitor existing between the source electrode, the drain electrode, and the gate electrode of the driving transistor T1 , but may be an external capacitor intentionally designed at the outside of the driving transistor T1 .

[0060] The light emitting element 310 may include an organic light emitting diode (OLED). The anode electrode of the light emitting element 310 may correspond to the pixel electrode, and another power supply voltage (e.g., base voltage) VSS corresponding to the common voltage may be applied to the cathode electrode of the light emitting element 310. The base voltage VSS may be a ground voltage or a voltage higher or lower than the ground voltage. In addition, the base voltage VSS may vary according to a driving state such as image driving or sensing driving.

[0061] Reference Figure 3 , the pixel circuit PC_R of the red sub-pixel may be a pixel circuit of a sub-pixel disposed on the i-th row and the j-th column among the sub-pixels (i is a positive integer less than or equal to m, and j is a positive integer less than or equal to n). For example, the pixel circuit PC_R may be a pixel circuit of a red sub-pixel included in one unit pixel. The pixel circuit PC_R may be connected to the i-th scan line SLi and the j-th data line DLj to control the light emitting element 310 to emit light in response to a signal received through the i-th scan line SLi and the j-th data line DLj.

[0062] In the following, reference will be made to Figures 4 to 8 Description included in Figure 2 The display panel DP (see Figure 1 ) can include a substrate SUB (see Fig. 9 ), a first conductive layer 400, a fifth conductive layer 500, a second conductive layer 600, a third conductive layer 700 and a fourth conductive layer 800 are sequentially arranged on a substrate SUB. Figures 4 to 8 Although not shown in the figure, each conductive layer may include a plurality of conductive layers. At least one insulating layer is provided between adjacent conductive layers to insulate the adjacent conductive layers. For example, each of the conductive layers may be formed as a single-layer structure or a multi-layer structure made of any one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu) or any alloy thereof. In addition, each of the insulating layers may be formed as a single-layer structure including silicon oxide (SiO x )、Silicon Nitride(SiN x ) and a silicon oxynitride (SiON) inorganic layer. However, this is only illustrative, and the present disclosure is not limited thereto.

[0063] Figure 4 It is shown in Figure 2 FIG. 1 is a plan view of an embodiment of a first conductive layer in a pixel circuit shown in FIG. Figure 4 , the first conductive layer 400 disposed on the substrate will be described. The substrate is an insulating substrate and may be a rigid substrate or a flexible substrate made of an insulating material such as glass, quartz, or a polymer resin. A pixel circuit driving a plurality of sub-pixels may include a plurality of conductive layers disposed on the substrate.

[0064] The first conductive layer 400 may be disposed on the substrate SUB and include a plurality of conductive layers. At least one insulating layer is disposed between the plurality of conductive layers included in the first conductive layer 400. The at least one insulating layer may insulate the plurality of conductive layers disposed in the first conductive layer 400.

[0065] Reference Figure 3 and Figure 4 , the first conductive layer 400 may include gate electrodes respectively disposed in the pixel circuit regions arranged along the first direction DR1. In an example, the first conductive layer 400 may include gate electrodes, source / drain electrodes 420 and 410 of a plurality of driving transistors T1 and a plurality of switching transistors T2 disposed in the pixel circuit region. The first insulating layer 110 (see Fig. 9 ) may be disposed on the gate electrode and the source / drain electrode so that the gate electrode and the source / drain electrode are electrically insulated from each other. For example, the first insulating layer 110 may be disposed on the gate electrode 421 of the driving transistor T1, and the source electrode and the drain electrode 422 of the driving transistor T1 may be disposed on the first insulating layer 110. The gate electrode 411 of the switching transistor T2, the first insulating layer 110, and the source electrode and the drain electrode 412 of the switching transistor T2 may be sequentially disposed on the substrate SUB. However, this describes an example of the order in which the plurality of layers included in the first conductive layer 400 are disposed, and the present disclosure is not limited thereto.

[0066] The gate electrode 421 of the driving transistor T1 included in the first conductive layer 400 may overlap the source electrode of the switching transistor T2 at the first node N1. The gate electrode 421 of the driving transistor T1 and the gate electrode 411 of the switching transistor T2 may be spaced apart from each other. The gate electrode 421 of the driving transistor T1 may extend in the second direction DR2, and the gate electrode 411 of the switching transistor T2 may extend in the first direction DR1.

[0067] Figure 5 It is shown in Figure 2 1 is a plan view of an embodiment of a fifth conductive layer in a pixel circuit shown in FIG.

[0068] The fifth conductive layer 500 may be disposed on the first conductive layer 400 and include a data line 510 and a third bridge pattern 520. In addition, the fifth conductive layer 500 may be electrically connected to the first conductive layer 400 through a contact hole 530 formed in the first insulating layer 110 disposed therebetween.

[0069] The data line 510 included in the fifth conductive layer 500 may supply a data signal to the switching transistor T2 of the sub-pixel included in one unit pixel. The data line 510 may be electrically connected to the drain electrode of the switching transistor T2 of the first conductive layer 400 through the contact hole 511 formed in the first insulating layer 110 on the first conductive layer 400. For example, the data line 510 included in the fifth conductive layer 500 may be disposed to overlap with the drain electrode (or source electrode) of the switching transistor T2 included in the first conductive layer 400. More specifically, the data line 510 may be disposed to extend from one side in the corresponding sub-pixel along the first direction DR1. In addition, the contact hole 511 may be formed in a region where the data line 510 overlaps with the corresponding drain electrode of the switching transistor T2 in the corresponding sub-pixel.

[0070] The gate signal supplied from the second conductive layer 600 may be supplied to the switching transistor T2 through the bridge pattern 521 among the third bridge patterns 520 included in the fifth conductive layer 500. For example, some of the bridge patterns 521 among the third bridge patterns 520 included in the fifth conductive layer 500 may be disposed to overlap the gate electrode 411 of the switching transistor T2 included in the first conductive layer 400. The bridge pattern 521 may be connected to the gate electrode 411 of the switching transistor T2 through a contact hole 532 formed in the first insulating layer 110 disposed on the first conductive layer 400.

[0071] Some of the third bridge patterns 520 may be disposed to overlap the gate electrode 421 of the driving transistor T1 included in the first conductive layer 400. The bridge pattern 522 may be connected to the gate electrode 421 of the driving transistor T1 through a contact hole 533 formed in the first insulating layer 110 disposed between the first conductive layer 400 and the fifth conductive layer 500.

[0072] In addition, some of the bridge patterns 523 and 524 among the third bridge patterns 520 may be disposed to overlap the source electrode and the drain electrode 422 of the driving transistor T1, respectively. Specifically, the bridge pattern 524 may correspond to one of the bridge patterns for connecting the drain electrode of the driving transistor T1 to the anode electrode. For example, some of the bridge patterns 524 among the third bridge patterns 520 may overlap the drain electrode of the driving transistor T1 included in the first conductive layer 400 and be connected to the drain electrode of the driving transistor T1 included in the first conductive layer 400. The bridge pattern 524 may connect the drain electrode of the driving transistor T1 to the anode electrode of the corresponding sub-pixel through the contact hole 535.

[0073] The bridge pattern 520 may be a conductive pattern for connecting different layers to each other. In addition, the bridge pattern 520 may be disposed between interlayer insulating layers and electrically connected to electrodes or bridge patterns included in different conductive layers through contact holes formed through the interlayer insulating layers. Therefore, the bridge patterns 520 may be disposed to be spaced apart from each other.

[0074] Figure 6 It is shown in Figure 2 FIG. 1 is a plan view of an embodiment of a second conductive layer in a pixel circuit shown in FIG. Figure 6 , the second conductive layer 600 disposed on the substrate will be described.

[0075] The second conductive layer 600 may be disposed on the fifth conductive layer 500 and include a gate line 610 and a first bridge pattern 620. The second conductive layer 600 may be formed by correspondingly forming a second insulating layer 120 (see FIG. 1 ) disposed on the fifth conductive layer 500. Fig. 9 ) is electrically connected to the fifth conductive layer 500.

[0076] The gate line 610 included in the second conductive layer 600 may supply a gate signal to the switching transistor T2 of the sub-pixel included in one unit pixel. The gate line 610 may be electrically connected to the gate electrode 411 of the switching transistor T2 of the first conductive layer 400 through a contact hole 631 formed in the second insulating layer 120 disposed on the fifth conductive layer 500. For example, the contact hole 631 may expose the bridge pattern 521 of the fifth conductive layer 500. More specifically, the gate line 610 may be provided to extend along the second direction DR2 from one side in the corresponding sub-pixel. In addition, the gate line 610 may be electrically connected to the bridge pattern 521 included in the fifth conductive layer 500 through the contact hole 631. In addition, the bridge pattern 521 may be connected to the gate electrode 411 of the switching transistor T2 through a contact hole 532 formed in the first insulating layer 110. Therefore, the gate signal may be supplied to one end of the gate electrode 411 connected to the switching transistor T2 through the gate line 610.

[0077] The first bridge pattern 620 included in the second conductive layer 600 may be connected to the gate electrode 421 and the source and drain electrodes 422 of the driving transistor T1 through contact holes 632, 633, and 634 formed in the second insulating layer 120 disposed on the fifth conductive layer 500, respectively. For example, some of the bridge patterns 621 among the first bridge patterns 620 included in the second conductive layer 600 may overlap with the bridge pattern 522 of the fifth conductive layer 500. The bridge pattern 621 may be connected to the bridge pattern 522 of the fifth conductive layer 500 through the contact hole 632, and connected to the gate electrode 421 of the driving transistor T1 through the contact hole 533 formed in the first insulating layer 110 disposed on the first conductive layer 400.

[0078] In addition, some bridge patterns 622 among the first bridge patterns 620 may overlap the bridge patterns 523 of the fifth conductive layer 500. The bridge patterns 622 may be connected to the bridge patterns 523 of the fifth conductive layer 500 through contact holes 633, and connected to the source electrode of the driving transistor T1 through contact holes 534 formed in the first insulating layer 110 disposed on the first conductive layer 400.

[0079] Some of the bridge patterns 623 among the first bridge patterns 620 may correspond to one of the bridge patterns for connecting the drain electrode of the driving transistor T1 to the anode electrode. For example, the bridge pattern 623 may overlap the bridge pattern 524 of the fifth conductive layer 500. The bridge pattern 623 of the second conductive layer 600 may be connected to the bridge pattern 524 of the fifth conductive layer 500 through the contact hole 634. That is, the bridge pattern 623 is connected to the bridge pattern 524 to be connected to the drain electrode of the driving transistor T1.

[0080] The bridge pattern 620 may be a conductive pattern for connecting different layers to each other. In addition, the bridge pattern 620 may be disposed on the interlayer insulating layer and electrically connected to electrodes or bridge patterns included in different conductive layers through contact holes formed through the interlayer insulating layer. Therefore, the bridge patterns 620 may be disposed to be spaced apart from each other.

[0081] Figure 7 It is shown in Figure 2 FIG. 1 is a plan view of an embodiment of a third conductive layer in a pixel circuit shown in FIG. Figure 7 , the third conductive layer 700 disposed on the substrate will be described.

[0082] The third conductive layer 700 may be disposed on the second conductive layer 600 and include a voltage supply line 710 and a second bridge pattern 720. The third conductive layer 700 may be formed on the third insulating layer 130 (see Fig. 9 ) and the fourth insulating layer 140 (see Fig. 9) electrically connects the second conductive layer 600 and the fourth conductive layer 800 to each other through the contact hole 730 in the substrate, the third insulating layer 130 is disposed between the second conductive layer 600 and the third conductive layer 700, and the fourth insulating layer 140 is disposed between the third conductive layer 700 and the fourth conductive layer 800. In addition, the third conductive layer 700 may form a storage capacitor in which the second conductive layer 600 and the third conductive layer 700 are overlapped in a plan view.

[0083] The voltage supply line 710 included in the third conductive layer 700 may supply the power supply voltage VDD to the driving transistor T1 of the sub-pixel included in one unit pixel. The voltage supply line 710 may extend along the first direction DR1 to overlap with the pixel circuit region. The pixel circuit region may be a region in which the pixel circuit of the sub-pixel included in one unit pixel is disposed. That is, the voltage supply line 710 may be formed in one conductive pattern to supply the same power supply voltage VDD to the sub-pixels included in one unit pixel.

[0084] The voltage supply line 710 may be electrically connected to the source electrode of the driving transistor T1 of the first conductive layer 400 through a contact hole 731 formed in the third insulating layer 130 disposed on the second conductive layer 600. For example, the third insulating layer 130 on which the voltage supply line 710 is disposed may include a contact hole 731 exposing the bridge pattern 622 of the second conductive layer 600. More specifically, the voltage supply line 710 may be connected to the bridge pattern 622 included in the second conductive layer 600 through the contact hole 731. In addition, the bridge pattern 622 may be connected to the bridge pattern 523 of the fifth conductive layer 500 through a contact hole 633 formed in the second insulating layer 120 disposed on the fifth conductive layer 500. The voltage supply line 710 connected to the bridge pattern 523 may be connected to the source electrode of the driving transistor T1 through a contact hole 534. That is, the voltage supply line 710 and the source electrode of the driving transistor T1 may be electrically connected to each other through a plurality of bridge patterns.

[0085] The second bridge pattern 720 included in the third conductive layer 700 may be connected to some of the bridge patterns 621 and 623 among the first bridge patterns 620 through second contact holes 732 and 733 formed in the third insulating layer 130, respectively. For example, some of the bridge patterns 721 among the second bridge patterns 720 included in the third conductive layer 700 may overlap the bridge pattern 621 of the second conductive layer 600. The bridge pattern 721 may be connected to the bridge pattern 621 of the second conductive layer 600 through the contact hole 732, and then connected to the bridge pattern 522 of the fifth conductive layer 500 through the contact hole 632. The bridge pattern 522 is a pattern connected to the gate electrode 421 of the driving transistor T1, and the bridge pattern 721 may be connected to the gate electrode 421 of the driving transistor T1.

[0086] Some of the bridge patterns 722 among the second bridge patterns 720 may correspond to one of the bridge patterns for connecting the drain electrode of the driving transistor T1 to the anode electrode. For example, the bridge pattern 722 may include a contact hole 733 exposing the bridge pattern 623 of the second conductive layer 600. The bridge pattern 722 may be connected to the bridge pattern 623 of the second conductive layer 600 through the contact hole 733, and then connected to the bridge pattern 524 of the fifth conductive layer 500 through the contact hole 634. The bridge pattern 524 is a pattern connected to the drain electrode of the driving transistor T1, and the bridge pattern 722 may be connected to the drain electrode of the driving transistor T1.

[0087] The bridge pattern 720 may be a conductive pattern for connecting different layers to each other. In addition, the bridge pattern 720 may be disposed on the interlayer insulating layer and electrically connected to electrodes or bridge patterns included in different conductive layers through contact holes formed through the interlayer insulating layer. Therefore, the bridge patterns 720 may be disposed to be spaced apart from each other.

[0088] Figure 8 It is shown in Figure 2 FIG. 1 is a plan view of an embodiment of a fourth conductive layer in a pixel circuit shown in FIG. Figure 8 , the fourth conductive layer 800 disposed on the substrate will be described.

[0089] The fourth conductive layer 800 may be disposed on the third conductive layer 700 and include a common electrode line 810. The fourth conductive layer 800 may include a common electrode line 810 electrically connected to the gate electrode through the third bridge pattern 520, the first bridge pattern 620, and the second bridge pattern 720 and electrically separated from the voltage supply line 710. The common electrode line 810 is a line commonly connected to the gate electrode 421 of the driving transistor T1 of each unit pixel, and does not represent a line to which another power supply voltage VSS is applied. The fourth conductive layer 800 may be electrically connected to the third conductive layer 700 through a contact hole 830 formed in the fourth insulating layer 140 disposed between the third conductive layer 700 and the fourth conductive layer 800.

[0090] The common electrode lines 810 may be arranged along a second direction DR2 crossing the first direction DR1, and each of the common electrode lines 810 may extend along the first direction DR1 to overlap the pixel circuit region. The common electrode lines 810 may be spaced apart from each other in the second direction DR2 along which the common electrode lines 810 are arranged. For example, when a red sub-pixel, a green sub-pixel, and a blue sub-pixel included in one unit pixel are sequentially arranged along the first direction DR1, each of the common electrode lines 810 may have a stripe pattern extending from the red sub-pixel to the blue sub-pixel along the first direction DR1.

[0091] The number of common electrode lines 810 may be equal to the number of sub-pixels included in one unit pixel. For example, the common electrode line 810 may be formed by a plurality of sub-pixels included in one unit pixel to be connected to corresponding gate electrodes included in the pixel circuit of the sub-pixel. More specifically, when a red sub-pixel, a green sub-pixel, and a blue sub-pixel are included in one unit pixel, the fourth conductive layer 800 may include a first common electrode line 811 connected to a gate electrode 421 of a driving transistor T1 included in a pixel circuit of a red sub-pixel, a second common electrode line 812 connected to a gate electrode 421 of a driving transistor T1 included in a pixel circuit of a green sub-pixel, and a third common electrode line 813 connected to a gate electrode 421 of a driving transistor T1 included in a pixel circuit of a blue sub-pixel.

[0092] The common electrode line 810 may be electrically connected to the gate electrode 421 of the driving transistor T1 through the second bridge pattern 721, the first bridge pattern 621, and the third bridge pattern 522. The fourth insulating layer 140 is disposed on the third conductive layer 700. The fourth insulating layer 140 may include first contact holes 831, 832, and 833 that expose the pixel circuit region of the corresponding sub-pixel. The common electrode line 810 may be connected to the second bridge pattern through the first contact holes 831, 832, and 833 formed in the fourth insulating layer 140, respectively, and connected to the gate electrode of the corresponding sub-pixel via the second bridge pattern, the first bridge pattern, and the third bridge pattern that overlap each other. For example, the first common electrode line 811 may be electrically connected to the second bridge pattern 721 of the third conductive layer 700 through one first contact hole 831 in the pixel circuit region of the red sub-pixel. The first common electrode line 811 may be electrically connected to the gate electrode 421 of the driving transistor T1 for driving the red sub-pixel via the first bridge pattern 621 of the second conductive layer 600 and the third bridge pattern 522 of the fifth conductive layer 500. The second common electrode line 812 may be connected to the second bridge pattern via one first contact hole 832 in the pixel circuit region of the green sub-pixel, and connected to the gate electrode 421 of the driving transistor T1 for driving the green sub-pixel via the second bridge pattern, the first bridge pattern, and the third bridge pattern. In addition, the third common electrode line 813 may be connected to the second bridge pattern via one first contact hole 833 in the pixel circuit region of the blue sub-pixel, and connected to the gate electrode 421 of the driving transistor T1 for driving the blue sub-pixel via the second bridge pattern, the first bridge pattern, and the third bridge pattern.

[0093] On the other hand, since the fourth insulating layer 140 does not include any contact hole in the area other than the pixel circuit area of ​​the corresponding sub-pixel, each of the common electrode lines 810 can be electrically separated from the voltage supply line 710. For example, the fourth insulating layer 140 disposed under the first common electrode line 811 includes one first contact hole 831 in the pixel circuit area of ​​the red sub-pixel, but may not include any contact hole in the pixel circuit area of ​​the green sub-pixel and the pixel circuit area of ​​the blue sub-pixel. Therefore, the first common electrode line 811 can be disposed on the voltage supply line 710 of the third conductive layer 700 and electrically separated from the voltage supply line 710 in the area other than the pixel circuit area of ​​the red sub-pixel.

[0094] Therefore, the common electrode line 810 and the voltage supply line 710 overlap each other with the fourth insulating layer 140 interposed therebetween may form a first storage capacitor. The common electrode line 810 is not electrically connected to the voltage supply line 710 (the voltage supply line 710 overlaps the pixel circuit region included in one unit pixel), but is separated from the voltage supply line 710, thereby forming a storage capacitor between the common electrode line 810 and the voltage supply line 710. Fig. 9 and Fig.10 The storage capacitor is described in detail.

[0095] The fourth bridge pattern 820 may correspond to one of the bridge patterns for connecting the drain electrode of the driving transistor T1 to the anode electrode. Figure 3 and Figure 8 , the fourth bridge pattern 820 may correspond to the second node N2 connected to the anode electrode. The fourth bridge pattern 820 may be connected to the bridge pattern 722 of the third conductive layer 700 through the contact hole 834, and may be connected to the drain electrode of the driving transistor T1 via the bridge pattern 722 of the third conductive layer 700, the bridge pattern 623 of the second conductive layer 600, and the bridge pattern 524 of the fifth conductive layer 500. The drain electrode of the driving transistor T1 may be electrically connected to the anode electrode of the organic light emitting diode through the corresponding path. Although in Figures 4 to 8 Although not shown in the figure, other lines and other patterns may be further provided in the pixel circuit of the sub-pixel included in one unit pixel.

[0096] Fig. 9 It is shown along the Figure 4 A cross-sectional view of a pixel circuit including a first conductive layer to a fifth conductive layer taken along line II' shown in FIG. Fig. 9 , an example of the storage capacitor 900 connected between the voltage supply line 710 and the first node N1 will be described. The storage capacitor 900 may store a voltage corresponding to a data signal, and includes a lower electrode LE and an upper electrode UE.

[0097] Reference Figure 4 and Fig. 9 , the storage capacitor 900 may be formed between the bridge pattern 621 of the second conductive layer 600 connected to the gate electrode 421 of the driving transistor T1 and the voltage supply line 710, and the gate electrode 421 of the driving transistor T1 is connected to the first node N1. The voltage supply line 710 and the bridge pattern 621 of the second conductive layer 600 connected to the gate electrode 421 of the driving transistor T1 may form the storage capacitor 900, and the third insulating layer 130 is interposed between the bridge pattern 621 of the second conductive layer 600 and the voltage supply line 710. The lower electrode LE of the storage capacitor 900 may be formed by the bridge pattern 621 of the second conductive layer 600 connected to the gate electrode 421 of the driving transistor T1, and the upper electrode UE of the storage capacitor 900 may be formed by the voltage supply line 710. For example, in a red sub-pixel included in one unit pixel, the bridge pattern 621 of the second conductive layer 600 forming the lower electrode LE may be connected to the gate electrode 421 of the driving transistor T1 for driving the red sub-pixel. In addition, the voltage supply line 710 forming the upper electrode UE of the third conductive layer 700 may be a conductive pattern extending in the first direction DR1 and widely (broadly) arranged as a shared by sub-pixels. Therefore, the sub-pixels included in one unit pixel share the voltage supply line 710, so that the overlapping area of ​​the upper electrode UE and the lower electrode LE can be increased, thereby increasing the capacitance of the storage capacitor 900.

[0098] Reference Fig. 9 , the storage capacitor 900 may form a first storage capacitor 910 and a second storage capacitor 920 with respect to the voltage supply line 710 of the third conductive layer 700, thereby forming a cavity structure. The first storage capacitor 910 may be formed by each of the common electrode lines 810 and the voltage supply line 710. In addition, the second storage capacitor 920 may be formed by the first bridge pattern 621 included in the second conductive layer 600 and the voltage supply line 710 of the third conductive layer 700.

[0099] For example, in a red sub-pixel included in a unit pixel, the lower electrode LE of the first storage capacitor 910 can be connected to the gate electrode 421 of the driving transistor T1 for driving the red sub-pixel via the third bridge pattern 522 of the fifth conductive layer 500, the first bridge pattern 621 of the second conductive layer 600, and the second bridge pattern 721 of the third conductive layer 700, and formed in the fourth conductive layer 800.

[0100] In addition, the lower electrode LE of the second storage capacitor 920 may be connected to the gate electrode 421 of the driving transistor T1 for driving the red sub-pixel via the third bridge pattern 522 of the fifth conductive layer 500 and formed in the first bridge pattern 621 of the second conductive layer 600 .

[0101] On the other hand, the upper electrodes UE of the first storage capacitor 910 and the second storage capacitor 920 may be formed in the voltage supply line 710 of the third conductive layer 700. Therefore, the storage capacitor 900 forms the first storage capacitor 910 and the second storage capacitor 920 connected in parallel between the gate electrode 421 of the driving transistor T1 and the voltage supply line 710, so that the capacitance of the storage capacitor 900 may be further increased.

[0102] Fig.10 It is shown along the Figure 4 A cross-sectional view of a pixel circuit including a first conductive layer to a fifth conductive layer taken along line II-II' shown in FIG. Fig.10 , another example of the storage capacitor 900 connected between the voltage supply line 710 and the first node N1 will be described.

[0103] Reference Figure 4 and Fig.10 , the first bridge pattern 621 of the second conductive layer 600 connected to the gate electrode 421 of the driving transistor T1 and the voltage supply line 710 may form a storage capacitor 900, and the third insulating layer 130 is interposed between the first bridge pattern 621 and the voltage supply line 710. For example, in a red sub-pixel included in one unit pixel, the lower electrode LE of the storage capacitor 900 may be the first bridge pattern 621 of the second conductive layer 600 connected to the gate electrode 421 of the driving transistor T1 for driving the red sub-pixel, and the upper electrode UE of the storage capacitor 900 may be the voltage supply line 710 of the third conductive layer 700.

[0104] exist Fig.10 In, with Fig. 9 Differently, at a specific position of the pixel circuit area, the first common electrode line 811 of the fourth conductive layer 800 can be electrically connected to the second bridge pattern 721 of the third conductive layer 700 through the first contact hole 831 overlapping the second bridge pattern 721. Therefore, a storage capacitor 900 can be formed at a corresponding position through the first common electrode line 811 and the bridge pattern 721. On the other hand, the storage capacitor 900 can be formed by the first bridge pattern 621 of the second conductive layer 600 and the voltage supply line 710 of the third conductive layer 700. Therefore, the bridge pattern 621 can be a bridge pattern that is set to overlap the voltage supply line 710 among the bridge patterns that connect the gate electrode 421 and the first common electrode line 811 to each other. Therefore, the sub-pixels included in one unit pixel share the voltage supply line 710, so that the overlapping area of ​​the upper electrode UE and the lower electrode LE can be increased, thereby increasing the capacitance of the storage capacitor 900.

[0105] In the following, reference will be described Figures 1 to 10A method of manufacturing a display device is described.

[0106] Fig.11 is a flowchart illustrating an embodiment of a method of manufacturing a display device.

[0107] Reference Figure 4 and Fig.11 In S1010, a first conductive layer may be formed on the substrate to include a gate electrode. In an embodiment, the first conductive layer 400 may be positioned between the substrate and the second conductive layer 600, and include gate electrodes respectively disposed in pixel circuit regions arranged along the first direction DR1 on the substrate. For example, the first conductive layer 400 may include a gate electrode 421 and source and drain electrodes 422 of the driving transistor T1 and a gate electrode 411 and source and drain electrodes 412 of the switching transistor T2, which are included in corresponding pixel circuits of sub-pixels included in one unit pixel.

[0108] The first conductive layer 400 may be formed such that the gate electrode 421 of the driving transistor T1 and the source electrode of the switching transistor T2 overlap each other in the first node N1. In addition, the gate electrode 421 of the driving transistor T1 and the gate electrode 411 of the switching transistor T2 may be spaced apart from each other. The gate electrode 421 of the driving transistor T1 may have a shape extending in the second direction DR2, and the gate electrode 411 of the switching transistor T2 may have a shape extending in the first direction DR1.

[0109] Reference Figure 6 and Fig.11 In S1020 , a second conductive layer may be formed on the first conductive layer to include a first bridge pattern. In an embodiment, the second conductive layer 600 may be positioned between the first conductive layer 400 and the third conductive layer 700 or between the fifth conductive layer 500 and the third conductive layer 700 and include a first bridge pattern 620 .

[0110] The gate line 610 included in the second conductive layer 600 may supply a gate signal to the switching transistor T2 of the sub-pixel included in one unit pixel. The gate line 610 may be connected to the gate electrode 411 of the switching transistor T2 included in the first conductive layer 400 via the bridge pattern 521 included in the fifth conductive layer 500 through a contact hole 631 formed in the second insulating layer 120 disposed on the first conductive layer 400.

[0111] The first bridge pattern 620 included in the second conductive layer 600 may be connected to the gate electrode 421 and the source and drain electrodes 422 of the driving transistor T1 through contact holes 632 , 633 , and 634 formed in the second insulating layer 120 disposed on the first conductive layer 400 , respectively.

[0112] In addition, some of the bridge patterns 622 among the first bridge patterns 620 may be connected to the bridge pattern 523 of the fifth conductive layer 500 through the contact hole 633 , and the bridge pattern 523 may be connected to the source electrode of the driving transistor T1 through the contact hole 534 .

[0113] Some of the bridge patterns 623 among the first bridge patterns 620 may correspond to one of the bridge patterns for connecting the drain electrode of the driving transistor T1 to the anode electrode. For example, the bridge pattern 623 may be connected to the bridge pattern 524 of the fifth conductive layer 500 through the contact hole 634, and the bridge pattern 524 may be connected to the drain electrode of the driving transistor T1 through the contact hole 535.

[0114] Reference Figure 7 and Fig.11 In S1030, a third conductive layer 700 may be formed on the second conductive layer 600 to include a voltage supply line and a second bridge pattern. In an embodiment, the third conductive layer 700 may be disposed on the third insulating layer 130 and include a voltage supply line 710 and a second bridge pattern 720, and the third insulating layer 130 is disposed between the second conductive layer 600 and the third conductive layer 700. In addition, the third conductive layer 700 may electrically connect the second conductive layer 600 and the fourth conductive layer 800 to each other through contact holes formed in the third insulating layer 130 and the fourth insulating layer 140, respectively. In addition, the third conductive layer 700 may form a storage capacitor in which the second conductive layer 600 overlaps the third conductive layer 700 in a plan view.

[0115] The voltage supply line 710 included in the third conductive layer 700 may supply the power supply voltage VDD to the driving transistor T1 of the sub-pixel included in one unit pixel. The voltage supply line 710 may extend along the first direction DR1 to overlap with the pixel circuit region. The pixel circuit region may be a region in which the pixel circuit of the sub-pixel included in one unit pixel is disposed. That is, the voltage supply line 710 may be formed in one conductive pattern to supply the same power supply voltage VDD to the sub-pixels included in one unit pixel.

[0116] The voltage supply line 710 may be electrically connected to the source electrode of the driving transistor T1 of the first conductive layer 400 through the contact hole 731 formed in the third insulating layer 130. For example, the voltage supply line 710 may be electrically connected to the source electrode of the driving transistor T1 via the bridge pattern 622 of the second conductive layer 600 and the bridge pattern 523 of the fifth conductive layer 500.

[0117] The second bridge pattern 720 may be connected to some of the bridge patterns 621 and 623 among the first bridge patterns 620 through second contact holes 732 and 733, respectively, formed in the third insulating layer 130 disposed between the second conductive layer 600 and the third conductive layer 700. For example, some of the bridge patterns 721 among the second bridge patterns 720 may be connected to the gate electrode 421 of the driving transistor T1 via the bridge pattern 621 of the second conductive layer 600 and the bridge pattern 522 of the fifth conductive layer 500.

[0118] Some of the bridge patterns 722 among the second bridge patterns 720 may correspond to one of the bridge patterns for connecting the drain electrode of the driving transistor T1 to the anode electrode. For example, the bridge pattern 722 may be connected to the drain electrode of the driving transistor T1 via the bridge pattern 623 of the second conductive layer 600 and the bridge pattern 524 of the fifth conductive layer 500 through a contact hole 733 formed in the third insulating layer 130 disposed between the second conductive layer 600 and the third conductive layer 700.

[0119] Reference Figure 8 and Fig.11 In S1040, a fourth conductive layer 800 may be formed on the third conductive layer 700 to include a common electrode line. In an embodiment, the fourth conductive layer 800 may be disposed on the third conductive layer 700 and include a common electrode line 810, and a fourth insulating layer 140 is disposed between the third conductive layer 700 and the fourth conductive layer 800. The fourth conductive layer 800 may include a common electrode line 810 electrically connected to the gate electrode through the first bridge pattern 620 and the second bridge pattern 720 and electrically separated from the voltage supply line 710.

[0120] The common electrode lines 810 may be arranged in a second direction DR2 crossing the first direction DR1. Each of the common electrode lines 810 may extend in the first direction DR1 to overlap the pixel circuit region. The common electrode lines 810 may be spaced apart from each other in the second direction DR2 along which the common electrode lines 810 are arranged.

[0121] The number of common electrode lines 810 may be equal to the number of sub-pixels included in one unit pixel. For example, the common electrode line 810 may be formed by a plurality of sub-pixels included in one unit pixel to be connected to corresponding gate electrodes included in pixel circuits of the sub-pixels.

[0122] The common electrode line 810 may be electrically connected to the gate electrode 421 of the driving transistor T1 through the second bridge pattern 721, the first bridge pattern 621, and the third bridge pattern 522. The fourth insulating layer 140 disposed between the third conductive layer 700 and the fourth conductive layer 800 may include first contact holes 831, 832, and 833. Each of the common electrode lines 810 may be connected to the second bridge pattern through the first contact holes 831, 832, and 833, and connected to the gate electrode of the corresponding sub-pixel via the second bridge pattern, the first bridge pattern, and the third bridge pattern overlapping each other. On the other hand, since each of the common electrode lines 810 does not include any contact hole in an area other than the pixel circuit area of ​​the corresponding sub-pixel, each of the common electrode lines 810 may be electrically separated from the voltage supply line 710.

[0123] In addition, the voltage supply line 710 and the common electrode line 810 may form a first storage capacitor. The common electrode line 810 is not electrically connected to the voltage supply line 710 (the voltage supply line 710 overlaps a pixel circuit region included in one unit pixel), but is separated from the voltage supply line 710, thereby forming a storage capacitor between the common electrode line 810 and the voltage supply line 710.

[0124] The fourth bridge pattern 820 may correspond to one of the bridge patterns for connecting the drain electrode of the driving transistor T1 to the anode electrode. For example, the fourth bridge pattern 820 may correspond to the second node N2 connected to the anode electrode, and the fourth bridge pattern 820 may be connected to the drain electrode of the driving transistor T1 via the bridge pattern 722 of the third conductive layer 700, the bridge pattern 623 of the second conductive layer 600, and the bridge pattern 524 of the fifth conductive layer 500. The drain electrode of the driving transistor T1 may be electrically connected to the anode electrode of the organic light emitting diode through the corresponding path. The fifth insulating layer 150 may be formed on the fourth conductive layer 800.

[0125] According to the present disclosure, it is possible to provide a display device capable of including electronic elements with ultra-high resolution in a relatively small area and a method of manufacturing the display device.

[0126] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless specifically indicated otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A display device, comprising: substrate; A first conductive layer, on the substrate and comprising gate electrodes, wherein the gate electrodes are respectively arranged in pixel circuit regions arranged along a first direction; A second conductive layer, disposed on the first conductive layer, wherein the second conductive layer comprises a first bridge pattern; a third conductive layer disposed on the second conductive layer, the third conductive layer comprising a voltage supply line for supplying a driving voltage and a second bridge pattern; as well as a fourth conductive layer disposed on the third conductive layer, the fourth conductive layer comprising a common electrode line, the common electrode line being electrically connected to the gate electrode through the first bridge pattern and the second bridge pattern and being electrically separated from the voltage supply line, The common electrode lines are arranged along a second direction crossing the first direction, and each of the common electrode lines extends along the first direction to overlap the pixel circuit region.

2. The display device according to claim 1, wherein: Each of the common electrode lines forms a first storage capacitor together with the voltage supply line.

3. The display device according to claim 2, wherein: Each of the first bridge patterns forms a second storage capacitor together with the voltage supply line.

4. The display device according to claim 1, wherein: The voltage supply line extends along the first direction to overlap the pixel circuit region.

5. The display device according to claim 1, wherein: Pixel circuits of sub-pixels included in one unit pixel are provided in the pixel circuit region, and the gate electrodes are respectively included in the pixel circuits of the sub-pixels.

6. The display device according to claim 5, wherein: The number of the common electrode lines in the one unit pixel is equal to the number of the sub-pixels included in the one unit pixel.

7. The display device according to claim 1, wherein: The first bridge pattern and the second bridge pattern overlap each other, wherein the common electrode line is connected to the second bridge pattern through a first contact hole, and The second bridge pattern is connected to the first bridge pattern through a second contact hole.

8. The display device according to claim 7, wherein: The common electrode lines in one unit pixel are connected to the second bridge patterns through the first contact holes, respectively. 9 . The display device according to claim 1 , further comprising a fifth conductive layer including a data line for supplying a data signal and disposed between the first conductive layer and the second conductive layer.

10. The display device according to claim 9, wherein: The fifth conductive layer further includes a third bridge pattern, and The common electrode line is electrically connected to the gate electrode through the first bridge pattern, the second bridge pattern and the third bridge pattern.

11. The display device according to claim 1, wherein: The second conductive layer further includes a gate line for supplying a gate signal.

12. A method for manufacturing a display device, the method comprising: forming a first conductive layer on a substrate, wherein the first conductive layer includes gate electrodes respectively disposed in pixel circuit regions arranged along a first direction; forming a second conductive layer disposed on the first conductive layer, wherein the second conductive layer includes a first bridge pattern; forming a third conductive layer disposed on the second conductive layer, the third conductive layer including a voltage supply line for supplying a driving voltage and a second bridge pattern; as well as forming a fourth conductive layer disposed on the third conductive layer, the fourth conductive layer including a common electrode line electrically connected to the gate electrode through the first bridge pattern and the second bridge pattern and electrically separated from the voltage supply line, The common electrode lines are arranged along a second direction crossing the first direction, and each of the common electrode lines extends along the first direction to overlap the pixel circuit region.

13. The method according to claim 12, wherein: Each of the common electrode lines forms a first storage capacitor together with the voltage supply line.

14. The method according to claim 13, wherein: Each of the first bridge patterns forms a second storage capacitor together with the voltage supply line.

15. The method according to claim 12, wherein: The voltage supply line extends along the first direction to overlap the pixel circuit region.

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