Array substrate and display device

Abstract

The invention provides an array substrate and a display device, belongs to the technical field of display, and can solve the problem that an existing array substrate is low in light transmittance. The array substrate comprises a substrate, a first signal line and a second signal line, the first signal line and the second signal line intersect to define a pixel region; the array substrate further comprises a first thin film transistor located on the substrate and arranged in the pixel area. The first thin film transistor includes: a first semiconductor layer; the first semiconductor layer comprises a first connecting part, a second connecting part and a third connecting part which are connected with one another; the orthographic projection of the first connecting part on the substrate is overlapped with the orthographic projection of the second signal line on the substrate; the orthographic projection of the third connecting part on the substrate falls between the orthographic projections of the adjacent second signal lines on the substrate, and is overlapped with the orthographic projection of the first signal line on the substrate; a first included angle is formed between the extension direction of the second connecting part and the extension direction of the first connecting part; the angle of the first included angle ranges from 90 degrees to 180 degrees.

Description

Array substrate and display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to an array substrate and a display device. Background Art

[0002] With the continuous development of display technology, high-PPI (pixel per inch) products such as augmented reality (AR) and virtual reality (VR) displays have attracted much attention in the display industry. However, due to factors such as increased metal wiring density, the aperture ratio and transmittance of high-PPI products in AR and VR products are significantly lower than those of conventional products.

[0003] In order to improve the aperture ratio and transmittance of AR and VR products, more complex process technology is needed, such as the use of low-temperature polycrystalline oxide (LTPO) technology. Although LTPO technology integrates two thin-film field-effect transistors (TFTs), low-temperature polysilicon (LTPS) and oxide, its production process involves many process steps, which increases production costs. In addition, the aperture ratio and transmittance of current AR and VR products still cannot meet users' demand for high aperture ratio and high transmittance, and further improvement is needed.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides an array substrate and a display device.

[0006] In a first aspect, an embodiment of the present disclosure provides an array substrate having a display area, wherein the array substrate comprises: a substrate, a first signal line and a second signal line located on one side of the substrate; the first signal line and the second signal line intersecting to define a pixel area; the array substrate further comprises: a first thin film transistor located on the substrate and disposed in the pixel area;

[0007] The first thin film transistor includes: a first semiconductor layer; the first semiconductor layer includes: a first connecting portion, a second connecting portion and a third connecting portion connected to each other;

[0008] The extension direction of the first connecting portion and the third connecting portion is the same as the extension direction of the second signal line; the orthographic projection of the first connecting portion on the substrate overlaps with the orthographic projection of the second signal line on the substrate; the orthographic projection of the third connecting portion on the substrate falls between adjacent orthographic projections of the second signal line on the substrate and overlaps with the orthographic projection of the first signal line on the substrate;

[0009] An extending direction of the second connecting portion and an extending direction of the first connecting portion form a first angle; the first angle is in a range of 90 degrees to 180 degrees.

[0010] Optionally, the first thin film transistor further includes: a light shielding layer, a second gate insulating layer, a first gate electrode, a second interlayer insulating layer and a first source electrode;

[0011] The light-shielding layer is located on the substrate; the second gate insulating layer covers the first semiconductor layer; the first gate is part of the first signal line and is located on the side of the second gate insulating layer away from the substrate; the second interlayer insulating layer covers the first gate; the first source is part of the second signal line and is located on the side of the second interlayer insulating layer away from the substrate; the first source is connected to the first connecting portion through a first via hole that penetrates the second gate insulating layer and the second interlayer insulating layer.

[0012] Optionally, along the extension direction of the first signal line, a width of at least one side of the first connecting portion is 0 to 3 micrometers greater than a width of the first via hole.

[0013] Optionally, an orthographic projection of the first via hole on the substrate falls outside an orthographic projection of the light shielding layer on the substrate.

[0014] Optionally, a distance between an edge of an orthographic projection of the first via hole on the substrate close to the light shielding layer and an edge of an orthographic projection of the light shielding layer on the substrate close to the first via hole is 0.5 micrometers to 10 micrometers.

[0015] Optionally, the array substrate further comprises: a first passivation layer located on a side of the first source electrode away from the substrate, and a first transfer electrode located on a side of the first passivation layer away from the substrate;

[0016] The first switching electrode is connected to the third connection portion through a second via hole that penetrates the first passivation layer, the second interlayer insulating layer, and the second gate insulating layer.

[0017] Optionally, the array substrate further comprises: a planarization layer located on the first switching electrode, and a pixel electrode located on the planarization layer;

[0018] The pixel electrode is connected to the first switching electrode through a third via hole penetrating the planarization layer.

[0019] Optionally, along the extension direction of the second signal line, the width of the first via is 1.9 microns to 2.5 microns; along the extension direction of the first signal line, the width of the second via is 1.9 microns to 2.5 microns; along the extension direction of the first signal line, the width of the third via is 2.5 microns to 3.0 microns.

[0020] Optionally, an orthographic projection of the third via hole on the substrate falls within an orthographic projection of the light shielding layer on the substrate.

[0021] Optionally, along the extension direction of the first signal line, a distance between an edge of an orthographic projection of the third via hole on the substrate and an edge of an orthographic projection of the light shielding layer on the substrate is 1.0 to 1.5 microns.

[0022] Optionally, the array substrate further comprises: a supporting structure located on the pixel electrode and arranged at the position of the third via hole;

[0023] An extending direction of the supporting structure is the same as an extending direction of the first signal line.

[0024] Optionally, the orthographic projection of the support structure on the substrate covers the orthographic projection of the third via hole on the substrate.

[0025] Optionally, a recessed portion is formed at a portion of the support structure, the position of the recessed portion corresponds to the position of the supported spacer, and the orthographic projection of the recessed portion on the substrate overlaps with the orthographic projection of the third via on the substrate.

[0026] Optionally, the slope angle of the support structure is 30 degrees to 70 degrees.

[0027] Optionally, a second passivation layer and a common electrode located between the pixel electrode and the support structure;

[0028] The common electrode is made of transparent metal.

[0029] Optionally, the array substrate further comprises: a metal layer located on the second passivation layer;

[0030] The orthographic projection of the metal layer on the substrate is located between the orthographic projections of adjacent pixel electrodes on the substrate.

[0031] Optionally, the array substrate further comprises a peripheral region disposed on at least one side of the display region, and the array substrate further comprises: a second thin film transistor located on the substrate and disposed in the peripheral region;

[0032] The second thin film transistor includes: a second semiconductor layer, a first gate insulating layer, a second gate, a first interlayer insulating layer, a second source electrode and a second drain electrode;

[0033] The second source and the second drain are both located on the side of the second interlayer insulating layer away from the substrate, and the second source and the second drain are respectively connected to the two ends of the second semiconductor layer through vias passing through the first gate insulating layer, the first interlayer insulating layer, the second gate insulating layer, and the second interlayer insulating layer.

[0034] Optionally, the second gate is provided on the same layer as the light shielding layer;

[0035] The second source and the second drain are both arranged in the same layer as the first source.

[0036] Optionally, the array substrate also includes: a light-shielding layer wiring, a gate layer wiring and a gate transfer electrode second transfer electrode that are electrically connected to each other; the light-shielding layer wiring is arranged on the same layer as the light-shielding layer; the gate layer wiring is arranged on the same layer as the first gate; and the second transfer electrode is arranged on the same layer as the first source.

[0037] Optionally, at least one edge of an orthographic projection of the light shielding layer on the substrate falls within an orthographic projection of the first gate on the substrate.

[0038] Optionally, a distance between at least one edge of an orthographic projection of the light shielding layer on the substrate and an edge of an orthographic projection of the first gate on the substrate is 0 micrometers to 2.0 micrometers.

[0039] Optionally, in the same row of the first thin film transistors, the light shielding layers in adjacent first thin film transistors are disconnected.

[0040] Optionally, an edge of the orthographic projection of the first semiconductor layer on the substrate close to the disconnection position falls within the orthographic projection of the light-shielding layer on the substrate.

[0041] Optionally, a distance between an edge of an orthographic projection of the light shielding layer on the substrate close to the disconnection position and an edge of an orthographic projection of the first semiconductor layer on the substrate close to the disconnection position is 0.3 micrometer to 1.0 micrometer.

[0042] Optionally, the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the first via hole on the substrate.

[0043] Optionally, a distance between an edge of an orthographic projection of the light shielding layer on the substrate and an edge of an orthographic projection of the first via hole on the substrate is 0.5 micrometers to 1.5 micrometers.

[0044] Optionally, the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the second signal line on the substrate.

[0045] Optionally, a distance between an edge of an orthographic projection of the light shielding layer on the substrate and an orthographic projection of the second signal line on the substrate is 0.3 micrometers to 2.0 micrometers.

[0046] In a second aspect, an embodiment of the present disclosure provides a display device, wherein the display device includes the array substrate provided as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1 is a schematic structural diagram of an array substrate provided in an embodiment of the present disclosure.

[0048] FIG. 2 is a schematic diagram of a partial planar structure of the array substrate shown in FIG. 1 .

[0049] FIG2 ′ is a schematic diagram of another partial planar structure of the array substrate shown in FIG1 .

[0050] FIG3 a is a schematic diagram of a top view of the structure of an array substrate provided in an embodiment of the present disclosure.

[0051] FIG. 3 b is a schematic diagram of the cross-sectional structure of the display substrate shown in FIG. 3 a at position AA′.

[0052] FIG. 3 c is a schematic diagram of the cross-sectional structure of the display substrate shown in FIG. 3 a at position BB′.

[0053] FIG3 d is a schematic diagram of the cross-sectional structure of the display substrate shown in FIG3 a at position CC′.

[0054] FIG. 4 is a schematic diagram of a first improved structure of a part of the array substrate shown in FIG. 2 .

[0055] FIG4 ′ is a schematic diagram of a cross-sectional structure of the structure shown in FIG4 along position DD′.

[0056] FIG5 is a schematic diagram showing the effect of the light shielding layer size on the light leakage current.

[0057] FIG6 is a schematic diagram of a second improved structure of a part of the array substrate shown in FIG2 .

[0058] FIG. 7 is a schematic diagram of a third improved structure of a portion of the array substrate shown in FIG. 2 .

[0059] FIG8 is a schematic diagram of a fourth improved structure of a part of the array substrate shown in FIG2 .

[0060] 9a to 9k are schematic diagrams of intermediate structures corresponding to various steps in the method for preparing an array substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0062] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0063] The thin film transistors used in the embodiments of the present disclosure may also be field effect transistors or other devices with the same characteristics. In addition, transistors can be divided into N-type and P-type according to their characteristics. The following embodiments are described using N-type transistors. When an N-type transistor is used, when a high-level signal is input to the gate, the source and drain are turned on, while the P-type is the opposite. It is conceivable that the use of P-type transistors is something that a person skilled in the art can easily think of without creative work, and therefore is also within the scope of protection of the embodiments of the present disclosure.

[0064] It should be further explained that in the array substrate provided in the embodiments of the present disclosure, the thin film transistor in the display area is referred to as the first thin film transistor, and the thin film transistor in the peripheral area is referred to as the second thin film transistor. The first thin film transistor may be an oxide thin film transistor, wherein the first semiconductor layer is an oxide semiconductor layer, and the second thin film transistor may be a low-temperature polycrystalline silicon thin film transistor, wherein the second semiconductor layer is a low-temperature polycrystalline silicon semiconductor layer. It is understood that the first thin film transistor and the second thin film transistor may also be other types of thin film transistors, which are not listed here one by one.

[0065] In a first aspect, an embodiment of the present disclosure provides an array substrate. FIG1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure, and FIG2 is a schematic planar structural diagram of a portion of the array substrate shown in FIG1 . As shown in FIG1 and FIG2 , the array substrate has a display area AA, and includes: a substrate 101, a first signal line, and a second signal line located on the substrate 101. The first signal line can be a line extending along a first direction, and the second signal line can be a line extending along a second direction. For example, the first signal line can be a gate line 102, and the second signal line can be a data line 103. In the following description, the gate line 102 and the data line 103 will be used as an example for detailed description. The gate line 102 and the data line 103 intersect to define a pixel area; the array substrate further includes: an oxide thin film transistor 104 located on the substrate 101 and disposed in the pixel area; the oxide thin film transistor 104 includes: an oxide semiconductor layer 1041; the oxide semiconductor layer 1041 includes: a first connecting portion 1041a, a second connecting portion 1041b and a third connecting portion 1041c connected to each other; the extension direction of the first connecting portion 1041a and the third connecting portion 1041c are both aligned with the extension direction of the data line 103 The orthographic projection of the first connecting portion 1041a on the substrate 101 overlaps with the orthographic projection of the data line 103 on the substrate 101; the orthographic projection of the third connecting portion 1041c on the substrate 101 falls between the orthographic projections of adjacent data lines 103 on the substrate 101, and overlaps with the orthographic projection of the gate line 102 on the substrate 101; a first angle α is formed between the extension direction of the second connecting portion 1041b and the extension direction of the first connecting portion 1041a; the angle of the first angle α is 90 degrees to 180 degrees.

[0066] The substrate 101 can be made of a rigid material such as glass to improve the substrate 101's ability to support other film layers thereon. Alternatively, the substrate 101 can be made of a flexible material such as polyimide (PI) to improve the overall bending and stretching resistance of the metal oxide thin film transistor, thereby preventing stress generated during bending, stretching, and twisting from causing the substrate 101 to break and cause a short circuit. In practical applications, the material of the substrate 101 can be appropriately selected based on actual needs to ensure good performance of the metal oxide thin film transistor.

[0067] It is understood that a buffer layer 101a can also be provided on the substrate 101. The buffer layer 101a can be made of at least one material selected from silicon nitride (SiN) and silicon oxide (SiO2). It can form a single-layer structure made of a single material or a multi-layer structure made of a variety of different materials, wherein the film layer in contact with the low-temperature polycrystalline silicon semiconductor layer 2011 is a SiO2 layer to prevent gases such as water and oxygen from invading from one side of the substrate 101 into other film layers thereon and causing damage to the array substrate. The buffer layer 101a can specifically be a stacked structure of silicon nitride (SiN) and silicon oxide (SiO2), wherein the thickness of the silicon nitride (SiN) is to The thickness of silicon oxide (SiO2) is to

[0068] The gate line 102 can be made of a metal material, such as one of molybdenum (Mo), aluminum (Al), titanium (Ti), or an alloy of the above-mentioned multiple materials, and can be a single-layer structure or a multi-layer structure. The data line 103 can also be made of the same material as the gate line 102. Wherein, the gate line 102 can extend along a first direction on the substrate 101, and the data line 103 extends along a second direction on the substrate 101, wherein the first direction and the second direction intersect and are parallel to the substrate 101, for example, the first direction can be a row direction, and the second direction can be a column direction. Specifically, the gate line 102 and the data line 103 are perpendicular to each other. The gate line 102 and the data line intersect to define a pixel area, and a pixel driving circuit is provided in the pixel area. The gate line 102 can provide a gate signal to the pixel driving circuit of the same row, and the data line 103 can provide a data signal to the corresponding pixel driving circuit to drive the liquid crystal molecules in the corresponding pixel area to deflect and realize the display function.

[0069] The oxide thin film transistor 104 is disposed in the pixel region and includes an oxide semiconductor layer 1041. The oxide semiconductor layer 1041 can be made of at least one of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), and indium tin zinc oxide (ITZO), which can reduce leakage current in the oxide thin film transistor 104.

[0070] The oxide semiconductor layer 1041 includes a first connecting portion 1041a, a second connecting portion 1041b, and a third connecting portion 1041c. The second connecting portion 1041b is located between the first connecting portion 1041a and the third connecting portion 1041c, with its ends connected to the first connecting portion 1041a and the third connecting portion 1041c, respectively. The orthographic projection of the first connecting portion 1041a on the substrate 101 may overlap with the orthographic projection of the data line 103 on the substrate 101. The first connecting portion 1041a and the second connecting portion 1041b may be conductively connected to form a conductive portion, serving as a source contact region. The orthographic projection of a portion of the third connection portion 1041c on the substrate 101 can overlap with the orthographic projection of the gate line 102 on the substrate 101, and the overlapping area of ​​the third connection portion 1041c with the gate line 102 can be used as a channel, wherein the area that does not overlap with the gate line 102 can be conductorized to form a conductor portion, the portion close to the second connection portion 1041b is connected to the second connection portion 1041b, and the portion away from the second connection portion 1041b is used as a drain contact area.

[0071] The first connection portion 1041a and the third connection portion 1041c may extend in the same direction. Specifically, the first connection portion 1041a and the third connection portion 1041c may extend in the same direction as the data line 103. The third connection portion 1041c is located between adjacent data lines 103. The second connection portion 1041b and the first connection portion 1041a have a first angle α therebetween. The first angle α is in a range from 90 to 180 degrees, for example, 120 degrees.

[0072] In the array substrate provided by the embodiment of the present disclosure, the oxide semiconductor layer 1041 of the oxide thin film transistor 104 is bent, wherein the orthographic projection of the first connecting portion 1041a on the substrate 101 overlaps with the orthographic projection of the data line 103 on the substrate 101, facilitating its connection to the data line 103. The orthographic projection of the third connecting portion 1041c on the substrate 101 overlaps with the orthographic projection of the gate line 102 on the substrate 101. This eliminates the need to protrude a portion of the gate line 103 into the pixel area to serve as the first gate of the oxide thin film transistor 104 (described in detail later). This can reduce the obstruction of the pixel area by the first gate, increase the aperture ratio of the pixel area, and improve light transmittance. At the same time, the position of the channel of the oxide thin film transistor 104 can be adjusted by controlling the bending angle of the second connecting portion 1041b (i.e., the first angle α), which helps to increase the pixel density of the array substrate to meet user requirements for high PPI. Furthermore, the oxide semiconductor layer 1041 of the oxide thin film transistor 104 can reduce its leakage current, and the oxide semiconductor layer 1041 is a transparent structure, thereby further improving the display effect of the array substrate.

[0073] In some embodiments, as shown in Figures 1 and 2, the oxide thin film transistor 104 further includes: a light shielding layer 1043, a second gate insulating layer 1045, a first gate electrode 1046, a second interlayer insulating layer 1047 and a first source electrode 1048; the light shielding layer 1043 is located on the substrate 101; the second gate insulating layer 1045 covers the oxide semiconductor layer 1041; the first gate electrode 1046 is part of the gate line 102 and is located on the side of the second gate insulating layer 1045 away from the substrate 101; the second interlayer insulating layer 1047 covers the first gate electrode 1046; the first source electrode 1048 is part of the data line 103 and is located on the side of the second interlayer insulating layer 1047 away from the substrate 101; the first source electrode 1048 is connected to the first connection portion 1041a through a first via hole V1 that penetrates the second gate insulating layer 1045 and the second interlayer insulating layer 1047.

[0074] The light shielding layer 1043 blocks light, preventing light from irradiating the substrate 101 side and reaching the channel of the oxide semiconductor layer 1041 in the display area AA. This protects the oxide semiconductor layer 1041 and prevents light from affecting the performance of the oxide semiconductor layer 1041, thereby improving the stability of the oxide thin film transistor 104. The light shielding layer 1043 can be made of a metal material, such as copper, aluminum, molybdenum, or an alloy of these materials, and can have a single-layer structure or a multi-layer structure.

[0075] The second gate insulating layer 1045 can be made of at least one of silicon nitride (SiN) and silicon oxide (SiO2). It can form a single-layer structure made of a single material or a multi-layer structure made of multiple different materials. Its thickness can be to The oxide semiconductor layer 1041 may be protected to prevent a short circuit between the oxide semiconductor layer 1041 and other film layers thereon.

[0076] The first gate 1046 can be a part of the gate line 102. The first gate 1046 can be formed at the same time as the gate line 102 is formed. It can be made of a metal material, such as molybdenum (Mo), aluminum (Al), titanium (Ti), or an alloy of the above materials. It can be a single-layer structure or a multi-layer structure with a total thickness of to

[0077] The second interlayer insulating layer 1047 can be made of at least one of silicon nitride (SiN) and silicon oxide (SiO2). It can form a single-layer structure made of a single material or a multi-layer structure made of multiple different materials. Its thickness can be to The second interlayer insulating layer 1047 can prevent the first gate 1046 from being short-circuited with other film layers thereon.

[0078] The first source electrode 1048 can be a part of the data line 103. The first source electrode 1048 can be formed at the same time as the data line 103 is formed. It can be made of a metal material, such as molybdenum (Mo), aluminum (Al), titanium (Ti), or an alloy of the above materials. It can be a single-layer structure or a multi-layer structure with a total thickness of to The first source electrode 1048 is connected to the first connection portion 1041 a of the oxide semiconductor layer 1041 through the first via hole V1 , and can input a data signal provided by the data line 103 to the first connection portion 1041 a of the oxide semiconductor layer 1041 .

[0079] In some embodiments, as shown in FIG. 2 , along the extending direction of the gate line 102 , the width of at least one side of the first connection portion 1041 a is 0 to 3 micrometers greater than the width of the first via hole V1 .

[0080] The first source electrode 1048 is connected to the first connecting portion 1041a via a first via hole V1 that penetrates the second gate insulating layer 1045 and the second interlayer insulating layer 1047. The first connecting portion 1041a is width-compensated at a position corresponding to the first via hole V1, such that the width of at least one side of the first connecting portion 1041a is 0 to 3 microns greater than the width of the first via hole V1. This prevents excessive OL deviation and etching deviation from causing the first via hole V1 to be too deep, thereby hitting the light shielding layer 1043 and causing a short circuit. For example, the width of both sides of the first connecting portion 1041a is 0 to 3 microns greater than the width of the first via hole V1, as indicated by the arrows on both sides of the first via hole V1 in FIG. Specifically, along the extension direction of the data line 103, the width of the first via hole V1 can be 1.9 to 2.5 microns, for example, 1.9 microns. It is understood that the width of the first via hole V1 may also be 1.9 microns to 2.5 microns, for example, 1.9 microns, along the extension direction of the gate line 102. The first via hole V1 may be formed as a regular square hole, a circular hole, or a hole of other shapes. For example, in actual applications, the first via hole V1 is a circular hole.

[0081] In some embodiments, as shown in FIG. 1 and FIG. 2 , the orthographic projection of the first via hole V1 on the substrate 101 falls outside the orthographic projection of the light shielding layer 1043 on the substrate 101 .

[0082] The orthographic projection of the first via hole V1 on the substrate 101 and the orthographic projection of the light shielding layer 1043 on the substrate 101 do not overlap. Even if the depth of the first via hole V1 is too great due to excessive OL deviation and etching deviation, the first via hole V1 can be prevented from hitting the light shielding layer 1043 and causing a short circuit. Specifically, the distance between the edge of the orthographic projection of the first via hole V1 on the substrate 101 close to the light shielding layer 1043 and the edge of the orthographic projection of the light shielding layer 1043 on the substrate close to the first via hole V1 is 0.5 microns to 10 microns, for example, 0.5 microns.

[0083] The width of the data line 103 needs to be set to ensure data signal transmission while avoiding occupying a large area and affecting light transmittance. Specifically, as shown in Figures 1 and 2, along the extension direction of the gate line 102, the width of the data line 103 can be set to 1.3 microns to 1.5 microns, for example, 1.3 microns.

[0084] In some embodiments, as shown in FIG. 1 , FIG. 2 , and FIG. 2 ′, an orthographic projection of the second via hole V2 on the substrate 101 at least partially overlaps with an orthographic projection of the light shielding layer 1043 on the substrate 101 .

[0085] The orthographic projection of the second via hole V2 on the substrate 101 may overlap with the orthographic projection of the light shielding layer 1043 on the substrate 101. For example, in FIG2 , the orthographic projection of the second via hole V2 on the substrate 101 falls within the orthographic projection of the light shielding layer 1043 on the substrate 101. Alternatively, as in FIG2 ′, the orthographic projection of the second via hole V2 on the substrate 101 only partially overlaps with the orthographic projection of the light shielding layer 1043 on the substrate 101. The light shielding layer 1043 may at least partially cover the position of the second via hole V2 to prevent light leakage from the second via hole V2 and affect the display effect.

[0086] In some embodiments, as shown in Figures 1 and 2, the oxide thin film transistor 104 further includes: a first passivation layer 1049 located on the side of the first source 1048 away from the substrate 101, and a first transfer electrode 1050 located on the side of the first passivation layer 1049 away from the substrate 101; the first transfer electrode 1050 is connected to the third connection portion 1041c through a second via hole V2 that penetrates the first passivation layer 1049, the second interlayer insulating layer 1047 and the second gate insulating layer 1045.

[0087] The first passivation layer 1049 can be made of at least one of silicon nitride (SiN) and silicon oxide (SiO2), and can be formed into a single-layer structure made of a single material or a multi-layer structure made of multiple different materials. The first passivation layer 1049 can prevent a short circuit between the first source electrode 1048 and other film layers thereon.

[0088] The first transfer electrode 1050 and the first source electrode 1048 are disposed in different film layers to avoid short circuits between the two due to the presence of numerous conductive layers in the same film layer. Furthermore, the first transfer electrode 1050 can be made of a transparent conductive material such as indium tin oxide (ITO) to prevent light from being blocked by the first transfer electrode 1050 and thereby improve the overall light transmittance of the array substrate.

[0089] In some embodiments, as shown in FIG. 1 and FIG. 2 , along the extension direction of the gate line 102 , at the position of the second via hole V2 , the width of the third connection portion 1041 c is 0 to 3 micrometers greater than the width of the second via hole V2 .

[0090] The first transfer electrode 1050 is connected to the third connection portion 1041c via a second via hole V2 that penetrates the first passivation layer 1049, the second interlayer insulating layer 1047, and the second gate insulating layer 1045. The third connection portion 1041c is width-compensated at a position corresponding to the second via hole V2, such that the width of the third connection portion 1041c is 0 to 3 microns greater than the width of the second via hole V2. This prevents the second via hole V2 from being too deep due to excessive OL deviation and etching deviation, which could cause the light shielding layer 1043 to short-circuit. Specifically, along the extension direction of the data line 103, the width of the second via hole V2 can be 1.9 to 2.5 microns, for example, 1.9 microns. It is understood that along the extension direction of the gate line 102, the width of the second via hole V2 can also be 1.9 to 2.5 microns, for example, 1.9 microns. The second via hole V2 may be formed into a regular square hole, which is beneficial for the connection between the first transfer electrode 1050 and the third connection portion 1041 c.

[0091] In some embodiments, as shown in FIG. 1 and FIG. 2 , the distance between the second via hole V2 and the adjacent data line 103 is 1.8 micrometers to 2.5 micrometers.

[0092] Because the third connection portion 1041c is disposed between adjacent data lines 103, the corresponding second via V2 is also disposed between adjacent data lines 103. A certain distance is provided between the second via V2 and the adjacent data line 103 to prevent the second via V2 from interrupting the data line 103, causing a short circuit and affecting data signal transmission. Specifically, the distance between the second via V2 and the adjacent data line 103 is 1.8 microns to 2.5 microns, for example, 1.8 microns.

[0093] In some embodiments, as shown in Figures 1 and 2, the array substrate further includes: a planarization layer 105 located on the first transfer electrode 1050, and a pixel electrode 106 located on the planarization layer 105; the pixel electrode 106 is connected to the second drain 1050 through a third via hole V3 penetrating the planarization layer 105.

[0094] The planarization layer 105 can be provided on the second drain electrode 1050. The planarization layer 105 can be made of an organic material such as acrylic, resin, polyimide or benzocyclobutene, and the specific material can be selected according to actual needs. The planarization layer 105 can flatten the second drain electrode 1050 to form a relatively flat surface, which facilitates the bonding of other film layers thereon. In addition, due to the presence of the planarization layer 105, the distance between the second drain electrode 1050 and other conductive film layers in the oxide thin film transistor 104 can be increased, thereby avoiding the generation of parasitic capacitance between the second drain electrode 1050 and other conductive film layers thereon.

[0095] The pixel electrode 106 can be disposed on the planarization layer 105. The pixel electrode 106 can be made of a transparent conductive material such as indium tin oxide (ITO) to prevent the pixel electrode 106 from blocking light and improve the overall light transmittance of the array substrate. The pixel electrode 106 can be electrically connected to the second drain electrode 1050 via a third via hole V3 that penetrates the planarization layer 105 to input a data signal to the pixel electrode 106. Specifically, along the extension direction of the gate line 103, the width of the third via hole V3 is 2.5 microns to 3.0 microns, for example, 2.5 microns, to ensure a stable connection between the pixel electrode 106 and the third connecting portion 1041c.

[0096] In some embodiments, as shown in FIG. 1 and FIG. 2 , the orthographic projection of the third via hole V3 on the substrate 101 falls within the orthographic projection of the light shielding layer 1043 on the substrate 101 .

[0097] The light shielding layer 1043 can shield the third via hole V3 to prevent light leakage from the third via hole V3 and affect the display effect. Specifically, along the extension direction of the gate line 102, the distance between the edge of the orthographic projection of the third via hole V3 on the substrate 101 and the edge of the orthographic projection of the light shielding layer 1043 on the substrate 101 is 1.0 to 1.5 microns, for example, 1.0 micron.

[0098] In some embodiments, as shown in Figures 1 and 2, the array substrate further includes: a support structure 107 located on the pixel electrode 106 and disposed at the position of the third via hole V3; as shown in Figure 3a, the extension direction of the support structure 107 is the same as the extension direction of the gate line 102.

[0099] The support structure 107 can be embedded in the third via hole V3 and can form a strip-shaped structure along the extension direction of the gate line 102, and can penetrate the entire array substrate. When forming a display panel, the support structure 107 can support the spacers in the color filter substrate to prevent the spacers from slipping and scratching the display devices in the array substrate, thereby affecting the display effect.

[0100] In some embodiments, as shown in FIG. 1 and FIG. 2 , the orthographic projection of the support structure 107 on the substrate 101 covers the orthographic projection of the third via hole V3 on the substrate 101 .

[0101] The support structure 107 extends throughout the entire array substrate. In some locations, the support structure 107 can correspond to spacers in the color filter substrate. At these locations, the support structure 107 has a larger area. The orthographic projection of the support structure 107 on the substrate 101 overlaps the orthographic projection of the third via V3 on the substrate 101, providing a larger platform for the spacers on the color filter substrate. This prevents the spacers from slipping and scratching the display devices in the array substrate, thereby affecting the display effect. As shown in Figure 3a, the width of the support structure 107 is greater at locations corresponding to spacers in the color filter substrate and is smaller at other locations.

[0102] In some embodiments, a recess 107a is formed at a portion of the support structure 107, the position of the recess 107a corresponds to the position of the supported spacer, and the orthographic projection of the recess 107a on the substrate 101 overlaps with the orthographic projection of the third via V3 on the substrate 101.

[0103] As shown in Figure 3b, in the cross-section of the array substrate along line AA', portions of the support structure 107 are formed with recessed portions 107a. These recessed portions 107a can secure the bottom of the spacer, preventing it from falling off the platform and potentially scratching the display device within the array substrate, which could affect the display quality. The top surface of the support structure 107 is not flat. Due to manufacturing processes, its top is typically convex, with an edge slope angle of 30 to 70 degrees. As shown in Figure 3c, in the cross-section of the array substrate along line BB', other portions of the support structure 107 are not used to support spacers and do not need to be formed into recessed portions 107a. Instead, their surfaces can naturally form convex shapes, reducing manufacturing complexity. Furthermore, as shown in Figures 3b and 3c, the slope angles of the edges of the light shielding layer 1043 can be 20 to 45 degrees, and the slope angles of the edges of the first gate electrode 1031 can be 30 to 60 degrees. This ensures that other layers above them can be smoothly positioned, preventing excessively steep angles from puncturing the layers above them and affecting their performance. The slope angle of the edge of the via hole corresponding to the first switching electrode 1050 can be 60 degrees to 80 degrees to ensure that the first switching electrode 1050 is not broken in the via hole and to ensure connection stability.

[0104] In some embodiments, the position where the first source 1048 of the oxide thin film transistor 104 is connected to the oxide semiconductor layer 1041 through the first via hole V1, as shown in Figure 3d, in the cross section of the array substrate CC', no supporting structure 107 is provided at this position, and the second interlayer insulating layer and the first passivation layer can be filled in the first via hole V1.

[0105] In some embodiments, as shown in FIG. 1 , the array substrate further includes: a second passivation layer 108 and a common electrode 109 located between the pixel electrode 106 and the support structure 107 ; the material of the common electrode 109 is transparent metal oxide.

[0106] The second passivation layer 108 can be made of at least one of silicon nitride (SiN) and silicon oxide (SiO2), and can be formed into a single-layer structure made of a single material or a multi-layer structure made of multiple different materials. The second passivation layer 108 can prevent a short circuit between the pixel electrode 106 and the common electrode 109.

[0107] The common electrode 109 may be disposed on the second passivation layer 108 and may be made of a transparent conductive material such as indium tin oxide (ITO) to prevent the common electrode 109 from blocking light and improve the overall light transmittance of the array substrate.

[0108] In some embodiments, as shown in FIG. 1 , the array substrate further includes: a metal layer 110 located on the second passivation layer 108 ; an orthographic projection of the metal layer 110 on the substrate 101 is located between orthographic projections of adjacent pixel electrodes 106 on the substrate 101 .

[0109] The metal layer 110 can be directly embedded in the common electrode 109, so that the metal layer 110 can be directly connected to the common electrode 109, avoiding the use of vias and other methods to increase the contact resistance between the two. At the same time, it can simplify the process steps, save process costs, and reduce the thickness of the array substrate.

[0110] The metal layer 110 can be made of the same metal material as the first gate electrode 1041, or the same metal material as the first source electrode 1048 and the first transfer electrode 1050. It blocks light, preventing crosstalk between adjacent pixel regions in the array substrate, thereby improving the display quality of the array substrate. Furthermore, the metal layer 110 is electrically connected to the common electrode 109, reducing the load on the common electrode 109 and improving the recovery capability of the common signal. The common signal can also be transmitted to the metal layer 110, preventing the metal layer 110 from accumulating static electricity while suspended, thereby minimizing the impact of static electricity on the stability of the array substrate.

[0111] In some embodiments, as shown in Figure 1, the array substrate further has a peripheral area BB arranged on at least one side of the display area AA, and the array substrate further includes: a low-temperature polycrystalline silicon thin film transistor 201 located on the substrate 101 and arranged in the peripheral area BB; the low-temperature polycrystalline silicon thin film transistor 201 includes: a low-temperature polycrystalline silicon layer 2011, a first gate insulating layer 1042, a second gate 2012, a first interlayer insulating layer 1044, a second source 2013 and a second drain 2014 stacked in sequence on the substrate 101; the second source 2013 and the second drain 2014 are both located on a side of the second interlayer insulating layer 1047 away from the substrate 101, and the second source 2013 and the second drain 2014 are respectively connected to the two ends of the low-temperature polycrystalline silicon layer 2011 through vias penetrating the first gate insulating layer 1042, the first interlayer insulating layer 1044, the second gate insulating layer 1045, and the second interlayer insulating layer 1047.

[0112] The first gate insulating layer 1042 can be made of at least one of silicon nitride (SiN) and silicon oxide (SiO2), and can form a single-layer structure made of a single material or a multi-layer structure made of multiple different materials. The first gate insulating layer 1042 can be a stacked structure of silicon nitride (SiN) and silicon oxide (SiO2), with a total thickness of to

[0113] The first interlayer insulating layer 1044 can be made of at least one of silicon nitride (SiN) and silicon oxide (SiO2). It can form a single-layer structure made of a single material or a multi-layer structure made of multiple different materials. Its thickness can be to

[0114] To prevent mutual interference between the low-temperature polysilicon semiconductor layer 2011 of the low-temperature polysilicon thin-film transistor 201 and the oxide semiconductor layer 1041 of the oxide thin-film transistor 104 during the fabrication process, the low-temperature polysilicon semiconductor layer 2011 and the oxide semiconductor layer 1041 are typically located in different layers, with the low-temperature polysilicon semiconductor layer 2011 formed first, followed by the oxide semiconductor layer 1041. That is, the oxide semiconductor layer 1041 may be located on the side of the low-temperature polysilicon semiconductor layer 2011 facing away from the substrate 101. Furthermore, insulating layers, such as a first gate insulating layer 1042, a first interlayer insulating layer 1044, and a second gate insulating layer 1045, are disposed between adjacent conductive layers to prevent short circuits between adjacent conductive layers.

[0115] The low temperature polysilicon semiconductor layer 2011 can be disposed on the buffer layer 101a in the peripheral region BB, and can be made of amorphous silicon material. The thickness of the amorphous silicon material is to Amorphous silicon material is converted into polycrystalline silicon material through processes such as laser annealing, and the polycrystalline silicon material layer is patterned to form a low-temperature polycrystalline silicon semiconductor layer 2011. Specifically, the amorphous silicon material can be made of at least one of silicon (Si), germanium (Ge), and carbon (C), and can form a single-layer structure made of a single material or a multi-layer structure made of multiple different materials. The low-temperature polycrystalline silicon thin-film transistor 201 provides a driving voltage for the array substrate when used for display. The low-temperature polycrystalline silicon semiconductor layer 2011 can improve mobility and achieve the technical effect of narrowing the bezel.

[0116] The array substrate combines the technical effects of high mobility and narrow frame of the warm polysilicon thin film transistor 201 and the display effect of high transmittance of the gold oxide thin film transistor 104, so that when the array substrate is used in a display panel, the display effect can be further improved.

[0117] In some embodiments, as shown in FIG. 1 , the second gate electrode 2012 is disposed in the same layer as the light shielding layer 1043 ; the second source electrode 2013 and the second drain electrode 2014 are both disposed in the same layer as the first source electrode 1048 .

[0118] The second gate 2012 is arranged on the same layer as the light shielding layer 1043; the second source 2013 and the second drain 2014 are both arranged on the same layer as the first source 1048. The various structures arranged on the same layer can be made of the same material and formed using the same preparation process to simplify the process steps and save preparation costs.

[0119] In some embodiments, as shown in Figure 1, the array substrate also includes: a light shielding layer trace 111, a gate layer trace 112, and a second transfer electrode 113 electrically connected to each other; the light shielding layer trace 111 and the light shielding layer 1043 are arranged on the same layer; the gate layer trace 112 and the first gate 1046 are arranged on the same layer; the second transfer electrode 113 and the first source 1048 are arranged on the same layer.

[0120] In actual applications, the signal line is generally arranged in the film layer where the first source 1048 is located, such as the signal line connected to the signal output end of the gate drive circuit. The light shielding layer line 111, the gate layer line 112 and the second transfer electrode 113 that are electrically connected to each other can transmit the signal (such as the scan signal) in the signal line to the first gate 1046 to control the opening and closing of the oxide thin film transistor 104. The light shielding layer line 111 and the light shielding layer 1043 are arranged in the same layer, and the two can be formed by the same material and the same preparation process to simplify the process steps and save preparation costs. Similarly, the gate layer line 112 and the first gate 1046 are arranged in the same layer, and the second transfer electrode 113 and the first source 1048 are arranged in the same layer to simplify the process steps and save preparation costs. In addition, the light shielding layer line 111 can be connected to the light shielding layer 1043, and can transmit the signal to the light shielding layer 1043 to prevent the light shielding layer 1043 from being suspended and accumulating static electricity, thereby avoiding the influence of static electricity on the stability of the array substrate.

[0121] Typically, the light shielding layer 1043 of the oxide thin film transistor 104 in the display area AA of the array substrate completely covers the first gate electrode 1046, effectively shielding the channel of the oxide semiconductor layer 1041 below the first gate electrode 1046 and preventing light from affecting the performance of the oxide thin film transistor 104. However, current array substrates are prone to light leakage, which affects the display performance of the array substrate.

[0122] 4 is a schematic diagram of a first improved structure of a portion of the array substrate shown in FIG. 2 . In the structure shown in FIG. 4 , at least one edge of the orthographic projection of the light shielding layer 1043 on the substrate 101 falls within the orthographic projection of the first gate 1046 on the substrate 101 .

[0123] In practical applications, the originally outward-expanding light shielding layer 1043 can be adjusted to a retracted structure, and the edge of the light shielding layer 1043 can be positioned within the first gate 1046. Specifically, the distance between at least one edge of the orthographic projection of the light shielding layer 1043 on the substrate 101 and the edge of the orthographic projection of the first gate 1046 on the substrate 101 is 0 to 2.0 microns. Figure 4' is a schematic cross-sectional structure diagram of the structure shown in Figure 4 along the D-D' position. As shown in Figure 4', when the light shielding layer 1043 is not retracted, the overlapping distance between the light shielding layer 1043 and the first gate 1046 is l1+l2, which can effectively shield the channel of the oxide semiconductor layer 1041. After the light shielding layer 1043 is retracted, the distance between the edge of the light shielding layer 1043 and the first gate 1043 can be l1, which improves light transmittance while ensuring that the channel performance of the oxide semiconductor layer 1041 is not affected. For example, the distance l1 between the two can be greater than 0.6 microns.

[0124] Figure 5 is a schematic diagram showing the effect of light shielding layer size on light leakage current. As shown in Figure 5, after light shielding layer 1043 is retracted by 1.5 microns, the impact on the device is minimal, with leakage current Ioff remaining on the order of 10E-12. Therefore, the structure shown in Figure 4 can increase light transmittance from the original 40% to 45% while minimizing the impact of light leakage current, thereby improving the display quality of the array substrate. Taking the structure shown in Figure 4 as an example, the retracted edge of light shielding layer 1043 can be located away from the edge of the opening area.

[0125] Generally, the light shielding layer 1043 of the oxide thin film transistor 104 in the display area AA of the array substrate is designed to be horizontally penetrated. The light shielding layer 1043 in the oxide thin film transistor 104 in the same row is an integrated structure, and light shielding will be formed in positions where light shielding is not necessary, affecting light transmittance.

[0126] FIG6 is a schematic diagram of a second improved structure of a portion of the array substrate shown in FIG2 . In the array substrate shown in FIG6 , the light shielding layers 1043 in adjacent oxide thin film transistors 104 in the same row of oxide thin film transistors 104 are disconnected. The edge of the orthographic projection of the oxide semiconductor layer 1041 on the substrate 101 near the disconnected portion falls within the orthographic projection of the light shielding layer 1043 on the substrate 101.

[0127] The light shielding layer 1043 in adjacent oxide thin-film transistors 104 is disconnected, preventing the light shielding layer 1043 from unnecessarily blocking areas outside the channel of the oxide semiconductor layer 1041. While ensuring a good light shielding effect, this can further increase light transmittance, thereby enhancing the display quality of the array substrate. Specifically, the distance between the edge of the orthographic projection of the light shielding layer 1043 on the substrate 101 near the disconnected position and the edge of the orthographic projection of the oxide semiconductor layer 1041 on the substrate 101 near the disconnected position is 0.3 microns to 1.0 microns.

[0128] FIG7 is a schematic diagram of a third improved structure of a part of the array substrate shown in FIG2 . In the array substrate shown in FIG7 , the orthographic projection of the light shielding layer 1043 on the substrate 101 covers the orthographic projection of the first via hole V1 on the substrate 101 .

[0129] In actual applications, light depolarization occurs at the location of the first via hole V1, resulting in light leakage at the location of the first via hole V1, thereby reducing the contrast of the array substrate. In the array substrate provided by the embodiment of the present disclosure, the light shielding layer 1043 can block the location of the first via hole V1 to prevent light from escaping from the location of the first via hole V1, thereby preventing light leakage and improving the display effect of the array substrate. It is understood that via holes in other locations in the array substrate can also be shielded using similar methods described above, and this will not be further described here.

[0130] Specifically, the distance between the edge of the orthographic projection of the light shielding layer 1043 on the substrate 101 and the edge of the orthographic projection of the first via hole V1 on the substrate 101 is 0.5 micrometers to 1.5 micrometers, so as to completely shield the first via hole V1 and prevent light leakage.

[0131] FIG8 is a schematic diagram of a fourth improved structure of a portion of the array substrate shown in FIG2 . In the array substrate shown in FIG8 , the orthographic projection of the light shielding layer 1043 on the substrate 101 covers the orthographic projection of the data line 103 on the substrate 101 .

[0132] In an ultra-high-resolution array substrate, the line width of the data line 103 is often smaller than the width of its corresponding via hole, and the data line 103 at the via hole position needs to be compensated for its width. However, after the width compensation, the data line 103 cannot affect the vertical compensation design due to the diffraction problem of the exposure machine. The compensation position of the data line 103 in the actual array substrate is arc-shaped, which aggravates the depolarization of light and is more prone to light leakage, thereby resulting in a decrease in the contrast of the array substrate.

[0133] In the array substrate provided by the embodiment of the present disclosure, the light shielding layer 1043 can shield the data lines 103, preventing light from leaking out of the data lines 103, thereby preventing light leakage and improving the display effect of the array substrate. Specifically, the distance between the edge of the orthographic projection of the light shielding layer 1043 on the substrate 101 and the orthographic projection of the data lines 103 on the substrate 101 is 0.3 microns to 2.0 microns.

[0134] It is understandable that the array substrate can be improved by combining the structures shown in FIG. 4 , FIG. 6 , FIG. 7 , and FIG. 8 . The implementation principle is similar to that described above and will not be described in detail here.

[0135] 9a to 9k are schematic diagrams of intermediate structures corresponding to the various steps in the method for preparing an array substrate according to an embodiment of the present disclosure. The process flow for preparing the array substrate according to the embodiment of the present disclosure will be further described in detail below in conjunction with the intermediate structure diagrams of the various steps.

[0136] As shown in FIG9a, a buffer layer 101a is formed together with amorphous silicon (a-Si) on a substrate 101. After laser irradiation, annealing and other crystallization processes, the amorphous silicon (a-Si) is transformed into polycrystalline silicon (P-Si). Then, a masking process and a dry etching process are performed to form the channel pattern of the low-temperature polycrystalline silicon semiconductor layer 2011 of the low-temperature polycrystalline silicon thin film transistor 201 in the peripheral area BB. The buffer layer 101a can be a stacked structure of silicon nitride (SiN) and silicon oxide (SiO2), wherein the thickness of the silicon nitride (SiN) is to The thickness of silicon oxide (SiO2) is to The thickness of the low-temperature polysilicon semiconductor layer 2011 is to

[0137] As shown in FIG9b, after the channel of the low-temperature polysilicon semiconductor layer 2011 is formed, the first gate insulating layer 1042 is then formed. The first gate insulating layer 1042 does not require a mask plate. Then the first conductive layer is formed. After the mask process, the second gate 2012 is formed by wet etching. At the same time, the light shielding layer wiring 111 and the light shielding layer 1043 can also be formed. The first gate insulating layer 1042 can be a stacked structure of silicon nitride (SiN) and silicon oxide (SiO2), with a total thickness of about 100%. to The total thickness of the second gate 2012 can be to The light shielding layer 1043 and the second gate 2012 may be distributed in a strip shape, and the width may be 2 micrometers to 10 micrometers.

[0138] As shown in FIG9c, after the first conductive layer is formed, the first interlayer insulating layer 1044 is formed. The first interlayer insulating layer 1044 does not require a mask plate. Then the oxide semiconductor layer 1041 is formed. After a mask process and a dry etching process, the channel pattern of the oxide semiconductor layer 1041 is formed. The first interlayer insulating layer 1044 can be made of at least one material selected from silicon nitride (SiN) and silicon oxide (SiO2). It can form a single-layer structure made of a single material or a multi-layer structure made of multiple different materials. Its thickness can be to

[0139] As shown in Figure 9d, after the channel of the oxide semiconductor layer 1041 is formed, the second gate insulating layer 1045 is then formed. The second gate insulating layer 1045 does not require a mask plate. Then the second conductive layer is formed, and after a mask process, a wet etching process is used to form the first gate 1046. Since the slope angle of wet etching is small, it can ensure good coverage of the upper insulating layer, so wet etching is used. At the same time, the gate layer wiring 112 can also be formed. The second gate insulating layer 1045 can be made of at least one material selected from silicon nitride (SiN) and silicon oxide (SiO2). It can form a single-layer structure made of a single material, or it can form a multi-layer structure made of multiple different materials. Its thickness can be to The total thickness of the first gate 1046 may be to The total thickness of the gate layer trace 112 can be to

[0140] As shown in FIG9e, after the second conductive layer is formed, the second interlayer insulating layer 1047 is formed and coated with photoresist; then a mask process is performed to form a pattern of film openings in the peripheral area BB, and then a first etching is performed to form the above-mentioned vias. The second interlayer insulating layer 1047 can be made of at least one material selected from silicon nitride (SiN) and silicon oxide (SiO2). It can form a single-layer structure made of a single material or a multi-layer structure made of multiple different materials. Its thickness can be to

[0141] As shown in FIG9f, after each via hole is formed, the third conductive layer is then formed by a mask process and a dry etching process to form the second source 2013, the second drain 2014, the first source 1048, and the second transfer electrode 113, and each electrode is electrically connected to other conductive film layers through the corresponding via hole. The second source 2013, the second drain 2014 and the first source 1048 can be arranged on the second interlayer insulating layer 1047 in the same layer structure, which can form a single layer structure made of a single material or a multi-layer structure made of multiple different materials, and its thickness can be 10 ... to

[0142] As shown in FIG9g , after the third conductive layer is formed, the first passivation layer 1049 is formed, and a mask process and a dry etching process are performed to form a via hole corresponding to the first transfer electrode 1050 .

[0143] As shown in Figure 9h, after the via holes corresponding to the first transfer electrodes 1050 are formed, the fourth conductive layer is formed, and after a masking process, wet etching is performed to form the first transfer electrodes 1050. The first transfer electrodes 1050 are electrically connected to the oxide semiconductor layer 1041 through the via holes. The first transfer electrodes 1050 can be made of a transparent conductive material such as indium tin oxide (ITO) to prevent the first transfer electrodes 1050 from blocking light and improve the overall light transmittance of the array substrate.

[0144] As shown in FIG9i , after the fourth conductive layer is formed, the planarization layer 105 is formed, and a mask process is performed to form a via hole. Then, the pixel electrode 106 is formed, and a mask process and a wet etching process are performed to form the pixel electrode 106.

[0145] As shown in Figure 9j, after the pixel electrode 106 is formed, the second passivation layer 108 is formed, and then the mask process and dry etching process are used to form the via hole in the peripheral area BB. Since the display area AA is a PCI structure, the display area AA does not need to be opened. Then the common electrode 109 is formed, and then the mask process and wet etching process are used to form the common electrode 109.

[0146] As shown in Figure 9k, to balance cross-talk and light leakage, a metal layer 110 can be formed under the common electrode 109 film layer. This can not only improve cross-talk, but also reduce the load on the common electrode 109 and improve the recovery capability of the common signal. A support structure 107 is formed on the common electrode 109 to fill the formed groove. This eliminates the need for planarization of the location with filling material and provides spacers to prevent them from sliding and damaging other display devices.

[0147] In a second aspect, embodiments of the present disclosure provide a display device comprising an array substrate as provided in any of the aforementioned embodiments. Specifically, the display device may be a virtual reality display device or an augmented reality display device, having a resolution greater than or equal to 2000 PPI to achieve high-resolution display and meet user demands for high-resolution display images. It should be noted that the implementation principles and beneficial effects of the display device provided in embodiments of the present disclosure are the same as those of the array substrate provided in any of the aforementioned embodiments, and will not be further elaborated upon herein.

[0148] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. An array substrate having a display area, wherein: The array substrate comprises: a substrate, a first signal line and a second signal line located on one side of the substrate; the first signal line and the second signal line intersect to define a pixel area; the array substrate further comprises: a first thin film transistor located on the substrate and arranged in the pixel area; The first thin film transistor includes: a first semiconductor layer; the first semiconductor layer includes: a first connection portion, a second connection portion and a third connection portion connected to each other; The extension direction of the first connection portion and the third connection portion is the same as the extension direction of the second signal line; the orthographic projection of the first connection portion on the substrate overlaps with the orthographic projection of the second signal line on the substrate; the orthographic projection of the third connection portion on the substrate falls between adjacent orthographic projections of the second signal line on the substrate, and overlaps with the orthographic projection of the first signal line on the substrate; An extension direction of the second connection portion and an extension direction of the first connection portion form a first angle; the first angle is in a range of 90 degrees to 180 degrees.

2. The array substrate according to claim 1, wherein: The first thin film transistor further includes: a light shielding layer, a second gate insulating layer, a first gate electrode, a second interlayer insulating layer and a first source electrode; The light-shielding layer is located on the substrate; the second gate insulating layer covers the first semiconductor layer; the first gate is a part of the first signal line and is located on a side of the second gate insulating layer away from the substrate; the second interlayer insulating layer covers the first gate; the first source is a part of the second signal line and is located on a side of the second interlayer insulating layer away from the substrate; the first source is connected to the first connecting portion through a first via hole that penetrates the second gate insulating layer and the second interlayer insulating layer.

3. The array substrate according to claim 2, wherein: Along the extending direction of the first signal line, a width of at least one side of the first connecting portion is 0 to 3 micrometers greater than a width of the first via hole.

4. The array substrate according to claim 2, wherein: The orthographic projection of the first via hole on the substrate falls outside the orthographic projection of the light shielding layer on the substrate.

5. The array substrate according to claim 4, wherein: A distance between an edge of an orthographic projection of the first via hole on the substrate close to the light shielding layer and an edge of an orthographic projection of the light shielding layer on the substrate close to the first via hole is 0.5 micrometers to 10 micrometers.

6. The array substrate according to claim 2, wherein: The array substrate further comprises: a first passivation layer located on a side of the first source electrode away from the substrate, and a first transfer electrode located on a side of the first passivation layer away from the substrate; The first transfer electrode is connected to the third connection portion through a second via hole penetrating the first passivation layer, the second interlayer insulating layer, and the second gate insulating layer.

7. The array substrate according to claim 6, wherein: The array substrate further comprises: a planarization layer located on the first transfer electrode, and a pixel electrode located on the planarization layer; The pixel electrode is connected to the first transfer electrode through a third via hole penetrating the planarization layer.

8. The array substrate according to claim 7, wherein: Along the extension direction of the second signal line, the width of the first via is 1.9 microns to 2.5 microns; along the extension direction of the first signal line, the width of the second via is 1.9 microns to 2.5 microns; along the extension direction of the first signal line, the width of the third via is 2.5 microns to 3.0 microns.

9. The array substrate according to claim 7, wherein: The orthographic projection of the third via hole on the substrate falls within the orthographic projection of the light shielding layer on the substrate.

10. The array substrate according to claim 9, wherein: Along the extending direction of the first signal line, a distance between an edge of an orthographic projection of the third via hole on the substrate and an edge of an orthographic projection of the light shielding layer on the substrate is 1.0 to 1.5 micrometers.

11. The array substrate according to claim 7, wherein: The array substrate further comprises: a supporting structure located on the pixel electrode and arranged at the position of the third via hole; An extending direction of the supporting structure is the same as an extending direction of the first signal line.

12. The array substrate according to claim 11, wherein: The orthographic projection of the support structure on the substrate covers the orthographic projection of the third via hole on the substrate.

13. The array substrate according to claim 11, wherein: A recessed portion is formed at a portion of the support structure, the position of the recessed portion corresponds to the position of the supported spacer, and the orthographic projection of the recessed portion on the substrate overlaps with the orthographic projection of the third via hole on the substrate.

14. The array substrate according to claim 11, wherein: The slope angle of the support structure is 30 degrees to 70 degrees.

15. The array substrate according to claim 11, wherein: a second passivation layer and a common electrode located between the pixel electrode and the support structure; The material of the common electrode is transparent metal.

16. The array substrate according to claim 15, wherein: The array substrate further comprises: a metal layer located on the second passivation layer; The orthographic projection of the metal layer on the substrate is located between the orthographic projections of adjacent pixel electrodes on the substrate.

17. The array substrate according to claim 2, wherein: The array substrate also has a peripheral area arranged on at least one side of the display area, and the array substrate further comprises: a second thin film transistor located on the substrate and arranged in the peripheral area; The second thin film transistor includes: a second semiconductor layer, a first gate insulating layer, a second gate, a first interlayer insulating layer, a second source electrode and a second drain electrode; The second source and the second drain are both located on a side of the second interlayer insulating layer away from the substrate, and the second source and the second drain are respectively connected to the two ends of the second semiconductor layer through vias penetrating the first gate insulating layer, the first interlayer insulating layer, the second gate insulating layer, and the second interlayer insulating layer.

18. The array substrate according to claim 17, wherein: The second gate is arranged on the same layer as the light shielding layer; The second source and the second drain are both arranged in the same layer as the first source.

19. The array substrate according to claim 18, wherein: The array substrate also includes: a light shielding layer wiring, a gate layer wiring and a second transfer electrode electrically connected to each other; the light shielding layer wiring is arranged on the same layer as the light shielding layer; the gate layer wiring is arranged on the same layer as the first gate; and the second transfer electrode is arranged on the same layer as the first source.

20. The array substrate according to claim 2, wherein: At least one edge of an orthographic projection of the light shielding layer on the substrate falls within an orthographic projection of the first gate on the substrate.

21. The array substrate according to claim 20, wherein: A distance between at least one edge of an orthographic projection of the light shielding layer on the substrate and an edge of an orthographic projection of the first gate on the substrate is 0 micrometers to 2.0 micrometers.

22. The array substrate according to claim 2, wherein: In the same row of the first thin film transistors, the light shielding layers in adjacent first thin film transistors are disconnected.

23. The array substrate according to claim 22, wherein: An edge of the orthographic projection of the first semiconductor layer on the substrate close to the disconnection position falls within the orthographic projection of the light shielding layer on the substrate.

24. The array substrate according to claim 23, wherein: A distance between an edge of an orthographic projection of the light shielding layer on the substrate close to a disconnection position and an edge of an orthographic projection of the first semiconductor layer on the substrate close to a disconnection position is 0.3 micrometers to 1.0 micrometers.

25. The array substrate according to claim 2, wherein: The orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the first via hole on the substrate.

26. The array substrate according to claim 25, wherein: A distance between an edge of an orthographic projection of the light shielding layer on the substrate and an edge of an orthographic projection of the first via hole on the substrate is 0.5 micrometers to 1.5 micrometers.

27. The array substrate according to claim 2, wherein: The orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the second signal line on the substrate.

28. The array substrate according to claim 27, wherein: A distance between an edge of an orthographic projection of the light shielding layer on the substrate and an orthographic projection of the second signal line on the substrate is 0.3 micrometers to 2.0 micrometers.

29. A display device, wherein: The display device comprises the array substrate according to any one of claims 1 to 28.

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