Pixel structure, display panel and display device

Abstract

The invention provides a pixel structure, a display panel and a display device. The pixel structure comprises a plurality of pixel circuits (R11, G12, B13, G14, B21, G22, R23 and G24) which are arranged in rows and columns, wherein the plurality of pixel circuits (R11, G12, B13, G14, B21, G22, R23 and G24) comprise a first type of pixel circuits and a second type of pixel circuits; the data lines are electrically connected with the pixel circuits (R11, G12, B13, G14, B21, G22, R23 and G24) and are used for providing data voltages for the pixel circuits (R11, G12, B13, G14, B21, G22, R23 and G24); the pixel circuits which are electrically connected with at least one data line and are positioned in two adjacent rows are respectively a first type pixel circuit and a second type pixel circuit; and a plurality of light emitting elements (E11, E12, E13, E14, E21, E22, E23, E24), the plurality of light emitting elements (E11, E12, E13, E14, E21, E22, E23, E24) comprising a first light emitting element electrically connected to the first type of pixel circuit and a second light emitting element electrically connected to the second type of pixel circuit; the display brightness of the first light-emitting element is increased along with the increase of the data voltage accessed by the first type pixel circuit; and the display brightness of the second light-emitting element is reduced along with the increase of the data voltage accessed by the second type pixel circuit. The occurrence probability and the severity of block-shaped crosstalk can be reduced.

Description

Pixel structure, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel structure, a display panel, and a display device. Background Art

[0002] As the display PPI (Pixels Per Inch, pixel density) increases and the row time shortens, the potential of each node in the pixel circuit is increasingly affected by the data voltage.

[0003] In the related art, as the resolution requirements for AMOLED (active matrix organic light-emitting diode) display panels in the market gradually increase, the requirements for the refresh rate of AMOLED are also increasing. This reduces the line time (the line time is the time for scanning each row of pixel circuits), and the data writing time and threshold voltage compensation time of the pixel circuit are also reduced.

[0004] The related AMOLED pixel circuit that separates data voltage writing and threshold voltage compensation is prone to block crosstalk.

[0005] Summary of the Invention

[0006] In one aspect, an embodiment of the present disclosure provides a pixel structure, including:

[0007] a plurality of pixel circuits arranged in rows and columns, the plurality of pixel circuits including a first type pixel circuit and a second type pixel circuit;

[0008] A data line electrically connected to the pixel circuit, for providing a data voltage to the pixel circuit; pixel circuits located in two adjacent rows electrically connected to at least one of the data lines are respectively a first type pixel circuit and a second type pixel circuit; and

[0009] a plurality of light-emitting elements, the plurality of light-emitting elements including a first light-emitting element electrically connected to the first type pixel circuit and a second light-emitting element electrically connected to the second type pixel circuit;

[0010] The display brightness of the first light-emitting element increases as the data voltage connected to the first type pixel circuit increases; the display brightness of the second light-emitting element decreases as the data voltage connected to the second type pixel circuit increases.

[0011] Optionally, the plurality of pixel circuits located in the same row are all first-type pixel circuits or second-type pixel circuits.

[0012] Optionally, among a plurality of pixel circuits located in the same row, adjacent pixel circuits are respectively first-type pixel circuits and second-type pixel circuits.

[0013] Optionally, in a plurality of pixel circuits located in the same row,

[0014] The first pixel circuits are all first-type pixel circuits or second-type pixel circuits; and / or the second pixel circuits are all first-type pixel circuits or second-type pixel circuits;

[0015] The light-emitting element electrically connected to the first pixel circuit is a first-color light-emitting element, and the light-emitting element electrically connected to the second pixel circuit is a second-color light-emitting element.

[0016] Optionally, among the plurality of pixel circuits located in the same row, some of the third pixel circuits are first-type pixel circuits, and another part of the third pixel circuits are second-type pixel circuits;

[0017] The light-emitting element electrically connected to the third pixel circuit is a light-emitting element of a third color.

[0018] Optionally, the color of the first color light emitting element, the color of the second color light emitting element, and the color of the third color light emitting element are different from each other.

[0019] Optionally, the first pixel circuits are all first-type pixel circuits or second-type pixel circuits, and / or the second pixel circuits are all first-type pixel circuits or second-type pixel circuits.

[0020] Optionally, pixel circuits electrically connected to light-emitting elements having the same color are all first-type pixel circuits or second-type pixel circuits.

[0021] Optionally, in adjacent rows of pixel circuits, pixel circuits electrically connected to the same data line are located in the same column.

[0022] Optionally, in adjacent rows of pixel circuits, pixel circuits electrically connected to the same data line are located in adjacent columns.

[0023] Optionally, in adjacent rows of pixel circuits, the first pixel circuit and the second pixel circuit are electrically connected to the same data line, and the third pixel circuit and the second pixel circuit are electrically connected to another data line.

[0024] Optionally, in adjacent rows of pixel circuits, the first pixel circuits located in the same column are electrically connected to different column data lines, the second pixel circuits located in the same column are electrically connected to different column data lines, and the third pixel circuits located in the same column are electrically connected to the same column data line.

[0025] Optionally, the pixel structure includes a plurality of pixel units, each pixel unit includes a plurality of pixel circuits sequentially arranged along a row direction; the pixel unit is electrically connected to a plurality of column data lines; the plurality of pixel circuits include a first pixel circuit, a second pixel circuit, and a third pixel circuit;

[0026] The pixel circuits located in the same row are electrically connected to data lines in different columns respectively.

[0027] Optionally, the first type pixel circuit includes a first driving circuit, a first data writing circuit, a first energy storage circuit and a first reference voltage writing circuit;

[0028] The first driving circuit is electrically connected to the first node and the first light-emitting element respectively, and is configured to generate a driving current for driving the first light-emitting element under the control of the potential of the first node;

[0029] The first data writing circuit is electrically connected to the scanning end, the data line and the first node respectively, and is used to control the data line to provide a data voltage to the first node under the control of the scanning signal provided by the scanning end during the data writing phase;

[0030] The first reference voltage writing circuit is electrically connected to the initial control terminal, the first reference voltage terminal, and the first node, respectively, and is configured to write the first reference voltage provided by the first reference voltage terminal into the first node under the control of an initial control signal provided by the initial control terminal during an initialization phase provided before the data writing phase;

[0031] The first energy storage circuit is electrically connected to the first node and is used to store electrical energy.

[0032] Optionally, the second type pixel circuit includes a second driving circuit, a second data writing circuit, a second energy storage circuit and a second reference voltage writing circuit;

[0033] The second driving circuit is electrically connected to the second node and the second light-emitting element respectively, and is configured to generate a driving current for driving the second light-emitting element under the control of the potential of the second node;

[0034] The second energy storage circuit is electrically connected to the second node and the third node respectively, and is used to store electrical energy;

[0035] The second data writing circuit is electrically connected to the scan terminal, the data line and the third node respectively, and is used to write the data voltage provided by the data line into the third node under the control of the scan signal provided by the scan terminal during the data writing phase;

[0036] The second reference voltage writing circuit is electrically connected to the light-emitting control terminal, the second reference voltage terminal and the third node, respectively, and is used to write the second reference voltage provided by the second reference voltage terminal into the third node under the control of the light-emitting control signal provided by the light-emitting control terminal during a light-emitting stage set after the data writing stage.

[0037] In a second aspect, an embodiment of the present disclosure provides a display panel including the above-mentioned pixel structure.

[0038] In a third aspect, the present disclosure provides a display device comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is a structural diagram of a pixel structure according to at least one embodiment of the present disclosure;

[0040] FIG2 is a structural diagram of a pixel structure according to at least one embodiment of the present disclosure;

[0041] FIG3 is a structural diagram of a pixel structure according to at least one embodiment of the present disclosure;

[0042] FIG4 is a structural diagram of a pixel structure according to at least one embodiment of the present disclosure;

[0043] FIG5 is a structural diagram of a pixel structure according to at least one embodiment of the present disclosure;

[0044] FIG6 is a structural diagram of a pixel structure according to at least one embodiment of the present disclosure;

[0045] FIG7 is a structural diagram of a pixel structure according to at least one embodiment of the present disclosure;

[0046] FIG8 is a structural diagram of at least one embodiment of a first type pixel circuit;

[0047] FIG9 is a structural diagram of at least one embodiment of a first type pixel circuit;

[0048] FIG10 is a circuit diagram of at least one embodiment of a first type pixel circuit;

[0049] FIG11 is an operation timing diagram of at least one embodiment of the first type pixel circuit shown in FIG10 ;

[0050] FIG12 is a structural diagram of at least one embodiment of a second type pixel circuit;

[0051] FIG13 is a structural diagram of at least one embodiment of a second type pixel circuit;

[0052] FIG14 is a circuit diagram of at least one embodiment of a second type pixel circuit;

[0053] FIG15 is an operation timing diagram of at least one embodiment of the first type pixel circuit shown in FIG14 ;

[0054] FIG. 16 is a waveform diagram of a data voltage Vdt and a disturbed signal Vr in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0056] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0057] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0058] The pixel structure described in the embodiment of the present disclosure includes:

[0059] a plurality of pixel circuits arranged in rows and columns, the plurality of pixel circuits including a first type pixel circuit and a second type pixel circuit;

[0060] A data line electrically connected to the pixel circuit, for providing a data voltage to the pixel circuit; pixel circuits located in two adjacent rows electrically connected to at least one of the data lines are respectively a first type pixel circuit and a second type pixel circuit; and

[0061] a plurality of light-emitting elements, the plurality of light-emitting elements including a first light-emitting element electrically connected to the first type pixel circuit and a second light-emitting element electrically connected to the second type pixel circuit;

[0062] The display brightness of the first light-emitting element increases as the data voltage connected to the first type pixel circuit increases; and the display brightness of the second light-emitting element decreases as the data voltage connected to the second type pixel circuit increases.

[0063] In the related art, as the resolution requirements for AMOLED (active matrix organic light-emitting diode) display panels in the market gradually increase, the requirements for the refresh rate of AMOLED are also increasing. This reduces the row time (the row time is the time to scan each row of pixel circuits), and the data writing time and threshold voltage compensation time of the pixel circuit are reduced at the same time. In order to meet the requirements, the related art proposes an AMOELD pixel circuit with separated data voltage writing and threshold voltage compensation. Under normal circumstances, the capacitor area of ​​the AMOELD pixel circuit with separated data voltage writing and threshold voltage compensation is large and easily affected by the voltage jump of various surrounding signals. At the same time, due to the characteristics of the pixel circuit, the time of the threshold voltage compensation stage is greater than the time of one row. During the threshold voltage compensation stage, the gate state of the driving transistor in the driving circuit is close to a floating state. The gate voltage of the driving transistor is affected by the data voltage of multiple rows, which is easy to form block crosstalk.

[0064] Based on this, in the pixel structure described in the embodiment of the present disclosure, at least some of the adjacent rows of pixel circuits electrically connected to the data lines are respectively the first type of pixel circuit and the second type of pixel circuit, so that when the pixel structure displays a pure color picture, when multiple rows of gate lines are scanned sequentially, the data voltage on the data line is a high and low voltage that continuously alternates. Through such a data voltage conversion rule, the signals in the display area are affected by the data voltage and change rapidly, and the directions of changes of the signals in the display area affected by the data voltage are no longer accumulated, and the amplitude of the change becomes smaller, thereby reducing the probability and severity of Block Crosstalk.

[0065] In a specific implementation, for a pixel circuit with separate threshold voltage compensation and data voltage writing, by controlling the change trend of the data voltage from L0 to L255, depending on the structural design of the pixel circuit, the pixel brightness can be increased or decreased as the data voltage increases. Where L0 is grayscale 0 and L255 is grayscale 255.

[0066] In actual operation, when the first type pixel circuit is working, when the data voltage received by the first type pixel circuit increases, the display brightness of the first light emitting element electrically connected to the first type pixel circuit increases;

[0067] When the second type pixel circuit is in operation, when the data voltage received by the second type pixel circuit increases, the display brightness of the second light emitting element electrically connected to the second type pixel circuit decreases.

[0068] In at least one embodiment of the present disclosure, the structure of the first type pixel circuit is different from the structure of the second type pixel circuit. In the first type pixel circuit, a reference voltage writing operation is performed before the data voltage is written, and in the second type pixel circuit, a reference voltage writing operation is performed after the data voltage is written.

[0069] In a specific implementation, the first-type pixel circuit may be a pixel circuit corresponding to a normally black display mode, and the second-type pixel circuit may be a pixel circuit corresponding to a normally white display mode.

[0070] In at least one embodiment of the present disclosure, the pixel structure may include a plurality of pixel units, each pixel unit may include a plurality of pixel circuits, and light emitted by the plurality of pixel circuits included in the pixel unit may be mixed into white light.

[0071] Optionally, the colors of the light-emitting elements electrically connected to the multiple pixel circuits included in the pixel unit may be different from each other, or the colors of the light-emitting elements electrically connected to at least two pixel circuits in the multiple pixel units included in the pixel structure may be different from each other.

[0072] For example, the pixel unit includes a pixel circuit electrically connected to the first pixel circuit, the second pixel circuit and the third pixel circuit; or,

[0073] The pixel unit may include a first pixel circuit, two second pixel circuits and a third pixel circuit; or,

[0074] The pixel unit may include a first pixel circuit, a second pixel circuit, a third pixel circuit and a fourth pixel circuit;

[0075] But it is not limited to this.

[0076] In actual operation, the structure of the pixel unit may also be other structures.

[0077] Optionally, the first pixel circuit may be a pixel circuit electrically connected to a first color light-emitting element, the second pixel circuit may be a pixel circuit electrically connected to a second color light-emitting element, the third pixel circuit may be a pixel circuit electrically connected to a third color light-emitting element, and the fourth pixel circuit may be a pixel circuit electrically connected to a fourth color light-emitting element; for example, the first color light-emitting element may be a red light-emitting element, the second color light-emitting element may be a green light-emitting element, the third color light-emitting element may be a blue light-emitting element, and the fourth color light-emitting element may be a white light-emitting element.

[0078] In at least one embodiment of the present disclosure, pixel circuits in the same row may all be first-type pixel circuits or second-type pixel circuits, so that the driving signals used by the pixel circuits in each row are consistent and the layout difficulty is relatively low.

[0079] As shown in FIG1 , under a QHDR (quad-pixel high dynamic range imaging) pixel arrangement condition, among a plurality of pixel circuits located in the same row, the pixel circuits located in the Nth row are all first-type pixel circuits, and the pixel circuits located in the N+1th row are all second-type pixel circuits; N is a positive integer;

[0080] In FIG1 , R11 is the first pixel circuit at the Nth row and the Mth column, G12 is the second pixel circuit at the Nth row and the M+1th column, B13 is the third pixel circuit at the Nth row and the M+2th column, and G14 is the second pixel circuit at the Nth row and the M+3th column; M is a positive integer.

[0081] The third pixel circuit labeled B21 is in the N+1th row and Mth column, the second pixel circuit labeled G22 is in the N+1th row and M+1th column, the first pixel circuit labeled R23 is in the N+1th row and M+2th column, and the second pixel circuit labeled G24 is in the N+1th row and M+3th column.

[0082] R11 and B21 are both electrically connected to the Mth column data line DM, G12 and G22 are both electrically connected to the M+1th column data line DM+1, B13 and R23 are both electrically connected to the M+2th column data line DM+2, and G14 and G24 are both electrically connected to the M+3th column data line DM+3.

[0083] In FIG1 , the red light emitting element labeled E11 is in the Nth row and Mth column, the green light emitting element labeled E12 is in the Nth row and M+1th column, the blue light emitting element labeled E13 is in the Nth row and M+2th column, and the green light emitting element labeled E14 is in the Nth row and M+3th column.

[0084] The blue light-emitting element labeled E21 is in the N+1th row and Mth column, the green light-emitting element labeled E22 is in the N+1th row and M+1th column, the red light-emitting element labeled E23 is in the N+1th row and M+2th column, and the green light-emitting element labeled E24 is in the N+1th row and M+3th column.

[0085] R11 is electrically connected to E11, G12 is electrically connected to E12, B13 is electrically connected to E13, G14 is electrically connected to E14, B21 is electrically connected to E21, G22 is electrically connected to E22, R23 is electrically connected to E23, and G24 is electrically connected to E24.

[0086] In at least one embodiment of the pixel structure shown in FIG. 1 , R11 , G12 , B13 , and G14 are all first-type pixel circuits, and B21 , G22 , R23 , and G24 are all second-type pixel circuits.

[0087] As shown in Figure 1, the pixel circuits located in the Nth row are all first-type pixel circuits, the pixel circuits located in the N+1th row are all second-type pixel circuits, the two rows of pixel circuits electrically connected to the M-th column data line DM are respectively the first-type pixel circuit and the second-type pixel circuit, the two rows of pixel circuits electrically connected to the M+1-th column data line DM+1 are respectively the first-type pixel circuit and the second-type pixel circuit, the two rows of pixel circuits electrically connected to the M+2-th column data line DM+2 are respectively the first-type pixel circuit and the second-type pixel circuit, and the two rows of pixel circuits electrically connected to the M+3-th column data line DM+3 are respectively the first-type pixel circuit and the second-type pixel circuit.

[0088] As shown in FIG1 , when scanning the pixel circuit in the Nth row, the data voltage on DM is the normally black red data voltage Dr+, the data voltage on DM+1 is the normally black green data voltage Dg+, the data voltage on DM+2 is the normally black blue data voltage Db+, and the data voltage on DM+3 is the normally black green data voltage Dg+;

[0089] When scanning the pixel circuit in the N+1th row, the voltage of the data on DM is the normally white blue data voltage Db-, the data voltage on DM+1 is the normally white green data voltage Dg-, the data voltage on DM+2 is the normally white red data voltage Dr-, and the data voltage on DM+3 is the normally white green data voltage Dg-.

[0090] In at least one embodiment of the pixel structure shown in FIG1 , when in operation, the pixel circuits in the Nth row can all be electrically connected to the gate line in the Nth row, and the pixel circuits in the N+1th row can all be electrically connected to the gate line in the N+1th row. When scanning multiple rows of pixel circuits in sequence and displaying a pure color image, the data voltages on the data lines in each column are continuously alternating between high and low voltages, so that the driving signal in the pixel circuit changes rapidly under the influence of the data voltage, the direction of change is no longer accumulated, and the amplitude of change becomes smaller, thereby reducing the probability and severity of block crosstalk.

[0091] At least one embodiment of the pixel structure shown in FIG. 1 can achieve an effect similar to row flipping or dot flipping during operation.

[0092] In at least one embodiment of the pixel structure shown in FIG. 1 , R11 , G12 , B13 , and G14 may be replaced by second-type pixel circuits, and B21 , G22 , R23 , and G24 may be replaced by first-type pixel circuits.

[0093] In at least one embodiment of the present disclosure, among a plurality of pixel circuits located in the same row, adjacent pixel circuits are respectively a first-type pixel circuit and a second-type pixel circuit.

[0094] As shown in FIG2 , under the QHDR (quad-pixel high dynamic range imaging) pixel arrangement condition, in a plurality of pixel circuits located in the same row, adjacent pixel circuits are respectively a first type pixel circuit and a second type pixel circuit;

[0095] In FIG2 , R11 is the first pixel circuit in the Nth row and the Mth column, G12 is the second pixel circuit in the Nth row and the M+1th column, B13 is the third pixel circuit in the Nth row and the M+2th column, and G14 is the second pixel circuit in the Nth row and the M+3th column; both N and M are positive integers.

[0096] The third pixel circuit labeled B21 is in the N+1th row and Mth column, the second pixel circuit labeled G22 is in the N+1th row and M+1th column, the first pixel circuit labeled R23 is in the N+1th row and M+2th column, the second pixel circuit labeled G24 is in the N+1th row and M+3th column, and the third pixel circuit labeled B25 is in the N+1th row and M+4th column.

[0097] B21 is electrically connected to the M-th column data line DM, R11 and G22 are both electrically connected to the M+1-th column data line DM+1, G12 and R23 are both electrically connected to the M+2-th column data line DM+2, B13 and G24 are both electrically connected to the M+3-th column data line DM+3, and B25 is electrically connected to the M+4-th column data line DM+4.

[0098] In FIG2 , the red light emitting element labeled E11 is in the Nth row and Mth column, the green light emitting element labeled E12 is in the Nth row and M+1th column, the blue light emitting element labeled E13 is in the Nth row and M+2th column, and the green light emitting element labeled E14 is in the Nth row and M+3th column.

[0099] The blue light-emitting element labeled E21 is in the N+1th row and Mth column, the green light-emitting element labeled E22 is in the N+1th row and M+1th column, the red light-emitting element labeled E23 is in the N+1th row and M+2th column, the green light-emitting element labeled E24 is in the N+1th row and M+3th column, and the blue light-emitting element labeled E25 is in the N+1th row and M+4th column.

[0100] R11 is electrically connected to E11, G12 is electrically connected to E12, B13 is electrically connected to E13, and G14 is electrically connected to E14;

[0101] B21 is electrically connected to E21, G22 is electrically connected to E22, R23 is electrically connected to E23, G24 is electrically connected to E24, and B25 is electrically connected to E25.

[0102] In at least one embodiment of the pixel structure shown in FIG. 2 , R11 , B13 , B21 , R23 , and B25 are all first-type pixel circuits, and G12 , G14 , G22 , and G24 are all second-type pixel circuits.

[0103] In at least one embodiment of the pixel structure shown in FIG. 2 , DM may be electrically connected to the Nth row and M-1th column green pixel circuit, and the Nth row and M-1th column green pixel circuit may be a normally white green pixel circuit.

[0104] As shown in FIG2 , when scanning the pixel circuit in the Nth row, the data voltage on DM is the normally white-green data voltage Dg-, the data voltage on DM+1 is the normally black-red data voltage Dr+, the data voltage on DM+2 is the normally white-green data voltage Dg-, the data voltage on DM+3 is the normally black-blue data voltage Db+, and the data voltage on DM+4 is the normally white-green data voltage Dg-;

[0105] When scanning the pixel circuit in the N+1th row, the voltage of the data on DM is the normally black and blue data voltage Db+, the data voltage on DM+1 is the normally white and green data voltage Dg-, the data voltage on DM+2 is the normally black and red data voltage Dr+, the data voltage on DM+3 is the normally white and green data voltage Dg-, and the data voltage on DM+4 is the normally black and blue data voltage Db+.

[0106] In at least one embodiment of the pixel structure shown in FIG2 , when in operation, the pixel circuits in the Nth row can all be electrically connected to the gate line in the Nth row, and the pixel circuits in the N+1th row can all be electrically connected to the gate line in the N+1th row. When scanning multiple rows of pixel circuits in sequence and displaying a pure color image, the data voltages on the data lines in each column are continuously alternating between high and low voltages, so that the driving signal in the pixel circuit changes rapidly under the influence of the data voltage, the direction of change is no longer accumulated, and the amplitude of change becomes smaller, thereby reducing the probability and severity of block crosstalk.

[0107] In at least one embodiment of the pixel structure shown in Figure 2, the first pixel circuits are all first-type pixel circuits, the second pixel circuits are all first-type pixel circuits, and the third pixel circuits are all second-type pixel circuits, that is, the pixel circuits electrically connected to the light-emitting elements with the same color are all first-type pixel circuits or first-type pixel circuits, so as to achieve the convenience of Gamma adjustment.

[0108] In at least one embodiment of the present disclosure, in order to facilitate gamma adjustment, the layout may be adjusted so that the structures of pixel circuits of the same color are consistent.

[0109] In a specific implementation, since in the QHDR pixel arrangement, the second pixel circuit electrically connected to the green light-emitting element accounts for half, and the first pixel circuit electrically connected to the red light-emitting element and the third pixel circuit electrically connected to the blue light-emitting element account for half in total, the first pixel circuit electrically connected to the red light-emitting element and the third pixel circuit electrically connected to the blue light-emitting element can be set as a first type of pixel circuit, and the second pixel circuit electrically connected to the green light-emitting element can be set as a second type of pixel circuit, or the first pixel circuit electrically connected to the red light-emitting element and the third pixel circuit electrically connected to the blue light-emitting element can be set as the second type of pixel circuit, and the second pixel circuit electrically connected to the green light-emitting element can be set as the first type of pixel circuit.

[0110] As shown in FIG3 , under the Real RGB (red, green, and blue) pixel arrangement condition, among multiple pixel circuits located in the same row, the pixel circuits located in the Nth row are all first-type pixel circuits, and the pixel circuits located in the N+1th row are all second-type pixel circuits; N is a positive integer;

[0111] In FIG3 , the first pixel circuit labeled R11 is the Nth row, Mth column, the second pixel circuit labeled G12 is the Nth row, M+1th column, the third pixel circuit labeled B13 is the Nth row, M+2th column, the first pixel circuit labeled R14 is the Nth row, M+3th column, the second pixel circuit labeled G15 is the Nth row, M+4th column, and the third pixel circuit labeled B16 is the Nth row, M+5th column.

[0112] The first pixel circuit labeled R21 is the N+1th row, Mth column, the second pixel circuit labeled G22 is the N+1th row, M+1th column, the third pixel circuit labeled B23 is the N+1th row, M+2th column, the first pixel circuit labeled R24 is the N+1th row, M+3th column, the second pixel circuit labeled G25 is the N+1th row, M+4th column, and the third pixel circuit labeled B26 is the N+1th row, M+5th column; M is a positive integer;

[0113] R11 and R21 are both electrically connected to the M-th column data line DM, G12 and G22 are both electrically connected to the M+1-th column data line DM+1, B13 and B23 are both electrically connected to the M+2-th column data line DM+2, R14 and R24 are both electrically connected to the M+3-th column data line DM+3, G15 and G25 are both electrically connected to the M+4-th column data line DM+1, and B16 and B26 are both electrically connected to the M+5-th column data line DM+2.

[0114] In FIG3 , the red light-emitting element labeled E31 is in the Nth row and Mth column, the green light-emitting element labeled E32 is in the Nth row and M+1th column, the blue pixel circuit labeled E33 is in the Nth row and M+2th column, the red light-emitting element labeled E34 is in the Nth row and M+3th column, the green light-emitting element labeled E35 is in the Nth row and M+4th column, and the blue pixel circuit labeled E36 is in the Nth row and M+5th column.

[0115] The red light-emitting element labeled E41 is in the N+1th row and Mth column, the green light-emitting element labeled E42 is in the N+1th row and M+1th column, the blue light-emitting element labeled E43 is in the N+1th row and M+2th column, the red light-emitting element labeled E44 is in the N+1th row and M+3th column, the green light-emitting element labeled E45 is in the N+1th row and M+4th column, and the blue light-emitting element labeled B46 is in the N+1th row and M+5th column.

[0116] R11 is electrically connected to E31, G12 is electrically connected to E32, B13 is electrically connected to E33, R14 is electrically connected to E54, G15 is electrically connected to E35, and B15 is electrically connected to E36;

[0117] R21 is electrically connected to E41, G22 is electrically connected to E42, B23 is electrically connected to E43, R24 is electrically connected to E44, G25 is electrically connected to E45, and B25 is electrically connected to E46. In at least one embodiment of the pixel structure shown in FIG3 , R11, G12, B13, R14, G15, and B16 are all first-type pixel circuits, and R21, G22, B23, R24, G25, and B26 are all second-type pixel circuits.

[0118] As shown in Figure 3, the pixel circuits located in the Nth row are all first-type pixel circuits, the pixel circuits located in the N+1th row are all second-type pixel circuits, the two rows of pixel circuits electrically connected to the M-th column data line DM are respectively the first-type pixel circuit and the second-type pixel circuit, the two rows of pixel circuits electrically connected to the M+1-th column data line DM+1 are respectively the first-type pixel circuit and the second-type pixel circuit, the two rows of pixel circuits electrically connected to the M+2-th column data line DM+2 are respectively the first-type pixel circuit and the second-type pixel circuit, the two rows of pixel circuits electrically connected to the M+3-th column data line DM+3 are respectively the first-type pixel circuit and the second-type pixel circuit, the two rows of pixel circuits electrically connected to the M+4-th column data line DM+4 are respectively the first-type pixel circuit and the second-type pixel circuit, and the two rows of pixel circuits electrically connected to the M+5-th column data line DM+5 are respectively the first-type pixel circuit and the second-type pixel circuit.

[0119] As shown in FIG3 , when scanning the pixel circuit in the Nth row, the data voltage on DM is the normally black red data voltage Dr+, the data voltage on DM+1 is the normally black green data voltage Dg+, the data voltage on DM+2 is the normally black blue data voltage Db+, the data voltage on DM+3 is the normally black red data voltage Dr+, the data voltage on DM+4 is the normally black green data voltage Dg+, and the data voltage on DM+5 is the normally black blue data voltage Db+;

[0120] When scanning the pixel circuit in the N+1th row, the data voltage on DM is the normally white red data voltage Dr-, the data voltage on DM+1 is the normally white green data voltage Dg-, the data voltage on DM+2 is the normally white blue data voltage Db-, the data voltage on DM+3 is the normally white red data voltage Dr-, the data voltage on DM+4 is the normally white green data voltage Dg-, and the data voltage on DM+5 is the normally white blue data voltage Db-;

[0121] In at least one embodiment of the pixel structure shown in FIG3 , when in operation, the pixel circuits in the Nth row can all be electrically connected to the gate line in the Nth row, and the pixel circuits in the N+1th row can all be electrically connected to the gate line in the N+1th row. When scanning multiple rows of pixel circuits in sequence and displaying a pure color image, the data voltages on the data lines in each column are continuously alternating between high and low voltages, so that the driving signals in the pixel circuits change rapidly under the influence of the data voltage, the direction of change is no longer accumulated, and the amplitude of change becomes smaller, thereby reducing the probability and severity of block crosstalk.

[0122] In at least one embodiment of the pixel structure shown in FIG3 , the pixel circuits in each row are first-type pixel circuits or second-type pixel circuits, so that the driving signals of the pixel circuits in each row are consistent and the layout difficulty is relatively low.

[0123] In at least one embodiment of the pixel structure shown in FIG3 , the pixel circuits in the Nth row may be replaced with the second type pixel circuits, and the pixel circuits in the N+1th row may be replaced with the first type pixel circuits.

[0124] As shown in FIG4 , under the Real RGB (red, green, and blue) pixel arrangement condition, in a plurality of pixel circuits located in the same row, adjacent pixel circuits are respectively a first type pixel circuit and a second type pixel circuit;

[0125] In FIG4 , the first pixel circuit labeled R11 is the Nth row, Mth column, the second pixel circuit labeled G12 is the Nth row, M+1th column, the third pixel circuit labeled B13 is the Nth row, M+2th column, the first pixel circuit labeled R14 is the Nth row, M+3th column, the second pixel circuit labeled G15 is the Nth row, M+4th column, and the third pixel circuit labeled B16 is the Nth row, M+5th column.

[0126] The first pixel circuit labeled R21 is the N+1th row, Mth column, the second pixel circuit labeled G22 is the N+1th row, M+1th column, the third pixel circuit labeled B23 is the N+1th row, M+2th column, the first pixel circuit labeled R24 is the N+1th row, M+3th column, the second pixel circuit labeled G25 is the N+1th row, M+4th column, and the third pixel circuit labeled B26 is the N+1th row, M+5th column; M is a positive integer;

[0127] R11 and R21 are both electrically connected to the M-th column data line DM, G12 and G22 are both electrically connected to the M+1-th column data line DM+1, B13 and B23 are both electrically connected to the M+2-th column data line DM+2, R14 and R24 are both electrically connected to the M+3-th column data line DM+3, G15 and G25 are both electrically connected to the M+4-th column data line DM+1, and B16 and B26 are both electrically connected to the M+5-th column data line DM+2.

[0128] In FIG4 , the red light-emitting element labeled E31 is in the Nth row and Mth column, the blue light-emitting element labeled E32 is in the Nth row and M+1th column, the blue pixel circuit labeled E33 is in the Nth row and M+2th column, the red light-emitting element labeled E34 is in the Nth row and M+3th column, the green light-emitting element labeled E35 is in the Nth row and M+4th column, and the blue light-emitting element labeled E36 is in the Nth row and M+5th column.

[0129] The red pixel circuit labeled E41 is in the N+1th row, Mth column; the green light-emitting element labeled E42 is in the N+1th row, M+1th column; the blue light-emitting element labeled E43 is in the N+1th row, M+2th column; the red light-emitting element labeled E44 is in the N+1th row, M+3th column; the green light-emitting element labeled E45 is in the N+1th row, M+4th column; and the blue light-emitting element labeled E46 is in the N+1th row, M+5th column.

[0130] As shown in FIG4 , R11 is electrically connected to E31 , G12 is electrically connected to E32 , B13 is electrically connected to E33 , R14 is electrically connected to E34 , R15 is electrically connected to E35 , and R16 is electrically connected to E36 ;

[0131] R21 is electrically connected to E41, G22 is electrically connected to E42, B23 is electrically connected to E43, R24 is electrically connected to E44, R25 is electrically connected to E45, and R26 is electrically connected to E46.

[0132] In at least one embodiment of the pixel structure shown in FIG. 4 , R11 , B13 , G15 , G22 , R24 , and B26 are all first-type pixel circuits, and G12 , R14 , B16 , R21 , B23 , and G25 are all second-type pixel circuits.

[0133] In at least one embodiment shown in Figure 4, the two rows of pixel circuits electrically connected to DM are respectively the first type pixel circuit and the second type pixel circuit, the two rows of pixel circuits electrically connected to DM+1 are respectively the second type pixel circuit and the first type pixel circuit, the two rows of pixel circuits electrically connected to DM+2 are respectively the first type pixel circuit and the second type pixel circuit, the two rows of pixel circuits electrically connected to DM+3 are respectively the second type pixel circuit and the first type pixel circuit, the two rows of pixel circuits electrically connected to DM+4 are respectively the first type pixel circuit and the second type pixel circuit, and the two rows of pixel circuits electrically connected to DM+5 are respectively the second type pixel circuit and the first type pixel circuit.

[0134] As shown in FIG4 , when scanning the pixel circuit in the Nth row, the data voltage on DM is the normally black and red data voltage Dr+, the data voltage on DM+1 is the normally white and green data voltage Dg-, the data voltage on DM+2 is the normally black and blue data voltage Db+, the data voltage on DM+3 is the normally black and red data voltage Dr-, the data voltage on DM+4 is the normally black and green data voltage Dg+, and the data voltage on DM+5 is the normally white and blue data voltage Db-;

[0135] When scanning the pixel circuit in the N+1th row, the data voltage on DM is the normally white-red data voltage Dr-, the data voltage on DM+1 is the normally black-green data voltage Dg+, the data voltage on DM+2 is the normally white-blue data voltage Db-, the data voltage on DM+3 is the normally black-red data voltage Dr+, the data voltage on DM+4 is the normally white-green data voltage Dg-, and the data voltage on DM+5 is the normally black-blue data voltage Db+;

[0136] In at least one embodiment of the pixel structure shown in FIG4 , when in operation, the pixel circuits in the Nth row can all be electrically connected to the gate line in the Nth row, and the pixel circuits in the N+1th row can all be electrically connected to the gate line in the N+1th row. When scanning multiple rows of pixel circuits in sequence and displaying a pure color image, the data voltages on the data lines in each column are constantly alternating between high and low voltages, so that the driving signal in the pixel circuit changes rapidly under the influence of the data voltage, the direction of change is no longer accumulated, and the amplitude of change becomes smaller, thereby reducing the probability and severity of block crosstalk.

[0137] In order to further control the amplitude of the voltage jump during operation of at least one embodiment of the pixel structure shown in FIG4 , adjacent pixel circuits in each row of pixel circuits can be controlled to be first-type pixel circuits and second-type pixel circuits, respectively. Under this arrangement, when the data voltages of the pixel circuits in each row are switched, the data voltages of half of the pixel circuits jump down, and the data voltages of half of the pixel circuits jump up. The jump trends of the two parts of the data voltage offset each other, further reducing the actual disturbance received by the signals inside the pixel circuits.

[0138] Optionally, in a plurality of pixel circuits located in the same row,

[0139] The first pixel circuits are all of the first type pixel circuit or the second type pixel circuit; and / or the second pixel circuits are all of the first type pixel circuit or the second type pixel circuit;

[0140] The light-emitting element electrically connected to the first pixel circuit is a first-color light-emitting element, and the light-emitting element electrically connected to the second pixel circuit is a second-color light-emitting element.

[0141] Optionally, among the plurality of pixel circuits located in the same row, some of the third pixel circuits are first-type pixel circuits, and another part of the third pixel circuits are second-type pixel circuits;

[0142] The light-emitting element electrically connected to the third pixel circuit is a light-emitting element of a third color.

[0143] In at least one embodiment of the present disclosure, the color of the first-color light-emitting element, the color of the second-color light-emitting element, and the color of the third-color light-emitting element are different from each other.

[0144] In at least one embodiment of the present disclosure, the first color light emitting element may be a red light emitting element, the second color light emitting element may be a green light emitting element, and the third color light emitting element may be a blue light emitting element, but the present invention is not limited thereto.

[0145] In a specific implementation, since the brightness of the red light-emitting element and the green light-emitting element are larger, in the multiple pixel circuits located in the same row, the type of the first pixel circuit can be set to be consistent, the type of the second pixel circuit can be set to be consistent, and the brightness of the blue light-emitting element is relatively low, so in the multiple pixel circuits located in the same row, the third pixel circuit can adopt two different types of pixel circuits.

[0146] In at least one embodiment of the present disclosure,

[0147] The first pixel circuits are all first-type pixel circuits or second-type pixel circuits, and / or the second pixel circuits are all first-type pixel circuits or second-type pixel circuits.

[0148] In a specific implementation, in the pixel structure, the structures of the first pixel circuits may be the same, and the structures of the second pixel circuits may be the same, so as to control the types of pixel circuits electrically connected to the light-emitting elements of the same color to be consistent.

[0149] As shown in FIG5 , under the Real RGB (red, green, and blue) pixel arrangement condition, the first pixel circuits are all first-type pixel circuits, and the second pixel circuits are all second-type pixel circuits;

[0150] In FIG5 , the first pixel circuit labeled R11 is the Nth row, Mth column, the second pixel circuit labeled G12 is the Nth row, M+1th column, the third pixel circuit labeled B13 is the Nth row, M+2th column, the first pixel circuit labeled R14 is the Nth row, M+3th column, the second pixel circuit labeled G15 is the Nth row, M+4th column, and the third pixel circuit labeled B16 is the Nth row, M+5th column.

[0151] The first pixel circuit labeled R21 is the N+1th row, Mth column, the second pixel circuit labeled G22 is the N+1th row, M+1th column, the third pixel circuit labeled B23 is the N+1th row, M+2th column, the first pixel circuit labeled R24 is the N+1th row, M+3th column, the second pixel circuit labeled G25 is the N+1th row, M+4th column, and the third pixel circuit labeled B26 is the N+1th row, M+5th column; M is a positive integer;

[0152] B13 is a first-type pixel circuit, B16 is a second-type pixel circuit, B23 is a second-type pixel circuit, and B26 is a first-type pixel circuit;

[0153] R11 and G22 are both electrically connected to the M-th column data line DM, G12 and R21 are both electrically connected to the M+1-th column data line DM+1, B13 and B23 are both electrically connected to the M+2-th column data line DM+2, R14 and G25 are both electrically connected to the M+3-th column data line DM+3, G15 and R24 are both electrically connected to the M+4-th column data line DM+4, and B16 and B26 are both electrically connected to the M+5-th column data line DM+5.

[0154] In FIG5 , the red light-emitting element labeled E31 is in the Nth row and Mth column, the green light-emitting element labeled E32 is in the Nth row and M+1th column, the blue light-emitting element labeled E33 is in the Nth row and M+2th column, the red light-emitting element labeled E34 is in the Nth row and M+3th column, the green light-emitting element labeled E35 is in the Nth row and M+4th column, and the blue light-emitting element labeled E36 is in the Nth row and M+5th column.

[0155] The red light-emitting element labeled E41 is in the N+1th row and Mth column, the green light-emitting element labeled E42 is in the N+1th row and M+1th column, the blue light-emitting element labeled E43 is in the N+1th row and M+2th column, the red light-emitting element labeled E44 is in the N+1th row and M+3th column, the green light-emitting element labeled E45 is in the N+1th row and M+4th column, and the blue light-emitting element labeled E46 is in the N+1th row and M+5th column.

[0156] R11 is electrically connected to E31, G12 is electrically connected to E32, B13 is electrically connected to E33, R14 is electrically connected to E34, G15 is electrically connected to E35, and B16 is electrically connected to E36;

[0157] R21 is electrically connected to E41, G22 is electrically connected to E42, B23 is electrically connected to E43, R24 is electrically connected to E44, G25 is electrically connected to E45, and B26 is electrically connected to E46.

[0158] In at least one embodiment of the pixel structure shown in FIG5 , R11 , B13 , R14 , R21 , R24 , and B26 are all first-type pixel circuits, and G12 , G15 , B16 , G22 , and G25 are all second-type pixel circuits.

[0159] As shown in FIG5 , when scanning the pixel circuit in the Nth row, the data voltage on DM is the normally black and red data voltage Dr+, the data voltage on DM+1 is the normally white and green data voltage Dg-, the data voltage on DM+2 is the normally black and blue data voltage Db+, the data voltage on DM+3 is the normally black and red data voltage Dr+, the data voltage on DM+4 is the normally white and green data voltage Dg-, and the data voltage on DM+5 is the normally white and blue data voltage Db-;

[0160] When scanning the pixel circuit in the N+1th row, the data voltage on DM is the normally white-green data voltage Dg-, the data voltage on DM+1 is the normally black-red data voltage Dr+, the data voltage on DM+2 is the normally white-blue data voltage Db-, the data voltage on DM+3 is the normally white-green data voltage Dg-, the data voltage on DM+4 is the normally black-red data voltage Dr+, and the data voltage on DM+5 is the normally black-blue data voltage Db+;

[0161] When at least one embodiment of the pixel structure shown in Figure 5 is in operation, the pixel circuits in the Nth row can all be electrically connected to the gate line in the Nth row, and the pixel circuits in the N+1th row can all be electrically connected to the gate line in the N+1th row. When scanning multiple rows of pixel circuits in sequence and displaying a pure color image, the data voltages on the data lines in each column are constantly alternating between high and low voltages, so that the driving signals in the pixel circuits change rapidly under the influence of the data voltage, the change direction no longer accumulates, and the change amplitude becomes smaller, thereby reducing the probability and severity of block crosstalk.

[0162] In at least one embodiment of the pixel structure shown in FIG5 , R11, B13, R14, R21, R24, and B26 may be replaced with second-type pixel circuits, and G12, G15, B16, G22, and G25 may be replaced with first-type pixel circuits.

[0163] In at least one embodiment of the pixel circuit shown in FIG5 , in order to control the consistency of the types of pixel circuits electrically connected to the monochrome light-emitting elements, the red pixel circuits are all set to normally black-red pixel circuits, and the green pixel circuits are all set to normally white-green pixel circuits. Since the brightness of the blue pixel circuits is lower, the blue pixel circuits can adopt two different types of circuit structures.

[0164] Optionally, pixel circuits electrically connected to light-emitting elements having the same color are all first-type pixel circuits or second-type pixel circuits.

[0165] In at least one embodiment of the pixel structure shown in Figure 2, the first pixel circuits are all first-type pixel circuits, the second pixel circuits are all first-type pixel circuits, and the third pixel circuits are all second-type pixel circuits, that is, the pixel circuits electrically connected to the light-emitting elements with the same color are all first-type pixel circuits or first-type pixel circuits, so as to achieve the convenience of Gamma adjustment.

[0166] In at least one embodiment of the present disclosure, in order to facilitate gamma adjustment, the layout may be adjusted so that the structures of pixel circuits electrically connected to light-emitting elements of the same color are consistent.

[0167] In at least one embodiment of the present disclosure, in adjacent rows of pixel circuits, pixel circuits electrically connected to the same data line may be located in the same column.

[0168] As shown in FIG1 , in the pixel circuit of the Nth row and the pixel circuit of the N+1th row, R11 and B21 are both electrically connected to DM, G12 and G22 are both electrically connected to DM+1, B13 and R23 are both electrically connected to DM+2, and G14 and G24 are both electrically connected to DM+3.

[0169] As shown in Figure 3, in the pixel circuit of the Nth row and the pixel circuit of the N+1th row, R11 and R21 are both electrically connected to DM, G12 and G22 are both electrically connected to DM+1, B13 and B23 are both electrically connected to DM+2, R14 and R24 are both electrically connected to DM+3, G15 and G25 are both electrically connected to DM+4, and B16 and B26 are both electrically connected to DM+5.

[0170] As shown in Figure 4, in the pixel circuit of the Nth row and the pixel circuit of the N+1th row, R11 and R21 are both electrically connected to DM, G12 and G22 are both electrically connected to DM+1, B13 and B23 are both electrically connected to DM+2, R14 and R24 are both electrically connected to DM+3, G15 and G25 are both electrically connected to DM+4, and B16 and B26 are both electrically connected to DM+5.

[0171] In at least one embodiment of the present disclosure, in adjacent rows of pixel circuits, pixel circuits electrically connected to the same data line may be located in adjacent columns.

[0172] As shown in FIG2 , B21 is electrically connected to DM, R11 and G22 are both electrically connected to DM+1, G12 and R23 are both electrically connected to DM+2, B13 and G24 are both electrically connected to DM+3, and G14 and B25 are both electrically connected to DM+4;

[0173] R11 and G22 are located in adjacent columns, G12 and R23 are located in adjacent columns, B13 and G24 are located in adjacent columns, and G14 and B25 are located in adjacent columns.

[0174] As shown in FIG6 , R11 and G22 are both electrically connected to DM+1, G12 and B23 are both electrically connected to DM+2, R11 and G22 are located in adjacent columns, and G12 and B23 are located in adjacent columns.

[0175] As shown in FIG7 , R21 and G12 are both electrically connected to DM+1, B13 and G22 are both electrically connected to DM+2, G12 and R21 are located in adjacent columns, and B13 and G22 are located in adjacent columns.

[0176] In a specific implementation, when in adjacent rows of pixel circuits, the pixel circuits electrically connected to the same data line are located in adjacent columns, in adjacent rows of pixel circuits, the first pixel circuit and the second pixel circuit are electrically connected to the same data line, and the third pixel circuit and the second pixel circuit are electrically connected to another data line.

[0177] In at least one embodiment of the present disclosure, in adjacent rows of pixel circuits, the first pixel circuit located in the same column is electrically connected to different column data lines, the second pixel circuit located in the same column is electrically connected to different column data lines, and the third pixel circuit located in the same column is electrically connected to the same column data line.

[0178] Optionally, the pixel structure may include a plurality of pixel units;

[0179] The pixel unit includes a plurality of pixel circuits sequentially arranged along a row direction; the pixel unit is electrically connected to a plurality of column data lines; the plurality of pixel circuits include a first pixel circuit, a second pixel circuit and a third pixel circuit;

[0180] The pixel circuits located in the same row are electrically connected to data lines in different columns respectively.

[0181] As shown in FIG5 , the pixel structure includes a first pixel unit P1 , a second pixel unit P2 , a third pixel unit P3 and a fourth pixel unit P4 ;

[0182] The first pixel unit P1 includes a first pixel circuit R11 in the Nth row and the Mth column, a second pixel circuit G12 in the Nth row and the M+1th column, and a third pixel circuit B13 in the Nth row and the M+2th column, which are sequentially arranged along the row direction;

[0183] The second pixel unit P2 includes a first pixel circuit R14 in the Nth row and the M+3th column, a second pixel circuit G15 in the Nth row and the M+4th column, and a third pixel circuit B16 in the Nth row and the M+5th column, which are sequentially arranged along the row direction;

[0184] The third pixel unit P3 includes a first pixel circuit R21 in the N+1th row and the Mth column, a second pixel circuit G22 in the N+1th row and the M+1th column, and a third pixel circuit B23 in the N+1th row and the M+2th column, which are arranged sequentially along the row direction;

[0185] The fourth pixel unit P4 includes a first pixel circuit R24 in the N+1th row and the M+3th column, a second pixel circuit G25 in the Nth row and the M+4th column, and a third pixel circuit B26 in the Nth row and the M+5th column, which are sequentially arranged along the row direction;

[0186] In at least one embodiment shown in FIG5 , in the pixel circuits in the Nth row and the N+1th row, R11 and R21 are electrically connected to data lines in different columns, G12 and G22 are electrically connected to data lines in different columns, R14 and R24 are electrically connected to data lines in different columns, G15 and G25 are electrically connected to data lines in different columns, B13 and B23 are electrically connected to data lines in the same column, and B16 and B25 are electrically connected to data lines in the same column; pixel circuits located in the same row are electrically connected to data lines in different columns, respectively.

[0187] As shown in FIG6 , the pixel circuit includes a first pixel unit P1 and a second pixel unit P2;

[0188] The first pixel unit P1 includes a first pixel circuit R11 in the Nth row and the Mth column, a second pixel circuit G12 in the Nth row and the M+1th column, and a third pixel circuit B13 in the Nth row and the M+2th column, which are sequentially arranged along the row direction;

[0189] The second pixel unit P2 includes a first pixel circuit R21 in the N+1th row and the Mth column, a second pixel circuit G22 in the N+1th row and the M+1th column, and a third pixel circuit B23 in the N+1th row and the M+2th column, which are arranged sequentially along the row direction;

[0190] R21 is electrically connected to the M-th column data line DM;

[0191] R11 and G22 are both electrically connected to the M+1th column data line DM+1;

[0192] G12 and B23 are both electrically connected to the M+2th column data line DM+2;

[0193] B13 is electrically connected to the fourth column data line DM+3.

[0194] In FIG6 , the red light emitting element labeled E31 is in the Nth row and the Mth column, the green light emitting element labeled E32 is in the Nth row and the M+1th column, and the blue light emitting element labeled E33 is in the Nth row and the M+2th column;

[0195] The red light emitting element labeled E41 is in the N+1th row and Mth column, the green light emitting element labeled E42 is in the N+1th row and M+1th column, and the blue light emitting element labeled E43 is in the N+1th row and M+2th column.

[0196] R11 is electrically connected to E31, G12 is electrically connected to E32, B13 is electrically connected to E33, R21 is electrically connected to E41, G22 is electrically connected to E42, and B23 is electrically connected to E43.

[0197] In at least one embodiment of the pixel structure shown in FIG6 , when scanning the pixel circuits in the Nth row, the data voltage on DM is the normally white virtual data voltage Dd−, the data voltage on DM+1 is the normally black red data voltage Dr+, the data voltage on DM+2 is the normally white green data voltage Dg−, and the data voltage on DM+3 is the normally black blue data voltage Db+.

[0198] When scanning the pixel circuit in the N+1th row, the data voltage on DM is the normally black red data voltage Dr+, the data voltage on DM+1 is the normally white green data voltage Dg-, the data voltage on DM+2 is the normally black blue data voltage Db+, and the data voltage on DM+3 is the normally white virtual data voltage Dd-.

[0199] When at least one embodiment of the pixel structure shown in Figure 6 is in operation, the pixel circuits in the Nth row can all be electrically connected to the gate line in the Nth row, and the pixel circuits in the N+1th row can all be electrically connected to the gate line in the N+1th row. When scanning multiple rows of pixel circuits in sequence and displaying a pure color image, the data voltages on the data lines in each column are constantly alternating between high and low voltages, so that the driving signals in the pixel circuits change rapidly under the influence of the data voltage, the change direction no longer accumulates, and the change amplitude becomes smaller, thereby reducing the probability and severity of block crosstalk.

[0200] As shown in FIG7 , the pixel circuit includes a first pixel unit P1 and a second pixel unit P2;

[0201] The first pixel unit P1 includes a first pixel circuit R11 in the Nth row and the Mth column, a second pixel circuit G12 in the Nth row and the M+1th column, and a third pixel circuit B13 in the Nth row and the M+2th column, which are sequentially arranged along the row direction;

[0202] The second pixel unit P2 includes a first pixel circuit R21 in the N+1th row and the Mth column, a second pixel circuit G22 in the N+1th row and the M+1th column, and a third pixel circuit B23 in the N+1th row and the M+2th column, which are arranged sequentially along the row direction;

[0203] R11 is electrically connected to the M-th column data line DM;

[0204] R21 and G12 are both electrically connected to the M+1th column data line DM+1;

[0205] G22 and B13 are both electrically connected to the M+2 column data line DM+2;

[0206] B23 is electrically connected to the M+3 th column data line DM+3.

[0207] In FIG7 , the red light emitting element labeled E31 is in the Nth row and the Mth column, the green light emitting element labeled E32 is in the Nth row and the M+1th column, and the blue light emitting element labeled E33 is in the Nth row and the M+2th column;

[0208] The red light emitting element labeled E41 is in the N+1th row and Mth column, the green light emitting element labeled E42 is in the N+1th row and M+1th column, and the blue light emitting element labeled E43 is in the N+1th row and M+2th column.

[0209] R11 is electrically connected to E31, G12 is electrically connected to E32, B13 is electrically connected to E33, R21 is electrically connected to E41, G22 is electrically connected to E42, and B23 is electrically connected to E43.

[0210] In at least one embodiment of the pixel structure shown in FIG7 , when scanning the pixel circuits in the Nth row, the data voltage on DM is the normally black red data voltage Dr+, the data voltage on DM+1 is the normally white green data voltage Dg-, the data voltage on DM+2 is the normally black blue data voltage Db+, and the data voltage on DM+3 is the normally white dummy data voltage Dd-.

[0211] When scanning the pixel circuit in the N+1th row, the data voltage on DM is the normally white virtual data voltage Dd-, the data voltage on DM+1 is the normally black red data voltage Dr+, the data voltage on DM+2 is the normally white green data voltage Dg-, and the data voltage on DM+3 is the normally black blue data voltage Db+.

[0212] When at least one embodiment of the pixel structure shown in Figure 7 is in operation, the pixel circuits in the Nth row can all be electrically connected to the gate line in the Nth row, and the pixel circuits in the N+1th row can all be electrically connected to the gate line in the N+1th row. When scanning multiple rows of pixel circuits in sequence and displaying a pure color image, the data voltages on the data lines in each column are constantly alternating between high and low voltages, so that the driving signals in the pixel circuits change rapidly under the influence of the data voltage, the direction of change is no longer accumulated, and the amplitude of change becomes smaller, thereby reducing the probability and severity of block crosstalk.

[0213] In at least one embodiment of the present disclosure, the first type pixel circuit includes a first driving circuit, a first data writing circuit, a first energy storage circuit and a first reference voltage writing circuit;

[0214] The first driving circuit is electrically connected to the first node and the first light-emitting element respectively, and is configured to generate a driving current for driving the first light-emitting element under the control of the potential of the first node;

[0215] The first data writing circuit is electrically connected to the scanning end, the data line and the first node respectively, and is used to control the data line to provide a data voltage to the first node under the control of the scanning signal provided by the scanning end during the data writing phase;

[0216] The first reference voltage writing circuit is electrically connected to the initial control terminal, the first reference voltage terminal, and the first node, respectively, and is configured to write the first reference voltage provided by the first reference voltage terminal into the first node under the control of an initial control signal provided by the initial control terminal during an initialization phase provided before the data writing phase;

[0217] The first energy storage circuit is electrically connected to the first node and is used to store electrical energy.

[0218] In a specific implementation, when the first type pixel circuit is in operation, before data is written, the first reference voltage is written into the first node.

[0219] Optionally, the first light emitting element may be an organic light emitting diode, but is not limited thereto.

[0220] As shown in FIG8 , at least one embodiment of the first type pixel circuit includes a first driving circuit 81 , a first data writing circuit 82 , a first energy storage circuit 83 and a first reference voltage writing circuit 84 ;

[0221] The first driving circuit 81 is electrically connected to the first node N1 and the first light emitting element E1, and is configured to generate a driving current for driving the first light emitting element E1 under the control of the potential of the first node N1.

[0222] The first data writing circuit 82 is electrically connected to the scanning terminal GT, the data line DT and the first node N1 respectively, and is used to control the data line DT to provide a data voltage Vdt to the first node N1 under the control of the scanning signal provided by the scanning terminal GT during the data writing phase;

[0223] The first reference voltage writing circuit 84 is electrically connected to the initial control terminal AZ, the first reference voltage terminal R1 and the first node N1, respectively, and is configured to write the first reference voltage Vref1 provided by the first reference voltage terminal R1 into the first node N1 under the control of the initial control signal provided by the initial control terminal AZ during an initialization phase provided before the data writing phase;

[0224] The first energy storage circuit 83 is electrically connected to the first node N1 and is configured to store electrical energy.

[0225] As shown in FIG9 , based on at least one embodiment of the first type pixel circuit shown in FIG8 , at least one embodiment of the first type pixel circuit may further include a first light emitting control circuit 91 , a second light emitting control circuit 92 , a first initialization circuit 93 , and a second initialization circuit 94 ;

[0226] The first light emitting control circuit 91 is electrically connected to the light emitting control terminal E0, the high voltage terminal VDD, and the first terminal of the first driving circuit 81, respectively, and is used to control the communication between the high voltage terminal VDD and the first terminal of the first driving circuit 81 under the control of the light emitting control signal provided by the light emitting control terminal E0;

[0227] The second light emitting control circuit 92 is electrically connected to the light emitting control terminal E0, the second terminal of the first driving circuit 81, and the first electrode of the first light emitting element E1, respectively, and is configured to control the second terminal of the first driving circuit 81 to communicate with the first electrode of the first light emitting element E1 under the control of a light emitting control signal provided by the light emitting control terminal E0; the second electrode of the first light emitting element E1 is electrically connected to the low voltage terminal VSS;

[0228] The first initialization circuit 93 is electrically connected to the initial control terminal AZ, the initial voltage terminal I1, and the first terminal of the first driving circuit 81, respectively, and is configured to write the initial voltage Vinit provided by the initial voltage terminal I1 into the first terminal of the first driving circuit 81 under the control of the initial control signal provided by the initial control terminal AZ;

[0229] The second initialization circuit 94 is electrically connected to the initial control terminal AZ, the initial voltage terminal I1 and the first electrode of the first light-emitting element E1 respectively, and is used to write the initial voltage Vinit into the first electrode of the first light-emitting element E1 under the control of the initial control signal.

[0230] As shown in FIG10 , based on at least one embodiment of the first type pixel circuit shown in FIG9 , the first light-emitting element is a first organic light-emitting diode O1; the first driving circuit includes a first driving transistor T01; the first data writing circuit includes a first transistor T1, the first reference voltage writing circuit includes a second transistor T2, the first energy storage circuit includes a first capacitor C1 and a second capacitor C2, the first light-emitting control circuit includes a third transistor T3, the second light-emitting control circuit includes a fourth transistor T4, the first initialization circuit 93 includes a fifth transistor T5, and the second initialization circuit 94 includes a sixth transistor T6;

[0231] The gate of T01 is electrically connected to the first node N1;

[0232] A first end of C1 is electrically connected to the first node N1, a second end of C1 is electrically connected to the source of T01, a first end of C2 is electrically connected to the second end of C1, and a second end of C2 is electrically connected to the high voltage terminal VDD;

[0233] The gate of T1 is electrically connected to the scanning terminal GT, the source of T1 is electrically connected to the data line DT, and the drain of T1 is electrically connected to the first node N1;

[0234] The gate of T2 is electrically connected to the initial control terminal AZ, the source of T2 is electrically connected to the first reference voltage terminal R1, and the drain of T2 is electrically connected to the first node N1;

[0235] The gate of T3 is electrically connected to the light emitting control terminal E0, the source of T3 is electrically connected to the high voltage terminal VDD, and the drain of T3 is electrically connected to the source of T0;

[0236] The gate of T4 is electrically connected to the light emitting control terminal E0, the source of T4 is electrically connected to the drain of T0, and the drain of T4 is electrically connected to the anode of O1;

[0237] The gate of T5 is electrically connected to the initial control terminal AZ, the source of T5 is electrically connected to the initial voltage terminal I1, and the drain of T5 is electrically connected to the drain of T01;

[0238] The gate of T6 is electrically connected to the initial control terminal AZ, the source of T6 is electrically connected to the initial voltage terminal I1, and the drain of T6 is electrically connected to the anode of O1.

[0239] In at least one embodiment of the first-type pixel circuit shown in FIG. 10 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0240] As shown in FIG11 , when at least one embodiment of the first type pixel circuit shown in FIG10 is in operation, a display cycle may include an initialization phase S1 , a data writing phase S2 , and a light emitting phase S3 , which are arranged in sequence;

[0241] In the initialization phase S1, AZ provides a low voltage signal, GT and E0 both provide high voltage signals, T2, T5, and T6 are turned on to write the first reference voltage Vref1 provided by the first reference voltage terminal R1 into the first node N1, and the initial voltage Vinit provided by the initial voltage terminal I1 is written into the drain of T01 and the anode of O1, so that when the data writing phase S2 begins, T01 can be turned on and control O1 to not emit light, clearing the residual charge on the anode of O1;

[0242] In the data writing phase S2, AZ provides a high voltage signal, GT provides a low voltage signal, E0 provides a high voltage signal, and T1 is turned on to write the data voltage Vdt provided by DT into the first node to perform data voltage writing and threshold voltage compensation;

[0243] In the light-emitting stage S3, AZ and GT both provide high voltage signals, E0 provides a low voltage signal, T3 and T4 are turned on, and T01 drives O1 to emit light.

[0244] In at least one embodiment of the present disclosure, the second type pixel circuit includes a second light emitting element, a second driving circuit, a second data writing circuit, a second energy storage circuit, and a second reference voltage writing circuit;

[0245] The second driving circuit is electrically connected to the second node and the second light-emitting element respectively, and is configured to generate a driving current for driving the second light-emitting element under the control of the potential of the second node;

[0246] The second energy storage circuit is electrically connected to the second node and the third node respectively, and is used to store electrical energy;

[0247] The second data writing circuit is electrically connected to the scan terminal, the data line and the third node respectively, and is used to write the data voltage provided by the data line into the third node under the control of the scan signal provided by the scan terminal during the data writing phase;

[0248] The second reference voltage writing circuit is electrically connected to the light-emitting control terminal, the second reference voltage terminal and the third node, respectively, and is used to write the second reference voltage provided by the second reference voltage terminal into the third node under the control of the light-emitting control signal provided by the light-emitting control terminal during a light-emitting stage set after the data writing stage.

[0249] In a specific implementation, when the second type pixel circuit is in operation, after data is written, the first reference voltage is written into the first node.

[0250] As shown in FIG12 , the second type pixel circuit includes a second driving circuit 121 , a second data writing circuit 122 , a second energy storage circuit 123 and a second reference voltage writing circuit 124 ;

[0251] The second driving circuit 121 is electrically connected to the second node N2 and the second light-emitting element E2, and is configured to generate a driving current for driving the second light-emitting element E2 under the control of the potential of the second node N2;

[0252] The second energy storage circuit 123 is electrically connected to the second node N2 and the third node N3 respectively, and is used to store electrical energy;

[0253] The second data writing circuit 122 is electrically connected to the scan terminal GT, the data line DT and the third node N3 respectively, and is used to write the data voltage Vdt provided by the data line DT into the third node N3 under the control of the scan signal provided by the scan terminal GT during the data writing phase;

[0254] The second reference voltage writing circuit 124 is electrically connected to the light-emitting control terminal E0, the second reference voltage terminal R2 and the third node N3, respectively, and is used to write the second reference voltage Vref2 provided by the second reference voltage terminal R2 into the third node N3 under the control of the light-emitting control signal provided by the light-emitting control terminal E0 during the light-emitting stage set after the data writing stage.

[0255] As shown in FIG13 , based on at least one embodiment of the second-type pixel circuit shown in FIG12 , at least one embodiment of the second-type pixel circuit may further include a first control circuit 131, a third initialization circuit 132, a compensation control circuit 133, a fourth initialization circuit 134, and a third light-emitting control circuit 135.

[0256] The second energy storage circuit 123 is also electrically connected to the fourth node N4; the first end of the second driving circuit 121 is electrically connected to the high voltage terminal VDD;

[0257] The first control circuit 131 is electrically connected to the initial control terminal AZ, the scanning terminal GT, the high voltage terminal VDD, and the fourth node N4, respectively, and is configured to control the communication between the high voltage terminal VDD and the fourth node N4 under the control of an initial control signal provided by the initial control terminal AZ, and to control the communication between the high voltage terminal VDD and the fourth node N4 under the control of a scanning signal provided by the scanning terminal GT;

[0258] The third initialization circuit 132 is electrically connected to the reset terminal R0, the initial voltage terminal I1 and the second node N2 respectively, and is used to write the initial voltage Vinit provided by the initial voltage terminal I1 into the second node N2 under the control of the reset signal provided by the reset terminal R0;

[0259] The compensation control circuit 133 is electrically connected to the initial control terminal AZ, the second node N2, and the second end of the second driving circuit 121, respectively, and is used to control the second node N2 to be connected to the second end of the second driving circuit 121 under the control of the initial control signal;

[0260] The fourth initialization circuit 134 is electrically connected to the reset terminal R0, the initial voltage terminal I1 and the first electrode of the second light-emitting element E2, respectively, and is used to write the initial voltage Vinit into the first electrode of the second light-emitting element E2 under the control of the reset signal;

[0261] The third light emitting control circuit 135 is electrically connected to the light emitting control terminal E0, the second terminal of the second driving circuit 121, and the first electrode of the second light emitting element E2, respectively, and is used to control the second terminal of the second driving circuit 121 to communicate with the first electrode of the second light emitting element E2 under the control of the light emitting control signal provided by the light emitting control terminal E0;

[0262] The second electrode of the second light emitting element E2 is electrically connected to the low voltage terminal VSS.

[0263] As shown in FIG14 , based on at least one embodiment of the second type pixel circuit shown in FIG13 , the second light-emitting element is a second organic light-emitting diode O2, the second driving circuit includes a second driving transistor T02, the second data writing circuit includes a seventh transistor T7, the second energy storage circuit includes a third capacitor C3 and a fourth capacitor C4, the second reference voltage writing circuit includes an eighth transistor T8, the first control circuit includes a ninth transistor T9 and a tenth transistor T10, the third initialization circuit includes an eleventh transistor T11, the compensation control circuit includes a twelfth transistor T12, the fourth initialization circuit includes a thirteenth transistor T13, and the third light-emitting control circuit includes a fourteenth transistor T14;

[0264] The gate of T02 is electrically connected to the second node N2, and the source of T02 is electrically connected to the high voltage terminal VDD;

[0265] A first end of C3 is electrically connected to the second node N2, a second end of C3 is electrically connected to the fourth node N4, a first end of C4 is electrically connected to the fourth node N4, and a second end of C4 is electrically connected to the third node N3;

[0266] The gate of T7 is electrically connected to the scanning terminal GT, the source of T7 is electrically connected to the data line DT, and the drain of T7 is electrically connected to the third node N3;

[0267] The gate of T8 is electrically connected to the light emitting control terminal E0, the source of T8 is electrically connected to the second reference voltage terminal R2, and the drain of T8 is electrically connected to the third node N3. The second reference voltage terminal R2 is used to provide a second reference voltage Vref2.

[0268] The gate of T9 is electrically connected to the initial control terminal AZ, the source of T9 is electrically connected to the high voltage terminal VDD, and the drain of T9 is electrically connected to the fourth node N4;

[0269] The gate of T10 is electrically connected to the scanning terminal GT, the source of T10 is electrically connected to the high voltage terminal VDD, and the drain of T10 is electrically connected to the fourth node N4;

[0270] The gate of T11 is electrically connected to the reset terminal R0, the source of T11 is electrically connected to the initial voltage terminal I1, and the drain of T11 is electrically connected to the second node N2;

[0271] The gate of T12 is electrically connected to the initial control terminal AZ, the source of T12 is electrically connected to the second node N2, and the drain of T12 is electrically connected to the drain of T02;

[0272] The gate of T13 is electrically connected to the reset terminal R0, the source of T13 is electrically connected to the initial voltage terminal I1, the drain of T13 is electrically connected to the anode of O2; the cathode of O2 is electrically connected to the low voltage terminal VSS;

[0273] The gate of T14 is electrically connected to the light emitting control terminal E0, the source of T14 is electrically connected to the drain of T02, the drain of T14 is electrically connected to the anode of O2; and the cathode of O2 is electrically connected to the low voltage terminal VSS.

[0274] In at least one embodiment of the second-type pixel circuit shown in FIG. 14 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0275] As shown in FIG15 , when at least one embodiment of the second type pixel circuit shown in FIG14 is in operation, a display cycle may include a reset phase S0 , an initialization phase S1 , a data writing phase S2 , and a light emitting phase S3 , which are sequentially arranged;

[0276] In the reset phase S0, R0 provides a low voltage signal, AZ, GT and E0 all provide high voltage signals, T11 and T13 are turned on to write Vinit provided by I1 into the anodes of the second nodes N2 and O2;

[0277] In the initialization phase S1, R0 provides a high voltage signal, AZ provides a low voltage signal, GT and E0 both provide high voltage signals, T9 is turned on to control the connection between the fourth node N4 and VDD, T12 is turned on, and the gate of T02 is connected to the drain of T02;

[0278] In the data writing phase S2, R0 and AZ both provide high voltage signals, GT provides a low voltage signal, E0 provides a high voltage signal, T10 is turned on to control the connection between VDD and the fourth node N4, and T7 is turned on to write the data voltage Vdt provided by DT into the third node N3;

[0279] In the light-emitting stage S3, E0 provides a low voltage signal, R0, AZ and GT all provide high voltage signals, T14 is turned on, and T02 drives O2 to emit light.

[0280] As shown in Figure 16, the voltage value of the data voltage Vdt constantly fluctuates, and the disturbances experienced by other signal lines within the pixel also rapidly alternate between positive and negative. Since all signal lines have their own capacitance, when subjected to disturbances, their capacitance can filter high-frequency signals, thus controlling the amplitude of signal transitions. At the same time, when the crosstalk pattern appears and the image data is switched, the signal voltage change is very small compared to the pure color area. In Figure 16, Vr is the disturbed signal.

[0281] The display panel described in the embodiment of the present disclosure includes the above-mentioned pixel structure.

[0282] The display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

[0283] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel structure, comprising: A plurality of pixel circuits arranged in rows and columns, the plurality of pixel circuits comprising a first type pixel circuit and a second type pixel circuit; A data line electrically connected to the pixel circuit, used to provide a data voltage to the pixel circuit; the pixel circuits located in two adjacent rows electrically connected to at least one of the data lines are respectively a first type pixel circuit and a second type pixel circuit; as well as, a plurality of light-emitting elements, the plurality of light-emitting elements comprising a first light-emitting element electrically connected to the first type pixel circuit and a second light-emitting element electrically connected to the second type pixel circuit; The display brightness of the first light-emitting element increases as the data voltage connected to the first type pixel circuit increases; the display brightness of the second light-emitting element decreases as the data voltage connected to the second type pixel circuit increases.

2. The pixel structure according to claim 1, wherein: The plurality of pixel circuits located in the same row are all first-type pixel circuits or second-type pixel circuits.

3. The pixel structure according to claim 1, wherein: Among the multiple pixel circuits located in the same row, adjacent pixel circuits are first-type pixel circuits and second-type pixel circuits respectively.

4. The pixel structure according to claim 1 or 3, wherein: In a plurality of pixel circuits located in the same row, The first pixel circuits are all first-type pixel circuits or second-type pixel circuits; and / or the second pixel circuits are all first-type pixel circuits or second-type pixel circuits; The light emitting element electrically connected to the first pixel circuit is a first color light emitting element, and the light emitting element electrically connected to the second pixel circuit is a second color light emitting element.

5. The pixel structure according to claim 4, wherein: Among the plurality of pixel circuits located in the same row, some of the third pixel circuits are first-type pixel circuits, and another part of the third pixel circuits are second-type pixel circuits; The light emitting element electrically connected to the third pixel circuit is a light emitting element of a third color.

6. The pixel structure according to claim 5, wherein: The color of the first color light emitting element, the color of the second color light emitting element, and the color of the third color light emitting element are different from each other.

7. The pixel structure according to claim 4, wherein: The first pixel circuits are all first-type pixel circuits or second-type pixel circuits, and / or the second pixel circuits are all first-type pixel circuits or second-type pixel circuits.

8. The pixel structure according to claim 1 or 3, wherein: The pixel circuits electrically connected to the light emitting elements having the same color are all first-type pixel circuits or second-type pixel circuits.

9. The pixel structure according to claim 1, wherein: In adjacent rows of pixel circuits, pixel circuits electrically connected to the same data line are located in the same column.

10. The pixel structure according to claim 5, wherein: In adjacent rows of pixel circuits, pixel circuits electrically connected to the same data line are located in adjacent columns.

11. The pixel structure according to claim 10, wherein: In adjacent rows of pixel circuits, the first pixel circuit and the second pixel circuit are electrically connected to the same data line, and the third pixel circuit and the second pixel circuit are electrically connected to another data line.

12. The pixel structure according to claim 5, wherein: In adjacent rows of pixel circuits, first pixel circuits in the same column are electrically connected to different column data lines, second pixel circuits in the same column are electrically connected to different column data lines, and third pixel circuits in the same column are electrically connected to the same column data line.

13. The pixel structure according to claim 12, wherein: The pixel structure includes a plurality of pixel units, wherein the pixel units include a plurality of pixel circuits sequentially arranged along a row direction; the pixel units are electrically connected to a plurality of columns of data lines; the plurality of pixel circuits include a first pixel circuit, a second pixel circuit and a third pixel circuit; The pixel circuits located in the same row are electrically connected to data lines in different columns respectively.

14. The pixel structure according to any one of claims 1 to 3, wherein: The first type pixel circuit includes a first driving circuit, a first data writing circuit, a first energy storage circuit and a first reference voltage writing circuit; The first driving circuit is electrically connected to the first node and the first light-emitting element respectively, and is used to generate a driving current for driving the first light-emitting element under the control of the potential of the first node; The first data writing circuit is electrically connected to the scanning end, the data line and the first node respectively, and is used to control the data line to provide a data voltage to the first node under the control of the scanning signal provided by the scanning end during the data writing phase; The first reference voltage writing circuit is electrically connected to the initial control terminal, the first reference voltage terminal and the first node respectively, and is used to write the first reference voltage provided by the first reference voltage terminal into the first node under the control of the initial control signal provided by the initial control terminal in an initialization phase provided before the data writing phase; The first energy storage circuit is electrically connected to the first node and is used for storing electric energy.

15. The pixel structure according to any one of claims 1 to 3, wherein: The second type pixel circuit includes a second driving circuit, a second data writing circuit, a second energy storage circuit and a second reference voltage writing circuit; The second driving circuit is electrically connected to the second node and the second light emitting element respectively, and is used to generate a driving current for driving the second light emitting element under the control of the potential of the second node; The second energy storage circuit is electrically connected to the second node and the third node respectively, and is used to store electrical energy; The second data writing circuit is electrically connected to the scanning end, the data line and the third node respectively, and is used to write the data voltage provided by the data line into the third node under the control of the scanning signal provided by the scanning end during the data writing phase; The second reference voltage writing circuit is electrically connected to the light-emitting control terminal, the second reference voltage terminal and the third node, respectively, and is used to write the second reference voltage provided by the second reference voltage terminal into the third node under the control of the light-emitting control signal provided by the light-emitting control terminal during a light-emitting stage set after the data writing stage.

16. A display panel comprising the pixel structure according to any one of claims 1 to 15.

17. A display device comprising the display panel according to claim 16.

Images