Display substrate and display device

Abstract

The invention discloses a display substrate and a display device, the display substrate comprises a display area and a non-display area, the display substrate comprises a substrate and a circuit structure layer arranged on the substrate, and the circuit structure layer comprises a plurality of pixel circuits located in the display area and arranged in an array and a plurality of driving circuits located in the non-display area; at least one pixel circuit comprises a plurality of transistors, and a plurality of driving circuits are arranged to provide driving signals to the plurality of transistors; the circuit structure layer further comprises a high-level power line and a low-level power line which are located in the non-display area, the at least one driving circuit is electrically connected with the high-level power line and the low-level power line, and the high-level power line and the low-level power line extend in the first direction; the high-level power lines connected with the at least two driving circuits are the same power line and / or the low-level power lines connected with the at least two driving circuits are the same power line.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting elements and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] SUMMARY OF THE INVENTION

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure further provides a display substrate comprising: a display area and a non-display area, the display substrate comprising: a base and a circuit structure layer disposed on the base, the circuit structure layer comprising: a plurality of pixel circuits arranged in an array in the display area and a plurality of driving circuits in the non-display area; at least one pixel circuit comprising: a plurality of transistors, the plurality of driving circuits being configured to provide driving signals to the plurality of transistors;

[0006] The circuit structure layer further includes: a high-level power line and a low-level power line located in the non-display area, at least one driving circuit being electrically connected to the high-level power line and the low-level power line, respectively, and the high-level power line and the low-level power line extending along a first direction;

[0007] The high-level power lines connected to at least two driving circuits are the same power line and / or the low-level power lines connected to at least two driving circuits are the same power line.

[0008] In some possible implementations, the display area includes: a first side and a second side arranged opposite to each other, and at least one driving circuit is located on the first side and / or the second side of the display area;

[0009] The plurality of driving circuits extend along a second direction, and the first direction intersects the second direction.

[0010] In some possible implementations, the circuit structure layer includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer stacked sequentially on a substrate;

[0011] The high-level power line and the low-level power line are located in the third conductive layer and / or the fourth conductive layer.

[0012] In some possible implementations, the circuit structure layer may further include: a fifth insulating layer and a fifth conductive layer;

[0013] The fifth insulating layer and the fifth conductive layer are located between the second conductive layer and the third insulating layer, and the fifth insulating layer is located on a side of the fifth conductive layer close to the substrate.

[0014] In some possible implementations, the multiple transistors include: a write transistor, a compensation transistor, and a light-emitting transistor; the multiple driving circuits include: a light-emitting driving circuit and a control driving circuit; the light-emitting driving circuit is configured to provide a driving signal to the light-emitting transistor, and the control driving circuit is configured to provide a driving signal to the write transistor and / or the compensation transistor;

[0015] The high level power line connected to the light emitting drive circuit and the high level power line connected to the control drive circuit are the same power line and / or the low level power line connected to the light emitting drive circuit and the low level power line connected to the control drive circuit are the same power line.

[0016] In some possible implementations, when the high-level power line connected to the light-emitting driving circuit and the high-level power line connected to the control driving circuit are the same power line, the orthographic projection of the high-level power line on the substrate at least partially overlaps with the orthographic projection of the light-emitting driving circuit or the control driving circuit on the substrate, or is located between the light-emitting driving circuit and the control driving circuit.

[0017] In some possible implementations, when the low-level power line connected to the light-emitting driving circuit and the low-level power line connected to the control driving circuit are the same power line, the orthographic projection of the low-level power line on the substrate at least partially overlaps with the orthographic projection of the light-emitting driving circuit or the control driving circuit on the substrate, or is located between the light-emitting driving circuit and the control driving circuit.

[0018] In some possible implementations, the light-emitting driving circuit is located on a side of the control driving circuit away from the display area;

[0019] The circuit structure layer further includes: a light-emitting initial signal line, a plurality of light-emitting clock signal lines, a control initial signal line, and a plurality of control clock signal lines, which are located in the non-display area and extend along a first direction; the light-emitting drive circuit is electrically connected to the light-emitting initial signal line and the plurality of light-emitting clock signal lines, respectively; and the control drive circuit is electrically connected to the control initial signal line and the plurality of control clock signal lines, respectively.

[0020] The light-emitting initial signal line and the plurality of light-emitting clock signal lines are located on a side of the control initial signal line and the plurality of control clock signal lines away from the display area, and the light-emitting initial signal line is located on a side of the plurality of light-emitting clock signal lines close to the display area or on a side away from the display area;

[0021] The control initial signal line is located on a side of the plurality of control clock signal lines close to the display area, or on a side away from the display area.

[0022] In some possible implementations, the light-emitting drive circuit includes: a plurality of light-emitting transistors and a plurality of light-emitting capacitors; the control drive circuit includes: a plurality of control transistors and a plurality of control capacitors;

[0023] The first conductive layer includes: gate electrodes of a plurality of light emitting transistors, gate electrodes of a plurality of control transistors, first plates of a plurality of light emitting capacitors, and first plates of a plurality of control capacitors;

[0024] The second conductive layer includes: a plurality of second plates of light-emitting capacitors and a plurality of second plates of control capacitors;

[0025] The third conductive layer includes: source and drain electrodes of a plurality of light emitting transistors and source and drain electrodes of a plurality of control transistors;

[0026] The fourth conductive layer includes: a light-emitting initial signal line, at least one light-emitting clock signal line, a control initial signal line, and at least one control clock signal line.

[0027] In some possible implementations, the multiple transistors include: a write transistor, a first reset transistor, a compensation transistor, and a light-emitting transistor, the transistor types of the first reset transistor and the compensation transistor are different from the transistor types of the write transistor and the light-emitting transistor, and the multiple driving circuits include: a light-emitting driving circuit, a scan driving circuit, and a control driving circuit; the light-emitting driving circuit is configured to provide a driving signal to the light-emitting transistor, the control driving circuit is configured to provide a driving signal to the write transistor, and the scan driving circuit is configured to provide a driving signal to the first reset transistor and / or the compensation transistor;

[0028] The high-level power lines connected to at least two adjacent drive circuits among the light-emitting drive circuit, the scanning drive circuit and the control drive circuit are the same power line and / or the low-level power lines connected to at least two adjacent drive circuits among the light-emitting drive circuit, the scanning drive circuit and the control drive circuit are the same power line.

[0029] In some possible implementations, when the high-level power line connected to two adjacent driving circuits among the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit is the same power line, an orthographic projection of the high-level power line on the substrate partially overlaps with an orthographic projection of one of the driving circuits connected to the high-level power line on the substrate, or is located between the two adjacent driving circuits connected thereto;

[0030] Alternatively, when the high-level power line connected to the light-emitting drive circuit, the scanning drive circuit and the control drive circuit is the same power line, the orthographic projection of the high-level power line on the substrate partially overlaps with the orthographic projection of one of the drive circuits connected to the high-level power line on the substrate, or is located between two adjacent drive circuits.

[0031] In some possible implementations, when the low-level power line connected to two adjacent drive circuits among the light-emitting drive circuit, the scan drive circuit, and the control drive circuit is the same power line, an orthographic projection of the low-level power line on the substrate partially overlaps with an orthographic projection of one of the drive circuits connected to the low-level power line on the substrate, or is located between the two adjacent drive circuits connected thereto;

[0032] Alternatively, when the low-level power lines connected to the light-emitting drive circuit, the scanning drive circuit and the control drive circuit are the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the drive circuits connected to the low-level power line on the substrate, or is located between two adjacent drive circuits.

[0033] In some possible implementations, the light-emitting driving circuit is located on a side of the scanning driving circuit away from the display area, and the control driving circuit is located on a side of the scanning driving circuit close to the display area;

[0034] The circuit structure layer further includes: a light-emitting initial signal line, a plurality of light-emitting clock signal lines, a control initial signal line, a plurality of control clock signal lines, a scan initial signal line, and a plurality of scan clock signal lines, which are located in the non-display area and extend along a first direction; the light-emitting drive circuit is electrically connected to the light-emitting initial signal line and the plurality of light-emitting clock signal lines, respectively; the control drive circuit is electrically connected to the control initial signal line and the plurality of control clock signal lines, respectively; and the scan drive circuit is electrically connected to the scan initial signal line and the plurality of scan clock signal lines, respectively.

[0035] The light-emitting initial signal line and the plurality of light-emitting clock signal lines are located on a side of the scanning initial signal line and the plurality of scanning clock signal lines away from the display area, and the light-emitting initial signal line is located on a side of the plurality of light-emitting clock signal lines close to the display area or on a side away from the display area;

[0036] The control initial signal line and the plurality of control clock signal lines are located on a side of the scan initial signal line and the plurality of scan clock signal lines close to the display area, and the control initial signal line is located on a side of the plurality of control clock signal lines close to the display area or on a side away from the display area;

[0037] The scan initial signal line is located on a side of the plurality of scan clock signal lines close to the display area, or on a side away from the display area.

[0038] In some possible implementations, the light-emitting drive circuit includes: a plurality of light-emitting transistors and a plurality of light-emitting capacitors; the scan drive circuit includes: a plurality of scan transistors and a plurality of scan capacitors; and the control drive circuit includes: a plurality of control transistors and a plurality of control capacitors.

[0039] The first conductive layer includes: gate electrodes of a plurality of light emitting transistors, gate electrodes of a plurality of scanning transistors, gate electrodes of a plurality of control transistors, first plates of a plurality of light emitting capacitors, first electrodes of a plurality of scanning capacitors, and first plates of a plurality of control capacitors;

[0040] The second conductive layer includes: second plates of a plurality of light-emitting capacitors, second plates of a plurality of scanning capacitors, and second plates of a plurality of control capacitors;

[0041] The third conductive layer includes: source-drain electrodes of a plurality of light-emitting transistors, source-drain electrodes of a plurality of scanning transistors, and source-drain electrodes of a plurality of control transistors;

[0042] The fourth conductive layer includes: a light-emitting initial signal line, at least one light-emitting clock signal line, a scanning initial signal line, at least one scanning clock signal line, a control initial signal line, and at least one control clock signal line.

[0043] In some possible implementations, the write transistor and the light emission control transistor are P-type transistors, and the first reset transistor and the compensation transistor are N-type metal oxide transistors.

[0044] In some possible implementations, the multiple transistors include: a write transistor, a compensation transistor, a first reset transistor, a second reset transistor, and a light-emitting transistor; the multiple driving circuits include: a light-emitting driving circuit, a first reset driving circuit, a second reset driving circuit, and a control driving circuit; the light-emitting driving circuit is configured to provide a driving signal to the light-emitting transistor, the control driving circuit is configured to provide a driving signal to the write transistor and / or the compensation transistor, the first reset driving circuit is configured to provide a driving signal to the first reset transistor, and the second reset driving circuit is configured to provide a driving signal to the second reset transistor;

[0045] The high-level power lines connected to at least two adjacent drive circuits among the light-emitting drive circuit, the first reset drive circuit, the second reset drive circuit and the control drive circuit are the same power line and / or the low-level power lines connected to at least two adjacent drive circuits among the light-emitting drive circuit, the first reset drive circuit, the second reset drive circuit and the control drive circuit are the same power line.

[0046] In some possible implementations, when the high-level power line connected to two adjacent drive circuits among the light-emitting drive circuit, the first reset drive circuit, the second reset drive circuit, and the control drive circuit is the same power line, an orthographic projection of the high-level power line on the substrate partially overlaps with an orthographic projection of one of the drive circuits connected to the high-level power line on the substrate, or is located between the two adjacent drive circuits connected thereto;

[0047] Alternatively, when the high-level power lines connected to at least three adjacent drive circuits among the light-emitting drive circuit, the first reset drive circuit, the second reset drive circuit and the control drive circuit are the same power line, the orthographic projection of the high-level power line on the substrate partially overlaps with the orthographic projection of one of the drive circuits connected to the high-level power line on the substrate, or is located between two adjacent drive circuits.

[0048] In some possible implementations, when the low-level power line connected to two adjacent drive circuits among the light-emitting drive circuit, the first reset drive circuit, the second reset drive circuit, and the control drive circuit is the same power line, an orthographic projection of the low-level power line on the substrate partially overlaps with an orthographic projection of one of the drive circuits connected to the low-level power line on the substrate, or is located between the two adjacent drive circuits connected thereto;

[0049] Alternatively, when the low-level power lines connected to at least three adjacent drive circuits among the light-emitting drive circuit, the first reset drive circuit, the second reset drive circuit and the control drive circuit are the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the drive circuits connected to the low-level power line on the substrate, or is located between two adjacent drive circuits.

[0050] In some possible implementations, the light-emitting drive circuit is located on a side of the control drive circuit away from the display area, the first reset drive circuit is located between the light-emitting drive circuit and the control drive circuit, and the second reset drive circuit is located on a side of the control drive circuit close to the display area;

[0051] The circuit structure layer further includes: a light-emitting initial signal line, a plurality of light-emitting clock signal lines, a control initial signal line, a plurality of control clock signal lines, a first reset initial signal line, a plurality of first reset clock signal lines, a second reset initial signal line, and a plurality of second reset clock signal lines, which are located in the non-display area and extend along the first direction; the light-emitting drive circuit is electrically connected to the light-emitting initial signal line and the plurality of light-emitting clock signal lines, respectively; the control drive circuit is electrically connected to the control initial signal line and the plurality of control clock signal lines, respectively; the first reset drive circuit is electrically connected to the first reset initial signal line and the plurality of first reset clock signal lines, respectively; and the second reset drive circuit is electrically connected to the second reset initial signal line and the plurality of second reset clock signal lines, respectively.

[0052] The light-emitting initial signal line and the plurality of light-emitting clock signal lines are located on a side of the first reset initial signal line and the plurality of first reset clock signal lines away from the display area, and the light-emitting initial signal line is located on a side of the plurality of light-emitting clock signal lines close to the display area or on a side away from the display area;

[0053] The first reset initial signal line and the plurality of first reset clock signal lines are located on a side of the control initial signal line and the plurality of control clock signal lines close to the display area, and the first reset initial signal line is located on a side of the plurality of first reset clock signal lines close to the display area or on a side away from the display area;

[0054] The control initial signal line and the control clock signal line are located on a side of the second reset initial signal line and the plurality of second reset clock signal lines away from the display area, and the control initial signal line is located on a side of the plurality of control clock signal lines close to the display area or away from the display area;

[0055] The second reset initial signal line is located on a side of the plurality of second reset clock signal lines close to the display area or on a side away from the display area.

[0056] In some possible implementations, the light-emitting drive circuit includes: a plurality of light-emitting transistors and a plurality of light-emitting capacitors; the scan drive circuit includes: a plurality of scan transistors and a plurality of scan capacitors; the first reset drive circuit includes: a plurality of first reset transistors and a plurality of first reset capacitors; and the second reset drive circuit includes: a plurality of second reset transistors and a plurality of second reset capacitors.

[0057] The first conductive layer includes: gate electrodes of multiple light-emitting transistors, gate electrodes of multiple control transistors, gate electrodes of multiple first reset transistors, gate electrodes of multiple second reset transistors, first plates of multiple light-emitting capacitors, first plates of multiple control capacitors, first plates of multiple first reset capacitors, and first plates of multiple second reset capacitors;

[0058] The second conductive layer includes: a plurality of second plates of light-emitting capacitors, a plurality of second plates of control capacitors, a plurality of second plates of first reset capacitors, and a plurality of second plates of second reset capacitors;

[0059] The third conductive layer includes: source-drain electrodes of a plurality of light-emitting transistors, source-drain electrodes of a plurality of control transistors, source-drain electrodes of a plurality of first reset transistors, and source-drain electrodes of a plurality of second reset transistors;

[0060] The fourth conductive layer includes: a light-emitting initial signal line, at least one light-emitting clock signal line, a control initial signal line, at least one control clock signal line, a first reset initial signal line, at least one first reset clock signal line, a second reset initial signal line, and at least one second reset clock signal line.

[0061] In some possible implementations, the boundary of the display area includes: at least one arc-shaped boundary.

[0062] In a second aspect, the present disclosure further provides a display device comprising the above-mentioned display substrate.

[0063] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0064] Summary of the Figures

[0065] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0066] FIG1 is a schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0067] 2A to 2C are schematic diagrams showing connections between multiple driving circuits and power lines according to an exemplary embodiment;

[0068] FIG3 is a schematic diagram of an equivalent circuit of a pixel circuit;

[0069] 4A to 4C are partial schematic diagrams of a display substrate including two driving circuits provided by an exemplary embodiment;

[0070] FIG5A is an equivalent circuit diagram of a light-emitting shift register provided by an exemplary embodiment;

[0071] FIG5B is a timing diagram of the light-emitting shift register provided in FIG5A ;

[0072] FIG6A is an equivalent circuit diagram of a control shift register provided by an exemplary embodiment;

[0073] FIG6B is a timing diagram of the control shift register provided in FIG6A ;

[0074] 7A to 7F are partial schematic diagrams of a display substrate including three driving circuits provided by an exemplary embodiment;

[0075] FIG8A is an equivalent circuit diagram of a scan shift register provided by an exemplary embodiment;

[0076] FIG8B is a timing diagram of the scan shift register provided in FIG8A ;

[0077] 9A to 9I are partial schematic diagrams of a display substrate including four driving circuits provided by an exemplary embodiment;

[0078] FIG10 is a schematic diagram after forming a semiconductor layer;

[0079] FIG11 is a schematic diagram of a first conductive layer;

[0080] FIG12 is a schematic diagram after forming the first conductive layer;

[0081] FIG13 is a schematic diagram of a second conductive layer;

[0082] FIG14 is a schematic diagram after forming a second conductive layer;

[0083] FIG15 is a schematic diagram of a fifth conductive layer;

[0084] FIG16 is a schematic diagram after forming a fifth conductive layer;

[0085] FIG17 is a schematic diagram of a third conductive layer;

[0086] FIG18 is a schematic diagram after forming a third conductive layer;

[0087] FIG19 is a schematic diagram of a fourth conductive layer;

[0088] FIG20 is a schematic diagram after forming a fourth conductive layer;

[0089] FIG21 is a schematic diagram of a sixth conductive layer;

[0090] FIG. 22 is a schematic diagram after forming the sixth conductive layer.

[0091] Details

[0092] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0093] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0094] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0095] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of the present disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0096] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0097] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0098] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0099] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0100] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0101] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0102] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0103] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0104] Display substrates offer advantages such as high resolution, high response speed, high brightness, and a high aperture ratio, and have broad application prospects. To achieve a better visual experience, narrow bezels are a key development direction for displays. Display substrates contain driver circuits that drive pixel circuits to emit light, thereby enabling display. However, display substrates cannot achieve narrow bezels.

[0105] FIG1 is a schematic diagram of the structure of a display substrate provided by an embodiment of the present disclosure, and FIG2A to FIG2C are schematic diagrams of the connection between multiple driving circuits and power lines provided by an exemplary embodiment. As shown in FIG1 and FIG2A to FIG2C, the display substrate provided by an embodiment of the present disclosure includes: a display area AA and a non-display area AA', the display substrate includes: a substrate and a circuit structure layer provided on the substrate, the circuit structure layer includes: a plurality of pixel circuits P arranged in an array in the display area and a plurality of driving circuits GOA1 to GOA2 in the non-display area. M At least one pixel circuit includes: a plurality of transistors, a plurality of driving circuits configured to provide driving signals to the plurality of transistors.

[0106] In an exemplary embodiment, as shown in Figures 2A to 2C, the circuit structure layer further includes: a high-level power line VGH and a low-level power line VGL located in the non-display area, and at least one driving circuit electrically connected to the high-level power line VGH and the low-level power line VGL, respectively. The high-level power line VGH continuously provides a high-level signal, and the low-level power line VGL continuously provides a low-level signal.

[0107] In an exemplary embodiment, the high-level power line VGH and the low-level power line VGL extend along a first direction.

[0108] In an exemplary embodiment, as shown in Figures 2A to 2C, the high-level power lines connected to at least two driving circuits are the same power line and / or the low-level power lines connected to at least two driving circuits are the same power line. Figure 2A is illustrated using the example of the high-level power lines connected to at least two driving circuits being the same power line, Figure 2B is illustrated using the example of the low-level power lines connected to at least two driving circuits being the same power line, and Figure 2C is illustrated using the example of the high-level power lines connected to at least two driving circuits being the same power line and the low-level power lines connected to at least two driving circuits being the same power line.

[0109] In an exemplary embodiment, the display substrate disclosed herein can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0110] In an exemplary embodiment, the display substrate may be an LTPO display substrate or an LTPS display substrate.

[0111] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0112] In an exemplary embodiment, the positional relationship of the plurality of driving circuits may be determined according to the structure and function of the display substrate, which is not limited in the present disclosure.

[0113] In an exemplary embodiment, the display substrate may further include a light emitting structure layer disposed on a side of the circuit structure layer away from the substrate, and an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate.

[0114] In one exemplary embodiment, the light-emitting structure layer includes: light-emitting elements arranged in an array in the display area. The light-emitting elements include: a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), with the anode located on the side of the organic light-emitting layer closer to the substrate and the cathode located on the side of the organic light-emitting layer farther from the substrate. The light-emitting elements are electrically connected to the pixel circuit.

[0115] In an exemplary embodiment, the circuit structure layer may further include: a second power line located in the non-display area, the second power line being electrically connected to the cathode of the light emitting element.

[0116] In one exemplary embodiment, the light emitting element may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).

[0117] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0118] In an exemplary embodiment, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

[0119] In an exemplary embodiment, the pixel circuit may be a 7T1C or 8T1C structure.

[0120] In an exemplary embodiment, FIG3 is a schematic diagram of an equivalent circuit of a pixel circuit. As shown in FIG3 , the pixel circuit may include seven transistors (first transistor T1 to seventh transistor T7), one capacitor C, and eight signal terminals (data signal terminal Data, control signal terminal G, scan signal terminal S, first reset signal terminal Reset1, second reset signal terminal Reset2, light emitting signal terminal EM, initial signal terminal Vinit, first power supply terminal VDD, and second power supply terminal VSS).

[0121] In an exemplary embodiment, a first plate of capacitor C is connected to a first power supply terminal VDD, and a second plate of capacitor C is connected to a first node N1. A control electrode of the first transistor T1 is connected to a reset signal terminal Reset, a first electrode of the first transistor T1 is connected to an initial signal terminal Vinit, and a second electrode of the first transistor is connected to the first node N1. A control electrode of the second transistor T2 is connected to a scan signal terminal S, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to a second node N2. A control electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to a third node N3. A control electrode of the fourth transistor T4 is connected to a control signal terminal G, a first electrode of the fourth transistor T4 is connected to a data signal terminal Data, and a second electrode of the fourth transistor T4 is connected to a third node N3. The control electrode of the fifth transistor T5 is connected to the light-emitting signal terminal EM, the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is connected to the third node N3. The control electrode of the sixth transistor T6 is connected to the light-emitting signal terminal EM, the first electrode of the sixth transistor T6 is connected to the second node N2, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The control electrode of the seventh transistor T7 is connected to the control signal terminal G, the first electrode of the seventh transistor T7 is connected to the initial signal terminal Vinit, the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device, and the second electrode of the light-emitting device is connected to the second power supply terminal VSS.

[0122] In an exemplary embodiment, the first transistor T1 may be referred to as a first reset transistor. When a valid level signal is input to the first reset signal terminal Reset1 , the first transistor T1 transmits an initialization voltage to the first node N1 to initialize the charge of the first node N1 .

[0123] In an exemplary embodiment, the seventh transistor T7 can be called a second reset transistor. When the second reset signal terminal Reset2 inputs a valid level signal, the seventh transistor T7 transmits an initialization voltage to the anode of the light-emitting element to initialize the charge amount of the anode of the light-emitting element.

[0124] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor. When the scan signal terminal S inputs an effective level signal, the second transistor T2 transmits the signal of the second node to the first node N1 to compensate the control electrode of the driving transistor.

[0125] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines a driving current flowing between the first power supply terminal VDD and the second power supply terminal VSS according to a potential difference between the control electrode and the first electrode.

[0126] In an exemplary embodiment, the fourth transistor T4 may be referred to as a writing transistor. When the control signal terminal S1 inputs an active level signal, the fourth transistor T4 inputs the data voltage of the data signal terminal Data into the pixel circuit.

[0127] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 can be referred to as light emitting transistors. When a valid level signal is input to the light emitting signal terminal E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply terminal VDD and the second power supply terminal VSS to enable the light emitting element to emit light.

[0128] In an exemplary embodiment, the signal of the first power supply terminal VDD is a continuously high-level signal, and the signal of the second power supply terminal VSS is a low-level signal.

[0129] In an exemplary embodiment, the first power supply terminal VDD is configured to continuously provide a high level signal, and the second power supply terminal VSS is configured to continuously provide a low level signal.

[0130] In an exemplary embodiment, the first reset signal terminal Reset1 and the second reset signal terminal Reset2 may be the same signal terminal, and the control signal terminal G and the scan signal terminal S may be the same signal terminal.

[0131] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. For example, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0132] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, and oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0133] In an exemplary embodiment, the display substrate further includes: a data signal line, a first reset signal line, a second reset signal line, a control signal line, a scan signal line, and a light-emitting signal line. The first reset signal terminal of the pixel circuit is electrically connected to the first reset signal line, the second reset signal terminal is electrically connected to the second reset signal line, the control signal terminal is electrically connected to the control signal line, the scan signal terminal is electrically connected to the scan signal line, the light-emitting signal terminal is connected to the light-emitting signal line, and the data signal terminal is electrically connected to the data signal line. When the first reset signal terminal and the second reset signal terminal are the same signal terminal, the first reset signal line and the second reset signal line can be the same signal line. When the control signal terminal and the scan signal terminal are the same signal terminal, the control signal line and the scan signal line can be the same signal line.

[0134] The display substrate provided by the embodiment of the present disclosure includes: a display area and a non-display area, the display substrate includes: a base and a circuit structure layer arranged on the base, the circuit structure layer includes: a plurality of pixel circuits located in the display area and arranged in an array and a plurality of driving circuits located in the non-display area; at least one pixel circuit includes: a plurality of transistors, and the plurality of driving circuits are configured to provide driving signals to the plurality of transistors; the circuit structure layer also includes: a high-level power line and a low-level power line located in the non-display area, at least one driving circuit is electrically connected to the high-level power line and the low-level power line, respectively, and the high-level power line and the low-level power line extend along a first direction; the high-level power lines connected to at least two driving circuits are the same power line and / or the low-level power lines connected to at least two driving circuits are the same power line. The present disclosure can reduce the area occupied by multiple driving circuits and achieve a narrow frame by having the high-level power lines connected to at least two driving circuits be the same power line and / or the low-level power lines connected to at least two driving circuits be the same power line.

[0135] In an exemplary embodiment, the display area includes a first side and a second side disposed opposite each other, and at least one driving circuit is located on the first side and / or the second side of the display area. FIG1 illustrates an example in which at least one driving circuit is located on the first side and the second side of the display area.

[0136] In an exemplary embodiment, the plurality of driving circuits extend along the second direction, and the first direction intersects the second direction.

[0137] In one exemplary embodiment, the circuit structure layer includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer stacked sequentially on a substrate. The high-level power line and the low-level power line may be located in the third conductive layer and / or the fourth conductive layer.

[0138] In an exemplary embodiment, the circuit structure layer may further include a fifth insulating layer and a fifth conductive layer, wherein the fifth insulating layer and the fifth conductive layer are located between the second conductive layer and the third insulating layer, and the fifth insulating layer is located on a side of the fifth conductive layer close to the substrate.

[0139] In an exemplary embodiment, the circuit structure layer may further include: a sixth insulating layer and a sixth conductive layer, wherein the sixth insulating layer is located on a side of the fourth conductive layer away from the substrate, and the sixth conductive layer is located on a side of the sixth insulating layer away from the substrate.

[0140] In an exemplary embodiment, Figures 4A to 4C are partial schematic diagrams of a display substrate including two drive circuits, provided in accordance with an exemplary embodiment. As shown in Figures 4A to 4C, when the display substrate is an LTPS display substrate, the write transistor, compensation transistor, and light-emitting transistor are of the same type, the first reset signal terminal and the second reset signal terminal are the same signal terminal, and the control signal terminal and the scan signal terminal are the same signal terminal. The multiple drive circuits include a light-emitting drive circuit (EM GOA) and a control drive circuit (GateP GOA). The light-emitting drive circuit (EM GOA) is configured to provide drive signals to the light-emitting transistor, and the control drive circuit (GateP GOA) is configured to provide drive signals to the write transistor and / or the compensation transistor.

[0141] In an exemplary embodiment, the high-level power line EVGH connected to the light-emitting driving circuit EM GOA and the high-level power line GVGH connected to the control driving circuit GateP GOA are the same power line and / or the low-level power line EVGL connected to the light-emitting driving circuit EM GOA and the low-level power line GVGL connected to the control driving circuit GateP GOA are the same power line.

[0142] FIG4A illustrates an example in which the low-level power line EVGL connected to the light-emitting drive circuit EM GOA and the low-level power line GVGL connected to the control drive circuit GateP GOA are the same power line, while the high-level power line EVGH connected to the light-emitting drive circuit EM GOA and the high-level power line GVGH connected to the control drive circuit GateP GOA are different power lines. FIG4B illustrates an example in which the low-level power line EVGL connected to the light-emitting drive circuit EM GOA and the low-level power line GVGL connected to the control drive circuit GateP GOA are different power lines, while the high-level power line EVGH connected to the light-emitting drive circuit EM GOA and the high-level power line GVGH connected to the control drive circuit GateP GOA are the same power line. Figure 4C is explained by taking the low-level power line EVGL connected to the light-emitting driving circuit EM GOA and the low-level power line GVGL connected to the control driving circuit GateP GOA as the same power line, and the high-level power line EVGH connected to the light-emitting driving circuit EM GOA and the high-level power line GVGH connected to the control driving circuit GateP GOA as the same power line as an example.

[0143] In an exemplary embodiment, when the high-level power line connected to the light-emitting driver circuit and the high-level power line connected to the control driver circuit are the same power line, the orthographic projection of the high-level power line on the substrate at least partially overlaps with the orthographic projection of the light-emitting driver circuit or the control driver circuit on the substrate, or is located between the light-emitting driver circuit and the control driver circuit. Having the orthographic projection of the high-level power line on the substrate at least partially overlap with the orthographic projection of the light-emitting driver circuit or the control driver circuit on the substrate, or being located between the light-emitting driver circuit and the control driver circuit, can reduce the area occupied by multiple driver circuits and achieve a narrow bezel.

[0144] In an exemplary embodiment, when the low-level power line connected to the light-emitting driver circuit and the low-level power line connected to the control driver circuit are the same power line, the orthographic projection of the low-level power line on the substrate at least partially overlaps with the orthographic projection of the light-emitting driver circuit or the control driver circuit on the substrate, or is located between the light-emitting driver circuit and the control driver circuit. Having the orthographic projection of the low-level power line on the substrate at least partially overlap with the orthographic projection of the light-emitting driver circuit or the control driver circuit on the substrate, or being located between the light-emitting driver circuit and the control driver circuit, can reduce the area occupied by multiple driver circuits and achieve a narrow bezel.

[0145] In an exemplary embodiment, the positional relationship between the control driving circuit and the light emitting control circuit can be determined according to the structure and function of the display substrate. The light emitting driving circuit EM GOA can be located on a side of the control driving circuit GateP GOA away from the display area.

[0146] In one exemplary embodiment, as shown in Figures 4A to 4C , the circuit structure layer further includes: a light-emission start signal line ESTV, multiple light-emission clock signal lines, a control start signal line GSTV, and multiple control clock signal lines, located in the non-display area and extending along a first direction; a light-emission drive circuit electrically connected to the light-emission start signal line ESTV and the multiple light-emission clock signal lines, respectively; and a control drive circuit electrically connected to the control start signal line GSTV and the multiple control clock signal lines, respectively. Figures 4A to 4C illustrate the three light-emission clock signal lines ECLK1 to ECLK3 and the two control clock signal lines GCLK1 and GCLK2 as examples.

[0147] In an exemplary embodiment, as shown in Figures 4A to 4C, the light-emitting start signal line ESTV and the multiple light-emitting clock signal lines ECLK1 to ECLK3 are located on a side of the control start signal line GSTV and the multiple control clock signal lines GCLK1 and GCLK2 that is away from the display area, and the light-emitting start signal line ESTV is located on a side of the multiple light-emitting clock signal lines ECLK1 to ECLK3 that is either close to the display area or away from the display area. The control start signal line GSTV is located on a side of the multiple control clock signal lines GCLK1 and GCLK2 that is either close to the display area or away from the display area. Figures 4A to 4C illustrate the example of the light-emitting start signal line ESTV being located on a side of the multiple light-emitting clock signal lines ECLK1 to ECLK3 that is away from the display area, and the control start signal line GSTV being located on a side of the multiple control clock signal lines GCLK1 and GCLK2 that is close to the display area. The positional relationship between the light-emitting start signal line ESTV, the multiple light-emitting clock signal lines, the control start signal line GSTV, and the multiple control clock signal lines can be determined based on the structure and function of the display substrate, and this disclosure does not impose any limitations on this.

[0148] In an exemplary embodiment, a light-emitting drive circuit includes: multiple light-emitting transistors and multiple light-emitting capacitors, and a control drive circuit includes: multiple control transistors and multiple control capacitors. The first conductive layer includes: gate electrodes of multiple light-emitting transistors, gate electrodes of multiple control transistors, first plates of multiple light-emitting capacitors, and first plates of multiple control capacitors; the second conductive layer includes: second plates of multiple light-emitting capacitors and second plates of multiple control capacitors; the third conductive layer includes: source and drain electrodes of multiple light-emitting transistors and source and drain electrodes of multiple control transistors; and the fourth conductive layer includes: a light-emitting initial signal line, at least one light-emitting clock signal line, a control initial signal line, and at least one control clock signal line.

[0149] In an exemplary embodiment, the light-emitting driving circuit may include: multiple cascaded light-emitting shift registers, at least one light-emitting shift register includes: multiple light-emitting control transistors and multiple light-emitting capacitors, and at least one level of light-emitting shift register is electrically connected to at least one light-emitting signal line.

[0150] In an exemplary embodiment, the light emitting shift register may include: a plurality of light emitting control transistors and a plurality of light emitting capacitors. The circuit structure of the light emitting shift register may be 14T3C, 13T3C or 10T3C, which is not limited in the present disclosure.

[0151] Figure 5A is an equivalent circuit diagram of a light-emitting shift register provided in an exemplary embodiment, and Figure 5B is a timing diagram of the light-emitting shift register provided in Figure 5A. As shown in Figure 5A, in an exemplary embodiment, the light-emitting shift register includes: first to thirteenth light-emitting control transistors ET1 to ET13 and first to third light-emitting capacitors EC1 to EC3.

[0152] In an exemplary embodiment, a control electrode of the first emission control transistor ET1 is electrically connected to the third clock signal terminal ECK3, a first electrode of the first emission control transistor ET1 is electrically connected to the input terminal EIN, and a second electrode of the first emission control transistor ET1 is electrically connected to the first node E1. A control electrode of the second emission control transistor ET2 is electrically connected to the first node E1, a first electrode of the second emission control transistor ET2 is electrically connected to the third clock signal terminal ECK3, and a second electrode of the second emission control transistor ET2 is electrically connected to the second node E2. A control electrode of the third emission control transistor ET3 is electrically connected to the third clock signal terminal ECK3, a first electrode of the third emission control transistor ET3 is electrically connected to the second power supply terminal VGL, and a second electrode of the third emission control transistor ET3 is electrically connected to the second node E2. A control electrode of the fourth emission control transistor ET4 is electrically connected to the third node E3, a first electrode of the fourth emission control transistor ET4 is electrically connected to the first clock signal terminal ECK1, and a second electrode of the fourth emission control transistor ET4 is electrically connected to the fifth node E5. A control electrode of a fifth emission control transistor ET5 is electrically connected to a fourth node E4, a first electrode of the fifth emission control transistor ET5 is electrically connected to a fifth node E5, and a second electrode of the fifth emission control transistor ET5 is electrically connected to a first power supply terminal VGH. A control electrode of a sixth emission control transistor ET6 is electrically connected to a fourth node E4, a first electrode of the sixth emission control transistor ET6 is electrically connected to a first clock signal terminal ECK1, and a second electrode of the sixth emission control transistor ET6 is electrically connected to a sixth node E6. A control electrode of a seventh emission control transistor ET7 is electrically connected to a first clock signal terminal ECK1, a first electrode of the seventh emission control transistor ET7 is electrically connected to a sixth node E6, and a second electrode of the seventh emission control transistor ET7 is electrically connected to a seventh node E7. A control electrode of an eighth emission control transistor ET8 is electrically connected to a first node E1, a first electrode of the eighth emission control transistor ET8 is electrically connected to a first power supply terminal VGH, and a second electrode of the eighth emission control transistor ET8 is electrically connected to a seventh node E7. A control electrode of the ninth emission control transistor ET9 is electrically connected to the seventh node E7, a first electrode of the ninth emission control transistor ET9 is electrically connected to the first power supply terminal VGH, and a second electrode of the ninth emission control transistor ET9 is electrically connected to the output terminal EOUT. A control electrode of the tenth emission control transistor ET10 is electrically connected to the third node E3, a first electrode of the tenth emission control transistor ET10 is electrically connected to the second power supply terminal VGL, and a second electrode of the tenth emission control transistor ET10 is electrically connected to the output terminal EOUT. A control electrode of the eleventh emission control transistor ET11 is electrically connected to the second power supply terminal VGL, a first electrode of the eleventh emission control transistor ET11 is electrically connected to the second node E2, and a second electrode of the eleventh emission control transistor ET11 is electrically connected to the fourth node E4.A control electrode of the twelfth emission control transistor ET12 is electrically connected to the second power supply terminal VGL, a first electrode of the twelfth emission control transistor ET12 is electrically connected to the first node E1, and a second electrode of the twelfth emission control transistor ET12 is electrically connected to the third node E3. A control electrode of the thirteenth emission control transistor ET13 is electrically connected to the second clock signal terminal ECK2, a first electrode of the thirteenth emission control transistor ET13 is electrically connected to the first node E1, and a second electrode of the thirteenth emission control transistor ET13 is electrically connected to the first power supply terminal VGH. A first plate EC11 of the first light emitting capacitor EC1 is electrically connected to a fourth node E4, and a second plate EC12 of the first light emitting capacitor EC1 is electrically connected to a sixth node E6. A first plate EC21 of the second light emitting capacitor EC2 is electrically connected to a seventh node E7, and a second plate EC22 of the second light emitting capacitor EC2 is electrically connected to the first power supply terminal VGH. A first plate EC31 of the third light emitting capacitor EC3 is electrically connected to a third node E3, and a second plate EC32 of the third light emitting capacitor EC3 is electrically connected to a fifth node E5.

[0153] In an exemplary embodiment, the first to thirteenth light emission control transistors ET1 to ET13 may be P-type transistors or N-type transistors.

[0154] In an exemplary embodiment, the first power supply terminal VGH continuously provides a high level signal and the second power supply terminal VGL continuously provides a low level signal. Since the second power supply terminal VGL continuously provides a low level signal, the eleventh emission control transistor ET11 and the twelfth emission control transistor ET12 are continuously turned on.

[0155] In an exemplary embodiment, the second clock signal terminal ECK2 is a low-level signal during the power-on initialization phase to prevent the ninth and tenth light-emitting control transistors ET9 and ET10 of the last light-emitting shift register from being simultaneously turned on due to a delay in the output signal. Alternatively, the second clock signal terminal ECK2 is a low-level signal during the abnormal shutdown phase to prevent the ninth and tenth light-emitting control transistors ET9 and ET10 from being simultaneously turned on. The second clock signal terminal ECK2 continuously provides a high-level signal during the normal display phase, i.e., during the normal display phase, the thirteenth light-emitting control transistor ET13 is continuously turned off.

[0156] Taking the first to thirteenth light-emitting control transistors ET1 to ET13 as P-type transistors as an example, as shown in FIG5B , the operation process of the light-emitting shift register provided by an exemplary embodiment includes the following stages:

[0157] In the first phase B1, the signal at the first clock signal terminal ECK1 is a high-level signal, and the signal at the third clock signal terminal ECK3 is a low-level signal. The signal at the third clock signal terminal ECK3 is a low-level signal, and the first emission control transistor ET1, the third emission control transistor ET3, and the twelfth emission control transistor ET12 are turned on. The turned-on first emission control transistor ET1 transmits the high-level signal at the input terminal EIN to the first node E1, thereby changing the level of the first node E1 to a high-level signal. The turned-on twelfth emission control transistor ET12 transmits the high-level signal at the first node E1 to the third node E2, and the second emission control transistor ET2, the fourth emission control transistor ET4, the eighth emission control transistor ET8, and the tenth emission control transistor ET10 are turned off. In addition, the conductive third emission control transistor ET3 transmits the low-level signal from the third power supply terminal VGL to the second node E2, thereby causing the level of the second node E2 to change to a low level. The conductive eleventh emission control transistor ET11 transmits the low-level signal from the second node E2 to the fourth node E4, thereby causing the level of the fourth node E4 to change to a low level. The fifth emission control transistor ET5 and the sixth emission control transistor ET6 are also turned on. The signal at the first clock signal terminal ECK1 is a high-level signal, and the seventh emission control transistor ET7 is turned off. In addition, the third emission capacitor EC3 turns off the ninth emission control transistor ET9. In the first phase P1, because the ninth emission control transistor ET9 and the tenth emission control transistor ET10 are both turned off, the signal at the output terminal EOUT remains at the previous low level.

[0158] In the second phase B2, the first clock signal terminal ECK1 is a low-level signal, and the signal at the third clock signal terminal ECK3 is a high-level signal. The signal at the first clock signal terminal ECK1 is a low-level signal, turning on the seventh emission control transistor ET7. The signal at the third clock signal terminal ECK3 is a high-level signal, turning off the first and third emission control transistors ET1 and ET3. Under the action of the third emission capacitor EC3, the first and third nodes E1 and E3 can continue to maintain the high-level signals from the previous phase. Under the action of the first emission capacitor EC1, the fourth node E4 can continue to maintain the low-level signal from the previous phase, turning on the fifth and sixth emission control transistors ET5 and ET6. The second, fourth, eighth, and tenth emission control transistors ET2, ET4, ET8, and ET10 are turned off. In addition, the low-level signal of the first clock signal terminal ECK1 is transmitted to the seventh node E7 through the turned-on sixth emission control transistor ET6 and the seventh emission control transistor ET7, and the ninth emission control transistor ET9 is turned on. The turned-on ninth emission control transistor ET9 outputs the high-level signal of the first power supply terminal VGH, so the signal of the output terminal EOUT is a high-level signal. In addition,

[0159] In the third phase B3, the signal at the third clock signal terminal ECK3 is a low-level signal, and the signal at the first clock signal terminal ECK1 is a high-level signal. The signal at the first clock signal terminal ECK1 is a high-level signal, and the seventh emission control transistor ET7 is turned off. The second emission control transistor ET2, the fourth emission control transistor ET4, the eighth emission control transistor ET8, and the tenth emission control transistor ET10 are turned off. The signal at the third clock signal terminal ECK3 is a low-level signal, and the first emission control transistor ET1 and the third emission control transistor ET3 are turned on. Under the action of the second emission capacitor EC3, the ninth emission control transistor ET9 remains on. The turned-on ninth emission control transistor ET9 outputs the high-level signal from the first power supply terminal VGH, so the signal at the output terminal EOUT remains high.

[0160] In the fourth phase B4, the signal at the first clock signal terminal ECK1 is low, and the signal at the third clock signal terminal ECK3 is high. The signal at the third clock signal terminal ECK3 is high, turning off the first and third emission control transistors ET1 and ET3. The signal at the first clock signal terminal ECK1 is low, turning on the seventh emission control transistor ET7. Due to the storage function of the third emission capacitor EC3, the levels at the first and third nodes E1 and E3 remain high from the previous phase, turning off the second, fourth, eighth, and tenth emission control transistors ET2, ET4, ET8, and ET10. Due to the storage function of the first emission capacitor EC1, the fourth node E4 continues to maintain the low level from the previous phase, turning on the fifth and sixth emission control transistors ET5 and ET6. In addition, the low-level signal of the first clock signal terminal ECK1 is transmitted to the seventh node E7 through the conductive sixth light-emitting control transistor ET6 and the seventh light-emitting control transistor ET7, and the conductive ninth light-emitting control transistor ET9 outputs the high-level signal of the first power supply terminal VGH, so the signal of the output terminal EOUT is still a high-level signal.

[0161] In the fifth phase B5, the signal at the first clock signal terminal ECK1 is high, and the signal at the third clock signal terminal ECK3 is low. The signal at the third clock signal terminal ECK3 is low, turning on the first and third emission control transistors ET1 and ET3. The signal at the first clock signal terminal ECK1 is high, and the seventh emission control transistor ET7 is turned off. The turned-on first emission control transistor ET1 transmits the low-level signal at the input terminal EIN to the first node E1, causing the voltage at the first node E1 to go low. The turned-on twelfth emission control transistor ET12 transmits the low-level signal at the first node E1 to the third node E3, causing the voltage at the third node E3 to go low. This turns on the second, fourth, eighth, and tenth emission control transistors ET2, ET4, ET8, and ET10. The conductive second emission control transistor ET2 transmits the low-level signal from the third clock signal terminal ECK3 to the second node E2, further lowering the level of the second node E2. As a result, the second node E2 and the fourth node E4 continue to maintain the low level from the previous stage, turning on the fifth emission control transistor ET5 and the sixth emission control transistor ET6. The signal from the first clock signal terminal ECK1 is high, turning off the seventh emission control transistor ET7. Furthermore, the conductive eighth emission control transistor ET8 transmits the high-level signal from the first power supply terminal VGH to the seventh node E7, turning off the ninth emission control transistor ET9. The conductive tenth emission control transistor ET10 outputs the low-level signal from the second power supply terminal VGL, causing the signal at the output terminal EOUT to become low.

[0162] The input end of the first-level light-emitting shift register is electrically connected to the light-emitting initial signal line, and the output end of the i-th level light-emitting shift register is electrically connected to the input end of the i+1-level light-emitting shift register; the first clock signal end of the i-th level light-emitting shift register is electrically connected to the first light-emitting clock signal line, the second clock signal end is electrically connected to the second light-emitting clock signal line, and the third clock signal end is electrically connected to the third light-emitting clock signal line, the first clock signal end of the i+1-level light-emitting shift register is electrically connected to the third light-emitting clock signal line, the second clock signal end is electrically connected to the second light-emitting clock signal line, and the third clock signal end is electrically connected to the first light-emitting clock signal line, the first power supply end of the i-th level light-emitting shift register is electrically connected to the high-level power supply line connected to the light-emitting drive circuit, and the second power supply end of the i-th level light-emitting shift register is electrically connected to the low-level power supply line connected to the light-emitting drive circuit.

[0163] In an exemplary embodiment, the scan signal line and the control signal line are the same signal line, and the control driving circuit includes: a plurality of cascaded control shift registers, at least one stage of the control shift register is electrically connected to the control signal line. The at least one stage of the control shift register includes: a plurality of control transistors and a plurality of control capacitors.

[0164] In an exemplary embodiment, the control shift register includes: a plurality of control transistors and a plurality of control capacitors. The circuit structure of the control shift register may be 8T2C, which is not limited in the present disclosure.

[0165] Figure 6A is an equivalent circuit diagram of a control shift register provided by an exemplary embodiment, and Figure 6B is a timing diagram of the control shift register provided by Figure 6A. As shown in Figure 6A, the control shift register includes: first to eighth control transistors GT1 to GT8, a first control capacitor GC1, and a second control capacitor GC2.

[0166] In an exemplary embodiment, the control electrode of the first control transistor GT1 is electrically connected to the first clock signal terminal CK, the first electrode of the first control transistor GT1 is electrically connected to the input terminal GIN, and the second electrode of the first control transistor GT1 is electrically connected to the first node G1; the control electrode of the second control transistor GT2 is electrically connected to the first node G1, the first electrode of the second control transistor GT2 is electrically connected to the first clock signal terminal CK, and the second electrode of the second control transistor GT2 is electrically connected to the second node G2; the control electrode of the third control transistor GT3 is electrically connected to the first clock signal terminal GGCK11, the first electrode of the third control transistor GT3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third control transistor GT3 is electrically connected to the second node G2; the control electrode of the fourth control transistor GT4 is electrically connected to the second node G2, the first electrode of the fourth control transistor GT4 is electrically connected to the first power supply terminal VGH, and the second electrode of the fourth control transistor GT4 is electrically connected to the output terminal GOUT; the control electrode of the fifth control transistor GT5 is electrically connected to the third node G3, the first electrode of the fifth control transistor GT5 is electrically connected to the second clock signal terminal The signal terminal GCK2 is electrically connected, and the second electrode of the fifth control transistor GT5 is electrically connected to the output terminal GOUT; the control electrode of the sixth control transistor GT6 is electrically connected to the second node G2, the first electrode of the sixth control transistor GT6 is electrically connected to the first power supply terminal VGH, and the second electrode of the sixth control transistor GT6 is electrically connected to the first electrode of the seventh control transistor GT7; the control electrode of the seventh control transistor GT7 is electrically connected to the second clock signal terminal GCK2, and the second electrode of the seventh control transistor GT7 is electrically connected to the first node G1; the control electrode of the eighth control transistor GT8 is electrically connected to the second power supply terminal VGL, the first electrode of the eighth control transistor GT8 is electrically connected to the first node G1, and the second electrode of the eighth control transistor GT8 is electrically connected to the third node G3; the first plate GC11 of the first control capacitor GC1 is electrically connected to the first power supply terminal VGH, and the second plate GC12 of the first control capacitor GC1 is electrically connected to the second node G2; the first plate GC21 of the second control capacitor GC2 is electrically connected to the output terminal GOUT, and the second plate GC22 of the second control capacitor GC2 is electrically connected to the third node G3.

[0167] In an exemplary embodiment, the first to eighth control transistors GT1 to GT8 may be P-type transistors or N-type transistors.

[0168] In an exemplary embodiment, the first power supply terminal VGH continuously provides a high-level signal, and the second power supply terminal VGL continuously provides a low-level signal.

[0169] Taking the first to eighth control transistors GT1 to GT8 as P-type transistors as an example, as shown in FIG6B , the working process of the control shift register provided by an exemplary embodiment includes the following stages:

[0170] During input phase D1, the signals at the first clock signal terminal GCK1 and the input terminal GIN are low-level signals, while the signal at the second clock signal terminal GCK2 is high-level. Since the signal at the first clock signal terminal GCK1 is low-level, the first control transistor GT1 is turned on, and the signal at the input terminal GIN is transmitted to the first node G1 via the first control transistor GT1. Since the signal at the eighth control transistor GT8 receives the low-level signal from the second power supply terminal VGL, the eighth control transistor GT8 is turned on. The level at the third node G3 controls the conduction of the fifth control transistor GT5, and the signal at the second clock signal terminal GCK2 is transmitted to the output terminal GOUT via the fifth control transistor GT5. That is, during input phase D1, the signal at the second clock signal terminal GCK2 is high-level at the output terminal GOUT. Furthermore, since the signal at the first clock signal terminal GCK1 is low-level, the third control transistor GT3 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the second node G2 via the third control transistor GT3. At this time, both the fourth control transistor GT4 and the sixth control transistor GT6 are turned on. Since the signal at the second clock signal terminal GCK2 is a high-level signal, the seventh control transistor GT7 is turned off.

[0171] During output phase D2, the signal at the first clock signal terminal GCK1 is high, the signal at the second clock signal terminal GCK2 is low, and the signal at the input terminal GIN is high. The fifth control transistor GT5 is turned on, and the signal at the second clock signal terminal GCK2 is transmitted through the fifth control transistor GT5 as the signal at the output terminal GOUT. During output phase D2, the voltage level at the end of the second control capacitor GC2 connected to the output terminal OUT changes to the voltage level at the second power supply terminal VGL. Due to the bootstrap effect of the second control capacitor GC2, the eighth control transistor GT8 is turned off, allowing the fifth control transistor GT5 to turn on more effectively, and the signal at the output terminal GOUT becomes low. Furthermore, the signal at the first clock signal terminal GCK1 is high, turning off both the first control transistor GT1 and the third control transistor GT3. The second control transistor GT2 is turned on, and the high-level signal at the first clock signal terminal GCK1 is transmitted to the second node G2 via the second control transistor GT2. Consequently, the fourth control transistor GT4 and the sixth control transistor GT6 are both turned off. Because the signal at the second clock signal terminal GCK2 is low, the seventh control transistor GT7 is turned on.

[0172] During the buffering phase D3, the signals at both the first clock signal terminal GCK1 and the second clock signal terminal GCK2 are high-level signals. The signal at the input terminal GIN is high-level, the fifth control transistor GT5 is turned on, and the second clock signal terminal GCK2 outputs the signal GOUT via the fifth control transistor GT5. Due to the bootstrap effect of the second control capacitor C2, the level of the first node G1 becomes VGL-VthN1. Furthermore, the signal at the first clock signal terminal GCK1 is high-level, causing the first control transistor GT1 and the third control transistor GT3 to be turned off. The eighth control transistor GT8 is turned on, and the second control transistor GT2 is turned on. The high-level signal at the first clock signal terminal GCK1 is transmitted to the second node G2 via the second control transistor GT2. Consequently, the fourth control transistor GT4 and the sixth control transistor GT6 are both turned off. Because the signal at the second clock signal terminal GCK2 is high-level, the seventh control transistor GT7 is turned off.

[0173] In the first sub-phase D41 of the stable phase D4, the signal at the first clock signal terminal GCK1 is a low-level signal, while the signals at the second clock signal terminal GCK2 and the input terminal GIN are high-level signals. Because the signal at the first clock signal terminal GCK1 is a low-level signal, the first control transistor GT1 is turned on, and the signal at the input terminal GIN is transmitted to the first node G1 via the first control transistor GT1. The second control transistor GT2 is turned off. Because the eighth control transistor GT8 is turned on, the fifth control transistor GT5 is turned off. Because the signal at the first clock signal terminal GCK1 is a low-level signal, the third control transistor GT3 is turned on, and the fourth and sixth control transistors GT4 and GT6 are both turned on. The high-level signal at the first power supply terminal VGH is transmitted to the output terminal GOUT via the fourth control transistor GT4, resulting in a high-level signal at the output terminal GOUT.

[0174] In the second sub-phase t42 of the stable phase t4, the signal at the first clock signal terminal GCK1 is a high-level signal, the signal at the second clock signal terminal GCK2 is a low-level signal, and the signal at the input terminal GIN is a high-level signal. The fifth control transistor GT5 and the second control transistor GT2 are both turned off. The signal at the first clock signal terminal GCK1 is a high-level signal, so the first control transistor GT1 and the third control transistor GT3 are both turned off. Due to the holding effect of the first control capacitor GC1, the fourth control transistor GT4 and the sixth control transistor GT6 are both turned on, and the high-level signal is transmitted to the output terminal GOUT via the fourth control transistor GT4. That is, the signal at the output terminal GOUT is a high-level signal.

[0175] In the second sub-phase t42, since the signal at the second clock signal terminal GCK2 is a low-level signal, the seventh control transistor GT7 is turned on, so that the high-level signal is transmitted to the third node G3 and the first node G1 via the sixth control transistor GT6 and the seventh control transistor GT7, so that the signals at the third node G3 and the first node G1 remain high-level signals.

[0176] In the third sub-phase t43, the signals at the first clock signal terminal GCK1 and the second clock signal terminal GCK2 are both high-level signals, and the signal at the input terminal GIN is also high-level. The fifth control transistor GT5 and the second control transistor GT2 are turned off. The signal at the first clock signal terminal GCK1 is high-level, so the first control transistor GT1 and the third control transistor GT3 are both turned off, and the fourth control transistor GT4 and the sixth control transistor GT6 are both turned on. The high-level signal is transmitted to the output terminal GOUT via the fourth control transistor GT4, that is, the signal at the output terminal GOUT is also high-level.

[0177] The input end of the first-stage control shift register is electrically connected to the control initial signal line, and the output end of the i-th stage control shift register is electrically connected to the input end of the i+1-th stage control shift register; the first clock signal end of the i-th stage control shift register is electrically connected to the first control clock signal line, and the second clock signal end is electrically connected to the second control clock signal line, the first clock signal end of the i+1-th stage control shift register is electrically connected to the second control clock signal line, and the second clock signal end is electrically connected to the first control clock signal line, the first power supply end of the i-th stage control shift register is electrically connected to the high-level power supply line connected to the control drive circuit, and the second power supply end of the i-th stage control shift register is electrically connected to the low-level power supply line connected to the control drive circuit.

[0178] In an exemplary embodiment, Figures 7A to 7F are partial schematic diagrams of a display substrate including three drive circuits, provided in an exemplary embodiment. As shown in Figures 7A to 7F, when the display substrate is an LTPO display substrate, the multiple transistors include: a write transistor, a first reset transistor, a compensation transistor, and a light-emitting transistor. The transistor types of the first reset transistor and the compensation transistor are different from those of the write transistor and the light-emitting transistor. The first reset signal terminal and the second reset signal terminal are the same signal terminal, and the control signal terminal and the scan signal terminal are different signal terminals. The multiple drive circuits include: a light-emitting drive circuit EM GOA, a scan drive circuit GateN GOA, and a control drive circuit GateP GOA. The light-emitting drive circuit EM GOA is configured to provide a drive signal to the light-emitting transistor, the control drive circuit GateP GOA is configured to provide a drive signal to the write transistor, and the scan drive circuit GateN GOA is configured to provide a drive signal to the first reset transistor and / or the compensation transistor.

[0179] In an exemplary embodiment, the write transistor and the light emission control transistor may be P-type transistors.

[0180] In an exemplary embodiment, the first reset transistor and the compensation transistor may be N-type metal oxide transistors.

[0181] In an exemplary embodiment, the high-level power line connected to at least two adjacent driving circuits among the light-emitting driving circuit EM GOA, the scan driving circuit GateN GOA, and the control driving circuit GateP GOA is the same power line, and / or the low-level power line connected to at least two adjacent driving circuits among the light-emitting driving circuit EM GOA, the scan driving circuit GateN GOA, and the control driving circuit GateP GOA is the same power line. When the high-level power line connected to at least two adjacent driving circuits among the light-emitting driving circuit EM GOA, the scan driving circuit GateN GOA, and the control driving circuit GateP GOA is the same power line, and the low-level power line connected to at least two adjacent driving circuits among the light-emitting driving circuit EM GOA, the scan driving circuit GateN GOA, and the control driving circuit GateP GOA is the same power line, the driving circuit connected to the same low-level power line may be the same driving circuit as the driving circuit connected to the same high-level power line, or may be a different driving circuit.

[0182] In an exemplary embodiment, the power line may be a high-level power line and / or a low-level power line, and the two driving circuits connected to the power line connected to the two driving circuits may be a light-emitting driving circuit EM GOA and a scanning driving circuit GateN GOA, or a scanning driving circuit GateN GOA and a control driving circuit GateP GOA.

[0183] FIG7A is an example in which the low-level power line SVGL connected to the scan driving circuit GateN GOA and the low-level power line GVGL connected to the control driving circuit GateP GOA are the same power line. FIG7B is an example in which the high-level power line SVGH connected to the scan driving circuit GateN GOA and the low-level power line GVGH connected to the control driving circuit GateP GOA are the same power line. FIG7C is an example in which the low-level power line SVGL connected to the scan driving circuit GateN GOA and the low-level power line GVGL connected to the control driving circuit GateP GOA are the same power line, and the high-level power line SVGH connected to the scan driving circuit GateN GOA and the low-level power line GVGH connected to the control driving circuit GateP GOA are the same power line. FIG7D is an example in which the low-level power line EVGL connected to the light emitting driving circuit EM GOA, the low-level power line SVGL connected to the scan driving circuit GateN GOA and the control driving circuit GateP GOA are the same power line. The low-level power line GVGL connected to GOA is the same power line as an example for explanation, Figure 7E is explained by taking the low-level power line EVGH connected to the light-emitting drive circuit EM GOA, the high-level power line SVGH connected to the scan drive circuit GateN GOA, and the low-level power line GVGH connected to the control drive circuit GateP GOA as the same power line as an example, and Figure 7F is explained by taking the low-level power line EVGL connected to the light-emitting drive circuit EM GOA, the low-level power line SVGL connected to the scan drive circuit GateN GOA, and the low-level power line GVGL connected to the control drive circuit GateP GOA as the same power line, and the low-level power line EVGH connected to the light-emitting drive circuit EM GOA, the high-level power line SVGH connected to the scan drive circuit GateN GOA, and the low-level power line GVGH connected to the control drive circuit GateP GOA as the same power line.

[0184] In an exemplary embodiment, when the high-level power line connected to two adjacent driving circuits among the light-emitting driving circuit EM GOA, the scanning driving circuit GateN GOA, and the control driving circuit GateP GOA is the same power line, the orthographic projection of the high-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the high-level power line on the substrate, or is located between the two adjacent driving circuits connected; or, when the high-level power line connected to the light-emitting driving circuit EM GOA, the scanning driving circuit GateN GOA, and the control driving circuit GateP GOA is the same power line, the orthographic projection of the high-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the high-level power line on the substrate, or is located between the two adjacent driving circuits.

[0185] In an exemplary embodiment, when the low-level power line connected to two adjacent driving circuits among the light-emitting driving circuit EM GOA, the scanning driving circuit GateN GOA, and the control driving circuit GateP GOA is the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power line on the substrate, or is located between the two adjacent driving circuits connected; or, when the low-level power line connected to the light-emitting driving circuit EM GOA, the scanning driving circuit GateN GOA, and the control driving circuit GateP GOA is the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power line on the substrate, or is located between the two adjacent driving circuits.

[0186] In one exemplary embodiment, the positional relationship between the control driving circuit, the scan driving circuit, and the light emitting control circuit can be determined based on the structure and function of the display substrate. The light emitting driving circuit EM GOA can be located on a side of the scan driving circuit GateN GOA that is away from the display area, and the control driving circuit GateP GOA can be located on a side of the scan driving circuit GateN GOA that is closer to the display area.

[0187] In one exemplary embodiment, the circuit structure layer further includes: a light-emitting start signal line ESTV, multiple light-emitting clock signal lines, a control start signal line GSTV, multiple control clock signal lines, a scan start signal line SSTV, and multiple scan clock signal lines, located in the non-display area and extending along a first direction; a light-emitting drive circuit EM GOA electrically connected to the light-emitting start signal line and the multiple light-emitting clock signal lines, a control drive circuit GateP GOA electrically connected to the control start signal line GSTV and the multiple control clock signal lines, and a scan drive circuit GateN GOA electrically connected to the scan start signal line SSTV and the multiple scan clock signal lines. Figures 7A to 7F illustrate three light-emitting clock signal lines ECLK1 to ECLK3, three scan clock signal lines SCLK1 to SCLK3, and two control clock signal lines GCLK1 and GCLK2 as examples.

[0188] In an exemplary embodiment, as shown in Figures 7A to 7F , the light-initiating signal line and multiple light-emitting clock signal lines are located on a side of the scanning initial signal line and multiple scanning clock signal lines that is away from the display area, and the light-initiating signal line is located on a side of the multiple light-emitting clock signal lines that is close to the display area or on a side away from the display area. Figures 7A to 7F illustrate the light-initiating signal line located on a side of the multiple light-emitting clock signal lines that is away from the display area.

[0189] In an exemplary embodiment, as shown in Figures 7A to 7F , the control initial signal line and the multiple control clock signal lines are located on the side of the scan initial signal line and the multiple scan clock signal lines that is closer to the display area, and the control initial signal line is located on the side of the multiple control clock signal lines that is closer to the display area or farther away from the display area. Figures 7A to 7F illustrate the case where the control initial signal line is located on the side of the multiple control clock signal lines that is farther away from the display area.

[0190] In an exemplary embodiment, as shown in Figures 7A to 7F, the scan initialization signal line is located on a side of the multiple scan clock signal lines that is close to the display area, or on a side that is away from the display area. Figures 7A to 7F illustrate the case where the scan initialization signal line is located on a side of the multiple scan clock signal lines that is close to the display area.

[0191] In one exemplary embodiment, the scan drive circuit may include multiple cascaded scan shift registers, with at least one stage of the scan shift registers electrically connected to at least one reset signal line. In another exemplary embodiment, the scan shift register may include multiple scan transistors and multiple scan capacitors. The circuit structure of the scan shift register may be 13T3C or 10T3C, which is not limited in this disclosure.

[0192] Figure 8A is an equivalent circuit diagram of a scan shift register according to an exemplary embodiment, and Figure 8B is a timing diagram of the scan shift register according to Figure 8A. As shown in Figure 8A, in an exemplary embodiment, the scan shift register includes: first to thirteenth scan transistors ST1 to ST13 and first to third scan capacitors SC1 to SC3.

[0193] In one exemplary embodiment, the control electrode of the first scan transistor ST1 is electrically connected to the third clock signal terminal SCK3, the first electrode of the first scan transistor ST1 is electrically connected to the input terminal SIN, and the second electrode of the first scan transistor ST1 is electrically connected to the first node S1. The control electrode of the second scan transistor ST2 is electrically connected to the first node S1, the first electrode of the second scan transistor ST2 is electrically connected to the third clock signal terminal SCK3, and the second electrode of the second scan transistor ST2 is electrically connected to the second node S2. The control electrode of the third scan transistor ST3 is electrically connected to the third clock signal terminal SCK3, the first electrode of the third scan transistor ST3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third scan transistor ST3 is electrically connected to the second node S2. The control electrode of the fourth scan transistor ST4 is electrically connected to the third node S3, the first electrode of the fourth scan transistor ST4 is electrically connected to the first clock signal terminal SCK1, and the second electrode of the fourth scan transistor ST4 is electrically connected to the fifth node S5. The control electrode of the fifth scan transistor ST5 is electrically connected to the fourth node S4, the first electrode of the fifth scan transistor ST5 is electrically connected to the fifth node S5, and the second electrode of the fifth scan transistor ST5 is electrically connected to the first power supply terminal VGH. The control electrode of the sixth scanning transistor ST6 is electrically connected to the fourth node S4, the first electrode of the sixth scanning transistor ST6 is electrically connected to the first clock signal terminal SCK1, and the second electrode of the sixth scanning transistor ST6 is electrically connected to the sixth node S6. The control electrode of the seventh scanning transistor ST7 is electrically connected to the first clock signal terminal SCK1, the first electrode of the seventh scanning transistor ST7 is electrically connected to the sixth node S6, and the second electrode of the seventh scanning transistor ST7 is electrically connected to the seventh node S7. The control electrode of the eighth scanning transistor ST8 is electrically connected to the first node S1, the first electrode of the eighth scanning transistor ST8 is electrically connected to the first power supply terminal VGH, and the second electrode of the eighth scanning transistor ST8 is electrically connected to the seventh node S7. The control electrode of the ninth scanning transistor ST9 is electrically connected to the seventh node S7, the first electrode of the ninth scanning transistor ST9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth scanning transistor ST9 is electrically connected to the output terminal SOUT. The control electrode of the tenth scanning transistor ST10 is electrically connected to the third node S3, the first electrode of the tenth scanning transistor ST10 is electrically connected to the second power supply terminal VGL, and the second electrode of the tenth scanning transistor ST10 is electrically connected to the output terminal SOUT. A control electrode of the eleventh scanning transistor ST11 is electrically connected to the second power supply terminal VGL, a first electrode of the eleventh scanning transistor ST11 is electrically connected to the second node S2, and a second electrode of the eleventh scanning transistor ST11 is electrically connected to the fourth node S4. A control electrode of the twelfth scanning transistor ST12 is electrically connected to the second power supply terminal VGL, a first electrode of the twelfth scanning transistor ST12 is electrically connected to the first node S1, and a second electrode of the twelfth scanning transistor ST12 is electrically connected to the third node S3.A control electrode of the thirteenth scan transistor ST13 is electrically connected to the second clock signal terminal SCK2, a first electrode of the thirteenth scan transistor ST13 is electrically connected to the first node S1, and a second electrode of the thirteenth scan transistor ST13 is electrically connected to the first power supply terminal VGH. A first plate SC11 of the first scan capacitor SC1 is electrically connected to the fourth node S4, and a second plate SC12 of the first scan capacitor SC1 is electrically connected to the sixth node S6. A first plate SC21 of the second scan capacitor SC2 is electrically connected to the seventh node S7, and a second plate SC22 of the second scan capacitor SC2 is electrically connected to the first power supply terminal VGH. A first plate SC31 of the third scan capacitor SC3 is electrically connected to the third node S3, and a second plate SC32 of the third scan capacitor SC3 is electrically connected to the fifth node S5.

[0194] In an exemplary embodiment, the first to thirteenth scanning transistors ST1 to ST13 may be P-type transistors or N-type transistors. The tenth scanning transistor ST10 is an output transistor.

[0195] In an exemplary embodiment, the first power supply terminal VGH continuously provides a high level signal, and the second power supply terminal VGL continuously provides a low level signal. Since the second power supply terminal VGL continuously provides a low level signal, the eleventh scanning transistor ST11 and the twelfth scanning transistor ST12 are continuously turned on.

[0196] In an exemplary embodiment, the second clock signal terminal SCK2 is a low-level signal during the power-on initialization phase to prevent the ninth scanning transistor ST9 and the tenth scanning transistor ST10 of the last-stage scanning shift register from being simultaneously turned on due to a delay in the output signal. Alternatively, the second clock signal terminal SCK2 is a low-level signal during the abnormal shutdown phase to prevent the ninth scanning transistor ST9 and the tenth scanning transistor ST10 from being simultaneously turned on. The second clock signal terminal SCK2 continuously provides a high-level signal during the normal display phase, i.e., during the normal display phase, the thirteenth scanning transistor ST13 is continuously turned off.

[0197] Taking the first scanning transistor ST1 to the thirteenth scanning transistor ST13 as P-type transistors as an example, as shown in FIG8B , the operation process of the scanning shift register provided by an exemplary embodiment includes the following stages:

[0198] In the first phase C1, the signal at the first clock signal terminal SCK1 is a high-level signal, and the signal at the third clock signal terminal SCK3 is a low-level signal. The signal at the third clock signal terminal SCK3 is a low-level signal. The first scanning transistor ST1, the third scanning transistor ST3, and the twelfth scanning transistor ST12 are turned on. The turned-on first scanning transistor ST1 transmits the high-level signal at the input terminal SIN to the first node S1, thereby changing the level of the first node S1 to a high-level signal. The turned-on twelfth scanning transistor ST12 transmits the high-level signal at the first node S1 to the third node S2. The second scanning transistor ST2, the fourth scanning transistor ST4, the eighth scanning transistor ST8, and the tenth scanning transistor ST10 are turned off. In addition, the turned-on third scanning transistor ST3 transmits the low-level signal at the second power supply terminal VGL to the second node S2, thereby changing the level of the second node S2 to a low level. The turned-on eleventh scanning transistor ST11 transmits the low-level signal at the second node S2 to the fourth node S4, thereby changing the level of the fourth node S4 to a low level. The fifth scanning transistor ST5 and the sixth scanning transistor ST6 are turned on. The signal on the first clock signal line SCK1 is high, turning off the seventh scanning transistor ST7. Furthermore, the third scanning capacitor SC3 turns off the ninth scanning transistor ST9. During the first phase P1, since both the ninth scanning transistor ST9 and the tenth scanning transistor ST10 are turned off, the signal at the output terminal SOUT remains at the previous low level.

[0199] In the second phase C2, the signal at the first clock signal terminal SCK1 is a low-level signal, and the signal at the third clock signal terminal SCK3 is a high-level signal. The signal at the first clock signal terminal SCK1 is a low-level signal, turning on the seventh scanning transistor ST7. The signal at the third clock signal terminal SCK3 is a high-level signal, turning off the first scanning transistor ST1 and the third scanning transistor ST3. Under the action of the third scanning capacitor SC3, the first node S1 and the third node S3 can continue to maintain the high-level signals from the previous phase. Under the action of the first scanning capacitor SC1, the fourth node S4 can continue to maintain the low-level signal from the previous phase, turning on the fifth scanning transistor ST5 and the sixth scanning transistor ST6. The second scanning transistor ST2, the fourth scanning transistor ST4, the eighth scanning transistor ST8, and the tenth scanning transistor ST10 are turned off. In addition, the low-level signal of the first clock signal terminal SCK1 is transmitted to the seventh node S7 through the turned-on sixth scanning transistor ST6 and the seventh scanning transistor ST7, and the ninth scanning transistor ST9 is turned on. The turned-on ninth scanning transistor ST9 outputs the high-level signal of the first power supply terminal VGH, so the signal of the output terminal SOUT is a high-level signal.

[0200] In the third phase C3, the signal at the third clock signal terminal SCK3 is a low-level signal, and the signal at the first clock signal terminal SCK1 is a high-level signal. The signal at the first clock signal terminal SCK1 is a high-level signal, and the seventh scanning transistor ST7 is turned off. The second scanning transistor ST2, the fourth scanning transistor ST2, the eighth scanning transistor ST8, and the tenth scanning transistor ST10 are turned off. The signal at the third clock signal terminal SCK3 is a low-level signal, and the first scanning transistor ST1 and the third scanning transistor ST3 are turned on. Under the action of the third scanning capacitor SC3, the ninth scanning transistor ST9 remains in the on state. The turned-on ninth scanning transistor ST9 outputs the high-level signal from the first power supply terminal VGH, so the signal at the output terminal SOUT remains a high-level signal.

[0201] In the fourth phase C4, the signal at the first clock signal terminal SCK1 is low, and the signal at the third clock signal terminal SCK3 is high. The signal at the third clock signal terminal SCK3 is high, turning off the first and third scan transistors ST1 and ST3. The signal at the first clock signal terminal SCK1 is low, turning on the seventh scan transistor ST7. Due to the storage function of the third scan capacitor SC3, the levels at the first and third nodes S1 and S3 remain high from the previous phase, turning off the scan transistors ST2, ST4, ST8, and ST10. Due to the storage function of the first scan capacitor SC1, the fourth node S4 continues to maintain the low level from the previous phase, turning on the fifth and sixth scan transistors ST5 and ST6. Furthermore, the low level signal at the first clock signal terminal SCK1 is transmitted to the seventh node S7 via the turned-on sixth and seventh scan transistors ST6 and ST7. The turned-on ninth scan transistor ST9 outputs the high level signal from the first power supply terminal VGH, so the signal at the output terminal SOUT remains high.

[0202] In the fifth phase C5, the signal at the first clock signal terminal SCK1 is a high-level signal, and the signal at the third clock signal terminal SCK3 is a low-level signal. The signal at the third clock signal terminal SCK3 is a low-level signal, turning on the first scan transistor ST1 and the third scan transistor ST3. The signal at the first clock signal terminal SCK1 is a high-level signal, and the seventh scan transistor ST7 is turned off. The turned-on first scan transistor ST1 transmits the low-level signal at the input terminal SIN to the first node S1, thereby changing the level of the first node S1 to a low level. The turned-on twelfth scan transistor ST12 transmits the low-level signal at the first node S1 to the third node S3, thereby changing the level of the third node S3 to a low level. The second scan transistor ST2, the fourth scan transistor ST4, the eighth scan transistor ST8, and the tenth scan transistor ST10 are turned on. The turned-on second scan transistor ST2 transmits the low-level signal of the third clock signal terminal SCK3 to the second node S2, thereby further lowering the level of the second node S2. As a result, the second node S2 and the fourth node S4 continue to maintain the low level from the previous stage, thereby turning on the fifth scan transistor ST5 and the sixth scan transistor ST6. The signal of the first clock signal terminal SCK1 is a high-level signal, and the seventh scan transistor ST7 is turned off. In addition, the turned-on eighth scan transistor ST8 transmits the high-level signal of the first power supply terminal VGH to the seventh node S7, and the ninth scan transistor ST9 is turned off. The turned-on tenth scan transistor ST10 outputs the low-level signal of the second power supply terminal VGL, so the signal of the output terminal SOUT becomes low.

[0203] In an exemplary embodiment, the input end of the first-level scanning shift register is electrically connected to the scanning initial signal line, the output end of the i-th level scanning shift register is electrically connected to the input end of the i+1-th level scanning shift register, the first clock signal end of the i-th level scanning shift register is electrically connected to the first scanning clock signal line, the second clock signal end is electrically connected to the second scanning clock signal line, and the third clock signal end is electrically connected to the third scanning clock signal line, the first clock signal end of the i+1-th level scanning shift register is electrically connected to the third scanning clock signal line, the second clock signal end is electrically connected to the second scanning clock signal line, and the third clock signal end is electrically connected to the first scanning clock signal line, the first power supply end of the i-th level scanning shift register is electrically connected to the high-level power supply line connected to the scanning driving circuit, and the second power supply end of the i-th level scanning shift register is electrically connected to the low-level power supply line connected to the scanning driving circuit.

[0204] In an exemplary embodiment, the first conductive layer may include: gate electrodes of multiple light-emitting transistors, gate electrodes of multiple scanning transistors, gate electrodes of multiple control transistors, first plates of multiple light-emitting capacitors, first electrodes of multiple scanning capacitors and first plates of multiple control capacitors.

[0205] In an exemplary embodiment, the second conductive layer may include: second plates of a plurality of light emitting capacitors, second plates of a plurality of scanning capacitors, and second plates of a plurality of control capacitors;

[0206] In an exemplary embodiment, the third conductive layer may include: source-drain electrodes of a plurality of light emitting transistors, source-drain electrodes of a plurality of scanning transistors, and source-drain electrodes of a plurality of control transistors;

[0207] In an exemplary embodiment, the fourth conductive layer may include a light emitting initial signal line, at least one light emitting clock signal line, a scanning initial signal line, at least one scanning clock signal line, a control initial signal line, and at least one control clock signal line.

[0208] In an exemplary embodiment, Figures 9A to 9I are partial schematic diagrams of a display substrate including four drive circuits, provided in an exemplary embodiment. As shown in Figures 9A to 9I , when the display substrate is an LTPO display substrate, and as shown in Figures 9A to 9I , when the display substrate is an LTPS display substrate, the first reset signal terminal and the second reset signal terminal are different signal terminals, and the control signal terminal and the scan signal terminal are the same signal terminal. The multiple drive circuits include: an emission drive circuit EM GOA, a first reset drive circuit RST1GOA, a second reset drive circuit RST2GOA, and a control drive circuit GateP GOA. The emission drive circuit EM GOA is configured to provide a drive signal to the emission transistor, the control drive circuit GateP GOA is configured to provide a drive signal to the write transistor and / or the compensation transistor, the first reset drive circuit RST1GOA is configured to provide a drive signal to the first reset transistor, and the second reset drive circuit RST2GOA is configured to provide a drive signal to the second reset transistor.

[0209] In an exemplary embodiment, the high-level power line connected to at least two adjacent driving circuits among the light-emitting driving circuit EM GOA, the first reset driving circuit RST1GOA, the second reset driving circuit RST2GOA, and the control driving circuit GateP GOA is the same power line, and / or the low-level power line connected to at least two adjacent driving circuits among the light-emitting driving circuit EM GOA, the first reset driving circuit RST1GOA, the second reset driving circuit RST2GOA, and the control driving circuit GateP GOA is the same power line. When the high-level power line connected to at least two adjacent driving circuits among the light-emitting driving circuit EM GOA, the first reset driving circuit RST1GOA, the second reset driving circuit RST2GOA, and the control driving circuit GateP GOA is the same power line, and the low-level power line connected to at least two adjacent driving circuits among the light-emitting driving circuit EM GOA, the first reset driving circuit RST1GOA, the second reset driving circuit RST2GOA, and the control driving circuit GateP GOA is the same power line, the driving circuit connected to the same low-level power line may be the same driving circuit as the driving circuit connected to the same high-level power line, or may be a different driving circuit.

[0210] In an exemplary embodiment, the power line may be a high-level power line and / or a low-level power line. The two driving circuits connected to the power line connected to the two driving circuits may be a light-emitting driving circuit EM GOA and a first reset driving circuit RST1GOA, or the first reset driving circuit RST1GOA and a control driving circuit GateP GOA, or the control driving circuit GateP GOA and the second reset driving circuit RST2GOA. The three driving circuits connected to the power line connected to the three driving circuits may be a light-emitting driving circuit EM GOA, a first reset driving circuit RST1GOA, and a control driving circuit GateP GOA, or the first reset driving circuit RST1GOA, the control driving circuit GateP GOA, and the second reset driving circuit RST2GOA.

[0211] FIG9A is an example in which the low-level power line EVGL connected to the light-emitting drive circuit EM GOA and the low-level power line RVGL connected to the first reset drive circuit RST1GOA are the same power line. FIG9B is an example in which the high-level power line EVGH connected to the light-emitting drive circuit EM GOA and the high-level power line RVGH connected to the first reset drive circuit RST1GOA are the same power line. FIG9C is an example in which the low-level power line EVGL connected to the light-emitting drive circuit EM GOA and the low-level power line RVGL connected to the first reset drive circuit RST1GOA are the same power line, and the high-level power line EVGH connected to the light-emitting drive circuit EM GOA and the high-level power line RVGH connected to the first reset drive circuit RST1GOA are the same power line. FIG9D is an example in which the low-level power line EVGL connected to the light-emitting drive circuit EM GOA, the low-level power line RVGL1 connected to the first reset drive circuit RST1GOA, and the low-level power line GVGL connected to the control drive circuit GateP GOA are the same power line. FIG9E is an example in which the light-emitting drive circuit EM The high-level power line EVGL connected to GOA, the high-level power line RVGH1 connected to the first reset drive circuit RST1GOA, and the high-level power line GVGH connected to the control drive circuit GateP GOA are the same power line for explanation, and FIG9F is explained by taking the low-level power line EVGL connected to the light-emitting drive circuit EM GOA, the low-level power line RVGL1 connected to the first reset drive circuit RST1GOA, and the low-level power line GVGL connected to the control drive circuit GateP GOA as the same power line, and the high-level power line EVGL connected to the light-emitting drive circuit EM GOA, the high-level power line RVGH1 connected to the first reset drive circuit RST1GOA, and the high-level power line GVGH connected to the control drive circuit GateP GOA as the same power line for explanation, and FIG9G is explained by taking the low-level power line EVGL connected to the light-emitting drive circuit EM GOA, the low-level power line RVGL1 connected to the first reset drive circuit RST1GOA, and the low-level power line GVGH connected to the control drive circuit GateP GOA as the same power line. The low-level power line GVGL connected to GOA and the low-level power line RVGL2 connected to the second reset drive circuit RST2GOA are described as an example. FIG9H illustrates an example in which the high-level power line EVGL connected to the light-emitting drive circuit EM GOA, the high-level power line RVGH1 connected to the first reset drive circuit RST1GOA, the high-level power line GVGH connected to the control drive circuit GateP GOA, and the high-level power line RVGH2 connected to the second reset drive circuit RST2GOA are described as an example.FIG9I illustrates an example in which the low-level power line EVGL connected to the light-emitting drive circuit EM GOA, the low-level power line RVGL1 connected to the first reset drive circuit RST1GOA, the low-level power line GVGL connected to the control drive circuit GateP GOA, and the low-level power line RVGL2 connected to the second reset drive circuit RST2GOA are the same power line, and the high-level power line EVGL connected to the light-emitting drive circuit EM GOA, the high-level power line RVGH1 connected to the first reset drive circuit RST1GOA, the high-level power line GVGH connected to the control drive circuit GateP GOA, and the high-level power line RVGH2 connected to the second reset drive circuit RST2GOA are the same power line.

[0212] In an exemplary embodiment, when the high-level power line connected to two adjacent driving circuits among the light-emitting driving circuit EM GOA, the first reset driving circuit RST1GOA, the second reset driving circuit RST2GOA, and the control driving circuit GateP GOA is the same power line, the orthographic projection of the high-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the high-level power line on the substrate, or is located between the two adjacent driving circuits connected; or, when the high-level power line connected to at least three adjacent driving circuits among the light-emitting driving circuit EM GOA, the first reset driving circuit RST1GOA, the second reset driving circuit RST2GOA, and the control driving circuit GateP GOA is the same power line, the orthographic projection of the high-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the high-level power line on the substrate, or is located between the two adjacent driving circuits.

[0213] In an exemplary embodiment, when the low-level power line connected to two adjacent driving circuits among the light-emitting driving circuit EM GOA, the first reset driving circuit RST1GOA, the second reset driving circuit RST2GOA, and the control driving circuit GateP GOA is the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power line on the substrate, or is located between the two adjacent driving circuits connected; or, when the low-level power line connected to at least three adjacent driving circuits among the light-emitting driving circuit EM GOA, the first reset driving circuit RST1GOA, the second reset driving circuit RST2GOA, and the control driving circuit GateP GOA is the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power line on the substrate, or is located between the two adjacent driving circuits.

[0214] In an exemplary embodiment, the light emitting driving circuit EM GOA is located on a side of the control driving circuit GateP GOA away from the display area, the first reset driving circuit RST1GOA is located between the light emitting driving circuit and the control driving circuit GateP GOA, and the second reset driving circuit RST2GOA is located on a side of the control driving circuit GateP GOA close to the display area.

[0215] In an exemplary embodiment, as shown in Figures 9A to 9I , the circuit structure layer further includes: a light-emission initial signal line ESTV, multiple light-emission clock signal lines, a control initial signal line GSTV, multiple control clock signal lines, a first reset initial signal line RSTV1, multiple first reset clock signal lines, a second reset initial signal line RSTV2, and multiple second reset clock signal lines, located in the non-display area and extending along a first direction. A light-emission driver circuit EM GOA is electrically connected to the light-emission initial signal line ESTV and the multiple light-emission clock signal lines, respectively; a control driver circuit GateP GOA is electrically connected to the control initial signal line GSTV and the multiple control clock signal lines, respectively; a first reset driver circuit RST1GOA is electrically connected to the first reset initial signal line RSTV1 and the multiple first reset clock signal lines, respectively; and a second reset driver circuit RST2GOA is electrically connected to the second reset initial signal line RSTV2 and the multiple second reset clock signal lines, respectively. 9A to 9I are described by taking three emission clock signal lines ECLK1 to ECLK3 , two control clock signal lines GCLK1 and GCLK2 , two first reset clock signal lines RCLK1 and RCLK2 , and two second reset clock signal lines RCLK3 and RCLK4 as examples.

[0216] In an exemplary embodiment, as shown in Figures 9A to 9I , the light-emission initialization signal line and multiple light-emission clock signal lines are located on a side of the first reset initialization signal line and multiple first reset clock signal lines that is away from the display area, and the light-emission initialization signal line is located on a side of the multiple light-emission clock signal lines that is close to the display area or on a side that is away from the display area. Figures 9A to 9I illustrate this by taking the example of the light-emission initialization signal line being located on a side of the multiple light-emission clock signal lines that is away from the display area.

[0217] In an exemplary embodiment, as shown in Figures 9A to 9I , the first reset initial signal line and the plurality of first reset clock signal lines are located on a side of the control initial signal line and the plurality of control clock signal lines that is closer to the display area, and the first reset initial signal line is located on a side of the plurality of first reset clock signal lines that is closer to the display area or on a side that is farther from the display area. Figures 9A to 9I illustrate the case where the first reset initial signal line is located on a side of the plurality of first reset clock signal lines that is farther from the display area.

[0218] In an exemplary embodiment, as shown in Figures 9A to 9I , the control initial signal line and the control clock signal line are located on a side of the second reset initial signal line and the plurality of second reset clock signal lines that is away from the display area, and the control initial signal line is located on a side of the plurality of control clock signal lines that is close to the display area or on a side away from the display area. Figures 9A to 9I illustrate the case where the control initial signal line is located on a side of the plurality of control clock signal lines that is away from the display area.

[0219] In an exemplary embodiment, as shown in Figures 9A to 9I , the second reset initial signal line is located on a side of the plurality of second reset clock signal lines that is closer to the display area or farther from the display area. Figures 9A to 9I illustrate the case where the second reset initial signal line is located on a side of the plurality of second reset clock signal lines that is farther from the display area.

[0220] In an exemplary embodiment, the arrangement of the signal lines connected to the multiple driving circuits may be determined according to the structure and function of the display substrate, and the present disclosure does not impose any limitation on this.

[0221] In an exemplary embodiment, the first reset driving circuit includes: a plurality of cascaded first reset shift registers, at least one stage of the first reset shift register is electrically connected to the control signal line, and at least one stage of the first reset shift register includes: a plurality of first reset transistors and a plurality of first reset capacitors.

[0222] In one exemplary embodiment, the first reset shift register includes: a plurality of first reset transistors and a plurality of first reset capacitors. The circuit structure of the first reset shift register may be 8T2C, which is not limited in this disclosure. The circuit structure of the first reset shift register may be the same as that of the control shift register, and is not further described in this disclosure.

[0223] The connection method between multiple cascaded first reset shift registers and the first reset initial signal line and two first reset clock signal lines is the same as the connection method between multiple cascaded control shift registers and the control initial signal line and two control clock signal lines, which will not be repeated in this disclosure.

[0224] In one exemplary embodiment, the second reset shift register includes: a plurality of second reset transistors and a plurality of second reset capacitors. The circuit structure of the second reset shift register may be 8T2C, which is not limited in this disclosure. The circuit structure of the second reset shift register may be the same as that of the control shift register, and this disclosure will not further elaborate on this.

[0225] The connection method between multiple cascaded second reset shift registers and the second reset initial signal line and two second reset clock signal lines is the same as the connection method between multiple cascaded control shift registers and the control initial signal line and two control clock signal lines, which will not be repeated in this disclosure.

[0226] In an exemplary embodiment, the boundary of the display area AA includes at least one arc-shaped boundary. In an exemplary embodiment, the shape of the boundary of the display area can be a rounded rectangle.

[0227] The display substrate provided by the present disclosure can achieve large-angle bending function on all four sides, improve the module fitting wrinkle problem, and improve product yield.

[0228] In an exemplary embodiment, the display substrate may further include other film layers, such as spacers and columns, etc., which is not limited in the present disclosure.

[0229] The "patterning process" referred to in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal, inorganic, or transparent conductive materials. For organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be achieved by any one or more of spraying, spin coating, and inkjet printing; and etching can be achieved by any one or more of dry etching and wet etching, all of which are not limited in this disclosure. A "thin film" refers to a thin layer of a material produced on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire production process, it can also be referred to as a "layer." If the "thin film" requires a patterning process during the entire production process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. The "thickness" of the film layer refers to the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0230] The following takes a plurality of driving circuits including a light-emitting driving circuit, a scanning driving circuit and a control driving circuit as an example to illustrate a display substrate provided by an exemplary embodiment through a manufacturing process of the display substrate.

[0231] (1) Forming an active layer on a substrate includes: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer. As shown in FIG10 , FIG10 is a schematic diagram after forming the semiconductor layer.

[0232] In an exemplary embodiment, the semiconductor layer includes: an active layer ET11 of the first light-emitting control transistor to an active layer ET131 of the thirteenth light-emitting control transistor, an active layer ST11 of the first scanning transistor to an active layer ST131 of the thirteenth scanning transistor, and an active layer GT11 of the first control transistor to an active layer GT81 of the eighth control transistor.

[0233] In an exemplary embodiment, the active layer ET41 of the fourth light-emitting control transistor and the active layer ET51 of the fifth light-emitting control transistor are an integrally formed structure, the active layer ET81 of the eighth light-emitting control transistor and the active layer ET131 of the thirteenth light-emitting control transistor are an integrally formed structure, the active layer ET91 of the ninth light-emitting control transistor and the active layer ET101 of the tenth light-emitting control transistor are an integrally formed structure, the active layer ST91 of the ninth scanning transistor and the active layer ST101 of the tenth scanning transistor are an integrally formed structure, the active layer GT41 of the fourth control transistor and the active layer GT51 of the fifth control transistor are an integrally formed structure, and the active layer GT61 of the sixth control transistor and the active layer GT71 of the seventh control transistor are an integrally formed structure.

[0234] (2) forming a first conductive layer, comprising: depositing a first insulating film on the substrate on which the above-mentioned pattern is formed, patterning the first insulating film through a patterning process to form a first insulating layer, depositing a first conductive film on the first insulating layer, and patterning the first conductive film through a patterning process to form a first metal layer, as shown in FIG11 and FIG12 , FIG11 is a schematic diagram of the first conductive layer, and FIG12 is a schematic diagram after the first conductive layer is formed.

[0235] In an exemplary embodiment, the first conductive layer may include: the control electrode ET12 of the first light-emitting control transistor to the control electrode ET132 of the thirteenth light-emitting control transistor, the first plate EC11 of the first light-emitting capacitor to the first plate EC31 of the third light-emitting capacitor, the control electrode ST12 of the first scanning transistor to the control electrode ST132 of the thirteenth scanning transistor, the first plate SC11 of the first scanning capacitor to the first plate SC31 of the third scanning capacitor, the control electrode GT12 of the first control transistor to the control electrode GT82 of the eighth control transistor, the first plate GC11 of the first control capacitor and the first plate GC21 of the second control capacitor, and the first connecting electrode VL1.

[0236] In an exemplary embodiment, the control electrode ET12 of the first light-emitting control transistor and the control electrode ET32 of the third light-emitting control transistor are an integrated structure, the control electrode ET112 of the eleventh light-emitting control transistor and the control electrode ET122 of the twelfth light-emitting control transistor are an integrated structure, the control electrode ET62 of the sixth light-emitting control transistor and the first electrode plate EC11 of the first light-emitting capacitor are an integrated structure, the control electrode ET42 of the fourth light-emitting control transistor, the first electrode plate EC31 of the third light-emitting capacitor and the control electrode ET102 of the tenth light-emitting control transistor are an integrated structure, the control electrode ET92 of the ninth light-emitting control transistor and the first electrode plate EC21 of the second light-emitting capacitor are an integrated structure, the scanning electrode ST12 of the first scanning transistor and the scanning electrode ST32 of the third scanning transistor are an integrated structure, and the scanning electrode ST 112 and the scanning electrode ST122 of the twelfth scanning transistor are an integrated structure, the scanning electrode ST62 of the sixth scanning transistor and the first electrode plate SC11 of the first scanning capacitor are an integrated structure, the scanning electrode ST42 of the fourth scanning transistor, the first electrode plate SC31 of the third scanning capacitor and the scanning electrode ST102 of the tenth scanning transistor are an integrated structure, the scanning electrode ST92 of the ninth scanning transistor and the first electrode plate SC21 of the second scanning capacitor are an integrated structure, the control electrode GT12 of the first control transistor and the control electrode GT32 of the third control transistor are an integrated structure, the control electrode GT42 of the fourth control transistor, the control electrode GT62 of the sixth control transistor and the first electrode plate GC11 of the first control capacitor are an integrated structure, and the control electrode GT52 of the fifth control transistor and the first electrode plate GC21 of the second control capacitor are an integrated structure.

[0237] (3) Forming a second conductive layer, comprising: depositing a second insulating film on the substrate having the pattern formed thereon, and patterning the second insulating film through a patterning process to form a second insulating layer. Depositing a second conductive film on the substrate having the second insulating layer formed thereon, and patterning the second conductive film through a patterning process to form a second conductive layer. As shown in Figures 13 and 14, Figure 13 is a schematic diagram of the second conductive layer, and Figure 14 is a schematic diagram after the second conductive layer is formed.

[0238] In an exemplary embodiment, the second conductive layer includes: a second connecting electrode VL2 to an eighth connecting electrode VL8, a second plate EC12 of the first light-emitting capacitor to a second plate EC32 of the third light-emitting capacitor, a second plate SC12 of the first scanning capacitor to a second plate SC32 of the third scanning capacitor, and a second plate GC12 of the first control capacitor and a second plate GC22 of the second control capacitor.

[0239] (4) forming a fifth conductive layer, comprising: depositing a fifth insulating film on the substrate having the above-mentioned pattern formed thereon, patterning the fifth insulating film through a patterning process to form a fifth insulating layer, depositing a fifth conductive film on the fifth insulating layer, and patterning the fifth conductive film through a patterning process to form a fifth conductive layer, as shown in FIG15 and FIG16 , FIG15 is a schematic diagram of the fifth conductive layer, and FIG16 is a schematic diagram after the fifth conductive layer is formed.

[0240] In an exemplary embodiment, the third conductive layer includes: an eighth connection electrode VL8 to a tenth connection electrode VL10.

[0241] (5) Forming a third conductive layer, comprising: depositing a third insulating film on the substrate formed with the above-mentioned substrate, patterning the third insulating film through a patterning process to form a third insulating layer, depositing a third conductive film on the third insulating layer, and patterning the third conductive film through a patterning process to form a third conductive layer, as shown in Figures 17 and 18, Figure 17 is a schematic diagram of the third conductive layer, and Figure 18 is a schematic diagram after the third conductive layer is formed.

[0242] In an exemplary embodiment, the fourth conductive layer includes at least: a low-level power line EVGL, the first electrode ET13 and the second electrode ET14 of the first light-emitting control transistor to the first electrode ET133 and the second electrode ET134 of the thirteenth light-emitting control transistor, the first electrode ST13 and the second electrode ST14 of the first scanning transistor to the first electrode ST133 and the second electrode ST134 of the thirteenth scanning transistor, a second scanning clock signal line SCLK2, the first electrode GT13 and the second electrode GT14 of the first control transistor to the first electrode GT83 and the second electrode GT84 of the eighth control transistor.

[0243] In an exemplary embodiment, the first connection electrode is electrically connected to VL1 and the first electrode ET13 of the first light-emitting control transistor and the eighth connection electrode VL8, respectively, the second connection electrode VL2 is electrically connected to the second electrode ET54 of the fifth light-emitting control transistor and the first electrode ET83 of the eighth light-emitting control transistor, the third connection electrode VL3 is electrically connected to the second electrode ET104 of the tenth light-emitting control transistor, the fourth connection electrode is electrically connected to the tenth connection electrode VL10 and the first electrode ST13 of the first scanning transistor, the fifth connection electrode VL5 is electrically connected to the second electrode ST114 of the eleventh scanning transistor and the control electrode of the sixth scanning transistor, the sixth connection electrode VL6 is electrically connected to the second electrode ST34 of the third scanning transistor and the second electrode ST24 of the second scanning transistor, the seventh connection electrode VL is electrically connected to the second electrode of the second control transistor and the second electrode of the fourth control transistor, respectively, and the tenth connection electrode VL10 is electrically connected to the second electrode ST104 of the tenth scanning transistor.

[0244] (6) forming a fourth conductive layer, comprising: depositing a fourth insulating film on the substrate having the above-mentioned pattern formed thereon, patterning the fourth insulating film through a patterning process to form a fourth insulating layer, depositing a fourth conductive film on the fourth insulating layer, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer, as shown in FIG19 and FIG20 , FIG19 is a schematic diagram of the fourth conductive layer, and FIG20 is a schematic diagram after the fourth conductive layer is formed.

[0245] In an exemplary embodiment, the fifth conductive layer includes at least: a light-emitting initial signal line ESTV, a first light-emitting clock signal line ECLK1 to a third light-emitting clock signal line ECLK3, a scan initial signal line SSTV, a first scan clock signal line SCLK1, a third scan clock signal line SCLK3, a control initial signal line GSTV, a first control clock signal line GCLK1, a second control clock signal line GCLK2, a high-level power line EVGH connected to the light-emitting drive circuit, a high-level power line SVGH connected to the scan drive circuit, a high-level power line GVGH connected to the control drive circuit, a low-level power line VGL connected to the scan drive circuit, a low-level power line GVGL connected to the control drive circuit, an eleventh connecting electrode VL11 and a twelfth connecting electrode VL12.

[0246] In an exemplary embodiment, the twelfth link electrode VL12 is electrically connected to the second electrode of the tenth scan transistor, and the eleventh link electrode is electrically connected to the eighth link electrode.

[0247] In an exemplary embodiment, the low-level power line SVGL connected to the scan driving circuit and the low-level power line GVGL connected to the control driving circuit are the same power line.

[0248] In an exemplary embodiment, the light-emitting driving circuit is connected to two low-level power lines, the control electrode of the tenth light-emitting transistor in the light-emitting driving circuit is electrically connected to the low-level power line EVGL connected to the light-emitting driving circuit, and the control electrode of the eleventh light-emitting transistor and the control electrode of the twelfth light-emitting transistor are electrically connected to the low-level power line SVGL connected to the scanning driving circuit.

[0249] In an exemplary embodiment, the widths of the high-level power line and the low-level power line are greater than the widths of any initial signal line and any clock signal line.

[0250] (7) forming a sixth conductive layer, comprising: coating a flat film on the substrate having the above-mentioned pattern formed thereon, forming a flat layer by masking, exposing, and developing the flat film, depositing a transparent conductive film on the flat layer, and patterning the transparent conductive film by a patterning process to form a sixth conductive layer, as shown in FIG21 and FIG22 , FIG21 is a schematic diagram of the sixth conductive layer, and FIG22 is a schematic diagram after the sixth conductive layer is formed.

[0251] In an exemplary embodiment, the sixth conductive layer includes: a first output signal line OL1. The first output signal line is an output signal line of the scan drive circuit; and an orthographic projection of at least one of the first output signal lines on the substrate at least partially overlaps with an orthographic projection of at least one of the control drive circuit, the scan drive circuit, and the light-emitting drive circuit on the substrate.

[0252] In an exemplary embodiment, the angle between the extension direction of the first output signal line and the first direction is greater than or equal to 0 degrees and less than 45 degrees, wherein the angle between the extension direction of the first output signal line and the first direction can be equal to 0 degrees, and the present disclosure does not impose any limitation on this.

[0253] (8) forming a light-emitting structure layer, comprising: coating a second flat film on the substrate formed with the above-mentioned pattern, patterning the second flat film through a patterning process to form a second flat layer, depositing an anode film on the second flat layer, patterning the anode film through a patterning process to form an anode, depositing a pixel definition film on the anode, patterning the pixel definition film through a patterning process to form a pixel definition layer, vapor-depositing an organic light-emitting film on the pixel definition layer, patterning the organic light-emitting film through a patterning process to form an organic light-emitting layer, depositing a cathode film on the organic light-emitting layer, and patterning the cathode film through a patterning process to form a cathode.

[0254] In an exemplary embodiment, an optical coupling layer pattern can be formed after the cathode is formed. The optical coupling layer is arranged on the cathode. The refractive index of the optical coupling layer can be greater than the refractive index of the cathode, which is conducive to light extraction and increases the light extraction efficiency. The material of the optical coupling layer can be organic material, or inorganic material, or organic material and inorganic material, and can be a single layer, a multi-layer or a composite layer, which is not limited in the present disclosure.

[0255] In an exemplary embodiment, the semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide comprising indium and tin, an oxide comprising tungsten and indium, an oxide comprising tungsten, indium and zinc, an oxide comprising titanium and indium, an oxide comprising titanium, indium and tin, an oxide comprising indium and zinc, an oxide comprising silicon, indium and tin, or an oxide comprising indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer. The active layer thin film may be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0256] In an exemplary embodiment, the first insulating layer, the second insulating layer, and the third to fifth insulating layers may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.

[0257] In an exemplary embodiment, the first to fifth conductive films may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0258] In one exemplary embodiment, the material of the pixel definition layer may include polyimide, acryl, or polyethylene terephthalate.

[0259] In an exemplary embodiment, a half-tone or gray-tone mask patterning process can be used to form a spacer post (PS) 25 pattern when forming a pixel definition layer. The spacer post 25 can be set on the outside of the pixel opening. The spacer post 25 is configured to support a fine metal mask in a subsequent evaporation process.

[0260] In an exemplary embodiment, the planar layer may be made of an organic material.

[0261] In an exemplary embodiment, the anode film may be made of indium tin oxide (ITO) or indium zinc oxide (IZO).

[0262] In exemplary embodiments, the cathode film may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the foregoing metals.

[0263] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0264] An embodiment of the present disclosure further provides a display device, including: a display substrate.

[0265] In an exemplary embodiment, the display device may be a monitor, a television, a mobile phone, a tablet computer, a navigator, a digital photo frame, a wearable display product, or any product or component with a display function.

[0266] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0267] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0268] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0269] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising: The display substrate includes a display area and a non-display area, and comprises a base and a circuit structure layer provided on the base, wherein the circuit structure layer comprises a plurality of pixel circuits arranged in an array in the display area and a plurality of driving circuits in the non-display area; at least one pixel circuit comprises a plurality of transistors, and the plurality of driving circuits are configured to provide driving signals to the plurality of transistors; The circuit structure layer further includes: a high-level power line and a low-level power line located in the non-display area, at least one driving circuit being electrically connected to the high-level power line and the low-level power line, respectively, and the high-level power line and the low-level power line extending along a first direction; The high-level power lines connected to at least two driving circuits are the same power line and / or the low-level power lines connected to at least two driving circuits are the same power line.

2. The display substrate according to claim 1, wherein The display area includes: a first side and a second side arranged opposite to each other, and at least one driving circuit is located on the first side and / or the second side of the display area; The plurality of driving circuits extend along a second direction, and the first direction intersects the second direction.

3. The display substrate according to claim 1 or 2, wherein: The circuit structure layer includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer and a fourth conductive layer stacked on the substrate in sequence; The high-level power line and the low-level power line are located in the third conductive layer and / or the fourth conductive layer.

4. The display substrate according to claim 3, wherein: The circuit structure layer may further include: a fifth insulating layer and a fifth conductive layer; The fifth insulating layer and the fifth conductive layer are located between the second conductive layer and the third insulating layer, and the fifth insulating layer is located on a side of the fifth conductive layer close to the substrate.

5. The display substrate according to claim 3 or 4, wherein: The plurality of transistors include: a write transistor, a compensation transistor and a light-emitting transistor; the plurality of drive circuits include: a light-emitting drive circuit and a control drive circuit; the light-emitting drive circuit is configured to provide a drive signal to the light-emitting transistor, and the control drive circuit is configured to provide a drive signal to the write transistor and / or the compensation transistor; The high level power line connected to the light emitting drive circuit and the high level power line connected to the control drive circuit are the same power line and / or the low level power line connected to the light emitting drive circuit and the low level power line connected to the control drive circuit are the same power line. The display substrate according to claim 5 , wherein: When the high-level power line connected to the light-emitting drive circuit and the high-level power line connected to the control drive circuit are the same power line, the orthographic projection of the high-level power line on the substrate at least partially overlaps with the orthographic projection of the light-emitting drive circuit or the control drive circuit on the substrate, or is located between the light-emitting drive circuit and the control drive circuit.

7. The display substrate according to claim 5, wherein: When the low-level power line connected to the light-emitting drive circuit and the low-level power line connected to the control drive circuit are the same power line, the orthographic projection of the low-level power line on the substrate at least partially overlaps with the orthographic projection of the light-emitting drive circuit or the control drive circuit on the substrate, or is located between the light-emitting drive circuit and the control drive circuit.

8. The display substrate according to any one of claims 5 to 7, wherein: The light-emitting driving circuit is located on a side of the control driving circuit away from the display area; The circuit structure layer further includes: a light-emitting initial signal line, a plurality of light-emitting clock signal lines, a control initial signal line, and a plurality of control clock signal lines, which are located in the non-display area and extend along a first direction; the light-emitting drive circuit is electrically connected to the light-emitting initial signal line and the plurality of light-emitting clock signal lines, respectively; and the control drive circuit is electrically connected to the control initial signal line and the plurality of control clock signal lines, respectively. The light-emitting initial signal line and the plurality of light-emitting clock signal lines are located on a side of the control initial signal line and the plurality of control clock signal lines away from the display area, and the light-emitting initial signal line is located on a side of the plurality of light-emitting clock signal lines close to the display area or on a side away from the display area; The control initial signal line is located on a side of the plurality of control clock signal lines close to the display area, or on a side away from the display area.

9. The display substrate according to claim 8, wherein: The light-emitting drive circuit includes: a plurality of light-emitting transistors and a plurality of light-emitting capacitors; the control drive circuit includes: a plurality of control transistors and a plurality of control capacitors; The first conductive layer includes: gate electrodes of a plurality of light emitting transistors, gate electrodes of a plurality of control transistors, first plates of a plurality of light emitting capacitors, and first plates of a plurality of control capacitors; The second conductive layer includes: a plurality of second plates of light-emitting capacitors and a plurality of second plates of control capacitors; The third conductive layer includes: source and drain electrodes of a plurality of light emitting transistors and source and drain electrodes of a plurality of control transistors; The fourth conductive layer includes: a light-emitting initial signal line, at least one light-emitting clock signal line, a control initial signal line, and at least one control clock signal line.

10. The display substrate according to claim 3 or 4, wherein: The plurality of transistors include: a write transistor, a first reset transistor, a compensation transistor, and a light-emitting transistor, wherein the transistor types of the first reset transistor and the compensation transistor are different from the transistor types of the write transistor and the light-emitting transistor, and the plurality of driving circuits include: a light-emitting driving circuit, a scan driving circuit, and a control driving circuit; the light-emitting driving circuit is configured to provide a driving signal to the light-emitting transistor, the control driving circuit is configured to provide a driving signal to the write transistor, and the scan driving circuit is configured to provide a driving signal to the first reset transistor and / or the compensation transistor; The high-level power lines connected to at least two adjacent drive circuits among the light-emitting drive circuit, the scanning drive circuit and the control drive circuit are the same power line and / or the low-level power lines connected to at least two adjacent drive circuits among the light-emitting drive circuit, the scanning drive circuit and the control drive circuit are the same power line.

11. The display substrate according to claim 10, wherein: When the high-level power line connected to two adjacent driving circuits among the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit is the same power line, the orthographic projection of the high-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the high-level power line on the substrate, or is located between the two adjacent driving circuits connected thereto; Alternatively, when the high-level power line connected to the light-emitting drive circuit, the scanning drive circuit and the control drive circuit is the same power line, the orthographic projection of the high-level power line on the substrate partially overlaps with the orthographic projection of one of the drive circuits connected to the high-level power line on the substrate, or is located between two adjacent drive circuits.

12. The display substrate according to claim 10, wherein: When the low-level power line connected to two adjacent driving circuits among the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit is the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power line on the substrate, or is located between the two adjacent driving circuits connected thereto; Alternatively, when the low-level power lines connected to the light-emitting drive circuit, the scanning drive circuit and the control drive circuit are the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the drive circuits connected to the low-level power line on the substrate, or is located between two adjacent drive circuits.

13. The display substrate according to any one of claims 10 to 12, wherein: The light emitting driving circuit is located on a side of the scanning driving circuit away from the display area, and the control driving circuit is located on a side of the scanning driving circuit close to the display area; The circuit structure layer further includes: a light-emitting initial signal line, a plurality of light-emitting clock signal lines, a control initial signal line, a plurality of control clock signal lines, a scan initial signal line, and a plurality of scan clock signal lines, which are located in the non-display area and extend along a first direction; the light-emitting drive circuit is electrically connected to the light-emitting initial signal line and the plurality of light-emitting clock signal lines, respectively; the control drive circuit is electrically connected to the control initial signal line and the plurality of control clock signal lines, respectively; and the scan drive circuit is electrically connected to the scan initial signal line and the plurality of scan clock signal lines, respectively. The light-emitting initial signal line and the plurality of light-emitting clock signal lines are located on a side of the scanning initial signal line and the plurality of scanning clock signal lines away from the display area, and the light-emitting initial signal line is located on a side of the plurality of light-emitting clock signal lines close to the display area or on a side away from the display area; The control initial signal line and the plurality of control clock signal lines are located on a side of the scan initial signal line and the plurality of scan clock signal lines close to the display area, and the control initial signal line is located on a side of the plurality of control clock signal lines close to the display area or on a side away from the display area; The scan initial signal line is located on a side of the plurality of scan clock signal lines close to the display area, or on a side away from the display area.

14. The display substrate according to claim 13, wherein: The light-emitting drive circuit includes: a plurality of light-emitting transistors and a plurality of light-emitting capacitors; the scan drive circuit includes: a plurality of scan transistors and a plurality of scan capacitors; the control drive circuit includes: a plurality of control transistors and a plurality of control capacitors; The first conductive layer includes: gate electrodes of a plurality of light emitting transistors, gate electrodes of a plurality of scanning transistors, gate electrodes of a plurality of control transistors, first plates of a plurality of light emitting capacitors, first electrodes of a plurality of scanning capacitors, and first plates of a plurality of control capacitors; The second conductive layer includes: second plates of a plurality of light-emitting capacitors, second plates of a plurality of scanning capacitors, and second plates of a plurality of control capacitors; The third conductive layer includes: source-drain electrodes of a plurality of light-emitting transistors, source-drain electrodes of a plurality of scanning transistors, and source-drain electrodes of a plurality of control transistors; The fourth conductive layer includes: a light-emitting initial signal line, at least one light-emitting clock signal line, a scanning initial signal line, at least one scanning clock signal line, a control initial signal line, and at least one control clock signal line.

15. The display substrate according to claim 10, wherein: The write transistor and the light emission control transistor are P-type transistors, and the first reset transistor and the compensation transistor are N-type metal oxide transistors.

16. The display substrate according to claim 3 or 4, wherein: The plurality of transistors include: a write transistor, a compensation transistor, a first reset transistor, a second reset transistor, and a light-emitting transistor; the plurality of drive circuits include: a light-emitting drive circuit, a first reset drive circuit, a second reset drive circuit, and a control drive circuit; the light-emitting drive circuit is configured to provide a drive signal to the light-emitting transistor, the control drive circuit is configured to provide a drive signal to the write transistor and / or the compensation transistor, the first reset drive circuit is configured to provide a drive signal to the first reset transistor, and the second reset drive circuit is configured to provide a drive signal to the second reset transistor; The high-level power lines connected to at least two adjacent drive circuits among the light-emitting drive circuit, the first reset drive circuit, the second reset drive circuit and the control drive circuit are the same power line and / or the low-level power lines connected to at least two adjacent drive circuits among the light-emitting drive circuit, the first reset drive circuit, the second reset drive circuit and the control drive circuit are the same power line.

17. The display substrate according to claim 16, wherein: When the high-level power line connected to two adjacent drive circuits among the light-emitting drive circuit, the first reset drive circuit, the second reset drive circuit, and the control drive circuit is the same power line, the orthographic projection of the high-level power line on the substrate partially overlaps with the orthographic projection of one of the drive circuits connected to the high-level power line on the substrate, or is located between the two adjacent drive circuits connected thereto; Alternatively, when the high-level power lines connected to at least three adjacent drive circuits among the light-emitting drive circuit, the first reset drive circuit, the second reset drive circuit and the control drive circuit are the same power line, the orthographic projection of the high-level power line on the substrate partially overlaps with the orthographic projection of one of the drive circuits connected to the high-level power line on the substrate, or is located between two adjacent drive circuits.

18. The display substrate according to claim 16, wherein: When the low-level power line connected to two adjacent drive circuits among the light-emitting drive circuit, the first reset drive circuit, the second reset drive circuit, and the control drive circuit is the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the drive circuits connected to the low-level power line on the substrate, or is located between the two adjacent drive circuits connected thereto; Alternatively, when the low-level power lines connected to at least three adjacent drive circuits among the light-emitting drive circuit, the first reset drive circuit, the second reset drive circuit and the control drive circuit are the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the drive circuits connected to the low-level power line on the substrate, or is located between two adjacent drive circuits.

19. The display substrate according to any one of claims 16 to 18, wherein: The light-emitting driving circuit is located on a side of the control driving circuit away from the display area, the first reset driving circuit is located between the light-emitting driving circuit and the control driving circuit, and the second reset driving circuit is located on a side of the control driving circuit close to the display area; The circuit structure layer further includes: a light-emitting initial signal line, a plurality of light-emitting clock signal lines, a control initial signal line, a plurality of control clock signal lines, a first reset initial signal line, a plurality of first reset clock signal lines, a second reset initial signal line, and a plurality of second reset clock signal lines, which are located in the non-display area and extend along the first direction; the light-emitting drive circuit is electrically connected to the light-emitting initial signal line and the plurality of light-emitting clock signal lines, respectively; the control drive circuit is electrically connected to the control initial signal line and the plurality of control clock signal lines, respectively; the first reset drive circuit is electrically connected to the first reset initial signal line and the plurality of first reset clock signal lines, respectively; and the second reset drive circuit is electrically connected to the second reset initial signal line and the plurality of second reset clock signal lines, respectively. The light-emitting initial signal line and the plurality of light-emitting clock signal lines are located on a side of the first reset initial signal line and the plurality of first reset clock signal lines away from the display area, and the light-emitting initial signal line is located on a side of the plurality of light-emitting clock signal lines close to the display area or on a side away from the display area; The first reset initial signal line and the plurality of first reset clock signal lines are located on a side of the control initial signal line and the plurality of control clock signal lines close to the display area, and the first reset initial signal line is located on a side of the plurality of first reset clock signal lines close to the display area or on a side away from the display area; The control initial signal line and the control clock signal line are located on a side of the second reset initial signal line and the plurality of second reset clock signal lines away from the display area, and the control initial signal line is located on a side of the plurality of control clock signal lines close to the display area or on a side away from the display area; The second reset initial signal line is located on a side of the plurality of second reset clock signal lines close to the display area or on a side away from the display area.

20. The display substrate according to claim 19, wherein The light-emitting drive circuit includes: a plurality of light-emitting transistors and a plurality of light-emitting capacitors; the scan drive circuit includes: a plurality of scan transistors and a plurality of scan capacitors; the first reset drive circuit includes: a plurality of first reset transistors and a plurality of first reset capacitors; the second reset drive circuit includes: a plurality of second reset transistors and a plurality of second reset capacitors; The first conductive layer includes: gate electrodes of multiple light-emitting transistors, gate electrodes of multiple control transistors, gate electrodes of multiple first reset transistors, gate electrodes of multiple second reset transistors, first plates of multiple light-emitting capacitors, first plates of multiple control capacitors, first plates of multiple first reset capacitors, and first plates of multiple second reset capacitors; The second conductive layer includes: a plurality of second plates of light-emitting capacitors, a plurality of second plates of control capacitors, a plurality of second plates of first reset capacitors, and a plurality of second plates of second reset capacitors; The third conductive layer includes: source-drain electrodes of a plurality of light-emitting transistors, source-drain electrodes of a plurality of control transistors, source-drain electrodes of a plurality of first reset transistors, and source-drain electrodes of a plurality of second reset transistors; The fourth conductive layer includes: a light-emitting initial signal line, at least one light-emitting clock signal line, a control initial signal line, at least one control clock signal line, a first reset initial signal line, at least one first reset clock signal line, a second reset initial signal line, and at least one second reset clock signal line.

21. The display substrate according to claim 1, wherein The boundary of the display area includes at least one arc-shaped boundary.

22. A display device comprising the display substrate according to any one of claims 1 to 21.

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