Display substrate, preparation method thereof and display device

Abstract

The invention provides a display substrate which comprises a first substrate body, a second substrate body, a third substrate body, a fourth substrate body, a fifth substrate body and a sixth substrate body. The at least one common voltage line is located in the display area, and each common voltage line is provided with at least one conductive connection area; the first passivation layer is positioned on one side, far away from the first substrate, of the common electrode wire; the common electrode is positioned on one side, far away from the first substrate, of the first passivation layer; the second passivation layer is positioned on one side, far away from the first substrate, of the common electrode; the pixel electrode is positioned on one side, far away from the first substrate, of the second passivation layer; the first conductive connection electrodes are located in the corresponding conductive connection areas, the first conductive connection electrodes and the pixel electrodes are arranged on the same layer, and the common electrodes are electrically connected with the common voltage lines through the first conductive connection electrodes. The embodiment of the invention further provides a preparation method of the display substrate and a display device.

Description

Display substrate, manufacturing method thereof, and display device Technical Field

[0001] The present invention relates to the field of display, and in particular to a display substrate, a preparation method thereof, and a display device. Background Art

[0002] To improve the viewing angle problem of liquid crystal display (LCD), the advanced super-dimensional switching (ADS) mode of liquid crystal display technology has been proposed. In an ADS mode display device, pixel electrodes and common electrodes are arranged on the same display substrate.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate, the display substrate comprising:

[0005] A first base substrate, comprising a display area and a peripheral area surrounding the display area;

[0006] At least one common voltage line is located in the display area, and each common voltage line is configured with at least one conductive connection area;

[0007] a first passivation layer, located on a side of the common electrode line away from the first substrate;

[0008] a common electrode, located on a side of the first passivation layer away from the first substrate;

[0009] a second passivation layer, located on a side of the common electrode away from the first substrate;

[0010] a pixel electrode, located on a side of the second passivation layer away from the first substrate;

[0011] The first conductive connection electrode is located in the corresponding conductive connection area and is provided in the same layer as the pixel electrode. The common electrode is electrically connected to the common voltage line through the first conductive connection electrode.

[0012] In some embodiments, the display substrate further comprises:

[0013] a plurality of thin film transistors, wherein the thin film transistors are located between the first substrate and the first passivation layer;

[0014] The common voltage line is arranged in the same layer as the gate of the thin film transistor.

[0015] In some embodiments, the first electrode and the second electrode of the thin film transistor are located on a side of the gate of the thin film transistor away from the first substrate, and an insulating layer is provided between the first electrode and the second electrode of the thin film transistor and the gate of the thin film transistor;

[0016] The display substrate further includes:

[0017] a second conductive connection electrode located in the corresponding conductive connection region and provided in the same layer as the first electrode and the second electrode of the thin film transistor, the second conductive connection electrode being in contact with the common voltage line through a first via hole in the insulating layer;

[0018] The first conductive connection electrode is electrically connected to the common voltage line through the second conductive connection electrode.

[0019] In some embodiments, a second via hole is formed in the conductive connection region, connecting the second conductive connection electrode from the surface of the second passivation layer away from the first substrate, and a third via hole is formed in the conductive connection region, connecting the common electrode from the surface of the second passivation layer away from the first substrate.

[0020] The first conductive connection electrode contacts the corresponding second conductive connection electrode through the second via hole, and the first conductive connection electrode contacts the portion of the common electrode located in the conductive connection area through the third via hole.

[0021] In some embodiments, the display substrate further comprises:

[0022] a plurality of gate lines and a plurality of data lines, wherein the gate lines extend along a first direction and the data lines extend along a second direction, the first direction intersecting the second direction, and the plurality of gate lines and the plurality of data lines defining a plurality of pixel areas arranged in an array along the first direction and the second direction;

[0023] The pixel area includes a light emitting area and a non-light emitting area arranged along the second direction, and the non-light emitting area is closer to the gate line corresponding to the pixel area than the light emitting area;

[0024] A thin film transistor is formed in the non-light-exiting area, a fourth via hole is further formed in the non-light-exiting area, and the fourth via hole is connected to the second electrode of the thin film transistor from the surface of the second passivation layer away from the first substrate. A pixel electrode is formed in the light-exiting area;

[0025] The gate electrode of the thin film transistor is electrically connected to the corresponding gate line, the first electrode of the thin film transistor is electrically connected to the corresponding data line, and the pixel electrode is electrically connected to the second electrode of the thin film transistor through the corresponding fourth via hole;

[0026] An extension direction of the common voltage line is parallel to an extension direction of the gate line. The common voltage line is located in the non-light emitting area and on a side of the thin film transistor close to the light emitting area.

[0027] In some embodiments, the second via hole and the third via hole are both located in the non-light-exiting area and between the corresponding common voltage line and the gate line.

[0028] In some embodiments, the second via holes and the third via holes are arranged along the second direction.

[0029] In some embodiments, the second via holes and the fourth via holes are arranged along the first direction;

[0030] The third via holes and the fourth via holes are arranged along the first direction.

[0031] In some embodiments, the first conductive connection electrode and the two pixel electrodes adjacent to each other in the second direction are spaced equally apart in the second direction.

[0032] In some embodiments, a fifth via hole is formed in the conductive connection region, connecting the second conductive connection electrode and the common electrode from a surface of the second passivation layer away from the first substrate.

[0033] The second via hole is a portion of the fifth via hole connected to the second conductive connection electrode, and the third via hole is a portion of the fifth via hole connected to the common electrode.

[0034] In some embodiments, for any one of the fifth via holes, the bottom of the fifth via hole has a first orthographic projection on the first substrate, and the portion of the common electrode exposed by the fifth via hole has a second orthographic projection on the first substrate;

[0035] The area of ​​the second orthographic projection is half the area of ​​the first orthographic projection.

[0036] In some embodiments, an edge of the second orthographic projection passes through a center of the first orthographic projection.

[0037] In some embodiments, the shape of the first orthographic projection is a first rectangle, and the shape of the second orthographic projection is a second rectangle;

[0038] The length of the first rectangle in the first direction is half the length of the second rectangle in the first direction;

[0039] The length of the first rectangle in the second direction is equal to the length of the second rectangle in the second direction.

[0040] In some embodiments, the fifth via holes and the first via holes are arranged along the second direction.

[0041] In some embodiments, a center of an orthographic projection of the fifth via hole on the first substrate overlaps with a center of an orthographic projection of the first conductive connection electrode on the first substrate.

[0042] In some embodiments, within the same conductive connection region, the orthographic projection of the bottom of the second via on the first substrate has a first projection area, and the orthographic projection of the bottom of the third via on the first substrate has a second projection area;

[0043] The first projected area is equal to the second projected area.

[0044] In some embodiments, within the same conductive connection region, the first conductive connection electrode and the corresponding second conductive connection electrode have a first contact area, and the first conductive connection electrode and the portion of the common electrode located within the conductive connection region have a second contact area;

[0045] The first contact area is equal to the second contact area.

[0046] In some embodiments, the display substrate further comprises:

[0047] a planarization layer located between the first passivation layer and the common electrode, wherein a sixth via hole is formed in the conductive connection region of the planarization layer, and a portion of the common electrode is located in the sixth via hole;

[0048] The orthographic projection of the sixth via hole on the first base substrate covers the orthographic projection of the second via hole on the first base substrate and the orthographic projection of the third via hole on the first base substrate.

[0049] In some embodiments, for any one of the sixth via holes, the sixth via hole has a third orthographic projection on the first substrate, and the portion of the common electrode located in the sixth via hole has a fourth orthographic projection on the first substrate;

[0050] The area of ​​the fourth orthographic projection is half the area of ​​the third orthographic projection.

[0051] In some embodiments, an edge of the fourth orthographic projection passes through a center of the third orthographic projection.

[0052] In some embodiments, the shape of the third orthographic projection is a third rectangle, and the shape of the fourth orthographic projection is a fourth rectangle;

[0053] The length of the third rectangle in the first direction is half the length of the fourth rectangle in the first direction;

[0054] The length of the fourth rectangle in the second direction is equal to the length of the fourth rectangle in the second direction.

[0055] In some embodiments, the orthographic projection of the first conductive connection electrode on the first base substrate covers the orthographic projection of the sixth via hole on the first base substrate.

[0056] In some embodiments, a center of an orthographic projection of the sixth via hole on the first substrate overlaps with a center of an orthographic projection of the first conductive connection electrode on the first substrate.

[0057] In some embodiments, the slope angle of the sidewall of the planarization layer surrounding the sixth via hole is 30° to 80°.

[0058] In some embodiments, the slope angle of the sidewall of the first passivation layer surrounding the second via hole is 15° to 50°;

[0059] The slope angle corresponding to the sidewall of the second passivation layer surrounding the third via hole is 15° to 50°.

[0060] In some embodiments, further comprising:

[0061] Common voltage peripheral leads, located in the peripheral area;

[0062] The common electrode extends to the peripheral area and is electrically connected to the common voltage peripheral lead.

[0063] In some embodiments, both ends of the common voltage line extend to the peripheral area and are electrically connected to the common voltage peripheral lead.

[0064] In some embodiments, the common voltage peripheral lead is arranged around the display area;

[0065] The display substrate further includes: a common voltage writing lead located in the peripheral area and located on a side of the common voltage peripheral lead away from the display area;

[0066] The common voltage writing lead is electrically connected to the common voltage peripheral lead.

[0067] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising: a display substrate and a cell-matching substrate as provided in the first aspect above, wherein the display substrate and the cell-matching substrate are arranged opposite to each other.

[0068] In a third aspect, an embodiment of the present disclosure further provides a method for preparing the display substrate as provided in the first aspect, comprising:

[0069] Providing a first base substrate, the first base substrate comprising a display area and a peripheral area surrounding the display area;

[0070] forming at least one common voltage line on one side of the first base substrate, the common voltage line being located in the display area, and each common voltage line being configured with at least one conductive connection area;

[0071] forming a first passivation layer on a side of the common voltage line away from the first substrate;

[0072] forming a common electrode on a side of the first passivation layer away from the first substrate;

[0073] forming a second passivation layer on a side of the common electrode away from the first substrate;

[0074] A pixel electrode and a first conductive connection electrode are formed on the same layer of the second passivation layer on a side away from the first base substrate. The first conductive connection electrode is located in the corresponding conductive connection area. The common electrode is electrically connected to the common voltage line through the first conductive connection electrode.

[0075] In some embodiments, before the step of forming the first passivation layer, the method further includes:

[0076] Forming a thin film transistor and a second conductive connection electrode on one side of the first substrate, including: forming a gate through a patterning process, forming an active layer through a patterning process, and forming a first electrode, a second electrode, and a second conductive connection electrode through a patterning process; wherein an insulating layer is provided between the first electrode, the second electrode, and the gate, and the second conductive connection electrode contacts the common voltage line through a first via hole in the insulating layer;

[0077] The gate electrode and the common electrode line are formed based on the same patterning process;

[0078] The first conductive connection electrode is electrically connected to the common voltage line through the second conductive connection electrode.

[0079] In some embodiments, the steps of forming a first passivation layer, forming a common electrode, forming a second passivation layer, and forming a pixel electrode specifically include:

[0080] forming a first passivation material film on a side of the common voltage line away from the first substrate;

[0081] forming a common electrode on a side of the first passivation material film away from the first substrate through a patterning process;

[0082] forming a second passivation material film on a side of the common electrode away from the first substrate;

[0083] Patterning the second passivation material film and the first passivation material film through a single patterning process to form a second via hole in the conductive connection region, the second via hole being connected from a surface of the second passivation layer away from the first substrate to the second conductive connection electrode, and a third via hole being connected from a surface of the second passivation layer away from the first substrate to the common electrode;

[0084] The pixel electrode and the first conductive connection electrode are formed by a patterning process, the first conductive connection electrode contacts the corresponding second conductive connection electrode through the second via hole, and the first conductive connection electrode contacts the portion of the common electrode located in the conductive connection area through the third via hole.

[0085] In some embodiments, the second via and the third via are different parts of the same via.

[0086] In some embodiments, between the step of forming the first passivation material film and the step of forming the common electrode, the method further includes:

[0087] forming a planarization layer on a side of the first passivation material film away from the first substrate through a patterning process, wherein the planarization layer has a sixth via hole formed in the conductive connection area;

[0088] Part of the common electrode formed in the subsequent steps is located in the sixth via hole, and the orthographic projections of the second via hole and the third via hole formed in the subsequent steps on the first base substrate are both located in the area covered by the orthographic projection of the sixth via hole on the first base substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0090] FIG1 is a schematic top view of a display substrate in the related art;

[0091] FIG2 is a schematic top view of a display substrate according to an embodiment of the present disclosure;

[0092] FIG3 is a schematic diagram of a circuit structure of a display area in an embodiment of the present disclosure;

[0093] FIG4 is a schematic top view of a conductive connection area and its vicinity in an embodiment of the present disclosure;

[0094] FIG5 is a schematic cross-sectional view taken along the line AA' in FIG4 ;

[0095] FIG6 is a schematic cross-sectional view taken along the line BB' in FIG4 ;

[0096] FIG7 is a scanning electron microscope image of a cross section of the second via hole and the third via hole in an embodiment of the present disclosure;

[0097] FIG8 is a schematic top view of an orthographic projection of the fifth via hole, the first conductive connection electrode, and the sixth via hole on the first base substrate in an embodiment of the present disclosure;

[0098] FIG9 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure;

[0099] FIG10 is a flow chart of a method for preparing a display substrate according to an embodiment of the present disclosure;

[0100] FIG11 is another flow chart of a method for preparing a display substrate according to an embodiment of the present disclosure;

[0101] 12A to 12J are schematic top views of a portion of an intermediate product formed by the preparation method shown in FIG. 11 . DETAILED DESCRIPTION

[0102] In order to enable those skilled in the art to better understand the technical solution of the present invention, a display substrate, a preparation method thereof, and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

[0103] The patterning process in the embodiments of the present disclosure is also referred to as a patterning process or a mask process, and specifically refers to processes including photoresist coating, exposure, development, film etching, and photoresist stripping. When the material film to be patterned is a photoresist film, the patterning of the material film can be achieved through the exposure and development processes.

[0104] Figure 1 is a top plan schematic diagram of a display substrate in the related art. As shown in Figure 1, the display substrate includes a first base substrate, and the first base substrate includes a display area 1a and a peripheral area 1b surrounding the display area 1a; wherein, a planar common electrode 2 is provided in the display area 1a, and a common voltage peripheral lead 3 is provided in the peripheral area 1b. The planar common electrode 2 extends to the peripheral area 1b and is electrically connected to the common voltage peripheral lead 3. The common voltage peripheral lead 3 can write a common voltage signal onto the planar common electrode 2.

[0105] In actual applications, it is found that in order to prevent the common electrode 2 from blocking the light output from the display area 1a, a transparent conductive material is selected to form the common electrode 2, generally a metal oxide, such as indium tin oxide (ITO). However, in actual applications, it is found that due to the relatively high resistivity of the metal oxide and the large size of the planar common electrode 2, the overall resistance of the common electrode 2 is relatively large. In the process of writing the common voltage signal from the common voltage peripheral lead 3 to the planar common electrode 2, there will be a significant signal delay on the common electrode 2. In addition, in a high refresh rate display device, the common voltage signal delay on the common electrode 2 will directly affect the final display effect of the display device.

[0106] In order to reduce the delay of a common voltage signal on a planar common electrode and improve the stability of the common voltage signal, an embodiment of the present disclosure provides a display substrate.

[0107] Figure 2 is a top plan schematic diagram of the display substrate in the embodiment of the present disclosure, Figure 3 is a circuit structure schematic diagram of the display area in the embodiment of the present disclosure, Figure 4 is a top plan schematic diagram of the conductive connection area and its vicinity in the embodiment of the present disclosure, Figure 5 is a cross-sectional schematic diagram along the A-A' direction in Figure 4, Figure 6 is a cross-sectional schematic diagram along the B-B' direction in Figure 4, and Figure 7 is a scanning electron microscope image of the cross section at the second via hole and the third via hole in the embodiment of the present disclosure. As shown in Figures 2 to 7, the display substrate includes: a first base substrate 1, at least one common voltage line VCOML, a first passivation layer 12, a common electrode 2, a second passivation layer 14, a pixel electrode 8 and a first conductive connection electrode 10. Among them, the first base substrate 1 includes a display area 1a and a peripheral area 1b surrounding the display area 1a; the common voltage line VCOML is located in the display area 1a, and each common voltage line VCOML is configured with at least one conductive connection area 5; the first passivation layer 12 is located on the side of the common electrode 2 away from the first base substrate 1; the common electrode 2 is located on the side of the first passivation layer 12 away from the first base substrate 1; the second passivation layer 14 is located on the side of the common electrode 2 away from the first base substrate 1; the pixel electrode 8 is located on the side of the second passivation layer 14 away from the first base substrate 1; the first conductive connection electrode 10 is located in the corresponding conductive connection area 5 and is arranged on the same layer as the pixel electrode 8, and the common electrode 2 is electrically connected to the common voltage line VCOML through the first conductive connection electrode 10.

[0108] In the embodiment of the present disclosure, a common voltage peripheral lead 3 is provided in the peripheral area 1 b , and the common electrode 2 extends to the peripheral area 1 b and is electrically connected to the common voltage peripheral lead 3 located in the peripheral area 1 b .

[0109] In addition, in the embodiment of the present disclosure, the pixel electrode 8 is a slit electrode.

[0110] On the one hand, in the embodiment of the present disclosure, common voltage lines VCOML are provided within the display area 1a, and each common voltage line VCOML is configured with at least one conductive connection area 5. The common electrode 2 is electrically connected to the common voltage line VCOML via a first conductive connection electrode 10 located in the conductive connection area 5. Compared to the technical solution in the related art that only utilizes the common voltage peripheral leads 3 located in the peripheral area 1b to provide a common voltage signal to the common electrode 2, the display substrate provided in the embodiment of the present disclosure can not only utilize the common voltage peripheral leads 3 located in the peripheral area 1b to provide a common voltage signal to the common electrode 2, but can also utilize the common voltage lines VCOML located in the display area 1a to provide a common voltage signal to the common electrode 2. Therefore, the loading speed of the common voltage signal on the common electrode 2 can be effectively increased, the delay of the common voltage signal can be reduced, and the stability of the common voltage signal can be improved.

[0111] On the other hand, in the embodiment of the present disclosure, since the first conductive connection electrode 10 and the pixel electrode 8 are arranged in the same layer, the first conductive connection electrode 10 and the pixel electrode 8 can be prepared based on the same MASK process. Therefore, the setting of the first conductive connection electrode 10 will not lead to an increase in the number of MASK processes.

[0112] At the same time, since the common electrode 2 is electrically connected to the common voltage line VCOML through the first conductive connection electrode 10 located on the side of the common electrode 2 away from the first substrate 1, rather than being directly connected to the common voltage line VCOML through the via hole on the first passivation layer 12, the MASK process of the first passivation layer 12 can also be performed after the MASK process of the common electrode 2; that is, the MASK process of the first passivation layer 12 can be the same MASK process as the MASK process of the second passivation layer 14 located on the side of the common electrode 2 away from the first substrate 1 (that is, the first passivation layer 12 and the second passivation layer 14 are subjected to the MASK process at the same time), thereby effectively reducing the number of MASK processes.

[0113] In some embodiments, the display substrate further includes a plurality of thin film transistors T, which are located between the first base substrate 1 and the first passivation layer 12. The common voltage line VCOML is provided on the same layer as the gates Tg of the thin film transistors T. In other words, the common voltage line VCOML and the gates Tg of the thin film transistors T can be fabricated using the same mask process. Therefore, the provision of the common voltage line VCOML does not increase the number of mask processes.

[0114] In some embodiments, the first electrode Ts and the second electrode Td of the thin film transistor T are located on a side of the gate Tg of the thin film transistor T away from the first substrate, and an insulating layer 11 is provided between the first electrode Ts and the second electrode Td of the thin film transistor T and the gate Tg of the thin film transistor T.

[0115] It should be noted that when the thin film transistor T is a bottom-gate thin film transistor T, the insulating layer 11 is a gate insulating layer 11 located between the gate electrode Tg and the active layer Ta. When the thin film transistor T is a top-gate thin film transistor T, the insulating layer 11 is an interlayer dielectric layer located between the gate electrode Tg and the first electrode Ts and the second electrode Td. In the embodiments of the present disclosure, the bottom-gate thin film transistor T is used as an example for illustrative purposes only and does not limit the technical solutions of the present disclosure.

[0116] The display substrate also includes: a second conductive connection electrode 9, which is located in the corresponding conductive connection area 5 and is arranged in the same layer as the first electrode Ts and the second electrode Td of the thin film transistor T. The second conductive connection electrode 9 is in contact with the common voltage line VCOML through the first via h1 on the insulating layer 11; the first conductive connection electrode 10 is electrically connected to the common voltage line VCOML through the second conductive connection electrode 9.

[0117] In the embodiment of the present disclosure, if the second conductive connection electrode 9 is not provided and the first conductive connection electrode 10 is directly connected to the common voltage line VCOML through a via, the first conductive connection electrode 10 needs to extend along the side wall of the corresponding via from the side surface of the second passivation layer 14 away from the first base substrate 1 to the side surface of the common voltage line VCOML away from the first base substrate 1. The first conductive connection electrode 10 as a whole will have a large step difference, and thus the risk of the first conductive connection electrode 10 breaking is easy to occur. However, by providing the second conductive connection electrode 9 and electrically connecting the first conductive connection electrode 10 to the common voltage line VCOML through the second conductive connection electrode 9, the first conductive connection electrode 10 needs to extend along the side wall of the corresponding via from the side surface of the second passivation layer 14 away from the first base substrate 1 to the side surface of the second conductive connection electrode 9 away from the first base substrate 1. At this time, the overall step difference of the first conductive connection electrode 10 can be effectively reduced, thereby reducing the risk of the first conductive connection electrode 10 breaking.

[0118] In some embodiments, a second via h2 is formed in the conductive connection area 5, connecting the surface of the second passivation layer 14 away from the first base substrate 1 to the second conductive connection electrode 9, and a third via h3 is formed in the conductive connection area 5, connecting the surface of the second passivation layer 14 away from the first base substrate 1 to the common electrode 2; the first conductive connection electrode 10 contacts the corresponding second conductive connection electrode 9 through the second via h2, and the first conductive connection electrode 10 contacts the portion of the common electrode 2 located in the conductive connection area 5 through the third via h3.

[0119] In some embodiments, the display substrate further includes: a plurality of gate lines GL and a plurality of data lines DL, wherein the gate lines GL extend along a first direction X, and the data lines DL extend along a second direction Y, wherein the first direction X intersects the second direction Y. The plurality of gate lines GL and the plurality of data lines DL define a plurality of pixel areas PIX arranged in an array along the first direction X and the second direction Y. In the embodiments of the present disclosure, an exemplary description is given using FIG. 2 as an example in which the first direction X is a row direction and the second direction Y is a column direction.

[0120] 3 and 4 , the pixel area PIX includes a light emitting area P1 and a non-light emitting area P2 arranged along the second direction Y. The non-light emitting area P2 is closer to the gate line GL corresponding to the pixel area than the non-light emitting area P1. A thin film transistor T is formed in the non-light emitting area P2. A fourth via hole h4 is also formed in the non-light emitting area P2, which is connected to the second pole Td of the thin film transistor T from the surface of the second passivation layer 14 away from the first base substrate 1. A pixel electrode 8 is formed in the light emitting area P1.

[0121] The gate electrode Tg of the thin film transistor T is electrically connected to the corresponding gate line GL, the first electrode Ts of the thin film transistor T is electrically connected to the corresponding data line DL, and part of the pixel electrode 8 extends to the non-light-emitting area P2 to be electrically connected to the second electrode Td of the thin film transistor T through the corresponding fourth via h4 (that is, part of the pixel electrode 8 is located in the non-light-emitting area P2); the extension direction of the common voltage line VCOML is parallel to the extension direction of the gate line GL, and the common voltage line VCOML is located in the non-light-emitting area and on the side of the thin film transistor T close to the light-emitting area.

[0122] In the embodiment of the present disclosure, the gate line GL and the gate Tg of the thin film transistor T are provided in the same layer; that is, the gate line GL, the common voltage line VCOML and the gate Tg of the thin film transistor T are provided in the same layer.

[0123] In some embodiments, the second via hole h2 and the third via hole h3 are both located in the non-light emitting area and between the corresponding common voltage line VCOML and the gate line GL.

[0124] In some embodiments, the second via holes h2 and the third via holes h3 are arranged along the second direction Y.

[0125] In some embodiments, the second via holes h2 and the fourth via holes h4 are arranged along the first direction X; the third via holes h3 and the fourth via holes h4 are arranged along the first direction X.

[0126] As shown in FIG4 , in a row of pixel areas where a common voltage line VCOML is provided, the thin film transistor T, the fourth via h4, the second via h2 and the third via h3 are all located between the common voltage line VCOML and the gate line GL, and the fourth via h4, the second via h2 and the third via h3 are arranged along the first direction X. At this time, the space in the non-light-emitting area between the common voltage line VCOML and the gate line GL in the first direction X can be fully and effectively utilized, which is beneficial to increasing the area ratio of the light-emitting area in the pixel area, that is, the pixel aperture ratio can be effectively improved.

[0127] In some embodiments, a common voltage line VCOML may be provided for each row of pixel regions PIX. Of course, a common voltage line VCOML may also be selectively provided for one or more rows of pixel regions PIX. These situations shall all fall within the scope of protection of the present disclosure.

[0128] As shown in FIG4 , in some embodiments, the spacings L1 and L2 between the first conductive connection electrode 10 and two adjacent pixel electrodes 8 in the second direction Y (i.e., the shortest distances between the first conductive connection electrode 10 and two adjacent pixel electrodes 8 in the second direction Y) are equal. This design allows for a certain process error margin between the first conductive connection electrode 10 and two adjacent pixel electrodes 8 in the second direction Y.

[0129] As shown in Figures 5-7, in some embodiments, a fifth via h5 is formed in the conductive connection area 5, connecting from the surface of the second passivation layer 14 on the side away from the first substrate 1 to the second conductive connection electrode 9 and the common electrode 2; the second via h2 is the part of the fifth via h5 connected to the second conductive connection electrode 9, and the third via h3 is the part of the fifth via h5 connected to the common electrode 2.

[0130] That is, the second via h2 and the third via h3 in the embodiment of the present disclosure are connected to form a fifth via h5; or in other words, a portion of the fifth via h5 in the present disclosure can serve as the second via h2, and another portion of the fifth via h5 can serve as the third via h3. In this case, only one fifth via h5 is required in the conductive connection area 5, and the first conductive connection electrode 10 can be connected to both the corresponding second conductive connection electrode 9 and the common electrode 2 through only one fifth via h5.

[0131] In actual applications, due to process limitations, the size of the minimum via that can be formed by the patterning process (the projected area of ​​the via on the substrate) is limited, and the size of the minimum via is related to factors such as the material and thickness of the thin film being processed. If the size of the minimum via that can be formed by the patterning process in this application is a, when the second via h2 and the third via h3 are two vias spaced apart, then in order to form the above-mentioned second via h2 and third via h3, the minimum opening area required in a conductive connection area 5 is 2*a; and when the second via h2 and the third via h3 are two different parts of the same fifth via h5, then the minimum opening area required in a conductive connection area 5 is a. It can be seen from this that by using part of a fifth via h5 as the second via h2 and using another part of the fifth via h5 as the third via h3, the opening area can be effectively reduced, which is beneficial to reducing the overall area of ​​the non-light-emitting area, thereby facilitating an improvement in the pixel aperture ratio.

[0132] In addition, in the embodiment of the present disclosure, the depth of the second via h2 is greater than the depth of the third via h3, and the second via h2 is connected to the third via h3, forming a deep-shallow hole connection (forming a step surface) design; in the subsequent preparation process of the alignment film (also called PI film), the above-mentioned deep-shallow hole connection design can increase the fluidity of the PI liquid during PI coating, avoiding the problem of uneven PI diffusion caused by poor fluidity of the PI liquid at the deep hole position.

[0133] In some embodiments, the thickness of the first conductive connection electrode 10 in the region where the second via hole h2 is located is greater than the thickness of the first conductive connection electrode 10 in the region where the third via hole h3 is located. In the disclosed embodiment, by increasing the thickness of the first conductive connection electrode 10 in the region where the second via hole h2 is located, such that the thickness of the first conductive connection electrode 10 in the region where the second via hole h2 is located is greater than the thickness of the first conductive connection electrode 10 in the region where the third via hole h3 is located, this can effectively reduce the resistance of the first conductive connection electrode 10 in the region where the second via hole h2 is located, thereby reducing the overall resistance of the first conductive connection electrode. Furthermore, it can effectively reduce the depth difference between deep and shallow hole locations, thereby facilitating uniform diffusion of PI.

[0134] Figure 8 is a top view schematic diagram of the orthographic projections of the fifth via, the first conductive connection electrode, and the sixth via on the first base substrate in an embodiment of the present disclosure. As shown in Figure 8, in some embodiments, for any fifth via h5, the bottom of the fifth via h5 has a first orthographic projection h5' on the first base substrate 1, and the portion of the common electrode 2 exposed by the fifth via h5 has a second orthographic projection 2' on the first base substrate 1; the area of ​​the second orthographic projection 2' is half of the area of ​​the first orthographic projection h5'.

[0135] In the present disclosure, the area of ​​the second orthographic projection 2' is half of the area of ​​the first orthographic projection h5' so that the second conductive connection electrode 9 also has a sufficient exposed area, thereby ensuring that the first conductive connection electrode 10 can have a large contact area with both the common electrode 2 and the second conductive connection electrode 9.

[0136] Of course, in the present disclosure, the area of ​​the second orthographic projection 2' is not limited to half of the area of ​​the first orthographic projection h5'; specifically, the ratio of the area of ​​the second orthographic projection 2' to the area of ​​the first orthographic projection h5' can be taken within a certain range (for example, 20% to 80%), and it can also ensure that the first conductive connection electrode 10 can simultaneously achieve reliable electrical connection with the common electrode 2 and the second conductive connection electrode 9.

[0137] In some embodiments, an edge of the second orthographic projection 2 ′ passes through the center of the first orthographic projection h5 ′.

[0138] In some embodiments, the shape of the first orthographic projection h5' is a first rectangle, and the shape of the second orthographic projection 2' is a second rectangle; the length of the first rectangle in the first direction X is half the length of the second rectangle in the first direction X; the length of the first rectangle in the second direction Y is equal to the length of the second rectangle in the second direction Y.

[0139] It should be noted that the “rectangle” in the present disclosure includes not only a rectangle with right angles, but also a rectangle with rounded or chamfered corners.

[0140] In some embodiments, the fifth via holes h5 and the first via holes h1 are arranged along the second direction Y.

[0141] In some embodiments, a center O of an orthographic projection h5 ′ of the fifth via hole h5 on the first base substrate 1 overlaps with a center of an orthographic projection 10 ′ of the first conductive connection electrode 10 on the first base substrate 1 .

[0142] In some embodiments, within the same conductive connection region 5 , the orthographic projection h2 ′ of the bottom of the second via h2 on the first base substrate 1 has a first projection area, and the orthographic projection h3 ′ of the bottom of the third via h3 on the first base substrate 1 has a second projection area; the first projection area is equal to the second projection area.

[0143] In some embodiments, within the same conductive connection region 5, the first conductive connection electrode 10 and the corresponding second conductive connection electrode 9 have a first contact area, and the first conductive connection electrode 10 and the portion of the common electrode 2 located within the conductive connection region 5 have a second contact area; the first contact area is equal to the second contact area.

[0144] Through the above design, the connection strength between the first conductive connection electrode 10 , the second conductive connection electrode 9 and the common electrode 2 can be improved.

[0145] In some embodiments, the display substrate further includes: a planarization layer 13; the planarization layer 13 is located between the first passivation layer 12 and the common electrode 2, and the planarization layer 13 forms a sixth via h6 in the conductive connection area 5, and part of the common electrode 2 is located in the sixth via h6; the orthographic projection h6' of the sixth via h6 on the first base substrate 1 covers the orthographic projection h2' of the second via h2 on the first base substrate 1 and the orthographic projection h3' of the third via h3 on the first base substrate 1.

[0146] In some embodiments, the slope angle of the sidewall of the planarization layer 13 surrounding the sixth via hole h6 is 30° to 80°.

[0147] It should be noted that the “slope angle of the side wall” in the present disclosure refers to the angle between the side wall and the bottom surface of the film structure in which it is located.

[0148] Taking the planarization layer as an example, generally, the smaller the slope angle of the sidewall of the sixth via h6, the lower the risk of fracture of the structure subsequently formed on the sidewall (such as the common electrode 2, the second passivation layer 14, and the first conductive connection electrode 10). However, the overall size of the sixth via h6 is larger, which is not conducive to improving the pixel aperture ratio. The larger the slope angle, the lower the risk of fracture of the structure subsequently formed on the sidewall, but the smaller the overall size of the sixth via h6 is, the more conducive to improving the pixel aperture ratio. Based on a comprehensive consideration of factors such as the risk of film layer fracture and the pixel aperture ratio, in the embodiment of the present disclosure, the slope angle corresponding to the sidewall of the planarization layer 13 surrounding the sixth via h6 is set to 30° to 80°.

[0149] In some embodiments, the slope angle of the sidewalls of the first passivation layer 12 surrounding the second via hole h2 is 15° to 50°; the slope angle of the sidewalls of the second passivation layer 14 surrounding the third via hole h3 is 15° to 50°.

[0150] Continuing to refer to FIG8 , for any sixth via hole h6 , the sixth via hole h6 has a third orthographic projection h6′ on the first base substrate 1 , and the portion of the common electrode 2 located within the sixth via hole h6 has a fourth orthographic projection 2′ on the first base substrate 1 ; the area of ​​the fourth orthographic projection 2′ is half of the area of ​​the third orthographic projection h6′.

[0151] In some embodiments, an edge of the fourth orthographic projection 2 ′ passes through the center of the third orthographic projection h6 ′.

[0152] In some embodiments, the shape of the third orthographic projection h6' is a third rectangle, and the shape of the fourth orthographic projection 2' is a fourth rectangle; the length of the third rectangle in the first direction X is half the length of the fourth rectangle in the first direction X; the length of the fourth rectangle in the second direction Y is equal to the length of the fourth rectangle in the second direction Y.

[0153] In some embodiments, the orthographic projection 10' of the first conductive connection electrode 10 on the first base substrate 1 overlaps the orthographic projection h6' of the sixth via h6 on the first base substrate 1. In other words, the orthographic projection area of ​​the fifth via h5 on the first base substrate 1 is less than or equal to the orthographic projection area of ​​the sixth via h6 on the first base substrate 1. Furthermore, the orthographic projection area of ​​the sixth via h6 on the first base substrate 1 is less than or equal to the orthographic projection area of ​​the first conductive connection electrode 10 on the first base substrate 1. This design ensures that the fifth via h5, the sixth via h6, and the first conductive connection electrode 10 have a high tolerance for alignment errors.

[0154] In some embodiments, the center of the orthographic projection of the sixth via hole h6 on the first base substrate 1 overlaps with the center of the orthographic projection of the first conductive connection electrode 10 on the first base substrate 1 .

[0155] In some embodiments, the second via h2, the third via h3, the fifth via h5, the sixth via h6, and the first conductive connection electrode 10 are rectangular or approximately rectangular (eg, rectangular with chamfered corners) in a cross section parallel to the first base substrate 1.

[0156] As an optional example, the length of the second via h2 in the first direction X is 3.5um, and the length of the second via h2 in the second direction Y is 5um; the length of the third via h3 in the first direction X is 3.5um, and the length of the third via h3 in the first direction X is 5um; the length of the fifth via h5 in the first direction X is 7um, and the length of the fifth via h5 in the second direction Y is 5um; the length of the sixth via h6 in the first direction X is 12um, and the length of the sixth via h6 in the first direction X is 7um; the length of the first conductive connection electrode 10 in the first direction X is 15um, and the length of the first conductive connection electrode 10 in the second direction Y is 12um.

[0157] As an optional example, the thickness of the common voltage line VCOML is approximately The thickness of the insulating layer 11 is approximately The thickness of the first electrode Ts and the second electrode Td is approximately The thickness of the active layer Ta is about The thickness of the first passivation layer 12 is approximately The thickness of the planarization layer 13 is approximately The thickness of the common electrode 2 is approximately The thickness of the second passivation layer 14 is approximately The thickness of the pixel electrode 8 is approximately At this time, the hole depth of the second via hole h2 is about 2.97 um, and the hole depth of the third via hole h3 is about 2.8 um.

[0158] Continuing to refer to the previous Figure 4, an eighth via hole h8 is formed on the common electrode 2, and the orthographic projection of the eighth via hole h8 on the first base substrate 1 completely covers the area for subsequently forming the fourth via hole h4, so as to ensure that the subsequently formed fourth via hole h4 can be connected to the second electrode Td of the thin film transistor T; the orthographic projection of the eighth via hole h8 on the first base substrate 1 also completely covers the area for subsequently forming the second via hole h2, so as to ensure that the subsequently formed second via hole h2 can be connected to the second conductive connection electrode 9.

[0159] Continuing with FIG. 2 , in some embodiments, common voltage peripheral leads 3 are provided in peripheral regions 1b on both sides of the display area 1a that are opposite each other along the first direction X. Both ends of the common voltage line VCOML extend to the peripheral regions 1b and are electrically connected to the common voltage peripheral leads 3. This design improves the speed at which the common voltage signal is loaded onto the common voltage line VCOML, which in turn further improves the speed at which the common voltage signal is loaded onto the common electrode 2.

[0160] In some embodiments, common voltage peripheral leads 3 are disposed around the display area 1a. The display substrate further includes common voltage write leads 7, which are located within the peripheral area 1b and on a side of the common voltage peripheral leads 3 away from the display area. Common voltage write leads 7 are electrically connected to the common voltage peripheral leads 3 (e.g., via a conductive connection structure 6). The voltage write leads can receive a common voltage signal provided by an external chip (not shown) and transmit the common voltage signal to the common voltage peripheral leads 3.

[0161] Based on the same inventive concept, the present disclosure also provides a display device. Figure 9 is a schematic structural diagram of a display device provided by the present disclosure. As shown in Figure 9, the display device includes the display substrate provided by the previous embodiment and a cell-aligning substrate for cell-aligning with the display substrate. Spacers and a liquid crystal layer are disposed between the display substrate and the cell-aligning substrate. A description of the display substrate can be found in the previous embodiment and will not be repeated here.

[0162] In some implementations, the display substrate may be an array substrate, and the cell substrate may be a color filter substrate; the color filter substrate may include a second base substrate and a color filter located on a side of the second base substrate facing the array substrate.

[0163] The display device provided in this embodiment can be any product or component with a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limiting the present invention.

[0164] Based on the same inventive concept, the present disclosure also provides a method for manufacturing a display device, which can be used to manufacture the display substrate provided in the previous embodiment. FIG10 is a flow chart of a method for manufacturing a display substrate provided in the present disclosure. As shown in FIG10 , the method includes:

[0165] Step S101: providing a first base substrate, wherein the first base substrate includes a display area and a peripheral area surrounding the display area.

[0166] Step S102 : forming at least one common voltage line on one side of the first base substrate, the common voltage line being located in the display area, and each common voltage line being configured with at least one conductive connection area.

[0167] Step S103 : forming a first passivation layer on a side of the common voltage line away from the first substrate.

[0168] Step S104 : forming a common electrode on a side of the first passivation layer away from the first substrate.

[0169] Step S105 : forming a second passivation layer on a side of the common electrode away from the first substrate.

[0170] Step S106: forming a pixel electrode and a first conductive connection electrode arranged in the same layer on a side of the second passivation layer away from the first base substrate, wherein the first conductive connection electrode is located in a corresponding conductive connection area, and the common electrode is electrically connected to the common voltage line through the first conductive connection electrode.

[0171] On the one hand, in the embodiment of the present disclosure, common voltage lines are provided within the display area, and each common voltage line is configured with at least one conductive connection area. The common electrode is electrically connected to the common voltage line via a first conductive connection electrode located in the conductive connection area. Compared to the technical solution in the related art that only utilizes common voltage peripheral leads located in the peripheral area to provide a common voltage signal to the common electrode, the display substrate provided by the embodiment of the present disclosure can not only utilize the common voltage peripheral leads located in the peripheral area to provide a common voltage signal to the common electrode, but can also utilize the common voltage lines located in the display area to provide a common voltage signal to the common electrode. Therefore, it can effectively increase the loading speed of the common voltage signal on the common electrode, reduce the delay of the common voltage signal, and improve the stability of the common voltage signal.

[0172] On the other hand, in the embodiment of the present disclosure, since the first conductive connection electrode and the pixel electrode are arranged in the same layer, the first conductive connection electrode and the pixel electrode can be prepared based on the same MASK process. Therefore, the setting of the first conductive connection electrode will not lead to an increase in the number of MASK processes.

[0173] FIG11 is another flow chart of a method for preparing a display substrate according to an embodiment of the present disclosure. FIG12A to FIG12J are schematic top views of a portion of an intermediate product formed by the preparation method shown in FIG11 . As shown in FIG11 to FIG12J , the preparation method includes:

[0174] Step S201: providing a first base substrate;

[0175] The first base substrate includes a display area and a peripheral area surrounding the display area.

[0176] Step S202 : forming a gate line, a gate electrode, and a common voltage line on one side of the first substrate through a single patterning process.

[0177] 12A , a first conductive material film is first formed. The first conductive material may be a metal material, such as copper, aluminum, molybdenum or other metal or alloy. The first conductive material film is then patterned based on a composition process to form patterns of the gate line GL, the gate electrode Tg and the common voltage line VCOML.

[0178] Step S203: forming an insulating layer on a side of the gate away from the first substrate.

[0179] 12B , an insulating material film is first formed. The insulating material may include silicon oxide, silicon nitride, or the like. The insulating material film is then patterned using a composition process to form an insulating layer 11. A first via h1 connected to the common voltage line VCOML is formed on the insulating layer 11.

[0180] Step S204 : forming an active layer on a side of the insulating layer away from the first substrate.

[0181] 12C , an active material film is first formed, and the active material may be an oxide-type active material. The active material film is then patterned based on a composition process to form a pattern of an active layer Ta, and the active layer Ta is located in the region where the gate Tg is located.

[0182] Step S205 : forming a data line, a first electrode, a second electrode, and a second conductive connection electrode on a side of the active layer away from the first base substrate through a single patterning process.

[0183] As shown in Figure 12D, a second conductive material film is first formed. The second conductive material can be a metal material, such as copper, aluminum, molybdenum or other metals or alloys; then the second conductive material film is patterned based on the composition process to form the pattern of the data line DL, the first electrode Ts, the second electrode Tg and the second conductive connecting electrode 9.

[0184] The first electrode and the second electrode are connected to the data active layer respectively, the first electrode is also connected to the corresponding data line, and the second conductive connection electrode is connected to the common voltage line through the corresponding first via hole.

[0185] Step S206 , forming a first passivation material film on a side of the first electrode and the second electrode away from the first substrate.

[0186] 12E , a first passivation material film 11 a is formed on the surface of the substrate shown in FIG12D through a deposition process; the first passivation material includes silicon oxide and / or silicon nitride.

[0187] Step S207 : forming a planarization layer on a side of the first passivation material film away from the first substrate through a single patterning process.

[0188] As shown in FIG12F , a planarization material film is first formed. The planarization material may include an organic material, such as photoresist. Then, the planarization material film is patterned using a composition process to form a planarization layer 13. Sixth via h6 and seventh via h7 are formed on planarization layer 13. Sixth via h6 completely covers the area where the second and third vias (fifth vias) are to be formed later. Seventh via h7 completely covers the area where the fourth via is to be formed later.

[0189] Step S208 : forming a common electrode on a side of the planarization layer away from the first base substrate through a single patterning process.

[0190] 12G , a common electrode material film is first formed. The common electrode material may include a transparent conductive material, such as a metal oxide material. Then, the common electrode material film is patterned using a patterning process to obtain a pattern of the common electrode 2. Part of the common electrode 2 is located within the sixth via hole h6.

[0191] In addition, an eighth via hole h8 is formed on the common electrode, and the orthographic projection of the eighth via hole h8 on the first base substrate completely covers an area where a fourth via hole is to be formed subsequently and an area where a second via hole is to be formed subsequently.

[0192] Step S209 : forming a second passivation material film on a side of the planarization layer away from the first substrate.

[0193] 12H , a second passivation material film 14 a is formed on the surface of the substrate shown in FIG. 12F through a deposition process; the second passivation material includes silicon oxide and / or silicon nitride.

[0194] Step S210 , performing pattern processing on the second passivation material film and the first passivation material film through a single patterning process to obtain patterns of the first passivation layer and the second passivation layer.

[0195] As shown in FIG12I , the second passivation material film and the first passivation material film are patterned through a single patterning process to obtain patterns of the first passivation layer 12 and the second passivation layer 14. A second via h2 is formed in the conductive connection region, connecting from the surface of the second passivation layer away from the first substrate to the second conductive connection electrode 9; a third via h3 is formed from the surface of the second passivation layer 14 away from the first substrate to the common electrode 2; and a fourth via h4 is formed from the surface of the second passivation layer 14 away from the first substrate to the second electrode.

[0196] The orthographic projections of the second via h2 and the third via h3 on the first base substrate are located within the area defined by the orthographic projection of the sixth via h6 on the first base substrate, and the orthographic projection of the fourth via h4 on the first base substrate is located within the area defined by the orthographic projection of the seventh via h7 on the first base substrate.

[0197] In some embodiments, the second via h2 and the third via h3 are different portions of the same via (the fifth via h5 in the previous embodiment). The orthographic projections of the second via h2 and the third via h3 on the first substrate are both located within the area covered by the orthographic projection of the sixth via h6 on the first substrate.

[0198] In the embodiment of the present disclosure, since the common electrode is electrically connected to the common voltage line through the first conductive connection electrode located on the side of the common electrode away from the first substrate, rather than being directly connected to the common voltage line through the via hole on the first passivation layer, the MASK process of the first passivation layer can also be performed after the MASK process of the common electrode; that is, the MASK process of the first passivation layer can be the same MASK process as the MASK process of the second passivation layer located on the side of the common electrode away from the first substrate (that is, the MASK process is performed on the first passivation layer and the second passivation layer at the same time), thereby effectively reducing the number of MASK processes.

[0199] Step S211 : forming a pixel electrode and a first conductive connection electrode on a side of the second passivation layer away from the first base substrate through a single patterning process.

[0200] As shown in FIG12J , a thin film of pixel electrode 8 material is first formed. The pixel electrode 8 material may include a transparent conductive material, such as a metal oxide material. Then, the pixel electrode 8 material film is patterned using a composition process to form the pattern of the pixel electrode 8 and the first conductive connection electrode 10. The pixel electrode 8 is a slit electrode. The pixel electrode 8 is connected to the second electrode Td of the corresponding thin-film transistor through a fourth via hole. The first conductive connection electrode 10 is connected to the corresponding second conductive connection electrode 9 through a second via hole h2. The first conductive connection electrode 10 is connected to the common electrode 2 through a third via hole h3.

[0201] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, wherein: include: A first base substrate, comprising a display area and a peripheral area surrounding the display area; At least one common voltage line is located in the display area, and each common voltage line is configured with at least one conductive connection area; a first passivation layer, located on a side of the common electrode line away from the first substrate; a common electrode, located on a side of the first passivation layer away from the first substrate; a second passivation layer, located on a side of the common electrode away from the first substrate; a pixel electrode, located on a side of the second passivation layer away from the first substrate; The first conductive connection electrode is located in the corresponding conductive connection area and is provided in the same layer as the pixel electrode. The common electrode is electrically connected to the common voltage line through the first conductive connection electrode.

2. The display substrate according to claim 1, wherein Also includes: a plurality of thin film transistors, wherein the thin film transistors are located between the first substrate and the first passivation layer; The common voltage line is arranged in the same layer as the gate of the thin film transistor.

3. The display substrate according to claim 2, wherein: The first electrode and the second electrode of the thin film transistor are located on a side of the gate of the thin film transistor away from the first substrate, and an insulating layer is provided between the first electrode and the second electrode of the thin film transistor and the gate of the thin film transistor; The display substrate further includes: a second conductive connection electrode located in the corresponding conductive connection region and provided in the same layer as the first electrode and the second electrode of the thin film transistor, the second conductive connection electrode being in contact with the common voltage line through a first via hole in the insulating layer; The first conductive connection electrode is electrically connected to the common voltage line through the second conductive connection electrode.

4. The display substrate according to claim 3, wherein: In the conductive connection region, a second via hole is formed, which is connected from a surface of the second passivation layer away from the first substrate to the second conductive connection electrode, and a third via hole is formed, which is connected from a surface of the second passivation layer away from the first substrate to the common electrode; The first conductive connection electrode contacts the corresponding second conductive connection electrode through the second via hole, and the first conductive connection electrode contacts the portion of the common electrode located in the conductive connection area through the third via hole.

5. The display substrate according to claim 4, wherein: Also includes: a plurality of gate lines and a plurality of data lines, wherein the gate lines extend along a first direction and the data lines extend along a second direction, the first direction intersecting the second direction, and the plurality of gate lines and the plurality of data lines defining a plurality of pixel areas arranged in an array along the first direction and the second direction; The pixel area includes a light emitting area and a non-light emitting area arranged along the second direction, and the non-light emitting area is closer to the gate line corresponding to the pixel area than the light emitting area; The thin film transistor is formed in the non-light-exiting area, a fourth via hole is further formed in the non-light-exiting area, and the fourth via hole is connected to the second electrode of the thin film transistor from the surface of the second passivation layer away from the first substrate. The pixel electrode is formed in the light-exiting area; The gate electrode of the thin film transistor is electrically connected to the corresponding gate line, the first electrode of the thin film transistor is electrically connected to the corresponding data line, and the pixel electrode is electrically connected to the second electrode of the thin film transistor through the corresponding fourth via hole; An extension direction of the common voltage line is parallel to an extension direction of the gate line. The common voltage line is located in the non-light emitting area and on a side of the thin film transistor close to the light emitting area. The display substrate according to claim 5 , wherein: The second via hole and the third via hole are both located in the non-light-exiting area and between the corresponding common voltage line and the gate line.

7. The display substrate according to claim 6, wherein: The second via holes and the third via holes are arranged along the second direction.

8. The display substrate according to claim 6, wherein: The second via holes and the fourth via holes are arranged along the first direction; The third via holes and the fourth via holes are arranged along the first direction.

9. The display substrate according to any one of claims 6 to 8, wherein: The first conductive connection electrode and the two pixel electrodes adjacent to each other in the second direction are spaced at equal distances in the second direction.

10. The display substrate according to any one of claims 5 to 9, wherein: In the conductive connection area, a fifth via hole is formed, which is connected from a surface of the second passivation layer away from the first substrate to the second conductive connection electrode and the common electrode; The second via hole is a portion of the fifth via hole connected to the second conductive connection electrode, and the third via hole is a portion of the fifth via hole connected to the common electrode.

11. The display substrate according to claim 10, wherein: For any one of the fifth via holes, the bottom of the fifth via hole has a first orthographic projection on the first base substrate, and the portion of the common electrode exposed by the fifth via hole has a second orthographic projection on the first base substrate; The area of ​​the second orthographic projection is half the area of ​​the first orthographic projection.

12. The display substrate according to claim 11, wherein: An edge of the second orthographic projection passes through a center of the first orthographic projection.

13. The display substrate according to claim 11 or 12, wherein: The shape of the first orthographic projection is a first rectangle, and the shape of the second orthographic projection is a second rectangle; The length of the first rectangle in the first direction is half the length of the second rectangle in the first direction; The length of the first rectangle in the second direction is equal to the length of the second rectangle in the second direction.

14. The display substrate according to any one of claims 10 to 13, wherein: The fifth via holes and the first via holes are arranged along the second direction.

15. The display substrate according to any one of claims 10 to 14, wherein: A center of an orthographic projection of the fifth via hole on the first base substrate overlaps with a center of an orthographic projection of the first conductive connection electrode on the first base substrate.

16. The display substrate according to any one of claims 4 to 15, wherein: In the same conductive connection region, an orthographic projection of the bottom of the second via hole on the first substrate has a first projection area, and an orthographic projection of the bottom of the third via hole on the first substrate has a second projection area; The first projected area is equal to the second projected area.

17. The display panel according to any one of claims 4 to 16, wherein: In the same conductive connection region, the first conductive connection electrode and the corresponding second conductive connection electrode have a first contact area, and the first conductive connection electrode and the portion of the common electrode located in the conductive connection region have a second contact area; The first contact area is equal to the second contact area.

18. The display substrate according to any one of claims 4 to 17, wherein: Also includes: a planarization layer located between the first passivation layer and the common electrode, wherein a sixth via hole is formed in the conductive connection region of the planarization layer, and a portion of the common electrode is located in the sixth via hole; The orthographic projection of the sixth via hole on the first base substrate covers the orthographic projection of the second via hole on the first base substrate and the orthographic projection of the third via hole on the first base substrate.

19. The display substrate according to claim 18, wherein: For any one of the sixth via holes, the sixth via hole has a third orthographic projection on the first substrate, and a portion of the common electrode located in the sixth via hole has a fourth orthographic projection on the first substrate; The area of ​​the fourth orthographic projection is half the area of ​​the third orthographic projection.

20. The display substrate according to claim 19, wherein An edge of the fourth orthographic projection passes through a center of the third orthographic projection.

21. The display substrate according to claim 19 or 20, wherein: The shape of the third orthographic projection is a third rectangle, and the shape of the fourth orthographic projection is a fourth rectangle; The length of the third rectangle in the first direction is half the length of the fourth rectangle in the first direction; The length of the fourth rectangle in the second direction is equal to the length of the fourth rectangle in the second direction.

22. The display substrate according to any one of claims 18 to 21, wherein: The orthographic projection of the first conductive connection electrode on the first base substrate covers the orthographic projection of the sixth via hole on the first base substrate.

23. The display substrate according to any one of claims 18 to 22, wherein: A center of an orthographic projection of the sixth via hole on the first base substrate overlaps with a center of an orthographic projection of the first conductive connection electrode on the first base substrate.

24. The display substrate according to any one of claims 18 to 23, wherein: The slope angle corresponding to the sidewall of the planarization layer surrounding the sixth via hole is 30° to 80°.

25. The display substrate according to any one of claims 4 to 24, wherein: The slope angle corresponding to the sidewall of the first passivation layer surrounding the second via hole is 15° to 50°; The slope angle corresponding to the sidewall of the second passivation layer surrounding the third via hole is 15° to 50°.

26. The display substrate according to any one of claims 4 to 25, wherein: Also includes: Common voltage peripheral leads, located in the peripheral area; The common electrode extends to the peripheral area and is electrically connected to the common voltage peripheral lead.

27. The display substrate according to claim 26, wherein: Both ends of the common voltage line extend to the peripheral area and are electrically connected to the common voltage peripheral lead.

28. The display substrate according to claim 26 or 27, wherein: The common voltage peripheral lead is arranged around the display area; The display substrate further includes: a common voltage writing lead located in the peripheral area and located on a side of the common voltage peripheral lead away from the display area; The common voltage writing lead is electrically connected to the common voltage peripheral lead.

29. A display device, wherein: include: The display substrate and the cell-matching substrate according to any one of claims 1 to 28, wherein the display substrate and the cell-matching substrate are arranged opposite to each other.

30. A method for preparing a display substrate according to any one of claims 1 to 28, wherein: include: Providing a first base substrate, the first base substrate comprising a display area and a peripheral area surrounding the display area; forming at least one common voltage line on one side of the first base substrate, the common voltage line being located in the display area, and each common voltage line being configured with at least one conductive connection area; forming a first passivation layer on a side of the common voltage line away from the first substrate; forming a common electrode on a side of the first passivation layer away from the first substrate; forming a second passivation layer on a side of the common electrode away from the first substrate; A pixel electrode and a first conductive connection electrode are formed on the same layer of the second passivation layer on a side away from the first base substrate. The first conductive connection electrode is located in the corresponding conductive connection area. The common electrode is electrically connected to the common voltage line through the first conductive connection electrode.

31. The preparation method according to claim 30, wherein Before the step of forming the first passivation layer, the method further includes: Forming a thin film transistor and a second conductive connection electrode on one side of the first substrate, including: forming a gate through a patterning process, forming an active layer through a patterning process, and forming a first electrode, a second electrode, and a second conductive connection electrode through a patterning process; wherein an insulating layer is provided between the first electrode, the second electrode, and the gate, and the second conductive connection electrode contacts the common voltage line through a first via hole in the insulating layer; The gate electrode and the common electrode line are formed based on the same patterning process; The first conductive connection electrode is electrically connected to the common voltage line through the second conductive connection electrode.

32. The preparation method according to claim 31, wherein The steps of forming a first passivation layer, forming a common electrode, forming a second passivation layer, and forming a pixel electrode specifically include: forming a first passivation material film on a side of the common voltage line away from the first substrate; forming a common electrode on a side of the first passivation material film away from the first substrate through a patterning process; forming a second passivation material film on a side of the common electrode away from the first substrate; Patterning the second passivation material film and the first passivation material film through a single patterning process to form a second via hole in the conductive connection region, the second via hole being connected from a surface of the second passivation layer away from the first substrate to the second conductive connection electrode, and a third via hole being connected from a surface of the second passivation layer away from the first substrate to the common electrode; The pixel electrode and the first conductive connection electrode are formed by a patterning process. The first conductive connection electrode contacts the corresponding second conductive connection electrode through the second via hole. The first conductive connection electrode contacts the portion of the common electrode located in the conductive connection area through the third via hole.

33. The preparation method according to claim 32, wherein The second via hole and the third via hole are different parts of the same via hole.

34. The preparation method according to claim 32 or 33, wherein Between the step of forming the first passivation material film and the step of forming the common electrode, the method further includes: forming a planarization layer on a side of the first passivation material film away from the first substrate through a patterning process, wherein the planarization layer has a sixth via hole formed in the conductive connection area; Part of the common electrode formed in the subsequent steps is located in the sixth via hole, and the orthographic projections of the second via hole and the third via hole formed in the subsequent steps on the first base substrate are both located in the area covered by the orthographic projection of the sixth via hole on the first base substrate.

Images