Multi-path battery charger

Abstract

A semiconductor device includes a wired input / output (204), a wireless input / output (206), and a battery (202). A wired charging path between the wired input / output (204) and the battery (202) includes a first transistor and a second transistor. A wireless charging path between the wireless input / output (206) and the battery (202) includes a third transistor and a second transistor.

Description

Background Art

[0001] The present disclosure generally relates to devices and methods for wireless and wired charging systems.

[0002] Charging systems often use multiple integrated circuits to perform various functions. For example, in some charging systems, a battery charging integrated circuit is used to manage the charging of the battery, a power multiplexing integrated circuit is used to manage the switching between wired and wireless charging modes, and a wireless power integrated circuit is used to manage wireless charging. However, these charging systems can be inefficient and require a significant footprint on multiple integrated circuits. Summary of the invention

[0003] In one embodiment, a semiconductor device is disclosed, the semiconductor device including a wired input / output, a wireless input / output and a battery. A wired charging path between the wired input / output and the battery includes a first transistor and a second transistor. A wireless charging path between the wireless input / output and the battery includes a third transistor and a second transistor.

[0004] In another embodiment, a method is disclosed, the method including detecting a current difference across a first transistor of a semiconductor device. The semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor are disposed on a wired charging path of the semiconductor device between a wired input / output of the semiconductor device and a battery of the semiconductor device. The first transistor and the third transistor are disposed on a wireless charging path of the semiconductor device between a wireless input / output of the semiconductor device and the battery. The method also includes generating a signal based at least in part on the current difference, and transmitting the signal to a rectifier controller of the semiconductor device. The rectifier controller is configured to control activation of the third transistor based at least in part on the signal.

[0005] In another embodiment, an integrated circuit is disclosed that includes a wired input / output, a wireless input / output, and a battery. A wired charging path between the wired input / output and the battery includes a wired connector transistor, a regulator transistor, and a charger transistor. A wireless charging path between the wireless input / output and the battery includes a rectifier transistor, a regulator transistor, and a charger transistor. The integrated circuit also includes a rectifier controller and a power flow detector circuit, the rectifier controller being configured to control activation of the rectifier transistor, the power flow detector circuit being configured to detect a current difference across the regulator transistor, generate a signal based at least in part on the current difference, and transmit the signal to the rectifier controller. The rectifier controller is configured to control activation of the rectifier transistor based at least in part on the signal.

[0006] The foregoing summary of the invention is illustrative only and is not intended to be limiting in any way. In addition to the above illustrative aspects, embodiments and features, other aspects, embodiments and features will become apparent by reference to the accompanying drawings and the following specific examples. In the accompanying drawings, the same reference numerals represent the same or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a circuit diagram of a charging system according to an embodiment.

[0008] Figure 2 is a circuit diagram of a charging system according to another embodiment.

[0009] Figure 3 According to the embodiment Figure 2 Schematic diagram of example signal states output by a power flow detector of a charging system.

[0010] Figure 4 is a circuit diagram of a charging system according to another embodiment.

[0011] Figure 5 is a circuit diagram of a charging system according to another embodiment.

[0012] Figure 6 According to the embodiment Figure 5 Schematic diagram of example signal states output by a power flow detector of a charging system. Specific embodiments

[0013] Figure 1 1 is a diagram of an example charging system 100 that includes a battery 102, a wired input / output 104, a wireless input / output 106, a battery charger circuit 110, a power multiplexer (MUX) circuit 130, and a wireless power circuit 150. The charging system 100 uses discrete integrated circuits for each of the battery charger circuit 110, the power MUX circuit 130, and the wireless power circuit 150. The battery 102 may include, for example, a capacitor or other device configured to store and release energy. The wired input / output 104 may include, for example, a wired connection such as a universal serial bus (USB) port or other wired connection. The wireless input / output 106 may include, for example, a coil or other wireless connection. For ease of understanding and reference, nodes between various components or connections in the charging system 100 are labeled, such as VRECT, VBUS, VMID, VSYS, and VBAT.

[0014] Battery charger circuit 110 includes linear charger controller 112 controlling switching element 114, coil 116, switching charger controller 118, and charger transistors 120, 122, and 124 such as power transistors or other switching transistors. Switching charger controller 118 controls activation of charger transistors 120, 122, and 124.

[0015] The power MUX circuit 130 includes a power MUX controller 132 that controls activation of power MUX transistors 134, 136, 138, and 140, such as power transistors or other switching transistors, depending on which of the wired input / output 104 and the wireless input / output 106 is in use. For example, the power MUX controller 132 may activate the power MUX transistors 134 and 136 when the wired input / output 104 is in use, and the power MUX controller 132 may activate the power MUX transistors 138 and 140 when the wired input / output 104 is in use.

[0016] The wireless power circuit 150 includes a low dropout regulator (LDO) controller 152 that controls activation of a low dropout regulator (LDO) transistor 154 and a rectifier controller 156 that controls activation of rectifier transistors 158, 160, 162, and 164 to supply power to a wireless input / output 106, such as a coil.

[0017] like Figure 1 As shown, the wired current flow path from the wired input / output 104 to the battery 102 passes through two pairs of transistors, namely, power MUX transistors 134 and 136 and charger transistors 120 and 122, and the wireless current flow path from the wireless input / output 106 flows through three pairs of transistors, namely, one of the rectifier transistors 158 and 164, the LDO transistor 154, the power MUX transistors 138 and 140, and the charger transistors 120 and 122.

[0018] Reference Figure 2 , shows a charging system 200 according to an illustrative embodiment. The charging system 200 provides higher efficiency than the charging system 100 by integrating wired and wireless charging functions into a single semiconductor device such as an integrated circuit, a printed circuit board (PCB), or other semiconductor device. In addition, the charging system 200 also reduces the number of components and transistors on each of the wired and wireless charging paths compared to the charging system 100, thereby reducing ohmic impedance and improving efficiency.

[0019] The charging system 200 includes a battery 202, a wired input / output 204, a wireless input / output 206, a linear charger controller 208 that controls a switching element 210, a coil 212, a switching charger controller 214 that controls charger transistors 216 and 218, an LDO controller 220 that controls an LDO transistor 222, a connector controller 224 that controls a connector transistor 226, and a rectifier controller 228 that controls rectifier transistors 230, 232, 234, and 236. For ease of understanding and reference, nodes between various components or connections in the charging system 200 are labeled, such as VBUS, VRECT, VMID, VSYS, and VBAT.

[0020] like Figure 2 As shown, the wired charging path and the wireless charging path merge at VRECT, wherein the wired charging path and the wireless charging path each include only three transistors. For example, the wired charging path includes the connector transistor 226, the LDO transistor 222, and the charger transistor 216, while the wireless charging path includes the LDO transistor 222, the charger transistor 216, and one of the rectifier transistors 230 and 236. In some embodiments, the LDO transistor 222 is optional, for example, Figure 5 shown.

[0021] However, there are some challenges in reducing the number of transistors in each charging path for both wired and wireless charging. For example, Figure 1 The power MUX circuit 130 in controls multiplexing between the wired input / output 104 and the wireless input / output 106 and includes back-to-back power MUX transistors 138 and 140, which inhibit current flow from VBAT to VRECT in the wireless power circuit 150 during a low quiescent current (Iq) state of the charging system 100, while the back-to-back power MUX transistors 138 and 140 are not present in the charging system 200.

[0022] To handle the reverse current from VBAT to VRECT in the low Iq state, the charging system 200 also includes a power flow detector circuit 238, which is configured to measure the current difference between VMID and VRECT, for example, the current difference across the LDO transistor 222 in this embodiment. In other embodiments, the power flow detector circuit 238 can measure the current difference between any other nodes of the charging system 200 or across any other components of the charging system 200.

[0023] refer to Figure 2 and Figure 3, the power flow detector circuit 238 is configured to provide an Iq state signal 240 to the connector controller 224, the rectifier controller 228, both, or any other component of the charging system 200 in response to the measurement of the current difference between VRECT and VMID. For example, if the current flow at VRECT is less than the current flow at VMID by a first threshold amount, such as 300 mV or any other amount, the power flow detector circuit 238 is configured to provide an Iq state signal 240 to the connector controller 224, the rectifier controller 228, or both, which commands the connector controller 224, the rectifier controller 228, or both to enter a standby state, such as deactivating one or more of their respective corresponding transistors. For example, in the standby state, the Iq state signal 240 can be set to low. In some embodiments, in response to the current flow at VRECT being less than the current flow at VMID by a first threshold amount, the Iq state signal 240 can cause some or all active circuits on the wireless charging path to enter a standby state. Examples of active circuits on the wireless charging path may include a rectifier controller 228, a ping detection circuit, an analog infrastructure LDO, a bandgap circuit, or any other circuitry for the wireless charging path of a charging system.

[0024] In another example, if the current flow at VRECT is greater than the current flow at VMID by a second threshold amount, such as 100 mV or any other amount, the power flow detector circuit 238 is configured to provide an Iq state signal 240 to the connector controller 224, the rectifier controller 228, or both, which commands the connector controller 224, the rectifier controller 228, or both to enter an active state, for example, to activate one or more of their respective corresponding transistors. For example, in the active state, the Iq state signal 240 can be set high. In some embodiments, in response to the current flow at VRECT being greater than the current flow at VMID by a second threshold amount, the Iq state signal 240 can cause some or all active circuits on the wireless charging path to enter an active state. In some embodiments, for example, the wired charging path, the wireless charging path, or both can begin to supply power to VRECT and increase VRECT to a second threshold amount higher than VMID, and the Iq state signal 240 can be used to drive the charging system 200 into an active state to begin performing charging or power supply operations, such as ping detection or other operations.

[0025] Since the wired current path and the wireless current path use the same components between VRECT and VBAT, the wired current path and the wireless current path can be operated simultaneously during startup without additional control to automatically charge the VRECT node in situations such as a dead battery. In some embodiments, for example, even if the battery 202 does not have enough power to supply power to the wireless input / output 206, the wired input / output 104 can be used to supply power to the wireless input / output 206, and a minimum number of intervening transistors are used, for example, only the connector transistor 226 and the rectifier transistors 230 and 236 are used in the power supply path between the wired input / output 204 and the wireless input / output 206.

[0026] Continue to refer Figure 2 In some embodiments, the charging system 200 further includes a charging detector circuit 242 that measures the current difference between VMID and VBAT and is configured to send a charging mode signal 244 to the linear charger controller 208 and the switching charger controller 214 to enable or disable the charging operation based on the current difference. For example, in some embodiments, the charging detector circuit 242 can be configured to send the charging mode signal 244 to the linear charger controller 208 and the switching charger controller 214 to command the linear charger controller 208 and the switching charger controller 214 to enable the charging operation in response to the current at VMID being greater than the current at VBAT, and the current at VMID being greater than the current at VBAT indicates that there is excess power available to charge the battery 202.

[0027] refer to Figure 4, a charging system 300 according to another embodiment will be described. The charging system 300 includes similar components to the charging system 200, including a battery 302, a wired input / output 304, a wireless input / output 306, a linear charger controller 308 controlling a switching element 310, a coil 312, a switching charger controller 314 controlling charger transistors 316 and 318, an LDO controller 320 controlling an LDO transistor 322, a connector controller 324 controlling a connector transistor 326, and a rectifier controller 328 controlling rectifier transistors 330, 332, 334, and 336, a power flow detector circuit 338 configured to send an Iq state signal 340 to the rectifier controller 328, and a charging detector circuit 342 configured to send a charging mode signal 344 to the linear charger controller 308 and the switching charger controller 314. For ease of understanding and reference, nodes between various components or connections in the charging system 300 are labeled, such as VBUS, VRECT, VMID, VSYS, and VBAT.

[0028] The components of charging system 300 are configured to operate in a similar manner to charging system 200 described above, except that Figure 4 As shown, the wired charging path from the wired input / output 304 to the battery 302 is connected at VMID instead of VRECT. By connecting the wired charging path at VMID instead of VRECT, the wired charging path gains the benefit of only passing through two transistors from VBUS to VBAT, which are the connector transistor 326 and the charger transistor 316, which provides higher efficiency for the wired charging path during wired charging, at the expense of reduced efficiency between the wired input / output 304 and the wireless input / output 306 when the wireless input / output 306 is supplied with power by the wired input / output 304 due to the addition of the LDO transistor 322 in the path. In addition, in some embodiments, it may be necessary to utilize a separate current sensing circuit to detect backflow or other current in the wired charging path because the measurement of the power flow detector circuit 338 is between VRECT and VMID across the LDO transistor 322, and the LDO transistor 322 is no longer in the wired charging path from VBUS to VBAT.

[0029] refer to Figure 5, a charging system 400 according to another embodiment will be described. The charging system 400 includes similar components to the charging system 200, including a battery 402, a wired input / output 404, a wireless input / output 406, a linear charger controller 408 controlling a switching element 410, a coil 412, a switching charger controller 414 controlling charger transistors 416 and 418, a connector controller 424 controlling a connector transistor 426, a rectifier controller 428 controlling rectifier transistors 430, 432, 434, and 436, a power flow detector circuit 438 configured to send an Iq state signal 440 to the rectifier controller 428, the connector controller 424, or both, and a charging detector circuit 442 configured to send a charging mode signal 444 to the linear charger controller 408 and the switching charger controller 414. For ease of understanding and reference, nodes between various components or connections in the charging system 400 are labeled, such as VBUS, VRECT, VSYS, and VBAT.

[0030] The components of charging system 400 are configured to operate in a similar manner to charging system 200 described above, except that Figure 5 As shown, the LDO transistor has been removed, the node label of VMID no longer exists, the power flow detector circuit 438 measures the current difference across the charger transistor 416, and the charge detector circuit 442 measures the current difference between VRECT and VBAT. Figure 5 As shown, the wired charging path from the wired input / output 404 to the battery 402 is connected at VRECT and passes through only two transistors from VBUS to VBAT, namely the connector transistor 426 and the charger transistor 416. Similarly, the wireless charging path also passes through only two transistors, namely the charger transistor 416 and one of the rectifier transistors 430 and 436. The power path between the wired input / output 404 and the wireless input / output 406 is the same as in the charging system 200. As shown in FIG. Figure 5 and Figure 6 As shown, the power flow detector circuit 438 of the charging system 400 utilizes the difference between VRECT and VBAT, such as across the charger transistor 416, rather than VRECT and VMID ( Figure 2 and Figure 3 ) to determine whether to command the rectifier controller 428, the connector controller 424, or both to enter an active state or a standby state in a manner similar to the charging system 200 described above.

[0031] By integrating the functionality of wired and wireless charging into a smaller number of integrated circuits or one integrated circuit as described in the above embodiments, additional efficiencies can be achieved in terms of circuit footprint and charging system efficiency. For example, according to the above embodiments, reducing the number of transistors in each wired and wireless charging path can reduce the ohmic impedance of the charging path and improve the efficiency of the charging system. In addition, by integrating the wired, wireless, power, and charging functions into a single integrated circuit, the circuit area can be significantly reduced, including, for example, a 30% reduction in circuit area compared to a charging system that includes discrete integrated circuits for each function.

[0032] The terms used herein are only used to describe specific embodiments and are not intended to limit the present invention. The singular forms "a", "an" and "the" used herein are also intended to include plural forms, unless the context clearly indicates otherwise. It can be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or combinations thereof.

[0033] In the following claims, if any means or step plus function elements are present, their corresponding structures, materials, acts, and equivalents are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The embodiments disclosed herein are presented for illustration and description purposes, but are not intended to be exhaustive or limited to the invention in the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments are selected and described in order to best explain the principles and practical application of the invention and to enable others of ordinary skill in the art to understand the various embodiments of the invention with various modifications suitable for the intended specific use.

Claims

1. A semiconductor device comprising: Wired input / output; Wireless input / output; Battery; A wired charging path between the wired input / output and the battery, the wired charging path comprising: a first transistor; and a second transistor; A wireless charging path between the wireless input / output and the battery, the wireless charging path comprising: a third transistor; and the second transistor.

2. The semiconductor device according to claim 1, wherein The semiconductor device further comprises: a wireless rectifier circuit comprising a rectifier controller configured to control activation of the third transistor; and A power flow detector circuit is configured to detect a current difference across the second transistor, the power flow detector circuit is configured to transmit a signal to the rectifier controller, and the rectifier controller is configured to control activation of the third transistor based at least in part on the signal.

3. The semiconductor device according to claim 2, wherein: The semiconductor device further includes a connector controller configured to control activation of the first transistor; as well as The power flow detector circuit is configured to transmit the signal to the connector controller, and the connector controller is configured to control activation of the first transistor based at least in part on the signal.

4. The semiconductor device according to claim 2, wherein: The power flow detector circuit is configured to: transmitting the signal having a first value in response to the current difference across the second transistor being less than a first threshold; as well as In response to the current difference across the second transistor being greater than a second threshold, the signal having a second value is transmitted.

5. The semiconductor device according to claim 1, wherein The wireless charging path further includes a fourth transistor disposed between the third transistor and the second transistor.

6. The semiconductor device according to claim 5, wherein: The wired charging path further includes the fourth transistor, which is disposed between the first transistor and the second transistor.

7. The semiconductor device according to claim 1, wherein The semiconductor device further comprises: a fourth transistor, the fourth transistor being arranged between the third transistor and the second transistor on the wireless charging path; a charger circuit, the charger circuit comprising a charger controller configured to control activation of the second transistor; a regulator controller configured to control activation of the fourth transistor; a wireless rectifier circuit comprising a rectifier controller configured to control activation of the third transistor; and A power flow detector circuit is configured to detect a current difference across the fourth transistor, the power flow detector circuit is configured to transmit a signal to the rectifier controller, and the rectifier controller is configured to control activation of the third transistor based at least in part on the signal.

8. The semiconductor device according to claim 7, wherein: The power flow detector circuit is configured to: transmitting the signal having a first value in response to the current difference across the fourth transistor being less than a first threshold; as well as In response to the current difference across the fourth transistor being greater than a second threshold, the signal having a second value is transmitted.

9. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: a charger controller configured to control activation of the second transistor; and A charge detector circuit, the charge detector circuit being configured to: detecting a first current at a first connection node between the second transistor and the third transistor; detecting a second current at a second connection node between the second transistor and the battery; and A signal is transmitted to the charger controller based at least in part on the first current and the second current, and the charger controller is configured to control activation of the second transistor based at least in part on the signal.

10. The semiconductor device according to claim 9, wherein The charge detector circuit is configured to: In response to the first current being greater than the second current, transmitting the signal having a first value; as well as In response to the first current being less than or equal to the second current, the signal having a second value is transmitted.

11. The semiconductor device according to claim 10, wherein The first value corresponds to a command to activate a battery charging operation of the semiconductor device.

12. A method performed by hardware, the method comprising: detecting a current difference across a first transistor of a semiconductor device, the semiconductor device comprising the first transistor, a second transistor, and a third transistor, the first transistor and the second transistor being disposed on a wired charging path of the semiconductor device between a wired input / output of the semiconductor device and a battery of the semiconductor device, and the first transistor and the third transistor being disposed on a wireless charging path of the semiconductor device between a wireless input / output of the semiconductor device and the battery; generating a signal based at least in part on the current difference; as well as The signal is transmitted to a rectifier controller of the semiconductor device, the rectifier controller being configured to control activation of the third transistor based at least in part on the signal.

13. The method according to claim 12, wherein: The method also includes transmitting the signal to a connector controller of the semiconductor device, the connector controller being configured to control activation of the second transistor based at least in part on the signal.

14. The method according to claim 12, wherein: Generating the signal based at least in part on the current difference includes: generating the signal having a first value in response to the current difference across the first transistor being less than a first threshold; and In response to the current difference across the first transistor being greater than a second threshold, the signal having a second value is generated.

15. The method according to claim 12, wherein: The method further comprises: detecting a first current at a first connection node between the first transistor and the third transistor; detecting a second current at a second connection node between the first transistor and the battery; generating a second signal based at least in part on the first current and the second current; and The second signal is transmitted to a charger controller of the semiconductor device, the charger controller being configured to control activation of the first transistor based at least in part on the second signal.

16. The method according to claim 15, wherein: Generating the second signal comprises: In response to the first current being greater than the second current, generating the second signal having a first value; and In response to the first current being less than or equal to the second current, the signal having a second value is generated.

17. The method according to claim 16, wherein: The first value corresponds to a command to activate a battery charging operation of the semiconductor device.

18. The method according to claim 12, wherein: The method further comprises: detecting a first current at a first connection node between the first transistor and a fourth transistor of the semiconductor device, the fourth transistor being disposed between the first transistor and the battery along the wireless charging path; detecting a second current at a second connection node between the fourth transistor and the battery; generating a second signal based at least in part on the first current and the second current; and The second signal is transmitted to a charger controller of the semiconductor device, the charger controller being configured to control activation of the fourth transistor based at least in part on the second signal.

19. An integrated circuit comprising: Wired input / output; Wireless input / output; Battery; A wired charging path between the wired input / output and the battery, the wired charging path comprising: Wired connector transistor; a regulator transistor; and Charger transistor; A wireless charging path between the wireless input / output and the battery, the wireless charging path comprising: Rectifier transistor; the regulator transistor; and Charger transistor; a rectifier controller configured to control activation of the rectifier transistor; and A power flow detector circuit, the power flow detector circuit being configured to: detecting a current difference across the regulator transistor; generating a signal based at least in part on the current difference; and The signal is transmitted to the rectifier controller, which is configured to control activation of the rectifier transistor based at least in part on the signal.

20. The integrated circuit of claim 19, wherein: The integrated circuit further comprises: a charger controller configured to control activation of the charger transistor; and A charge detector circuit, the charge detector circuit being configured to: detecting a first current at a first connection node between the rectifier transistor and the charger transistor; detecting a second current at a second connection node between the charger transistor and the battery; generating a second signal based at least in part on the first current and the second current; and The second signal is transmitted to the charger controller, and the charger controller is configured to control activation of the charger transistor based at least in part on the second signal.

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