Display panel and display device

Abstract

A display panel and a display device, the display panel comprising: a substrate (81), a plurality of first initial signal lines (2Vinit1), a plurality of second initial signal lines (2Vinit2), a plurality of first initial connecting lines (3Vinit1), and a plurality of second initial connecting lines (3Vinit2), orthographic projections of the plurality of first initial signal lines (2Vinit1) on the substrate (81) extending along a first direction (X) and being distributed at intervals along a second direction (Y), the first direction (X) and the second direction (Y) intersect; orthographic projections of the plurality of second initial signal lines (2Vinit2) on the substrate (81) extend along the first direction (X) and are distributed at intervals along the second direction (Y); the plurality of first initial connecting lines (3Vinit1) and the first initial signal lines (2Vinit1) are located on different conductive layers, orthographic projections of the plurality of first initial connecting lines (3Vinit1) on the substrate (81) extend along a second direction (Y) and are distributed at intervals along a first direction (X), and the first initial connecting lines (3Vinit1) are connected to at least part of the first initial signal lines (2Vinit1) intersecting with the orthographic projections of the first initial connecting lines (3Vinit1) on the substrate (81) through via holes; the plurality of second initial connecting lines (3Vinit2) and the second initial signal lines (2Vinit2) are located on different conductive layers, orthographic projections of the plurality of second initial connecting lines (3Vinit2) on the substrate (81) extend along the second direction (Y) and are distributed at intervals along the first direction (X), and the second initial connecting lines (3Vinit2) are connected to at least part of the second initial signal lines (2Vinit2) intersecting with the orthographic projections of the second initial connecting lines (3Vinit2) on the substrate (81) through via holes. The display panel has a good display effect.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related art, display panels have problems such as poor display uniformity and low-frequency flicker.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a display panel is provided, comprising: a base substrate, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of first initial connecting lines, and a plurality of second initial connecting lines, wherein the orthographic projections of the plurality of first initial signal lines on the base substrate extend along a first direction and are spaced apart along a second direction, and the first direction and the second direction intersect; a plurality of second initial signal lines and the first initial signal lines are located in the same conductive layer, and the orthographic projections of the second initial signal lines on the base substrate extend along the first direction and are spaced apart along the second direction; a plurality of first initial connecting lines and the first initial signal lines are located in different conductive layers, the orthographic projections of the plurality of first initial connecting lines on the base substrate extend along the second direction and are spaced apart along the first direction, and the first initial connecting lines are connected to at least some of the first initial signal lines whose orthographic projections on the base substrate intersect with them through vias; a plurality of second initial connecting lines and the first initial connecting lines are located in the same conductive layer, the orthographic projections of the plurality of second initial connecting lines on the base substrate extend along the second direction and are spaced apart along the first direction, and the second initial connecting lines are connected to at least some of the second initial signal lines whose orthographic projections on the base substrate intersect with them through vias.

[0006] In an exemplary embodiment of the present disclosure, the display panel further includes: a second conductive layer and a third conductive layer, the second conductive layer is located on one side of the base substrate, and the second conductive layer includes the first initial signal line and the second initial signal line; the third conductive layer is located on the side of the second conductive layer away from the base substrate, and the third conductive layer includes the first initial connection line and the second initial connection line.

[0007] In an exemplary embodiment of the present disclosure, the display panel further includes a pixel driving circuit, the pixel driving circuit including a driving transistor, a first transistor, and a capacitor, wherein the first electrode of the capacitor is connected to the gate of the driving transistor, the first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the gate of the driving transistor. The display panel further includes: a first conductive layer, the first conductive layer is located between the base substrate and the second conductive layer, the first conductive layer includes a first conductive portion, the first conductive portion is used to form the gate of the driving transistor and the first electrode of the capacitor; the second conductive layer further includes: a second conductive portion, the orthographic projection of the second conductive portion on the base substrate and the orthographic projection of the first conductive portion on the base substrate at least partially overlap, the second conductive portion is used to form the second electrode of the capacitor; the third conductive layer further includes: a first bridging portion, the first bridging portion is connected to the first conductive portion through a via, and is connected to the second electrode of the first transistor.

[0008] In an exemplary embodiment of the present disclosure, the display panel also includes a pixel driving circuit, which includes a driving transistor, a fourth transistor, and a second transistor; the first electrode of the fourth transistor is connected to the data line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the second reset signal line; the first electrode of the second transistor is connected to the gate of the driving transistor, the second electrode is connected to the second electrode of the driving transistor, and the gate is connected to the gate line.

[0009] In an exemplary embodiment of the present disclosure, the display panel also includes a pixel driving circuit, which includes a driving transistor and a second transistor, wherein the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode is connected to the second electrode of the driving transistor; the display panel also includes: an active layer and a second conductive layer, the active layer is located on one side of the base substrate, the active layer includes a second active portion, the second active portion is used to form a channel region of the second transistor, the second active portion includes a first sub-active portion and a second sub-active portion, and the active layer also includes a third sub-active portion connected between the first sub-active portion and the second sub-active portion; the second conductive layer is located on the side of the active layer away from the base substrate, the second conductive layer includes a third conductive portion, the orthographic projection of the third conductive portion on the base substrate and the orthographic projection of the third sub-active portion on the base substrate at least partially overlap, and the third conductive portion is connected to a stable voltage source.

[0010] In an exemplary embodiment of the present disclosure, the first sub-active portion as a channel region includes a first side extending along the length direction of the channel region, the second sub-active portion as a channel region includes a second side extending along the length direction of the channel region, and the third sub-active portion includes a third side and a fourth side; wherein the third side is connected to the first side, and the angle formed by the third side and the first side is less than or equal to 180°; and / or the fourth side is connected to the second side, and the angle formed by the fourth side and the second side is less than or equal to 180°.

[0011] In an exemplary embodiment of the present disclosure, the display panel further includes: a power line, wherein the power line is used to provide a power signal to the pixel driving circuit, and the power line is connected to the third conductive portion through a via hole.

[0012] In an exemplary embodiment of the present disclosure, the second conductive layer includes the first initial signal line, and the first initial signal line and the third conductive portion are connected in the same layer.

[0013] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a capacitor, a first electrode of the capacitor being connected to the gate of the driving transistor. The second conductive layer further includes: a second conductive portion, the second conductive portion being configured to form a second electrode of the capacitor; and the third conductive portion being connected to the second conductive portion in the same layer.

[0014] In an exemplary embodiment of the present disclosure, the display panel includes a pixel driving circuit arrayed in a first direction and a second direction, the pixel driving circuit including a driving transistor and a capacitor, wherein a first electrode of the capacitor is connected to a gate of the driving transistor. The display panel further includes: a second conductive layer and a third conductive layer, wherein the second conductive layer includes a second conductive portion and a fourth conductive portion, the second conductive portion being configured to form a second electrode of the capacitor, and the fourth conductive portion being connected between adjacent second conductive portions in the first direction; a third conductive layer located on a side of the second conductive layer facing away from the substrate, the third conductive layer including a power line configured to provide a power signal to the pixel driving circuit; wherein the power line includes: a first extension portion, a second extension portion, and a third extension portion, the third extension portion being connected between the first extension portion and the second extension portion; an orthographic projection of the first extension portion on the substrate and an orthographic projection of the second extension portion on the substrate extending along the second direction, and an orthographic projection of the third extension portion on the substrate extending along the first direction; and an orthographic projection of the third extension portion on the substrate and an orthographic projection of the fourth conductive portion on the substrate at least partially overlapping.

[0015] In an exemplary embodiment of the present disclosure, the display panel further includes: a fourth conductive layer, the fourth conductive layer is located on a side of the third conductive layer away from the base substrate, the fourth conductive layer includes a plurality of data lines, and the orthographic projections of the data lines on the base substrate extend along the second direction; wherein, the orthographic projections of some of the data lines on the base substrate at least partially overlap with the orthographic projections of the first initial connection lines on the base substrate; and / or, the orthographic projections of some of the data lines on the base substrate at least partially overlap with the orthographic projections of the second initial connection lines on the base substrate.

[0016] In an exemplary embodiment of the present disclosure, among the data line and the first initial connection line whose orthographic projections on the base substrate intersect, the overlapping area of ​​the orthographic projection of the data line on the base substrate and the orthographic projection of the first initial connection line on the base substrate is S1, the area of ​​the orthographic projection of the data line on the base substrate is S2, and S1 / S2 is greater than or equal to 50%; and / or, among the data line and the second initial connection line whose orthographic projections on the base substrate intersect, the overlapping area of ​​the orthographic projection of the data line on the base substrate and the orthographic projection of the second initial connection line on the base substrate is S3, the area of ​​the orthographic projection of the data line on the base substrate is S4, and S3 / S4 is greater than or equal to 50%.

[0017] In an exemplary embodiment of the present disclosure, the display panel includes a pixel driving circuit, and the third conductive layer also includes: a first connecting portion and a plurality of power lines, the orthographic projection of the first connecting portion on the base substrate extending along the first direction, and the first connecting portion being connected between the first initial connecting line and the pixel driving circuit; the plurality of power lines being used to provide power signals to the pixel driving circuit; wherein, some of the plurality of power lines include a plurality of power line segments spaced apart in the second direction, and the orthographic projection of the first connecting portion on the base substrate is located between the orthographic projections of adjacent power line segments in the same power line on the base substrate.

[0018] In an exemplary embodiment of the present disclosure, the display panel further includes: a third conductive layer, a fourth conductive layer, an electrode layer, and a pixel definition layer, wherein the third conductive layer is located on one side of the base substrate; the fourth conductive layer is located on the side of the third conductive layer away from the base substrate, wherein a portion of the structure of the fourth conductive layer is connected to a portion of the structure of the third conductive layer through a via; the electrode layer is located on the side of the fourth conductive layer away from the base substrate, and the electrode layer includes a plurality of electrode portions; the pixel definition layer is located on the side of the electrode layer away from the base substrate, and a plurality of pixel openings are formed on the pixel definition layer, the pixel openings and the electrode portions are correspondingly arranged, and the orthographic projection of the pixel opening on the base substrate coincides with the orthographic projection of the corresponding electrode portion on the base substrate; wherein the orthographic projection of the via connected between the third conductive layer and the fourth conductive layer on the base substrate and the orthographic projection of the electrode portion on the base substrate do not overlap.

[0019] In an exemplary embodiment of the present disclosure, the display panel further includes: a fourth conductive layer, an electrode layer, and a pixel definition layer, wherein the fourth conductive layer is located on one side of the substrate, and the fourth conductive layer includes a plurality of fifth bridging portions; the electrode layer is located on a side of the fourth conductive layer away from the substrate, and the electrode layer includes a plurality of electrode portions, the electrode portions and the fifth bridging portions are correspondingly arranged, and the electrode portions are connected to the corresponding fifth bridging portions through vias; the pixel definition layer is located on a side of the electrode layer away from the substrate, and a plurality of pixel openings are formed on the pixel definition layer, the pixel openings and the electrode portions are correspondingly arranged, and the pixel openings are located on the substrate. The orthographic projection on the substrate coincides with the orthographic projection of the corresponding electrode portion on the base substrate; wherein the fourth conductive layer also includes a sixth conductive portion, and the orthographic projection of part of the electrode portion on the base substrate overlaps with the orthographic projection of the sixth conductive portion on the base substrate and the orthographic projection of the fifth bridging portion on the base substrate respectively; and the orthographic projection of the sixth conductive portion on the base substrate is arranged close to one side of the orthographic projection of the electrode portion on the base substrate in the first direction, and the orthographic projection of the fifth bridging portion on the base substrate is arranged close to the other side of the orthographic projection of the electrode portion on the base substrate in the first direction.

[0020] In an exemplary embodiment of the present disclosure, the display panel also includes a pixel driving circuit, and the fourth conductive layer also includes: a power connection line, the orthographic projection of the power connection line on the base substrate extends along the second direction, and the power connection line is used to provide a power signal to the pixel driving circuit; the sixth conductive portion is connected to the power connection line, and the orthographic projection of the power connection line on the base substrate is located between the orthographic projection of the sixth conductive portion on the base substrate and the orthographic projection of the fifth bridging portion on the base substrate, and the orthographic projection of the power connection line on the base substrate overlaps with the orthographic projection of the electrode portion on the base substrate.

[0021] In an exemplary embodiment of the present disclosure, the fifth bridging portion is connected to the sixth conductive portion.

[0022] In an exemplary embodiment of the present disclosure, the display panel further includes a pixel driving circuit, comprising a driving transistor, a fourth transistor, and a fifth transistor; the fourth transistor having a first electrode connected to a data line and a second electrode connected to the first electrode of the driving transistor; the fifth transistor having a first electrode connected to a power line and a second electrode connected to the first electrode of the driving transistor. The display panel further includes an active layer and a first conductive layer. An active layer is located on one side of the base substrate, the active layer includes a third active portion, a fourth active portion, and a fifth active portion, the third active portion is used to form a channel region of the driving transistor, the fourth active portion is used to form a channel region of the fourth transistor, and the fifth active portion is used to form a channel region of the fifth transistor; a first conductive layer is located on a side of the active layer away from the base substrate, the first conductive layer includes a first conductive portion, a second reset signal line, and an enable signal line; the orthographic projection of the first conductive portion on the base substrate covers the orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form the gate of the driving transistor; the orthographic projection of the second reset signal line on the base substrate extends along the first direction and covers the orthographic projection of the fourth active portion on the base substrate, and a partial structure of the second reset signal line is used to form the gate of the fourth transistor pole; the orthographic projection of the enable signal line on the substrate extends along the first direction and covers the orthographic projection of the fifth active portion on the substrate, and a partial structure of the enable signal line is used to form the gate of the fifth transistor; the orthographic projection of the enable signal line on the substrate is located between the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the second reset signal line on the substrate; wherein, in the first direction, the orthographic projection of the fifth active portion on the substrate is located between the orthographic projection of at least a partial structure of the third active portion on the substrate and the orthographic projection of the fourth active portion on the substrate; or, in the first direction, the orthographic projection of the fourth active portion on the substrate is located between the orthographic projection of at least a partial structure of the third active portion on the substrate and the orthographic projection of the fifth active portion on the substrate.

[0023] In an exemplary embodiment of the present disclosure, the square resistance of the second conductive layer is greater than the square resistance of the third conductive layer, and the display panel also includes a first initial routing line and a second initial routing line; wherein, the orthographic projections of the first initial routing line and the second initial routing line on the substrate extend along the first direction, and the orthographic projections of the first initial routing line and the second initial routing line on the substrate are located on one side of the orthographic projections of the first initial connecting line and the second initial connecting line on the substrate in the second direction, the first initial routing line connects multiple first initial connecting lines, and the second initial routing line connects multiple second initial connecting lines.

[0024] In an exemplary embodiment of the present disclosure, the display panel also includes a pixel driving circuit and a gate driving circuit; the orthographic projection of the second initial routing line on the substrate is located on a side of the orthographic projection of the first initial routing line on the substrate away from the orthographic projection of the first initial connecting line and the second initial connecting line on the substrate; the third conductive layer also includes: a plurality of gate line access lines, the orthographic projections of the plurality of gate line access lines on the substrate extend along the first direction and are spaced apart along the second direction, and the gate line access lines are connected between the gate driving circuit and the pixel driving circuit; wherein the orthographic projections of the first initial routing line and the second initial routing line on the substrate are located between the orthographic projections of two adjacent gate line access lines on the substrate.

[0025] In an exemplary embodiment of the present disclosure, the display panel further includes a gate driving circuit and a plurality of pixel driving circuits; the display panel further includes: a fourth conductive layer, an electrode layer, and a pixel definition layer, the fourth conductive layer is located on one side of the base substrate, the fourth conductive layer includes a plurality of data lines, the data lines are used to provide data signals to the pixel driving circuit, and the orthographic projections of the plurality of data lines on the base substrate extend along the second direction and are spaced apart along the first direction; the electrode layer is located on the side of the fourth conductive layer away from the base substrate, the electrode layer includes a plurality of electrode portions; the pixel definition layer is located on the side of the electrode layer away from the base substrate, a plurality of pixel openings are formed on the pixel definition layer, the pixel openings and the electrode portions are correspondingly arranged, the orthographic projections of the pixel openings on the base substrate coincide with the orthographic projections of the corresponding electrode portions on the base substrate; the orthographic projections of some of the electrode portions on the base substrate coincide with the orthographic projections of the electrode portions adjacent to them in the first direction The orthographic projections of the two data lines on the base substrate overlap, and the orthographic projections of the two data lines adjacent in the first direction on the base substrate are respectively arranged close to the two sides of the orthographic projection of the overlapping electrode portion on the base substrate in the first direction; the fourth conductive layer also includes: an analog data line, the orthographic projection of the analog data line on the base substrate extends along the second direction, and the orthographic projection of the analog data line on the base substrate is located between the orthographic projection of the gate drive circuit on the base substrate and the orthographic projection of the data line closest to the gate drive circuit on the base substrate; the orthographic projections of the analog data line and the data lines adjacent to it on the base substrate overlap with the orthographic projection of the same electrode portion on the base substrate, and the orthographic projections of the analog data lines and the data lines adjacent in the first direction on the base substrate are respectively arranged close to the two sides of the orthographic projection of the overlapping electrode portion on the base substrate in the first direction.

[0026] In an exemplary embodiment of the present disclosure, the display panel also includes a first initial routing line and a second initial routing line; wherein, the orthographic projections of the first initial routing line and the second initial routing line on the substrate extend along the first direction, and the orthographic projections of the first initial routing line and the second initial routing line on the substrate are located on one side of the orthographic projections of the first initial connection line and the second initial connection line on the substrate in the second direction, the first initial routing line connects multiple first initial connection lines, and the second initial routing line connects multiple second initial connection lines; the orthographic projection of the second initial routing line on the substrate is located on a side of the orthographic projection of the first initial routing line on the substrate away from the orthographic projections of the first initial connection line and the second initial connection line on the substrate; the second initial routing line is connected to the analog data line, and the analog data line is connected to multiple second initial signal lines through vias.

[0027] The present disclosure also provides a display panel, which includes: a base substrate, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of first initial connecting lines, a plurality of second initial connecting lines, and a plurality of pixel driving circuits, wherein the orthographic projections of the plurality of first initial signal lines on the base substrate extend along a first direction and are spaced apart along a second direction, and the first direction and the second direction intersect; the plurality of second initial signal lines and the first initial signal lines are located in the same conductive layer, the orthographic projections of the second initial signal lines on the base substrate extend along the first direction and are spaced apart along the second direction; the plurality of first initial connecting lines and the first initial signal lines are located in different conductive layers, the orthographic projections of the plurality of first initial connecting lines on the base substrate extend along the second direction and are spaced apart along the first direction, and the first initial connecting lines are connected to at least a portion of the base substrate where the orthographic projections thereof intersect. The first initial signal line; multiple second initial connection lines are located in the same conductive layer as the first initial connection line, the orthographic projections of the multiple second initial connection lines on the substrate extend along the second direction and are spaced apart along the first direction, and the second initial connection lines are connected to at least part of the second initial signal lines whose orthographic projections on the substrate intersect with them; multiple pixel driving circuits are arranged in an array along the first direction and the second direction, the first direction is the row direction, and the second direction is the column direction; each row of the pixel driving circuits is correspondingly provided with a first initial signal line and a second initial signal line, and each column of the pixel driving circuits is correspondingly provided with a first initial connection line or a second initial connection line; the orthographic projections of the first initial connection line on the substrate and the orthographic projections of the second initial connection line on the substrate are alternately distributed in sequence in the first direction.

[0028] In an exemplary embodiment of the present disclosure, the display panel includes a pixel driving circuit and a light-emitting unit, and the pixel driving circuit includes: a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor, wherein the first electrode of the first transistor is connected to the first initial signal line, the second electrode is connected to the gate of the driving transistor, and the gate is connected to the first reset signal line; the first electrode of the second transistor is connected to the gate of the driving transistor, the second electrode is connected to the second electrode of the driving transistor, and the gate is connected to the gate line; the first electrode of the fourth transistor is connected to the data line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the second reset signal line; the first electrode of the fifth transistor is connected to the power line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the enable signal line; the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the enable signal line; the first electrode of the seventh transistor is connected to the second initial signal line, the second electrode is connected to the first electrode of the light unit, and the gate is connected to the second reset signal line; the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the power line.

[0029] In an exemplary embodiment of the present disclosure, the display panel further includes: an active layer and a first conductive layer, the active layer being located on one side of the base substrate, wherein a portion of the active layer is respectively used to form channel regions of the first transistor, the second transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor; the first conductive layer being located on a side of the active layer facing away from the base substrate, the first conductive layer including a first conductive portion, a first reset signal line, a second reset signal line, and an enable signal line, the first conductive portion being used to form a gate of the driving transistor, a portion of the first reset signal line being used to form a gate of the first transistor, a portion of the second reset signal line being used to form gates of the fourth transistor and the seventh transistor, and a portion of the enable signal line being used to form gates of the fifth transistor and the sixth transistor, respectively; wherein an orthographic projection of the first conductive portion on the base substrate is located between an orthographic projection of the first reset signal line on the base substrate and an orthographic projection of the enable signal line on the base substrate; and an orthographic projection of the second reset signal line on the base substrate is located on a side of the base substrate away from an orthographic projection of the enable signal line on the base substrate.

[0030] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0031] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are incorporated into and constitute a part of this specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure. It is apparent that the drawings described below are merely some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0033] FIG1 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed herein;

[0034] FIG2 is a timing diagram of signals at each node in a driving method of the pixel driving circuit shown in FIG1 ;

[0035] FIG3 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0036] FIG4 is a structural diagram of the active layer in FIG3 ;

[0037] FIG5 is a structural diagram of the first conductive layer in FIG3 ;

[0038] FIG6 is a structural diagram of the second conductive layer in FIG3 ;

[0039] FIG7 is a structural diagram of the third conductive layer in FIG3 ;

[0040] FIG8 is a structural diagram of the fourth conductive layer in FIG3;

[0041] FIG9 is a structural diagram of the electrode layer in FIG3 ;

[0042] FIG10 is a structural layout diagram of the active layer and the first conductive layer in FIG3 ;

[0043] FIG11 is a structural diagram of the active layer, the first conductive layer, and the second conductive layer in FIG3 ;

[0044] FIG12 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG3;

[0045] FIG13 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in FIG3 ;

[0046] FIG14 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0047] FIG15 is a structural diagram of the third conductive layer in FIG14;

[0048] FIG16 is a structural layout diagram of the fourth conductive layer in FIG14;

[0049] FIG17 is a structural diagram of the electrode layer in FIG14;

[0050] FIG18 is a structural layout diagram of the third conductive layer and the fourth conductive layer in FIG14;

[0051] FIG19 is a partial cross-sectional view of the display panel shown in FIG3 taken along dotted line AA;

[0052] FIG20 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0053] FIG21 is a structural diagram of the active layer in FIG20;

[0054] FIG22 is a structural layout diagram of the first conductive layer in FIG20 ;

[0055] FIG23 is a structural layout diagram of the second conductive layer in FIG20;

[0056] FIG24 is a structural layout diagram of the third conductive layer in FIG20;

[0057] FIG25 is a structural layout diagram of the fourth conductive layer in FIG20;

[0058] FIG26 is a structural diagram of the electrode layer in FIG20;

[0059] FIG27 is a structural layout diagram of the active layer and the first conductive layer in FIG20;

[0060] FIG28 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG20 ;

[0061] FIG29 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG20 ;

[0062] FIG30 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in FIG20 ;

[0063] FIG31 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0064] FIG32 is a structural layout diagram of the third conductive layer in FIG31;

[0065] FIG33 is a structural layout diagram of the fourth conductive layer in FIG31;

[0066] FIG34 is a structural diagram of the electrode layer in FIG31;

[0067] FIG35 is a structural layout diagram of the third conductive layer and the fourth conductive layer in FIG31;

[0068] FIG36 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0069] FIG37 is a structural diagram of the active layer in FIG36;

[0070] FIG38 is a structural layout diagram of the first conductive layer in FIG36;

[0071] FIG39 is a structural layout diagram of the second conductive layer in FIG36;

[0072] FIG40 is a structural layout diagram of the third conductive layer in FIG36;

[0073] FIG41 is a structural layout diagram of the fourth conductive layer in FIG36;

[0074] FIG42 is a structural layout diagram of the active layer and the first conductive layer in FIG36;

[0075] FIG43 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG36;

[0076] FIG44 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG36 ;

[0077] FIG45 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0078] FIG46 is an enlarged view of a local area C in FIG45 ;

[0079] FIG47 is a structural layout diagram of the third conductive layer in FIG46;

[0080] FIG48 is a structural layout diagram of the fourth conductive layer in FIG46;

[0081] FIG49 is an enlarged view of a local area D in FIG45 ;

[0082] FIG50 is an enlarged view of the local area E in FIG45 . DETAILED DESCRIPTION

[0083] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0084] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0085] This exemplary embodiment first provides a pixel driving circuit, as shown in FIG1 , which is a structural diagram of an exemplary embodiment of the pixel driving circuit disclosed in the present invention. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and the gate of the fourth transistor T4 is connected to the second reset signal terminal Re2; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and the gate of the fifth transistor T5 is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the node N; the first electrode of the second transistor T2 is connected to the node N, the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and the gate of the second transistor T2 is connected to the gate driving signal terminal Gat e; a first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, a second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, a gate of the sixth transistor T6 is connected to the enable signal terminal EM, a first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and a gate of the seventh transistor T7 is connected to the second reset signal terminal Re2; a second electrode of the first transistor T1 is connected to the node N, a first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, and a gate of the first transistor T1 is connected to the first reset signal terminal Re1; a first electrode of the capacitor C is connected to the node N, and a second electrode of the capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit can be connected to a light-emitting unit OLED, and the pixel driving circuit is used to drive the light-emitting unit OLED to emit light. The first electrode of the light-emitting unit OLED can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be an anode of the light-emitting unit, and the second electrode of the light-emitting unit can be a cathode of the light-emitting unit. The first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors. P-type transistors have high carrier mobility, which facilitates the realization of display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal may output the same or different voltage signals depending on actual conditions.

[0086] As shown in Figure 2, it is a timing diagram of the signals at each node in a driving method of the pixel driving circuit shown in Figure 1. Among them, Gate represents the timing diagram of the signal on the gate driving signal terminal Gate, Re1 represents the timing diagram of the signal on the first reset signal terminal Re1, Re2 represents the timing diagram of the signal on the second reset signal terminal Re2, and EM represents the timing diagram of the signal on the enable signal terminal EM. The driving method of the pixel driving circuit may include a reset phase t1, a first compensation phase t2, a second compensation phase t3, and a light-emitting phase t4. In the reset phase t1: the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the node N. In the first compensation stage t2: the second reset signal terminal Re2 and the gate drive signal terminal Gate output low-level signals, the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, and at the same time the data signal terminal Da outputs a data signal to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. The second initial signal terminal Vini2 inputs a second initial signal to the second electrode of the sixth transistor T6. In the second compensation stage t3: the gate drive signal terminal Gate outputs a low level, the second transistor T2 is turned on, and the second transistor T2 continues to input a compensation voltage to the node N. In the light-emitting stage t4: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the voltage Vdata+Vth at the node N. According to the output current formula of the driving transistor I=(μWCox / 2L)(Vgs-Vth) 2 , where μ is carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the pixel driver circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth)2. This pixel driver circuit can extend the time for inputting the compensation voltage to node N, so that the compensation voltage can be input to node N more fully.

[0087] This exemplary embodiment further provides a display panel, which may include a plurality of pixel driving circuits shown in FIG1. ​​In this exemplary embodiment, the display panel may further include a base substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and an electrode layer stacked in sequence, and an insulating layer may further be provided between the above structural layers. As shown in Figures 3 to 13, Figure 3 is a structural layout of another exemplary embodiment of the display panel disclosed herein, Figure 4 is a structural layout of the active layer in Figure 3, Figure 5 is a structural layout of the first conductive layer in Figure 3, Figure 6 is a structural layout of the second conductive layer in Figure 3, Figure 7 is a structural layout of the third conductive layer in Figure 3, Figure 8 is a structural layout of the fourth conductive layer in Figure 3, Figure 9 is a structural layout of the electrode layer in Figure 3, Figure 10 is a structural layout of the active layer and the first conductive layer in Figure 3, Figure 11 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in Figure 3, Figure 12 is a structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in Figure 3, and Figure 13 is a structural layout of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in Figure 3.

[0088] As shown in Figures 3, 4, and 10, the active layer may include a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion 77. The first active portion 71 is used to form a channel region of the first transistor T1, the second active portion 72 is used to form a channel region of the second transistor T2, the third active portion 73 is used to form a channel region of the driving transistor T3, the fourth active portion 74 is used to form a channel region of the fourth transistor T4, the fifth active portion 75 is used to form a channel region of the fifth transistor T5, the sixth active portion 76 is used to form a channel region of the sixth transistor T6, and the seventh active portion 77 is used to form a channel region of the seventh transistor T7. The first active portion 71 includes a fourth sub-active portion 714 and a fifth sub-active portion 715, and the active layer further includes a sixth sub-active portion connected between the fourth sub-active portion 714 and the fifth sub-active portion 715. The second active portion 72 includes a first sub-active portion 721 and a second sub-active portion 722, and the active layer further includes a third sub-active portion 723 connected between the first sub-active portion 721 and the second sub-active portion 722. As shown in Figures 3, 4, and 10, the active layer may further include an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a seventeenth active portion 717, and an eighteenth active portion 718. Among them, the eighth active portion 78 is connected to the end of the first active portion 71 away from the second active portion 72, the ninth active portion 79 is connected between the first active portion 71 and the second active portion 72, the tenth active portion 710 is connected between the sixth active portion 76 and the seventh active portion 77, the eleventh active portion 711 is connected to the end of the seventh active portion 77 away from the sixth active portion 76, the twelfth active portion 712 is connected to the end of the fifth active portion 75 away from the third active portion 73, the thirteenth active portion 713 and the seventeenth active portion 717 are connected to both ends of the fourth active portion 74, and the eighteenth active portion 718 is connected between the fifth active portion 75 and the third active portion 73.

[0089] In this exemplary embodiment, the active layer portion of each pixel driving circuit is independently designed, which is conducive to improving the vertical mura problem caused by the intra-screen hole (AA hole).

[0090] As shown in Figures 3, 5, and 10, the first conductive layer includes a first conductive portion 11, a gate line Gate, a first reset signal line Re1, a second reset signal line Re2, and an enable signal line EM. The orthographic projections of the gate line Gate, the first reset signal line Re1, the second reset signal line Re2, and the enable signal line EM on the base substrate extend along a first direction X. The gate line Gate is used to provide the gate drive signal terminal in Figure 1, the first reset signal line Re1 is used to provide the first reset signal terminal in Figure 1, the second reset signal line Re2 is used to provide the second reset signal terminal in Figure 1, and the enable signal line EM is used to provide the enable signal terminal in Figure 1. The orthographic projection of the gate line Gate on the base substrate covers the orthographic projection of the second active portion 72 on the base substrate, and a portion of the structure of the gate line Gate is used to form the gate of the second transistor T2. The orthographic projection of the first reset signal line Re1 on the substrate overlaps the orthographic projection of the first active portion 71 on the substrate. Part of the first reset signal line Re1 forms the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate overlaps the orthographic projections of the fourth active portion 74 and the seventh active portion 77 on the substrate. Part of the second reset signal line Re2 forms the gates of the fourth transistor T4 and the seventh transistor T7, respectively. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projections of the fifth active portion 75 and the sixth active portion 76 on the substrate. Part of the enable signal line EM forms the gates of the fifth transistors T5 and T6, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 forms the gate of the drive transistor T3 and the first electrode of the capacitor C.

[0091] In this exemplary embodiment, the second transistor T2 and the fourth transistor T4 can be provided with gate drive signals by different gate drive circuits, and the fourth transistor T4 and the seventh transistor T7 can be provided with gate drive signals by the same gate drive circuit. As shown in Figures 3, 5, and 10, adjacent rows of pixel drive circuits do not share a gate line. This arrangement can facilitate the insertion of analog pixel drive circuit rows in the display panel.

[0092] As shown in Figures 3, 6, and 11, the second conductive layer may include a first initial signal line 2Vinit1, a second initial signal line 2Vinit2, a second conductive portion 22, and a third conductive portion 23. The first initial signal line 2Vinit1 can be used to provide the first initial signal end in Figure 1, and the second initial signal line 2Vinit2 can be used to provide the second initial signal end in Figure 1. The orthographic projection of the first initial signal line 2Vinit1 on the base substrate and the orthographic projection of the second initial signal line 2Vinit2 on the base substrate can both extend along the first direction X. The orthographic projection of the second conductive portion 22 on the base substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate, and the second conductive portion 22 can be used to form a second electrode of the capacitor C, wherein a plurality of second conductive portions 22 distributed in the first direction X can be connected in sequence. The orthographic projection of the third conductive portion 23 on the substrate and the orthographic projection of the third sub-active portion 723 on the substrate at least partially overlap. The third conductive portion 23 can be connected to a stable voltage source. The third conductive portion 23 can stabilize the third sub-active portion 723, thereby improving the problem of leakage to the source and drain of the second transistor T2 caused by voltage changes in the third sub-active portion 723.

[0093] As shown in Figures 3, 4, and 10, the first sub-active portion 721, serving as a channel region, includes a first side 7211 extending along the length of the channel region. The second sub-active portion 722, serving as a channel region, includes a second side 7222 extending along the length of the channel region. The third sub-active portion 723 includes a third side 7233 and a fourth side 7234. The third side 7233 is connected to the first side 7211, and the angle formed between the third side 7233 and the first side 7211 is less than 180°. The fourth side 7234 is connected to the second side 7222, and the angle formed between the fourth side 7234 and the second side 7222 is less than 180°. In other words, the third sub-active portion 723 has an enlarged configuration, which increases the overlapping area of ​​the orthographic projections of the third sub-active portion 723 and the third conductive portion 23 on the substrate, thereby enhancing the voltage stabilization effect of the third conductive portion 23 on the third sub-active portion 723.

[0094] As shown in Figures 3, 6, and 11, the positive projection of the second initial signal line 2Vinit2 corresponding to the pixel driving circuit in the adjacent previous row can at least partially overlap with the positive projection of the sixth sub-active portion 716 on the substrate substrate. The second initial signal line 2Vinit2 corresponding to the pixel driving circuit in the adjacent previous row can stabilize the sixth sub-active portion 716, thereby improving the problem of leakage to the source and drain of the first transistor T1 due to the voltage change of the sixth sub-active portion 716.

[0095] As shown in Figures 3, 6, and 11, the pixel driving circuit shown in Figure 3 is the pixel driving circuit in the bottom row of the display panel. The second initial signal line 2Vinit2 corresponding to this pixel driving circuit does not need to block the sixth sub-active portion in the pixel driving circuit in the next row. Therefore, the second initial signal line 2Vinit2 corresponding to this pixel driving circuit has a slightly different structure from the second initial signal line 2Vinit2 corresponding to the pixel driving circuit in the adjacent previous row. Of course, in other exemplary embodiments, the second initial signal line 2Vinit2 corresponding to the pixel driving circuit in the bottom row of the display panel can also have the same structure as the other second initial signal lines 2Vinit2.

[0096] As shown in Figures 3, 7, and 12, the third conductive layer may include a power line 3VDD, a first initial connection line 3Vinit1, a second initial connection line 3Vinit2, a first bridge portion 31, a second bridge portion 32, a third bridge portion 33, a fourth bridge portion 34, a sixth bridge portion 36, and a seventh bridge portion 37. The power line 3VDD can be used to provide the first power terminal in the pixel driving circuit shown in Figure 1. The orthographic projections of the power line 3VDD, the first initial connection line 3Vinit1, and the second initial connection line 3Vinit2 on the substrate may extend along a second direction Y. The first direction X may intersect with the second direction Y. For example, the first direction X may be a row direction, and the second direction Y may be a column direction. A column of pixel driving circuits distributed in the second direction Y may be provided with a corresponding first initial connection line 3Vinit1 or a corresponding second initial connection line 3Vinit2. The orthographic projections of the first initial connection line 3Vinit1 and the second initial connection line 3Vinit2 on the substrate may be alternately distributed along the first direction X. The power line 3VDD can be connected to the second conductive portion 22 and the twelfth active portion 712 through vias, so as to connect the second electrode of the capacitor C, the first electrode of the fifth transistor T5 and the first power terminal.

[0097] As shown in Figures 3, 7, and 12, the power line 3VDD can also be connected to the third conductive portion 23 via a via, and the power line 3VDD can provide a stable voltage source to the third conductive portion 23. It should be understood that in other exemplary embodiments, the third conductive portion 23 can also be connected to the power line by being connected on the same layer as the second conductive portion 22. The third conductive portion 23 can also provide a stable voltage source through other structures. For example, the third conductive portion 23 can provide a stable voltage source through structures such as the first initial signal line 2Vinit1 and the second initial signal line 2Vinit2. The first bridge portion 31 can be connected to the first conductive portion 11 and the ninth active portion 79 via vias to connect the second electrode of the first transistor T1, the first electrode of the second transistor, and the gate of the driving transistor T3. The second conductive portion 22 has an opening 221 formed therein, and the orthographic projection of the via connecting between the first conductive portion 11 and the first bridge portion 31 on the substrate is located within the orthographic projection of the opening 221 on the substrate. The second bridge portion 32 can be connected to the tenth active portion 710 via a via to connect the second electrode of the sixth transistor T6. The third bridge portion 33 can be connected to the seventeenth active portion 717 and the eighteenth active portion 718 via vias, respectively, to connect the second electrode of the fourth transistor T4 and the first electrode of the driving transistor T3. The fourth bridge portion 34 can be connected to the thirteenth active portion 713 via vias to connect the first electrode of the fourth transistor T4. The sixth bridge portion 36 can be connected to the first initial signal line 2Vinit1 and the eighth active portion 78 via vias, respectively, to connect the first electrode of the first transistor T1 and the first initial signal terminal. The seventh bridge portion 37 can be connected to the second initial signal line 2Vinit2 and the eleventh active portion 711 via vias, respectively, to connect the first electrode and the second initial signal terminal of the seventh transistor T7. The first initial connection line 3Vinit1 can be connected to the first initial signal line 2Vinit1, which intersects its orthographic projection on the substrate, via the sixth bridge portion 36, to form a grid structure of the first initial signal line 2Vinit1. This arrangement can reduce the intrinsic resistance of the first initial signal line 2Vinit1, thereby improving the uniformity of the voltage of the first initial signal terminal connected to the pixel driving circuit at different locations on the display panel. The second initial connection line 3Vinit2 can be connected to the second initial signal line 2Vinit2 that intersects with its orthographic projection on the base substrate through the seventh bridge portion 37 to form a grid structure of the second initial signal line 2Vinit2. This setting can reduce the inherent resistance of the second initial signal line 2Vinit2, thereby improving the uniformity of the second initial signal terminal voltage connected to the pixel driving circuit at different positions of the display panel.It should be understood that in other exemplary embodiments, the first initial connection line 3Vinit1 and the second initial connection line 3Vinit2 may also have other distribution methods. As long as the first initial connection line 3Vinit1 and the first initial signal line 2Vinit1 form a grid structure, and the second initial connection line 3Vinit2 and the second initial signal line 2Vinit2 form a grid structure, the above-mentioned technical effect can be achieved.

[0098] As shown in Figures 3, 6, 7, and 12, the power line 3VDD may include: a first extension portion 3VDD1, a second extension portion 3VDD2, and a third extension portion 3VDD3. The third extension portion 3VDD3 is connected between the first extension portion 3VDD1 and the second extension portion 3VDD2. The orthographic projection of the first extension portion 3VDD1 and the orthographic projection of the second extension portion 3VDD2 on the base substrate extend along the second direction Y, and the orthographic projection of the third extension portion 3VDD3 on the base substrate extends along the first direction. The second conductive layer also includes a fourth conductive portion 24 connected between adjacent second conductive portions 22 in the first direction X. The orthographic projection of the third extension portion 3VDD3 and the orthographic projection of the fourth conductive portion 24 on the base substrate at least partially overlap. This arrangement can improve the transmittance of the display panel.

[0099] As shown in Figures 3, 8, and 13, the fourth conductive layer may include: a data line Da, a power connection line 4VDD, and a fifth bridge portion 45. The orthographic projections of the data line Da and the power connection line 4VDD on the substrate extend along the second direction Y. The data line Da is used to provide the data signal terminal shown in Figure 1. The data line Da can be connected to the fourth bridge portion 34 through a via to connect to the first electrode of the fourth transistor T4. The power connection line 4VDD can be connected to the power line 3VDD through a via to form a double-layer power line. This arrangement can reduce the power line's inherent resistance, thereby improving the uniformity of the voltage at the first power terminal at different locations on the display panel. The fifth bridge portion 45 can be connected to the second bridge portion 32 through a via to connect to the second electrode of the sixth transistor T6.

[0100] As shown in Figures 3, 8, and 13, the orthographic projections of some of the data lines Da on the base substrate at least partially overlap with the orthographic projections of the first initial connection lines 3Vinit1 on the base substrate; and the orthographic projections of some of the data lines Da on the base substrate at least partially overlap with the orthographic projections of the second initial connection lines 3Vinit2 on the base substrate. This arrangement can improve the transmittance of the display panel.

[0101] In this exemplary embodiment, for the data line Da and the first initial connection line 3Vinit1 whose orthographic projections on the base substrate intersect, the overlapping area of ​​the orthographic projection of the data line Da on the base substrate and the first initial connection line 3Vinit1 on the base substrate is S1, the area of ​​the orthographic projection of the data line Da on the base substrate is S2, and S1 / S2 is greater than or equal to 50%. For example, S1 / S2 can be equal to 50%, 60%, 70%, 80%, 90%, etc. For the data line Da and the second initial connection line 3Vinit2 whose orthographic projections on the base substrate intersect, the overlapping area of ​​the orthographic projection of the data line Da on the base substrate and the second initial connection line 3Vinit2 on the base substrate is S3, the area of ​​the orthographic projection of the data line Da on the base substrate is S4, and S3 / S4 is greater than or equal to 50%. For example, S3 / S4 can be equal to 50%, 60%, 70%, 80%, 90%, etc.

[0102] As shown in Figures 3 and 9, the electrode layer includes multiple electrode parts: a first electrode part G, a second electrode part B, and a third electrode part R. Each electrode part can be connected to the fifth bridge part 45 through a via to connect to the second pole of the sixth transistor. In particular, Figure 9 shows more electrode parts corresponding to the pixel driving circuit compared to Figure 3. The display panel may also include a pixel definition layer located on the side of the electrode layer away from the base substrate, and a plurality of pixel openings PH are formed on the pixel definition layer. The pixel openings PH are arranged corresponding to the electrode parts, and the orthographic projection of the pixel openings PH on the base substrate coincides with the orthographic projection of the electrode parts on the base substrate. The first electrode part G can be used to form the electrode part of the green light-emitting unit in the display panel, the second electrode part B can be used to form the electrode part of the blue light-emitting unit in the display panel, and the third electrode part R can be used to form the electrode part of the red light-emitting unit. Among the multiple electrode portions connected to the same row of pixel driving circuits, the second electrode portion B, the first electrode portion G, the third electrode portion R, and the first electrode portion G are alternately distributed in sequence in the row direction X; in two adjacent columns of pixel driving circuits, the multiple second electrode portions B and the multiple third electrode portions R are connected to the same column of pixel driving circuits, and the second electrode portions B and the third electrode portions R connected to the same column of pixel driving circuits are alternately distributed in sequence in the column direction Y; the multiple first electrode portions G are connected to the other column of pixel driving circuits, and the first electrode portions G connected to the same column of pixel driving circuits are spaced apart in the column direction.

[0103] As shown in Figures 14-18, Figure 14 is a structural layout diagram of an exemplary embodiment of a display panel of the present disclosure. The display panel shown in Figure 14 has the same structure as the display panel shown in Figure 3, and Figure 14 only shows the third conductive layer, fourth conductive layer, and electrode layer in the display panel. Figure 15 is a structural layout diagram of the third conductive layer in Figure 14, Figure 16 is a structural layout diagram of the fourth conductive layer in Figure 14, Figure 17 is a structural layout diagram of the electrode layer in Figure 14, and Figure 18 is a structural layout diagram of the third and fourth conductive layers in Figure 14.

[0104] As shown in Figures 14-18, a portion of the fourth conductive layer is connected to a portion of the third conductive layer via vias. For example, the power supply line 4VDD is connected to the power supply line 3VDD via the first via H1, the fifth bridge portion 45 is connected to the second bridge portion 32 via the second via H2, and the data line Da is connected to the fourth bridge portion 34 via the third via H3. The orthographic projections of the vias connecting the fourth and third conductive layers on the substrate and the orthographic projections of the various electrode portions on the substrate do not overlap. Because grooves exist in the fourth conductive layer at the locations of the first, second, and third vias H1, H2, and H3, the above arrangement prevents the electrode portions from being formed in the grooves, thereby improving the flatness of the electrode portions. As shown in Figures 14-18, the position of the first via H1 can be differentiated in different pixel drive circuits, so that the orthographic projections of the first via H1 on the substrate and the orthographic projections of the various electrode portions on the substrate do not overlap.

[0105] As shown in Figures 14-18, the fifth bridging portion 45 will raise the left side of the first electrode portion G, thereby affecting the flatness of the first electrode portion G. In this exemplary embodiment, the fourth conductive layer may further include a sixth conductive portion 46, and the orthographic projection of the first electrode portion G on the base substrate overlaps with the orthographic projections of the sixth conductive portion 46 and the fifth bridging portion 45 on the base substrate. The orthographic projection of the sixth conductive portion 46 on the base substrate is arranged near one side of the orthographic projection of the first electrode portion G on the base substrate in the first direction X, and the orthographic projection of the fifth bridging portion 45 on the base substrate is arranged near the other side of the orthographic projection of the first electrode portion G on the base substrate in the first direction X. The sixth conductive portion 46 and the fifth bridging portion 45 overlap with the left and right sides of the first electrode portion G, respectively, thereby improving the symmetry of the left and right sides of the first electrode portion G and thereby improving the flatness of the first electrode portion G.

[0106] As shown in Figures 14-18 , in the same pixel driving circuit, the sixth conductive portion 46 is connected to the side of the power supply line 4VDD away from the fifth bridge portion 45. The sixth conductive portion 46 has a stable voltage, thereby preventing voltage coupling from affecting other structures. It should be understood that in other exemplary embodiments, the sixth conductive portion 46 can be suspended or connected to another stable voltage source.

[0107] In this exemplary embodiment, the electrode portion overlapping with the fifth bridging portion 45 and the sixth conductive portion 46 is the first electrode portion G. It should be understood that in other exemplary embodiments, the electrode portion overlapping with the fifth bridging portion 45 and the sixth conductive portion 46 may also be other electrode portions, for example, the second electrode portion B, the third electrode portion R, etc.

[0108] As shown in Figures 14-18 , the third conductive layer further includes a first connecting portion 311, the orthographic projection of the first connecting portion 311 on the base substrate extending along the first direction X. The first connecting portion 311 is connected between the first initial connection line 3Vinit1 and the pixel driving circuit. As shown in Figures 14-18 , due to obstruction by the first connecting portion 311, some power lines 3VDD cannot be arranged through in the second direction Y. Some of the power lines 3VDD include multiple power line segments 3VDDx spaced apart in the second direction Y. The orthographic projection of the first connecting portion 311 on the base substrate is located between the orthographic projections of adjacent power line segments 3VDDx in the same power line on the base substrate.

[0109] As shown in FIG19 , which is a partial cross-sectional view of the display panel shown in FIG3 taken along the dotted line AA, the display panel may further include a buffer layer 82 , a first insulating layer 83 , a second insulating layer 84 , a first dielectric layer 85 , a passivation layer 86 , a first planarization layer 87 , and a second planarization layer 88 , wherein the base substrate 81 , the buffer layer 82 , the active layer, the first insulating layer 83 , the first conductive layer, the second insulating layer 84 , the second conductive layer, the first dielectric layer 85 , the third conductive layer, the passivation layer 86 , the first planarization layer 87 , the fourth conductive layer, the second planarization layer 88 , and the electrode layer are stacked in sequence. The first insulating layer 83 and the second insulating layer 84 can be silicon oxide layers, the first dielectric layer 85 can be a silicon nitride layer, the passivation layer 86 and the buffer layer 82 can be made of silicon oxide, silicon nitride, etc. The materials of the first planarization layer 87 and the second planarization layer 88 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The base substrate 81 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The materials of the first and second conductive layers can be molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate, etc. The materials of the third and fourth conductive layers can be metal materials, such as molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate, etc., or a titanium / aluminum / titanium laminate. The square resistance of any one of the first conductive layer and the second conductive layer may be greater than the square resistance of any one of the third conductive layer and the fourth conductive layer.

[0110] This exemplary embodiment also provides another display panel, which may include multiple pixel driving circuits shown in Figure 1. In this exemplary embodiment, the display panel may further include a base substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and an electrode layer stacked in sequence, and an insulating layer may be further provided between the above structural layers. As shown in Figures 20 to 30, Figure 20 is a structural layout of another exemplary embodiment of the display panel disclosed herein, Figure 21 is a structural layout of the active layer in Figure 20, Figure 22 is a structural layout of the first conductive layer in Figure 20, Figure 23 is a structural layout of the second conductive layer in Figure 20, Figure 24 is a structural layout of the third conductive layer in Figure 20, Figure 25 is a structural layout of the fourth conductive layer in Figure 20, Figure 26 is a structural layout of the electrode layer in Figure 20, Figure 27 is a structural layout of the active layer and the first conductive layer in Figure 20, Figure 28 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in Figure 20, Figure 29 is a structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in Figure 20, and Figure 30 is a structural layout of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in Figure 20.

[0111] As shown in Figures 20, 21, and 27, the active layer may include a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion 77. The first active portion 71 is used to form a channel region of the first transistor T1, the second active portion 72 is used to form a channel region of the second transistor T2, the third active portion 73 is used to form a channel region of the driving transistor T3, the fourth active portion 74 is used to form a channel region of the fourth transistor T4, the fifth active portion 75 is used to form a channel region of the fifth transistor T5, the sixth active portion 76 is used to form a channel region of the sixth transistor T6, and the seventh active portion 77 is used to form a channel region of the seventh transistor T7. The first active portion 71 includes a fourth sub-active portion 714 and a fifth sub-active portion 715, and the active layer further includes a sixth sub-active portion connected between the fourth sub-active portion 714 and the fifth sub-active portion 715. The second active portion 72 includes a first sub-active portion 721 and a second sub-active portion 722, and the active layer further includes a third sub-active portion 723 connected between the first sub-active portion 721 and the second sub-active portion 722. As shown in Figures 3, 4, and 10, the active layer may further include an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a seventeenth active portion 717, and an eighteenth active portion 718. Among them, the eighth active portion 78 is connected to the end of the first active portion 71 away from the second active portion 72, the ninth active portion 79 is connected between the first active portion 71 and the second active portion 72, the tenth active portion 710 is connected between the sixth active portion 76 and the seventh active portion 77, the eleventh active portion 711 is connected to the end of the seventh active portion 77 away from the sixth active portion 76, the twelfth active portion 712 is connected to the end of the fifth active portion 75 away from the third active portion 73, the thirteenth active portion 713 and the seventeenth active portion 717 are connected to both ends of the fourth active portion 74, and the eighteenth active portion 718 is connected between the fifth active portion 75 and the third active portion 73.

[0112] As shown in Figures 20, 22, and 27, the first conductive layer includes a first conductive portion 11, a gate line Gate, a first reset signal line Re1, a second reset signal line Re2, and an enable signal line EM. The orthographic projections of the gate line Gate, the first reset signal line Re1, the second reset signal line Re2, and the enable signal line EM on the base substrate extend along a first direction X. The gate line Gate is used to provide the gate drive signal terminal in Figure 1, the first reset signal line Re1 is used to provide the first reset signal terminal in Figure 1, the second reset signal line Re2 is used to provide the second reset signal terminal in Figure 1, and the enable signal line EM is used to provide the enable signal terminal in Figure 1. The orthographic projection of the gate line Gate on the base substrate covers the orthographic projection of the second active portion 72 on the base substrate, and part of the structure of the gate line Gate is used to form the gate of the second transistor T2. The orthographic projection of the first reset signal line Re1 on the substrate overlaps the orthographic projection of the first active portion 71 on the substrate. Part of the first reset signal line Re1 forms the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate overlaps the orthographic projections of the fourth active portion 74 and the seventh active portion 77 on the substrate. Part of the second reset signal line Re2 forms the gates of the fourth transistor T4 and the seventh transistor T7, respectively. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projections of the fifth active portion 75 and the sixth active portion 76 on the substrate. Part of the enable signal line EM forms the gates of the fifth transistors T5 and T6, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 forms the gate of the drive transistor T3 and the first electrode of the capacitor C.

[0113] As shown in Figures 20, 23, and 28, the second conductive layer may include a first initial signal line 2Vinit1, a second initial signal line 2Vinit2, a second conductive portion 22, and a third conductive portion 23. The first initial signal line 2Vinit1 can be used to provide the first initial signal terminal in Figure 1, and the second initial signal line 2Vinit2 can be used to provide the second initial signal terminal in Figure 1. The orthographic projection of the first initial signal line 2Vinit1 on the base substrate and the orthographic projection of the second initial signal line 2Vinit2 on the base substrate can both extend along the first direction X. The orthographic projection of the second conductive portion 22 on the base substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate. The second conductive portion 22 can be used to form a second electrode of the capacitor C, wherein a plurality of second conductive portions 22 distributed in the first direction X can be connected in sequence. The orthographic projection of the third conductive portion 23 on the substrate and the orthographic projection of the third sub-active portion 723 on the substrate at least partially overlap. The third conductive portion 23 can be connected to the first initial signal line 2Vinit1. The third conductive portion 23 can stabilize the voltage of the third sub-active portion 723, thereby improving the problem of leakage to the source and drain of the second transistor T2 due to voltage changes in the third sub-active portion 723.

[0114] As shown in Figures 20, 21 and 27, the third sub-active portion 723 has an enlarged setting, which can increase the overlapping area of ​​the third sub-active portion 723 and the third conductive portion 23 in the positive projection on the base substrate, thereby improving the voltage stabilizing effect of the third conductive portion 23 on the third sub-active portion 723.

[0115] As shown in Figures 20, 23, and 28, the positive projection of the second initial signal line 2Vinit2 corresponding to the pixel driving circuit in the adjacent previous row can at least partially overlap with the positive projection of the sixth sub-active portion 716 on the substrate substrate. The second initial signal line 2Vinit2 corresponding to the pixel driving circuit in the adjacent previous row can stabilize the sixth sub-active portion 716, thereby improving the problem of leakage to the source and drain of the first transistor T1 due to the voltage change of the sixth sub-active portion 716.

[0116] As shown in Figures 20, 23, and 28, the pixel driving circuit shown in Figure 20 is the pixel driving circuit in the bottom row of the display panel. The second initial signal line 2Vinit2 corresponding to this pixel driving circuit does not need to block the sixth sub-active portion in the pixel driving circuit in the next row. Therefore, the second initial signal line 2Vinit2 corresponding to this pixel driving circuit has a slightly different structure from the second initial signal line 2Vinit2 corresponding to the pixel driving circuit in the adjacent previous row. Of course, in other exemplary embodiments, the second initial signal line 2Vinit2 corresponding to the pixel driving circuit in the bottom row of the display panel can also have the same structure as the other second initial signal lines 2Vinit2.

[0117] As shown in Figures 20, 24, and 29, the third conductive layer may include a power line 3VDD, a first initial connection line 3Vinit1, a second initial connection line 3Vinit2, a first bridge portion 31, a second bridge portion 32, a third bridge portion 33, a fourth bridge portion 34, a sixth bridge portion 36, and a seventh bridge portion 37. The power line 3VDD can be used to provide a first power terminal in the pixel driving circuit shown in Figure 1. The orthographic projections of the power line 3VDD, the first initial connection line 3Vinit1, and the second initial connection line 3Vinit2 on the substrate can extend along the second direction Y. A column of pixel driving circuits distributed in the second direction Y can be provided with a corresponding first initial connection line 3Vinit1 or a corresponding second initial connection line 3Vinit2. The orthographic projections of the first initial connection line 3Vinit1 and the second initial connection line 3Vinit2 on the substrate can be alternately distributed along the first direction X. The power line 3VDD can be connected to the second conductive portion 22 and the twelfth active portion 712 through vias, so as to connect the second electrode of the capacitor C, the first electrode of the fifth transistor T5 and the first power terminal.

[0118] As shown in Figures 20, 24, and 29, the first bridge portion 31 can be connected to the first conductive portion 11 and the ninth active portion 79 through vias, respectively, to connect the second electrode of the first transistor T1, the first electrode of the second transistor, and the gate of the driving transistor T3. An opening 221 is formed on the second conductive portion 22, and the orthographic projection of the via connected between the first conductive portion 11 and the first bridge portion 31 on the substrate is located within the orthographic projection of the opening 221 on the substrate. The second bridge portion 32 can be connected to the tenth active portion 710 through a via to connect the second electrode of the sixth transistor T6. The third bridge portion 33 can be connected to the seventeenth active portion 717 and the eighteenth active portion 718 through vias, respectively, to connect the second electrode of the fourth transistor T4 and the first electrode of the driving transistor T3. The fourth bridge portion 34 can be connected to the thirteenth active portion 713 through a via to connect the first electrode of the fourth transistor T4. The sixth bridge portion 36 can connect the first initial signal line 2Vinit1 and the eighth active portion 78 through vias, thereby connecting the first electrode and the first initial signal terminal of the first transistor T1. The seventh bridge portion 37 can connect the second initial signal line 2Vinit2 and the eleventh active portion 711 through vias, thereby connecting the first electrode and the second initial signal terminal of the seventh transistor T7. The first initial connection line 3Vinit1 can be connected to the first initial signal line 2Vinit1 intersecting with its orthographic projection on the substrate through the sixth bridge portion 36, thereby forming a grid structure of the first initial signal line 2Vinit1. This arrangement can reduce the intrinsic resistance of the first initial signal line 2Vinit1, thereby improving the uniformity of the voltage of the first initial signal terminal connected to the pixel driving circuit at different locations on the display panel. The second initial connection line 3Vinit2 can be connected to the second initial signal line 2Vinit2 that intersects with its orthographic projection on the base substrate through the seventh bridge portion 37 to form a grid structure of the second initial signal line 2Vinit2. This setting can reduce the inherent resistance of the second initial signal line 2Vinit2, thereby improving the uniformity of the second initial signal terminal voltage connected to the pixel driving circuit at different positions of the display panel.

[0119] As shown in Figures 20, 25, and 30, the fourth conductive layer may include: a data line Da, a power connection line 4VDD, and a fifth bridge portion 45. The orthographic projections of the data line Da and the power connection line 4VDD on the substrate extend along the second direction. The data line Da is used to provide the data signal terminal shown in Figure 1. The data line Da can be connected to the fourth bridge portion 34 via a via to connect to the first electrode of the fourth transistor T4. The power connection line 4VDD can be connected to the power line 3VDD via a via to form a double-layer power line. This arrangement can reduce the power line's inherent resistance, thereby improving the uniformity of the first power terminal voltage at different locations on the display panel. The fifth bridge portion 45 can be connected to the second bridge portion 32 via a via to connect to the second electrode of the sixth transistor T6.

[0120] As shown in Figures 20 and 26, the electrode layer includes multiple electrode portions: a first electrode portion G, a second electrode portion B, and a third electrode portion R. Each electrode portion can be connected to the fifth bridge portion 45 through a via to connect to the second electrode of the sixth transistor. Figure 26 shows more electrode portions corresponding to the pixel driving circuit compared to Figure 30. The display panel may also include a pixel definition layer located on the side of the electrode layer away from the base substrate. A plurality of pixel openings PH are formed on the pixel definition layer. The pixel openings PH are arranged corresponding to the electrode portions, and the orthographic projections of the pixel openings PH on the base substrate coincide with the orthographic projections of the electrode portions on the base substrate. The first electrode portion G can be used to form the electrode portion of the green light-emitting unit in the display panel, the second electrode portion B can be used to form the electrode portion of the blue light-emitting unit in the display panel, and the third electrode portion R can be used to form the electrode portion of the red light-emitting unit. Among the multiple electrode portions connected to the same row of pixel driving circuits, the second electrode portion B, the first electrode portion G, the third electrode portion R, and the first electrode portion G are alternately distributed in sequence in the row direction X; in two adjacent columns of pixel driving circuits, the multiple second electrode portions B and the multiple third electrode portions R are connected to the same column of pixel driving circuits, and the second electrode portions B and the third electrode portions R connected to the same column of pixel driving circuits are alternately distributed in sequence in the column direction Y; the multiple first electrode portions G are connected to the other column of pixel driving circuits, and the first electrode portions G connected to the same column of pixel driving circuits are spaced apart in the column direction.

[0121] As shown in Figures 20, 25, 26, and 30, the fifth bridge portion 45 raises the left side of the first electrode portion G, thereby affecting the flatness of the first electrode portion G. In this exemplary embodiment, the fourth conductive layer may further include a sixth conductive portion 46. In the same pixel driving circuit, the sixth conductive portion 46 is connected to the side of the power connection line 4VDD away from the fifth bridge portion 45. The orthographic projection of the first electrode portion G on the base substrate overlaps with the orthographic projections of the sixth conductive portion 46 and the fifth bridge portion 45 on the base substrate. The sixth conductive portion 46 and the fifth bridge portion 45 overlap with the left and right sides of the first electrode portion G, respectively, thereby improving the symmetry between the left and right sides of the first electrode portion G and, in turn, improving the flatness of the first electrode portion G.

[0122] As shown in Figures 20, 25, 26, and 30, a portion of the fourth conductive layer is connected to a portion of the third conductive layer via vias. The orthographic projections of the vias connecting the fourth and third conductive layers on the substrate do not overlap with the orthographic projections of the respective electrode portions on the substrate. This arrangement can improve the flatness of the electrode portions.

[0123] As shown in Figures 31 to 35, Figure 31 is a structural layout of another exemplary embodiment of the display panel disclosed herein, and Figure 31 only shows the third conductive layer, the fourth conductive layer, and the electrode layer in the display panel. Figure 32 is a structural layout of the third conductive layer in Figure 31, Figure 33 is a structural layout of the fourth conductive layer in Figure 31, Figure 34 is a structural layout of the electrode layer in Figure 31, and Figure 35 is a structural layout of the third conductive layer and the fourth conductive layer in Figure 31.

[0124] Compared to the display panel shown in Figure 20 , the display panel shown in Figure 31 does not have a power supply connection line 4VDD in the fourth conductive layer. In the display panel shown in Figure 31 , the sixth conductive portion 46 is connected to the fifth bridge portion 45 in the same layer. The sixth conductive portion 46 and the fifth bridge portion 45 overlap the left and right sides of the first electrode portion G, respectively. This arrangement improves the symmetry of the left and right sides of the first electrode portion G, thereby improving the flatness of the first electrode portion G.

[0125] In this exemplary embodiment, the display panel shown in Figures 20 and 31 may also include a buffer layer, a first insulating layer, a second insulating layer, a first dielectric layer, a passivation layer, a first planarization layer, and a second planarization layer. The base substrate, buffer layer, active layer, first insulating layer, first conductive layer, second insulating layer, second conductive layer, first dielectric layer, third conductive layer, passivation layer, first planarization layer, fourth conductive layer, second planarization layer, and electrode layer are stacked in sequence. The first and second insulating layers may be silicon oxide layers, the first dielectric layer may be silicon nitride layers, the passivation layer and buffer layer may be made of silicon oxide, silicon nitride, or the like, and the first and second planarization layers may be made of organic materials such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or silicon-glass bonding (SOG). The base substrate may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer may be an inorganic material. The first and second conductive layers can be made of molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate. The third and fourth conductive layers can be made of metal materials, such as molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate, or a titanium / aluminum / titanium laminate. The sheet resistance of either the first or second conductive layer can be greater than the sheet resistance of either the third or fourth conductive layer.

[0126] This exemplary embodiment also provides another display panel, which may include multiple pixel driving circuits as shown in Figure 1. In this exemplary embodiment, the display panel may also include a base substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence, and an insulating layer may be provided between the above structural layers. As shown in Figures 36 to 44, Figure 36 is a structural layout diagram of another exemplary embodiment of the display panel disclosed herein, Figure 37 is a structural layout diagram of the active layer in Figure 36, Figure 38 is a structural layout diagram of the first conductive layer in Figure 36, Figure 39 is a structural layout diagram of the second conductive layer in Figure 36, Figure 40 is a structural layout diagram of the third conductive layer in Figure 36, Figure 41 is a structural layout diagram of the fourth conductive layer in Figure 36, Figure 42 is a structural layout diagram of the active layer and the first conductive layer in Figure 36, Figure 43 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in Figure 36, and Figure 44 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in Figure 36.

[0127] As shown in Figures 36, 37, and 42, the active layer may include a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion 77. The first active portion 71 is used to form a channel region of the first transistor T1, the second active portion 72 is used to form a channel region of the second transistor T2, the third active portion 73 is used to form a channel region of the driving transistor T3, the fourth active portion 74 is used to form a channel region of the fourth transistor T4, the fifth active portion 75 is used to form a channel region of the fifth transistor T5, the sixth active portion 76 is used to form a channel region of the sixth transistor T6, and the seventh active portion 77 is used to form a channel region of the seventh transistor T7. The first active portion 71 includes a fourth sub-active portion 714 and a fifth sub-active portion 715, and the active layer further includes a sixth sub-active portion connected between the fourth sub-active portion 714 and the fifth sub-active portion 715. The second active portion 72 includes a first sub-active portion 721 and a second sub-active portion 722, and the active layer further includes a third sub-active portion 723 connected between the first sub-active portion 721 and the second sub-active portion 722. As shown in Figures 3, 4, and 10, the active layer may further include an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a seventeenth active portion 717, and an eighteenth active portion 718. Among them, the eighth active portion 78 is connected to the end of the first active portion 71 away from the second active portion 72, the ninth active portion 79 is connected between the first active portion 71 and the second active portion 72, the tenth active portion 710 is connected between the sixth active portion 76 and the seventh active portion 77, the eleventh active portion 711 is connected to the end of the seventh active portion 77 away from the sixth active portion 76, the twelfth active portion 712 is connected to the end of the fifth active portion 75 away from the third active portion 73, the thirteenth active portion 713 and the seventeenth active portion 717 are connected to both ends of the fourth active portion 74, and the eighteenth active portion 718 is connected between the fifth active portion 75 and the third active portion 73.

[0128] As shown in Figures 36, 38, and 42, the first conductive layer includes a first conductive portion 11, a gate line Gate, a first reset signal line Re1, a second reset signal line Re2, and an enable signal line EM. The orthographic projections of the gate line Gate, the first reset signal line Re1, the second reset signal line Re2, and the enable signal line EM on the base substrate extend along a first direction X. The gate line Gate is used to provide the gate drive signal terminal in Figure 1, the first reset signal line Re1 is used to provide the first reset signal terminal in Figure 1, the second reset signal line Re2 is used to provide the second reset signal terminal in Figure 1, and the enable signal line EM is used to provide the enable signal terminal in Figure 1. The orthographic projection of the gate line Gate on the base substrate covers the orthographic projection of the second active portion 72 on the base substrate, and a portion of the structure of the gate line Gate is used to form the gate of the second transistor T2. The orthographic projection of the first reset signal line Re1 on the substrate overlaps the orthographic projection of the first active portion 71 on the substrate. Part of the first reset signal line Re1 forms the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate overlaps the orthographic projections of the fourth active portion 74 and the seventh active portion 77 on the substrate. Part of the second reset signal line Re2 forms the gates of the fourth transistor T4 and the seventh transistor T7, respectively. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projections of the fifth active portion 75 and the sixth active portion 76 on the substrate. Part of the enable signal line EM forms the gates of the fifth transistors T5 and T6, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 forms the gate of the drive transistor T3 and the first electrode of the capacitor C.

[0129] As shown in Figures 36, 38, and 43, the second conductive layer may include a first initial signal line 2Vinit1, a second initial signal line 2Vinit2, a second conductive portion 22, and a third conductive portion 23. The first initial signal line 2Vinit1 can be used to provide the first initial signal terminal in Figure 1, and the second initial signal line 2Vinit2 can be used to provide the second initial signal terminal in Figure 1. The orthographic projection of the first initial signal line 2Vinit1 on the base substrate and the orthographic projection of the second initial signal line 2Vinit2 on the base substrate can both extend along the first direction X. The orthographic projection of the second conductive portion 22 on the base substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate. The second conductive portion 22 can be used to form a second electrode of the capacitor C, wherein a plurality of second conductive portions 22 distributed in the first direction X can be connected in sequence. The orthographic projection of the third conductive portion 23 on the substrate and the orthographic projection of the third sub-active portion 723 on the substrate at least partially overlap. The third conductive portion 23 can be connected to the first initial signal line 2Vinit1. The third conductive portion 23 can stabilize the voltage of the third sub-active portion 723, thereby improving the problem of leakage to the source and drain of the second transistor T2 due to voltage changes in the third sub-active portion 723.

[0130] As shown in Figures 36, 37, and 42, the second sub-active portion 722, serving as a channel region, includes a second side 7222 extending along the length of the channel region, and the third sub-active portion 723 includes a fourth side 7234. The fourth side 7234 is connected to the second side 7222, and the angle formed by the fourth side 7234 and the second side 7222 is less than 180°. In other words, the third sub-active portion 723 has an enlarged configuration, which increases the overlapping area of ​​the orthographic projection of the third sub-active portion 723 and the third conductive portion 23 on the substrate, thereby improving the voltage stabilization effect of the third conductive portion 23 on the third sub-active portion 723.

[0131] As shown in Figures 36, 37 and 42, in the first direction X, the orthographic projection of the fourth active portion 74 on the base substrate is located between the orthographic projection of at least part of the structure of the third active portion 73 on the base substrate and the orthographic projection of the fifth active portion 75 on the base substrate.

[0132] In this exemplary embodiment, the fifth transistor T5 is positioned on the side of the fourth transistor T4 away from the driving transistor T3, thereby reserving more design space for the capacitor C. A larger capacitor C can help improve low-frequency flicker in the display panel and enhance low-grayscale image quality. Furthermore, by positioning the fifth transistor T5 on the side of the fourth transistor T4 away from the driving transistor T3, the portion of the active layer where the first electrode of the fifth transistor resides can be arranged without bending, thus facilitating spatial design of the display panel layout.

[0133] As shown in Figures 36, 40, and 44, the third conductive layer may include a power line 3VDD, a first initial connection line 3Vinit1, a second initial connection line 3Vinit2, a first bridge portion 31, a second bridge portion 32, a third bridge portion 33, a fourth bridge portion 34, a sixth bridge portion 36, a seventh bridge portion 37, and an eighth bridge portion 38. The power line 3VDD can be used to provide the first power terminal in the pixel driving circuit shown in Figure 1. The orthographic projections of the power line 3VDD, the first initial connection line 3Vinit1, and the second initial connection line 3Vinit2 on the substrate can extend along the second direction Y. A column of pixel driving circuits distributed in the second direction Y can be provided with either a corresponding first initial connection line 3Vinit1 or a corresponding second initial connection line 3Vinit2. The orthographic projections of the first initial connection line 3Vinit1 and the second initial connection line 3Vinit2 on the substrate can be alternately distributed along the first direction X. The power line 3VDD can be connected to the second conductive portion 22 via a via, thereby connecting the second electrode of the capacitor C to the first power terminal.

[0134] As shown in Figures 36, 40, and 44, the first bridge portion 31 can be connected to the first conductive portion 11 and the ninth active portion 79 through vias, respectively, to connect the second electrode of the first transistor T1, the first electrode of the second transistor, and the gate of the driving transistor T3. An opening 221 is formed on the second conductive portion 22, and the orthographic projection of the via connected between the first conductive portion 11 and the first bridge portion 31 on the substrate is located within the orthographic projection of the opening 221 on the substrate. The second bridge portion 32 can be connected to the tenth active portion 710 through a via to connect the second electrode of the sixth transistor T6. The third bridge portion 33 can be connected to the seventeenth active portion 717 and the eighteenth active portion 718 through vias, respectively, to connect the second electrode of the fourth transistor T4 and the first electrode of the driving transistor T3. The fourth bridge portion 34 can be connected to the thirteenth active portion 713 through a via to connect the first electrode of the fourth transistor T4. The sixth bridge portion 36 can connect the first initial signal line 2Vinit1 and the eighth active portion 78 through vias, thereby connecting the first electrode and the first initial signal terminal of the first transistor T1. The seventh bridge portion 37 can connect the second initial signal line 2Vinit2 and the eleventh active portion 711 through vias, thereby connecting the first electrode and the second initial signal terminal of the seventh transistor T7. The first initial connection line 3Vinit1 can be connected to the first initial signal line 2Vinit1 intersecting with its orthographic projection on the substrate through the sixth bridge portion 36, thereby forming a grid structure of the first initial signal line 2Vinit1. This arrangement can reduce the intrinsic resistance of the first initial signal line 2Vinit1, thereby improving the uniformity of the voltage of the first initial signal terminal connected to the pixel driving circuit at different locations on the display panel. The second initial connection line 3Vinit2 can be connected to the second initial signal line 2Vinit2, which intersects its orthographic projection on the substrate, via the seventh bridge portion 37, to form a grid structure of the second initial signal line 2Vinit2. This arrangement can reduce the intrinsic resistance of the second initial signal line 2Vinit2, thereby improving the uniformity of the voltage at the second initial signal terminal connected to the pixel driving circuit at different locations on the display panel. The eighth bridge portion 38 can be connected to the twelfth active portion 712 via a via to connect to the first electrode of the fifth transistor T5.

[0135] As shown in Figures 36 and 41 , the fourth conductive layer may include a data line Da and a power connection line 4VDD. The orthographic projections of the data line Da and the power connection line 4VDD on the substrate extend along the second direction. The data line Da is used to provide the data signal terminal shown in Figure 1 . The data line Da can be connected to the fourth bridge portion 34 via a via to connect to the first electrode of the fourth transistor T4. The power connection line 4VDD can also be connected to the power line 3VDD via a via to form a double-layer power line. This configuration can reduce the power line's inherent resistance, thereby improving the uniformity of the voltage at the first power terminal at different locations on the display panel.

[0136] In this exemplary embodiment, the display panel shown in FIG. 36 may also include a buffer layer, a first insulating layer, a second insulating layer, a first dielectric layer, a passivation layer, a first planarization layer, a second planarization layer, and an electrode layer. The base substrate, buffer layer, active layer, first insulating layer, first conductive layer, second insulating layer, second conductive layer, first dielectric layer, third conductive layer, passivation layer, first planarization layer, fourth conductive layer, second planarization layer, and electrode layer are stacked in sequence. The first and second insulating layers may be silicon oxide layers, the first dielectric layer may be silicon nitride layers, the passivation layer and buffer layer may be made of silicon oxide, silicon nitride, or the like, and the first and second planarization layers may be made of organic materials such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or silicon-glass bonding (SOG). The base substrate may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer may be an inorganic material. The first and second conductive layers can be made of molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate. The third and fourth conductive layers can be made of metal materials, such as molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate, or a titanium / aluminum / titanium laminate. The sheet resistance of either the first or second conductive layer can be greater than the sheet resistance of either the third or fourth conductive layer.

[0137] As shown in Figure 45, a schematic diagram of the structure of an exemplary embodiment of the display panel of the present disclosure is shown. The display panel may further include a first initial routing line 4Vinit1 and a second initial routing line 4Vinit2. The orthographic projections of the first initial routing line 4Vinit1 and the second initial routing line 4Vinit2 on the substrate extend along the first direction X. The orthographic projections of the first initial routing line 4Vinit1 and the second initial routing line 4Vinit2 on the substrate are located on one side of the orthographic projections of the first initial connecting line 3Vinit1 and the second initial connecting line 3Vinit2 on the substrate in the second direction Y. The first initial routing line 4Vinit1 connects multiple first initial connecting lines 3Vinit1, and the second initial routing line 4Vinit2 connects multiple second initial connecting lines 3Vinit1.

[0138] Since the sheet resistance of the third conductive layer is smaller than that of the second conductive layer, this exemplary embodiment provides initial signals to the first initial connection line 3Vinit1 and the second initial connection line 3Vinit2 with smaller sheet resistance through the first initial routing line 4Vinit1 and the second initial routing line 4Vinit2, respectively, thereby improving the writing speed of the initial signal.

[0139] As shown in Figures 46 to 48, Figure 46 is an enlarged view of the local area C in Figure 45, Figure 47 is a structural layout of the third conductive layer in Figure 46, and Figure 48 is a structural layout of the fourth conductive layer in Figure 46. In this exemplary embodiment, the third conductive layer may further include: a plurality of gate line access lines 3Gate, a second connecting portion 322, the orthographic projections of the plurality of gate line access lines 4Gate on the substrate extending along the first direction X and spaced apart along the second direction, and the gate line access lines 4Gate connected between the gate drive circuit and the pixel drive circuit. The gate drive circuit can provide a gate drive signal to the first reset signal line, the second reset signal line, the enable signal line and other gate lines located in the pixel area Pix through the gate line access lines 4Gate, and the pixel area Pix is ​​used to integrate the pixel drive circuit. As shown in Figures 46 to 48, the first initial routing line 4Vinit1 and the second initial routing line 4Vinit2 located in the rounded corner area of ​​the display panel are located in the fourth conductive layer. In the rounded corner area of ​​the display panel, the orthographic projections of the first initial routing line 4Vinit1 and the second initial routing line 4Vinit2 on the base substrate bend and extend along the first direction X. The orthographic projections of the first initial routing line 4Vinit1 and the second initial routing line 4Vinit2 on the base substrate are located between the orthographic projections of two adjacent gate line access lines 4Gate on the base substrate. The orthographic projection of the second connecting portion 322 on the base substrate extends along the second direction Y and intersects with the orthographic projection of the first initial routing line 4Vinit1 on the base substrate. The second connecting portion 322 is connected between the second initial routing line 4Vinit2 and the second initial connecting line 3Vinit2. The fourth conductive layer further includes a third connecting portion 43, the orthographic projection of the third connecting portion 43 on the substrate extending along the second direction Y and intersecting with the orthographic projection of a portion of the gate access line 4Gate on the substrate, the third connecting portion 43 being connected between the second connecting portion 322 and the second initial connection line 3Vinit2 located in the pixel area Pix. The first initial trace 4Vinit1 can be connected to the first initial connection line located in the pixel area Pix via a seventh connecting portion 47 connected to the same layer as the first initial trace 4Vinit1.

[0140] As shown in Figures 46 to 48, the fourth conductive layer may further include a power access line 4VDDx, which may be connected to the power connection line 4VDD located in the pixel area Pix through a fifth connection portion 325 located in the third conductive layer and a fourth connection portion 44 located in the fourth conductive layer.

[0141] As shown in Figures 3 and 20, the orthographic projection of the second electrode portion B on the substrate overlaps the orthographic projections of two adjacent data lines Da on the substrate, and the orthographic projections of the two adjacent data lines Da on the substrate in the first direction X are respectively arranged close to the orthographic projections of the overlapping electrode portion on the substrate in the first direction. This arrangement can improve the left-right symmetry of the second electrode portion B, thereby improving the flatness of the second electrode portion B. It should be understood that in other exemplary embodiments, two adjacent data lines may also overlap with other electrode portions to improve the flatness of the overlapping electrode portion.

[0142] As shown in FIG49 , which is an enlarged view of the local area D in FIG45 , the display panel further includes a gate drive circuit GOA and a plurality of pixel drive circuits. The fourth conductive layer further includes an analog data line Dda, whose orthographic projection on the base substrate extends along the second direction Y. The orthographic projection of the analog data line Dda on the base substrate is located between the orthographic projection of the gate drive circuit GOA on the base substrate and the orthographic projection of the data line Da closest to the gate drive circuit GOA on the base substrate. The orthographic projections of the analog data line Dda and the adjacent data line Da on the base substrate overlap with the orthographic projection of the second electrode portion B on the base substrate. Furthermore, the orthographic projections of the adjacent analog data line Dda and the data line Da on the base substrate are located adjacent to each other in the first direction X on either side of the orthographic projection of the overlapping second electrode portion B on the base substrate. In this exemplary embodiment, the addition of the analog data line Dda improves the flatness of the electrode portion closest to the gate drive circuit.

[0143] In this exemplary embodiment, as shown in FIG49 , the second initial trace 4Vinit2 can be connected to the analog data line Dda, which can be connected to multiple second initial signal lines located in the pixel area Pix through vias. This arrangement can also increase the access points for the second initial signal lines on both sides of the display panel, thereby further improving the writing speed of the initial signal.

[0144] As shown in FIG50 , which is an enlarged view of the local area E in FIG45 , first initial trace 4Vinit1 and second initial trace 4Vinit2 are located on the third conductive layer in the straight region of the lower frame of the display panel. In the straight region of the display panel, the orthographic projections of first initial trace 4Vinit1 and second initial trace 4Vinit2 on the substrate extend linearly along the first direction. Second initial trace 4Vinit2 can connect to the second initial connection line located in pixel area Pix via ninth connection portion 49 located on the fourth conductive layer.

[0145] It should be noted that, in this exemplary embodiment, the positions of the first initial routing 4Vinit1 and the second initial routing 4Vinit2 can also be swapped, that is, the orthographic projection of the first initial routing 4Vinit1 on the substrate is located on the side of the orthographic projection of the second initial routing 4Vinit2 on the substrate away from the orthographic projection of the first initial connection line on the substrate.

[0146] It should be noted that in this exemplary embodiment, the black squares drawn on the side of the third conductive layer facing away from the base substrate represent vias connecting the third conductive layer to other layers on the side facing the base substrate; the black squares drawn on the side of the fourth conductive layer facing away from the base substrate represent vias connecting the fourth conductive layer to other layers on the side facing the base substrate; and the black squares drawn on the side of the electrode layer facing away from the base substrate represent vias connecting the electrode layer to other layers on the side facing the base substrate. The black squares indicate the locations of the vias, and different vias represented by black squares in different locations can penetrate different insulating layers.

[0147] It should be noted that the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to define different structure names and do not have a specific order or quantity meaning. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending straight or curved along the direction. A transistor refers to an element that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this exemplary embodiment, the channel region refers to the region where current mainly flows. In this exemplary embodiment, the first electrode can be a drain and the second electrode can be a source, or the first electrode can be a source and the second electrode can be a drain. When using transistors with opposite polarity or when the direction of current changes during circuit operation, the functions of "source" and "drain" are sometimes reversed. Therefore, in this exemplary embodiment, "source" and "drain" can be reversed. Furthermore, the gate electrode can also be referred to as a control electrode.

[0148] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0149] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0150] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0151] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel comprises: substrate substrate; A plurality of first initial signal lines, the orthographic projections of which on the substrate extend along a first direction and are spaced apart along a second direction, wherein the first direction and the second direction intersect; A plurality of second initial signal lines are located in the same conductive layer as the first initial signal lines, and the orthographic projections of the second initial signal lines on the base substrate extend along the first direction and are spaced apart along the second direction; a plurality of first initial connection lines, which are located in a different conductive layer from the first initial signal lines, the orthographic projections of the plurality of first initial connection lines on the substrate extending along the second direction and spaced apart along the first direction, and the first initial connection lines connected to at least a portion of the first initial signal lines whose orthographic projections on the substrate intersect with the first initial connection lines through vias; A plurality of second initial connection lines are located in the same conductive layer as the first initial connection lines, the orthographic projections of the plurality of second initial connection lines on the substrate extend along the second direction and are spaced apart along the first direction, and the second initial connection lines are connected through vias to at least a portion of the second initial signal lines whose orthographic projections on the substrate intersect with the second initial signal lines.

2. The display panel according to claim 1, wherein: The display panel further includes: A second conductive layer, located on one side of the base substrate, the second conductive layer comprising the first initial signal line and the second initial signal line; The third conductive layer is located on a side of the second conductive layer away from the substrate, and the third conductive layer includes the first initial connection line and the second initial connection line.

3. The display panel according to claim 2, wherein: The display panel further includes a pixel driving circuit, the pixel driving circuit includes a driving transistor, a first transistor, and a capacitor, a first electrode of the capacitor is connected to a gate of the driving transistor, a first electrode of the first transistor is connected to the first initial signal line, and a second electrode is connected to the gate of the driving transistor; The display panel further includes: a first conductive layer, located between the second conductive layer and the base substrate, the first conductive layer comprising a first conductive portion, the first conductive portion being used to form a gate of the driving transistor and a first electrode of the capacitor; The second conductive layer further comprises: a second conductive portion, an orthographic projection of the second conductive portion on the base substrate and an orthographic projection of the first conductive portion on the base substrate at least partially overlapping, and the second conductive portion is used to form a second electrode of the capacitor; The third conductive layer further comprises: A first bridge portion, wherein the first bridge portion is connected to the first conductive portion through a via hole and is connected to the second electrode of the first transistor.

4. The display panel according to claim 1, wherein: The display panel further includes a pixel driving circuit, wherein the pixel driving circuit includes a driving transistor, a fourth transistor, and a second transistor; The first electrode of the fourth transistor is connected to the data line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the second reset signal line; The first electrode of the second transistor is connected to the gate of the driving transistor, the second electrode is connected to the second electrode of the driving transistor, and the gate is connected to the gate line.

5. The display panel according to claim 1, wherein: The display panel further includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and a second transistor, a first electrode of the second transistor is connected to a gate of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; The display panel further includes: an active layer, located on one side of the base substrate, the active layer comprising a second active portion, the second active portion being used to form a channel region of the second transistor, the second active portion comprising a first sub-active portion and a second sub-active portion, and the active layer further comprising a third sub-active portion connected between the first sub-active portion and the second sub-active portion; The second conductive layer is located on the side of the active layer away from the substrate, the second conductive layer includes a third conductive portion, the orthographic projection of the third conductive portion on the substrate and the orthographic projection of the third sub-active portion on the substrate at least partially overlap, and the third conductive portion is connected to a stable voltage source.

6. The display panel according to claim 5, wherein: The first sub-active portion as a channel region includes a first side extending along the length direction of the channel region, the second sub-active portion as a channel region includes a second side extending along the length direction of the channel region, and the third sub-active portion includes a third side and a fourth side; Wherein, the third side is connected to the first side, and an angle formed by the third side and the first side is less than or equal to 180°; And / or, the fourth side is connected to the second side, and an angle formed by the fourth side and the second side is less than or equal to 180°.

7. The display panel according to claim 5, wherein: The display panel further includes: A power line, the power line is used to provide a power signal to the pixel driving circuit, and the power line is connected to the third conductive part through a via hole.

8. The display panel according to claim 5, wherein: The second conductive layer includes the first initial signal line, and the first initial signal line and the third conductive part are connected in the same layer.

9. The display panel according to claim 5, wherein: The pixel driving circuit further comprises a capacitor, a first electrode of the capacitor being connected to the gate of the driving transistor; The second conductive layer further comprises: a second conductive portion, the second conductive portion being used to form a second electrode of the capacitor; The third conductive part and the second conductive part are connected in the same layer.

10. The display panel according to claim 1, wherein: The display panel includes a pixel driving circuit arrayed in the first direction and the second direction, the pixel driving circuit includes a driving transistor and a capacitor, and a first electrode of the capacitor is connected to a gate of the driving transistor; The display panel further includes: a second conductive layer, the second conductive layer comprising a second conductive portion and a fourth conductive portion, the second conductive portion being used to form a second electrode of the capacitor, and the fourth conductive portion being connected between the second conductive portions adjacent to each other in the first direction; A third conductive layer is located on a side of the second conductive layer away from the substrate, the third conductive layer comprising a power line, and the power line is used to provide a power signal to the pixel driving circuit; Wherein, the power line comprises: a first extension portion, a second extension portion, and a third extension portion, and the third extension portion is connected between the first extension portion and the second extension portion; The orthographic projection of the first extension portion on the base substrate and the orthographic projection of the second extension portion on the base substrate extend along the second direction, and the orthographic projection of the third extension portion on the base substrate extends along the first direction; The orthographic projection of the third extension portion on the substrate and the orthographic projection of the fourth conductive portion on the substrate The orthographic projections on the substrate at least partially overlap.

11. The display panel according to claim 2, wherein: The display panel further includes: a fourth conductive layer, located on a side of the third conductive layer away from the base substrate, the fourth conductive layer comprising a plurality of data lines, and an orthographic projection of the data lines on the base substrate extending along the second direction; Wherein, the orthographic projection of part of the data lines on the base substrate and the orthographic projection of the first initial connection line on the base substrate at least partially overlap; And / or, an orthographic projection of a portion of the data lines on the base substrate and an orthographic projection of the second initial connection line on the base substrate at least partially overlap.

12. The display panel according to claim 11, wherein: In the data line and the first initial connection line whose orthographic projections on the base substrate intersect, an overlapping area of ​​the orthographic projection of the data line on the base substrate and the orthographic projection of the first initial connection line on the base substrate is S1, an area of ​​the orthographic projection of the data line on the base substrate is S2, and S1 / S2 is greater than or equal to 50%; And / or, among the data line and the second initial connection line whose orthographic projections on the base substrate intersect, the overlapping area of ​​the orthographic projection of the data line on the base substrate and the orthographic projection of the second initial connection line on the base substrate is S3, the area of ​​the orthographic projection of the data line on the base substrate is S4, and S3 / S4 is greater than or equal to 50%.

13. The display panel according to claim 2, wherein: The display panel includes a pixel driving circuit, and the third conductive layer further includes: A first connecting portion, an orthographic projection of which on the base substrate extends along the first direction, and the first connecting portion is connected between the first initial connecting line and the pixel driving circuit; A plurality of power lines, used for providing power signals to the pixel driving circuit; Part of the multiple power lines include multiple power line segments spaced apart in the second direction, and the orthographic projection of the first connecting portion on the base substrate is located between the orthographic projections of adjacent power line segments in the same power line on the base substrate.

14. The display panel according to claim 1, wherein: The display panel further includes: A third conductive layer is located on one side of the substrate; a fourth conductive layer, located on a side of the third conductive layer away from the substrate, wherein a partial structure of the fourth conductive layer is connected to a partial structure of the third conductive layer through a via hole; An electrode layer, located on a side of the fourth conductive layer away from the base substrate, the electrode layer comprising a plurality of electrode portions; a pixel definition layer, located on a side of the electrode layer away from the base substrate, wherein a plurality of pixel openings are formed on the pixel definition layer, wherein the pixel openings and the electrode portions are arranged correspondingly, and the orthographic projections of the pixel openings on the base substrate coincide with the orthographic projections of the corresponding electrode portions on the base substrate; The orthographic projection of the via hole connected between the third conductive layer and the fourth conductive layer on the base substrate does not overlap with the orthographic projection of the electrode portion on the base substrate.

15. The display panel according to claim 1, wherein: The display panel further includes: A fourth conductive layer, located on one side of the base substrate, the fourth conductive layer comprising a plurality of fifth bridge portions; an electrode layer, located on a side of the fourth conductive layer away from the base substrate, the electrode layer comprising a plurality of electrode portions, the electrode portions and the fifth bridge portions being arranged correspondingly, and the electrode portions being connected to the corresponding fifth bridge portions through via holes; a pixel definition layer, located on a side of the electrode layer away from the base substrate, wherein a plurality of pixel openings are formed on the pixel definition layer, wherein the pixel openings and the electrode portions are arranged correspondingly, and the orthographic projections of the pixel openings on the base substrate coincide with the orthographic projections of the corresponding electrode portions on the base substrate; The fourth conductive layer further includes a sixth conductive portion, and the orthographic projection of a portion of the electrode portion on the base substrate overlaps with the orthographic projection of the sixth conductive portion on the base substrate and the orthographic projection of the fifth bridge portion on the base substrate respectively; The sixth conductive portion is arranged on one side of the orthographic projection of the electrode portion on the base substrate in the first direction, and the orthographic projection of the fifth bridging portion on the base substrate is arranged on the other side of the orthographic projection of the electrode portion on the base substrate in the first direction.

16. The display panel according to claim 15, wherein: The display panel further includes a pixel driving circuit, and the fourth conductive layer further includes: a power connection line, the orthographic projection of which on the substrate extends along the second direction, and the power connection line is used to provide a power signal to the pixel driving circuit; The sixth conductive portion is connected to the power connection line, and the power connection line is connected to the substrate base. The orthographic projection on the board is located between the orthographic projection of the sixth conductive part on the base substrate and the orthographic projection of the fifth bridge part on the base substrate, and the orthographic projection of the power connection line on the base substrate overlaps with the orthographic projection of the electrode part on the base substrate.

17. The display panel according to claim 15, wherein: The fifth bridging portion is connected to the sixth conductive portion.

18. The display panel according to claim 1, wherein: The display panel further includes a pixel driving circuit, wherein the pixel driving circuit includes a driving transistor, a fourth transistor, and a fifth transistor; A first electrode of the fourth transistor is connected to the data line, and a second electrode is connected to the first electrode of the driving transistor; A first electrode of the fifth transistor is connected to a power line, and a second electrode is connected to a first electrode of the driving transistor; The display panel further includes: an active layer, located on one side of the base substrate, the active layer comprising a third active portion, a fourth active portion, and a fifth active portion, the third active portion being used to form a channel region of the driving transistor, the fourth active portion being used to form a channel region of the fourth transistor, and the fifth active portion being used to form a channel region of the fifth transistor; A first conductive layer, located on a side of the active layer away from the base substrate, the first conductive layer comprising a first conductive portion, a second reset signal line, and an enable signal line; The orthographic projection of the first conductive portion on the base substrate covers the orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form a gate of the driving transistor; The orthographic projection of the second reset signal line on the base substrate extends along the first direction and covers the orthographic projection of the fourth active portion on the base substrate, and a partial structure of the second reset signal line is used to form a gate of the fourth transistor; The orthographic projection of the enable signal line on the base substrate extends along the first direction and covers the orthographic projection of the fifth active portion on the base substrate, and a partial structure of the enable signal line is used to form a gate of the fifth transistor; The positive projection of the enable signal line on the base substrate is located between the positive projection of the first conductive portion on the base substrate and the positive projection of the second reset signal line on the base substrate. Between projections; Wherein, in the first direction, the orthographic projection of the fifth active portion on the substrate is located between the orthographic projection of at least a part of the structure of the third active portion on the substrate and the orthographic projection of the fourth active portion on the substrate; Alternatively, in the first direction, the orthographic projection of the fourth active portion on the substrate is located between the orthographic projection of at least a partial structure of the third active portion on the substrate and the orthographic projection of the fifth active portion on the substrate.

19. The display panel according to claim 2, wherein: The square resistance of the second conductive layer is greater than the square resistance of the third conductive layer, and the display panel further includes: a first initial routing line and a second initial routing line; Among them, the orthographic projections of the first initial routing and the second initial routing on the substrate extend along the first direction, the orthographic projections of the first initial routing and the second initial routing on the substrate are located on one side of the orthographic projections of the first initial connecting line and the second initial connecting line on the substrate in the second direction, the first initial routing connects multiple first initial connecting lines, and the second initial routing connects multiple second initial connecting lines.

20. The display panel according to claim 19, wherein: The display panel also includes a pixel driving circuit and a gate driving circuit; The orthographic projection of the second initial routing line on the substrate is located on a side of the orthographic projection of the first initial routing line on the substrate away from the orthographic projections of the first initial connecting line and the second initial connecting line on the substrate; The third conductive layer further comprises: A plurality of gate line access lines, the orthographic projections of the plurality of gate line access lines on the substrate extend along the first direction and are spaced apart along the second direction, and the gate line access lines are connected between the gate driving circuit and the pixel driving circuit.

21. The display panel according to claim 1, wherein: The display panel also includes a gate driving circuit and a plurality of pixel driving circuits; The display panel further includes: a fourth conductive layer, located on one side of the base substrate, the fourth conductive layer comprising a plurality of data lines, the data lines being used to provide data signals to the pixel driving circuit, the orthographic projections of the plurality of data lines on the base substrate extending along the second direction and spaced along the first direction; Interval setting; an electrode layer, located on a side of the fourth conductive layer away from the base substrate, the electrode layer comprising a plurality of electrode portions; a pixel definition layer, located on a side of the electrode layer away from the base substrate, wherein a plurality of pixel openings are formed on the pixel definition layer, wherein the pixel openings and the electrode portions are arranged correspondingly, and the orthographic projections of the pixel openings on the base substrate coincide with the orthographic projections of the corresponding electrode portions on the base substrate; The orthographic projections of part of the electrode parts on the base substrate overlap with the orthographic projections of two adjacent data lines in the first direction on the base substrate, and the orthographic projections of two adjacent data lines in the first direction on the base substrate are respectively arranged close to the two sides of the orthographic projections of the overlapping electrode parts on the base substrate in the first direction; The fourth conductive layer further comprises: an analog data line, the orthographic projection of which on the substrate extends along the second direction, and the orthographic projection of which on the substrate is located between the orthographic projection of the gate driving circuit on the substrate and the orthographic projection of the data line closest to the gate driving circuit on the substrate; The orthographic projections of the analog data line and the data line adjacent thereto on the base substrate overlap with the orthographic projection of the same electrode portion on the base substrate, and the orthographic projections of the analog data line and the data line adjacent thereto in the first direction on the base substrate are respectively arranged close to the orthographic projections of the overlapping electrode portion on the base substrate on both sides in the first direction.

22. The display panel according to claim 21, wherein: The display panel further includes a first initial routing line and a second initial routing line; The orthographic projections of the first initial routing line and the second initial routing line on the substrate extend along the first direction, the orthographic projections of the first initial routing line and the second initial routing line on the substrate are located on one side of the orthographic projections of the first initial connecting line and the second initial connecting line on the substrate in the second direction, the first initial routing line connects a plurality of the first initial connecting lines, and the second initial routing line connects a plurality of the second initial connecting lines; The orthographic projection of the second initial routing line on the substrate is located on a side of the orthographic projection of the first initial routing line on the substrate away from the orthographic projections of the first initial connecting line and the second initial connecting line on the substrate; The second initial signal line is connected to the analog data line, and the analog data line is connected to a plurality of the second initial signal lines through vias.

23. A display panel, wherein: The display panel comprises: substrate substrate; A plurality of first initial signal lines, the orthographic projections of which on the substrate extend along a first direction and are spaced apart along a second direction, wherein the first direction and the second direction intersect; A plurality of second initial signal lines are located in the same conductive layer as the first initial signal lines, and the orthographic projections of the second initial signal lines on the base substrate extend along the first direction and are spaced apart along the second direction; a plurality of first initial connection lines, which are located in a different conductive layer from the first initial signal lines, wherein the orthographic projections of the plurality of first initial connection lines on the substrate extend along the second direction and are spaced apart along the first direction, and the first initial connection lines are connected to at least a portion of the first initial signal lines whose orthographic projections on the substrate intersect with the first initial connection lines; a plurality of second initial connection lines, which are located in the same conductive layer as the first initial connection lines, wherein the orthographic projections of the plurality of second initial connection lines on the substrate extend along the second direction and are spaced apart along the first direction, and the second initial connection lines are connected to at least a portion of the second initial signal lines whose orthographic projections on the substrate intersect with the second initial signal lines; A plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are arranged in an array along the first direction and the second direction, wherein the first direction is a row direction and the second direction is a column direction; Each row of the pixel driving circuits is correspondingly provided with a first initial signal line and a second initial signal line, and each column of the pixel driving circuits is correspondingly provided with a first initial connection line or a second initial connection line; The orthographic projection of the first initial connection line on the base substrate and the orthographic projection of the second initial connection line on the base substrate are alternately distributed in sequence in the first direction.

24. The display panel according to claim 23, wherein: The display panel includes a pixel driving circuit and a light emitting unit, and the pixel driving circuit includes: Driver transistor; a first transistor, a first electrode connected to the first initial signal line, a second electrode connected to the gate of the driving transistor, and a gate connected to the first reset signal line; A second transistor, a first electrode connected to the gate of the driving transistor, and a second electrode connected to the driving transistor The second electrode of the driving transistor, the gate is connected to the gate line; a fourth transistor, a first electrode connected to the data line, a second electrode connected to the first electrode of the driving transistor, and a gate connected to the second reset signal line; a fifth transistor, a first electrode connected to a power line, a second electrode connected to the first electrode of the driving transistor, and a gate connected to an enable signal line; a sixth transistor, a first electrode connected to the second electrode of the driving transistor, a second electrode connected to the first electrode of the light emitting unit, and a gate connected to the enable signal line; a seventh transistor, a first electrode connected to the second initial signal line, a second electrode connected to the first electrode of the light unit, and a gate connected to the second reset signal line; A capacitor, a first electrode of which is connected to the gate of the driving transistor, and a second electrode of which is connected to the power line.

25. The display panel according to claim 24, wherein: The display panel further includes: an active layer, located on one side of the substrate, wherein a portion of the active layer is used to form channel regions of the first transistor, the second transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, respectively; a first conductive layer, located on a side of the active layer away from the base substrate, the first conductive layer comprising a first conductive portion, a first reset signal line, a second reset signal line, and an enable signal line, the first conductive portion being used to form a gate of the driving transistor, a partial structure of the first reset signal line being used to form a gate of the first transistor, a partial structure of the second reset signal line being used to form gates of the fourth transistor and the seventh transistor, respectively, and a partial structure of the enable signal line being used to form gates of the fifth transistor and the sixth transistor, respectively; Wherein, the orthographic projection of the first conductive portion on the base substrate is located between the orthographic projection of the first reset signal line on the base substrate and the orthographic projection of the enable signal line on the base substrate; The orthographic projection of the second reset signal line on the base substrate is located on a side of the orthographic projection of the enable signal line on the base substrate away from the orthographic projection of the first conductive portion on the base substrate.

26. A display device, wherein: The display device comprises the display panel according to any one of claims 1-25.

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