Cache distribution method, system, equipment and medium

Abstract

The invention discloses a cache distribution method, system and device and a medium. The method comprises the steps that target acceleration process information is acquired; determining a target acceleration process according to the target acceleration process information; all the small-core CPUs are divided into a first cpush, and all the large-core CPUs are divided into a second cpush; scheduling the target acceleration process to a second cpush; sampling the last level of cache event to determine the cache reference times and the cache miss times of the target acceleration process; calculating a first ratio of the cache reference times to the cache miss times; and distributing LLC of different sizes to the first cpush according to the first ratio, and using the complete LLC by the second cpush. The whole LLC is allocated to the target acceleration process, and the other processes determine the corresponding LLC partitions according to the first ratio, so that the target acceleration process is ensured not to use the LLC by the other processes, the cache miss value and the operation delay of the target acceleration process are reduced, and the method can be widely applied to the technical field of memories.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a cache allocation method, system, device and medium. Background Art

[0002] As modern electronic devices have higher and higher requirements on processor performance, it becomes more and more important to optimize the internal structure of the processor. In order to improve the operating efficiency of the processor and reduce the time for the processor to access the main memory, a cache memory is introduced between the processor and the main memory.

[0003] During the operation of the existing Android or Linux system, all processes share the complete last level cache fairly. When the system runs an important bandwidth resource-based process, other processes may frequently compete and preempt the cache with the process, thereby increasing the cache miss value and runtime latency of the important process. Summary of the invention

[0004] In view of this, the purpose of the embodiments of the present invention is to provide a cache allocation method, system, device and medium, which can identify and allocate corresponding cache to accelerate bandwidth resource-based processes and reduce cache miss values ​​and runtime delays of bandwidth resource-based processes.

[0005] In a first aspect, an embodiment of the present invention provides a cache allocation method, comprising: Get target acceleration process information; Determine a target acceleration process according to the target acceleration process information, wherein the target acceleration process represents a bandwidth resource type process; All small-core CPUs are assigned to the first cpuset, and all large-core CPUs are assigned to the second cpuset; Dispatching the target acceleration process to the second cpuset; Sampling the last level cache events of the target acceleration process at a fixed period to obtain sampling data; Acquire the number of cache references and the number of cache misses of the target acceleration process according to the sampled data; Calculating a first ratio of the number of cache references to the number of cache misses; LLCs of different sizes are allocated to the first cpuset according to the first ratio, and the second cpuset uses the complete LLC, so that the target acceleration process is executed faster.

[0006] In some optional embodiments, obtaining target acceleration process information includes: Get the target acceleration process information sent by the APP; or The target acceleration process information is obtained through a target acceleration process identification program.

[0007] In some optional embodiments, the obtaining the target acceleration process information through a target acceleration process identification program includes: Obtaining a preset first threshold, a second threshold, a third threshold, and a fourth threshold; Acquire a nice value, a second ratio of the number of L1 data cache loads and the number of data cache loads, the number of L1 data cache loads, and the IPC when the process to be identified is running within the fixed period; When the nice value is less than the first threshold, the second ratio is greater than the second threshold, the L1 data cache load times is greater than the third threshold, and the IPC is less than the fourth threshold, the process to be identified is configured as a target acceleration process, and the target acceleration process information is generated.

[0008] In some optional embodiments, the target acceleration process is accelerated by a process boost program, and the running process of the process boost program includes: Receiving the target acceleration process information; Get the default LLC configuration; Initialize a partition size configuration variable, wherein the partition size configuration variable represents a variable for adjusting the size of the LLC partition; All small-core CPUs are assigned to the first cpuset, and all large-core CPUs are assigned to the second cpuset; Dispatching the target acceleration process to the second cpuset; Sampling the last level cache events of the target acceleration process within a fixed period to obtain sampling data; Acquire the number of cache references and the number of cache misses of the target acceleration process according to the sampled data; Calculating a first ratio of the number of cache references to the number of cache misses; Setting a first partition size configuration variable according to the first ratio; Allocating LLCs of different sizes to the first cpuset according to the first partition size configuration variable, and the second cpuset using a complete LLC, so that the target acceleration process is executed faster; When the target acceleration process is finished, the allocated LLC is restored to the default LLC configuration.

[0009] In some optional embodiments, the method further includes: Acquire PMU information of the process to be identified within the fixed period; Compare the nice value in the PMU information with the first threshold to obtain a first comparison result, and if the first comparison result indicates that the nice value is greater than or equal to the first threshold, obtain the PMU information within a next fixed period; When the first comparison result indicates that the nice value is less than the first threshold, compare a second ratio of the number of L1 data cache loads and the number of data cache loads in the PMU information with the second threshold to obtain a second comparison result, and when the second comparison result indicates that the second ratio is less than or equal to the second threshold, obtain the PMU information within a next fixed period; When the second comparison result indicates that the second ratio is greater than the second threshold, compare the number of L1 data cache loads in the PMU information with the third threshold to obtain a third comparison result, and when the third comparison result indicates that the number of L1 data cache loads is less than or equal to the third threshold, obtain the PMU information within a next fixed period; When the third comparison result indicates that the number of L1 data cache loads is greater than the third threshold, compare the IPC in the PMU information with the fourth threshold to obtain a fourth comparison result, and when the fourth comparison result indicates that the IPC is greater than or equal to the fourth threshold, obtain the PMU information within the next fixed period; When the fourth comparison result indicates that the IPC is less than the fourth threshold, the process to be identified is configured as a target acceleration process.

[0010] In some optional embodiments, allocating LLCs of different sizes to the first cpuset according to the first ratio includes: When the first ratio is less than or equal to 2, one eighth of the LLC is allocated to the first cpuset; When the first ratio is greater than 2 and less than or equal to 4, allocating one quarter of the LLC to the first cpuset; When the first ratio is greater than 4 and less than or equal to 8, half of the LLC is allocated to the first cpuset.

[0011] In some optional embodiments, after scheduling the target acceleration process to the second cpuset, the method further includes: Get confirmation information; In the case where the confirmation information indicates that the allocation of the LLC has started, sampling the last level cache events of the target acceleration process within a fixed period to obtain sampling data; When the confirmation information indicates that the allocation of the LLC is not started, comparing the size of the LLC partition of the first cpuset with the size of the entire LLC to obtain a fifth comparison result; When the fifth comparison result indicates that the LLC partition of the first cpuset is equal to the size of the entire LLC, terminating the process boost program; When the fifth comparison result indicates that the LLC partition of the first cpuset is not equal to the size of the entire LLC, the process boost program is terminated after the LLC is restored to the default LLC configuration.

[0012] In a second aspect, an embodiment of the present invention provides a cache allocation system, including: The first module is used to obtain target acceleration process information; A second module is used to determine a target acceleration process according to the target acceleration process information, wherein the target acceleration process represents a bandwidth resource type process; The third module is used to divide all small-core CPUs into the first cpuset and all large-core CPUs into the second cpuset; A fourth module is used to schedule the target acceleration process to the second cpuset; A fifth module is used to sample the last level cache events of the target acceleration process at a fixed period to obtain sampled data; A sixth module is used to obtain the number of cache references and the number of cache misses of the target acceleration process according to the sampled data; A seventh module, configured to calculate a first ratio of the number of cache references to the number of cache misses; An eighth module is used to allocate LLCs of different sizes to the first cpuset according to the first ratio, and the second cpuset uses a complete LLC so that the target acceleration process is executed faster.

[0013] In a third aspect, an embodiment of the present invention provides a computer device, comprising a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein the steps of the above method are implemented when the computer program is executed by the processor.

[0014] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, in which a program executable by a processor is stored. When the program executable by the processor is executed by the processor, it is used to perform the method as described above.

[0015] The implementation of the embodiment of the present invention includes the following beneficial effects: The embodiment of the present invention provides a cache allocation method, including: obtaining target acceleration process information; determining the target acceleration process according to the target acceleration process information, the target acceleration process characterizing the bandwidth resource type process; dividing all small core CPUs into a first cpuset, and dividing all large core CPUs into a second cpuset; scheduling the target acceleration process to the second cpuset; sampling the last level cache event of the target acceleration process at a fixed period to obtain sampling data; obtaining the number of cache references and the number of cache misses of the target acceleration process according to the sampling data; calculating the first ratio of the number of cache references to the number of cache misses; allocating LLCs of different sizes to the first cpuset according to the first ratio, and the second cpuset using the complete LLC, so that the target acceleration process is accelerated. By allocating the entire LLC to the target acceleration process, and other processes determining the corresponding LLC partition according to the first ratio of the number of cache references to the number of cache misses when the target acceleration process is running, it is ensured that the target acceleration process will not be preempted by other processes to use the LLC, and the target acceleration process is accelerated, thereby reducing the cache miss value and runtime delay of the target acceleration process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flowchart of the steps of a cache allocation method provided by an embodiment of the present invention; Figure 2 is a flow chart of cache allocation provided by an embodiment of the present invention; Figure 3 is another cache allocation flowchart provided by an embodiment of the present invention; Figure 4 It is a flow chart of identifying a target acceleration process of a process boost program provided by an embodiment of the present invention; Figure 5 is an operation flow chart of a process boost program provided by an embodiment of the present invention; Figure 6 It is a schematic block diagram of the structure of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0018] In the description of the present invention, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0019] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0020] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0021] The embodiment of the present invention provides a cache allocation method, system, device and medium, wherein a cache allocation method includes: obtaining target acceleration process information; determining the target acceleration process according to the target acceleration process information, wherein the target acceleration process represents a bandwidth resource type process; dividing all small-core CPUs into a first cpuset, and dividing all large-core CPUs into a second cpuset; scheduling the target acceleration process to the second cpuset; sampling the last-level cache event of the target acceleration process at a fixed period to obtain sampling data; obtaining the number of cache references and the number of cache misses of the target acceleration process according to the sampling data; calculating the first ratio of the number of cache references to the number of cache misses; allocating LLCs of different sizes to the first cpuset according to the first ratio, and using the complete LLC for the second cpuset, so that the target acceleration process is accelerated. By allocating the entire LLC to the target acceleration process, and other processes determining the corresponding LLC partition according to the first ratio of the number of cache references to the number of cache misses when the target acceleration process is running, it is ensured that the target acceleration process will not be preempted by other processes to use the LLC, and the target acceleration process is accelerated, thereby reducing the cache miss value and runtime delay of the target acceleration process.

[0022] The allocation method of the embodiment of the present invention is further described below.

[0023] Reference Figure 1 , Figure 1A flowchart of a cache allocation method provided in an embodiment of the present invention, the cache allocation method includes but is not limited to the following steps: S101, obtaining target acceleration process information; S102, determining a target acceleration process according to the target acceleration process information, where the target acceleration process represents a bandwidth resource-based process; S103, all small-core CPUs are divided into a first cpuset, and all large-core CPUs are divided into a second cpuset; S104, dispatching the target acceleration process to the second cpuset; S105, sampling the last level cache events of the target acceleration process at a fixed period to obtain sampling data; S106, obtaining the number of cache references and the number of cache misses of the target acceleration process according to the sampled data; S107, calculating a first ratio of the number of cache references to the number of cache misses; S108, allocating LLCs of different sizes to the first cpuset according to the first ratio, and the second cpuset using the complete LLC, so that the target acceleration process is executed faster.

[0024] It should be noted that cpuset is a kernel feature used to limit the CPU and memory nodes that can be used by one or more processes. It allows system administrators or users to bind processes to specific CPUs and memory, thereby improving system stability and performance. LLC (Last Level Cache) is not shared by all processes. During the operation of some important bandwidth resource-based processes (for example, user foreground real-time processes), cache is reasonably allocated to prevent other processes from competing with bandwidth resource-based processes for cache. The fixed period is the collection period of various performance information. The last level cache event is a performance monitoring event related to the last level cache (LLC) of the CPU. The cache-reference count is the number of times the CPU accesses the cache during the target acceleration process. The cache-miss count is the number of times the CPU fails to find the required cache data in the cache during the target acceleration process. The Nice value (process parameter) is an integer, usually ranging from -20 to 19. The lower the value, the higher the priority of the process and the more opportunities it has to get CPU time. The higher the value, the lower the priority of the process and the fewer opportunities it has to get CPU time.

[0025] In some optional embodiments, referring to Figure 2-3 , obtain the target acceleration process information, including: obtaining the target acceleration process information issued by the APP; or obtaining the target acceleration process information through the target acceleration process identification program.

[0026] Specifically, there are two sources of target acceleration process information: that is, it is sent through APP or identified through the target process identification program. The APP can be sent through the terminal APP. Through the preset target acceleration process list, when running the process in the target acceleration process list, the process is automatically marked as the target acceleration process and sent to the running system, and the target acceleration process is accelerated by the running system; it can also be displayed on the terminal APP. The running process information is determined by the selection information of the display end, that is, the user clicks on the display interface to select whether the running process is the target acceleration process, or the displayed process information is compared with the preset running parameters, so as to comprehensively determine the difference between the running parameters and the preset running parameters, and then determine whether the process is a target acceleration process according to the difference. When there are multiple target acceleration processes at the same time, the priority between the multiple target acceleration processes is judged, so that the multiple target acceleration processes are executed in sequence according to the priority, so as to ensure that the target acceleration process with a high priority is given priority. When the LLC used by the priority target acceleration process is still surplus, the corresponding LLC partition is allocated to other target acceleration processes with a priority behind it according to the surplus situation, so as to improve the utilization rate of LLC.

[0027] After obtaining the target acceleration process information of the target acceleration process, it is sent to the process boost program (process acceleration program). After the process boost program receives the information of the target process, it accelerates the process.

[0028] The CPU's PMU (Performance Monitor Unit) is used to monitor cache-references (the number of times the CPU accesses the cache) and cache-misses (the number of times the CPU does not find the required cache data in the cache). Linux uses the perf_event subsystem to collect last level cache events through PMU. perf_event is a subsystem in the Linux kernel that provides a performance monitoring framework that allows users and developers to collect detailed information about system and application performance. This subsystem is based on hardware-level performance monitoring units (PMUs) and software counters, and can monitor various hardware events such as CPU clock cycles, instruction execution times, cache misses, and so on.

[0029] In some optional embodiments, target acceleration process information is obtained through a target acceleration process identification program, including: obtaining a preset first threshold, a second threshold, a third threshold and a fourth threshold; obtaining a nice value, a second ratio of the number of L1 data cache loads and the number of data cache loads, the number of L1 data cache loads and the IPC when running the process to be identified within a fixed period; when the nice value is less than the first threshold, the second ratio is greater than the second threshold, the number of L1 data cache loads is greater than the third threshold and the IPC is less than the fourth threshold, the process to be identified is configured as a target acceleration process, and target acceleration process information is generated.

[0030] Specifically, refer to Figure 4 , set the highest nice threshold of the target acceleration process to A, which is the first threshold; set the lowest threshold of the L1-dcache_loads / LLC-loads ratio to B, which is the second threshold. L1-dcache_loads indicates the number of loads of the first-level data cache (i.e., L1) during the operation of the target acceleration process, and LLC-loads indicates the number of loads of the last-level data cache during the operation of the target acceleration process; set the lowest L1-dcache_loads threshold to C, which is the third threshold; set the highest threshold of insns per cycle (IPC, the number of instructions executed in each CPU clock cycle) to D, which is the fourth threshold; when the process to be identified meets the conditions of the target acceleration process, it is nice <a 且 l1-dcache_loads llc-loads>If B and L1 - dcache_loads > C and insns per cycle < D, it is determined that the process to be recognized is the target accelerated process.

[0031] In some alternative embodiments, the target accelerated process is accelerated through a process boost program. The running process of the process boost program includes: receiving target accelerated process information; obtaining the default LLC configuration; initializing the partition size configuration variable, where the partition size configuration variable represents a variable for adjusting the LLC partition size; dividing all small - core CPUs into the first cpuset and all large - core CPUs into the second cpuset; scheduling the target accelerated process to the second cpuset; sampling last - level cache events of the target accelerated process within a fixed period to obtain sampling data; obtaining the cache reference count and cache miss count of the target accelerated process according to the sampling data; calculating the first ratio of the cache reference count to the cache miss count; setting the first partition size configuration variable according to the first ratio; allocating different - sized LLCs to the first cpuset according to the first partition size configuration variable, and the second cpuset uses the complete LLC, so that the target accelerated process is accelerated for execution; when the target accelerated process ends, restoring the allocated LLC to the default LLC configuration.

[0032] Specifically, referring to Figure 2-5 , the process boost program in the system executes the acceleration of the target acceleration process. After the process boost program is executed, the target acceleration process information of the target acceleration process to be accelerated is obtained first, and the default LLC configuration preset by the system is obtained. The default LLC configuration is the default LLC partition. At the same time, the partition size configuration variable is initialized. The LLC partition size can be adjusted through the partition size configuration variable, that is, the LLC partition used by different processes can be adjusted. All small-core CPUs in the system are divided into the first cpuset (that is, Figure 5 cpuset0 in the cpuset, so that the small-core CPU can handle other less important processes; all large-core CPUs are divided into the second cpuset (that is, Figure 5cpuset1 in ), schedule the target acceleration process to the second cpuset, so that the large-core CPU is used to process the target acceleration process, so that the target acceleration process can be quickly executed. The last-level cache event sampling of the target acceleration process is performed within a fixed period (CPU clock cycle) to obtain sampling data, and the number of cache references and cache misses of the target acceleration process are obtained from the sampling data. The number of cache references is the number of times the CPU accesses the cache during the operation of the target acceleration process; the number of cache misses is the number of times the CPU does not find the required cache data in the cache. Then, the first ratio of the number of cache references to the number of cache misses is calculated, and the first partition size configuration variable is set according to the first ratio. Different first partition size configuration variables are set for different first ratios, so that LLC can be allocated to partitions of different sizes to the first cpuset according to the first partition size configuration variable, so that other processes use the first cpuset; and the second cpuset of the target acceleration process uses the complete LLC, so that the target acceleration process is accelerated. After the target acceleration process is completed, the allocated LLC is restored to the default LLC configuration, that is, the LLC partition is restored to the default configuration for subsequent cache allocation.

[0033] In some optional embodiments, PMU information of a process to be identified is obtained within a fixed period; a nice value in the PMU information is compared with a first threshold to obtain a first comparison result; if the first comparison result indicates that the nice value is greater than or equal to the first threshold, the PMU information within the next fixed period is obtained; if the first comparison result indicates that the nice value is less than the first threshold, a second ratio of the number of L1 data cache loads and the number of data cache loads in the PMU information is compared with a second threshold to obtain a second comparison result; if the second comparison result indicates that the second ratio is less than or equal to the second threshold, the PMU information within the next fixed period is obtained; if the second comparison result indicates that the second ratio is less than or equal to the second threshold, the PMU information within the next fixed period is obtained; When the ratio is greater than the second threshold, the number of L1 data cache loads in the PMU information is compared with the third threshold to obtain a third comparison result. When the third comparison result indicates that the number of L1 data cache loads is less than or equal to the third threshold, the PMU information within the next fixed period is obtained; when the third comparison result indicates that the number of L1 data cache loads is greater than the third threshold, the IPC in the PMU information is compared with the fourth threshold to obtain a fourth comparison result. When the fourth comparison result indicates that the IPC is greater than or equal to the fourth threshold, the PMU information within the next fixed period is obtained; when the fourth comparison result indicates that the IPC is less than the fourth threshold, the process to be identified is configured as a target acceleration process.

[0034] Specifically, refer to Figure 4, obtain the PMU information of the process to be identified within a fixed period P (CPU clock period), and the PMU information is obtained through the PMU unit. Compare the nice value in the PMU information with the first threshold A to obtain a first comparison result. When the first comparison result indicates that the nice value is greater than or equal to the first threshold A, obtain the PMU information within the next fixed period, that is, obtain the PMU information of the next fixed period, so as to periodically obtain the PMU information and periodically allocate cache. When the first comparison result indicates that the nice value is less than the first threshold value A, the second ratio of the number of L1 data cache loads and the number of data cache loads in the PMU information is continued to be compared with the second threshold value B to obtain a second comparison result. When the second comparison result indicates that the second ratio is less than or equal to the second threshold value B, the PMU information within the next fixed period is obtained; similarly, when the second comparison result indicates that the second ratio is greater than the second threshold value B, the number of L1 data cache loads in the PMU information is continued to be compared with the third threshold value C to obtain a third comparison result. When the third comparison result indicates that the number of L1 data cache loads is less than or equal to the third threshold value C, the PMU information within the next fixed period is obtained; when the third comparison result indicates that the number of L1 data cache loads is greater than the third threshold value C, the IPC in the PMU information is continued to be compared with the fourth threshold value to obtain a fourth comparison result. When the fourth comparison result indicates that the IPC (the number of instructions executed in each CPU clock cycle) is greater than or equal to the fourth threshold value D, the PMU information within the next fixed period is obtained; when the fourth comparison result indicates that the IPC is less than the fourth threshold value D, the process to be identified is configured as a target acceleration process, and the target acceleration process is accelerated through the process boost program.

[0035] In some optional embodiments, LLCs of different sizes are allocated to the first cpuset according to the first ratio, including: when the first ratio is less than or equal to 2, one-eighth of the LLC is allocated to the first cpuset; when the first ratio is greater than 2 and less than or equal to 4, one-quarter of the LLC is allocated to the first cpuset; when the first ratio is greater than 4 and less than or equal to 8, one-half of the LLC is allocated to the first cpuset.

[0036] Specifically, refer to Figure 5, full last level cache indicates the total size of the last level cache, cache_partition is the cache size to be allocated, and cache_partition is allocated to the first cpuset (i.e., cpuset0) for use by other processes. When the first ratio is less than or equal to 2, one eighth of the LLC is allocated to the first cpuset, that is, one eighth of the full last level cache is allocated to the first cpuset, and the full lastlevel cache is allocated to the second cpuset; similarly, when the first ratio is greater than 2 and less than or equal to 4, one quarter of the LLC is allocated to the first cpuset, and the full last level cache is allocated to the second cpuset; when the first ratio is greater than 4 and less than or equal to 8, one half of the LLC is allocated to the first cpuset, and the full lastlevel cache is allocated to the second cpuset. Thus, the LLC size that needs to be allocated to other processes is determined according to the performance parameters of the target acceleration process to ensure the operation of the target acceleration process.

[0037] In some optional embodiments, after scheduling the target acceleration process to the second cpuset, the method also includes: obtaining confirmation information; when the confirmation information indicates that LLC allocation is started, sampling the last level cache events of the target acceleration process within a fixed period to obtain sampling data; when the confirmation information indicates that LLC allocation is not started, comparing the size of the LLC partition of the first cpuset with the size of the entire LLC to obtain a fifth comparison result; when the fifth comparison result indicates that the LLC partition of the first cpuset is equal to the size of the entire LLC, terminating the process boost program; when the fifth comparison result indicates that the LLC partition of the first cpuset is not equal to the size of the entire LLC, restoring the LLC to the default LLC configuration and then terminating the process boost program.

[0038] Specifically, refer to Figure 5After the process boost program starts to allocate LLC, it samples the last level cache events of the target acceleration process within a fixed period to obtain sampling data, so as to allocate the subsequent LLC; when the process boost program does not start to allocate LLC, it compares the size of the LLC partition of the first cpuset and the entire LLC. When the LLC partition of the first cpuset is equal to the size of the entire LLC (that is, cache_partition is equal to the full last level cache), the process boost program is terminated, that is, other processes use the full LLC, other processes are target acceleration processes, and the current target acceleration process needs to be executed later. When the LLC partition of the first cpuset is not equal to the size of the entire LLC, the LLC is restored to the default LLC configuration and the process boost program is terminated, waiting for the subsequent LLC allocation.

[0039] The implementation of the embodiment of the present invention includes the following beneficial effects: the embodiment of the present invention provides a cache allocation method, including: obtaining target acceleration process information; determining the target acceleration process according to the target acceleration process information, the target acceleration process characterizing the bandwidth resource type process; dividing all small core CPUs into the first cpuset, dividing all large core CPUs into the second cpuset; scheduling the target acceleration process to the second cpuset; sampling the last level cache event of the target acceleration process in a fixed period to obtain sampling data; obtaining the number of cache references and the number of cache misses of the target acceleration process according to the sampling data; calculating the first ratio of the number of cache references to the number of cache misses; allocating LLCs of different sizes to the first cpuset according to the first ratio, and the second cpuset using the complete LLC, so that the target acceleration process is accelerated. By allocating the entire LLC to the target acceleration process, and other processes determining the corresponding LLC partition according to the first ratio of the number of cache references to the number of cache misses when the target acceleration process is running, it is ensured that the target acceleration process will not be preempted by other processes to use the LLC, and the target acceleration process is accelerated, thereby reducing the cache miss value and runtime delay of the target acceleration process.

[0040] In a second aspect, an embodiment of the present invention provides a cache allocation system, including: The first module is used to obtain target acceleration process information; The second module is used to determine the target acceleration process according to the target acceleration process information, where the target acceleration process represents a bandwidth resource type process; The third module is used to divide all small-core CPUs into the first cpuset and all large-core CPUs into the second cpuset; The fourth module is used to schedule the target acceleration process to the second cpuset; The fifth module is used to sample the last level cache events of the target acceleration process at a fixed period to obtain sampling data; The sixth module is used to obtain the number of cache references and cache misses of the target acceleration process according to the sampled data; A seventh module is used to calculate a first ratio of the number of cache references to the number of cache misses; The eighth module is used to allocate LLCs of different sizes to the first cpuset according to the first ratio, and the second cpuset uses the complete LLC, so that the target acceleration process is executed faster.

[0041] It can be seen that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0042] like Figure 6 As shown, in the third aspect, an embodiment of the present invention further provides a computer device, which can be a terminal. The computer device includes a processor, a memory, and a network interface connected via a system bus, wherein the memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium can store an operating system and a computer program. The computer program includes program instructions, which, when executed, enable the processor to execute any one of the methods for visualizing management of industrial equipment. The processor is used to provide computing and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium, which, when executed by the processor, enables the processor to execute any one of the methods for visualizing management of industrial equipment. The network interface is used for network communications, such as sending assigned tasks, etc. Those skilled in the art will appreciate that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present disclosure, and does not constitute a limitation on the computer device to which the solution of the present disclosure is applied. The specific computer device may include Figure 6More or less components shown in, or some components are combined, or there are different component arrangements. It should be understood that the processor can be a central processing unit (CPU), and the processor can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. In one embodiment, the processor is used to run a computer program stored in a memory to implement the following steps: obtaining target acceleration process information; determining the target acceleration process according to the target acceleration process information, wherein the target acceleration process represents a bandwidth resource-type process; dividing all small-core CPUs into a first cpuset, and dividing all large-core CPUs into a second cpuset; scheduling the target acceleration process to the second cpuset; sampling the last-level cache events of the target acceleration process at a fixed period to obtain sampling data; obtaining the number of cache references and the number of cache misses of the target acceleration process according to the sampling data; calculating a first ratio of the number of cache references to the number of cache misses; allocating LLCs of different sizes to the first cpuset according to the first ratio, and using a complete LLC for the second cpuset, so that the target acceleration process is accelerated.

[0043] It can be seen that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0044] In addition, the embodiment of the present application also discloses a computer program product or a computer program, and the computer program product or the computer program is stored in a computer-readable storage medium. The processor of the computer device can read the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device performs the above method. Similarly, the contents in the above method embodiment are all applicable to the storage medium embodiment, and the functions specifically implemented by the storage medium embodiment are the same as those in the above method embodiment, and the beneficial effects achieved are also the same as those achieved by the above method embodiment.

[0045] It is understood that all or some steps and systems in the disclosed method above can be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital information processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, and the computer-readable medium can include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassette, magnetic tape, disk storage or other magnetic storage device, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media generally contain computer readable instructions, data structures, program modules, or other data in modulated data information such as carrier waves or other transport mechanisms, and may include any information delivery media.

[0046] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the technical field without departing from the purpose of the present invention.

Claims

1. A cache allocation method, characterized in that: include: Get target acceleration process information; Determine a target acceleration process according to the target acceleration process information, wherein the target acceleration process represents a bandwidth resource type process; All small-core CPUs are assigned to the first cpuset, and all large-core CPUs are assigned to the second cpuset; Dispatching the target acceleration process to the second cpuset; Sampling the last level cache events of the target acceleration process at a fixed period to obtain sampling data; Acquire the number of cache references and the number of cache misses of the target acceleration process according to the sampled data; Calculating a first ratio of the number of cache references to the number of cache misses; LLCs of different sizes are allocated to the first cpuset according to the first ratio, and the second cpuset uses the complete LLC, so that the target acceleration process is executed faster.

2. The method according to claim 1, characterized in that The obtaining of target acceleration process information includes: Get the target acceleration process information sent by the APP; or The target acceleration process information is obtained through a target acceleration process identification program.

3. The method according to claim 2, characterized in that The step of obtaining the target acceleration process information through a target acceleration process identification program includes: Obtaining a preset first threshold, a second threshold, a third threshold, and a fourth threshold; Acquire a nice value, a second ratio of the number of L1 data cache loads and the number of data cache loads, the number of L1 data cache loads, and the IPC when the process to be identified is running within the fixed period; When the nice value is less than the first threshold, the second ratio is greater than the second threshold, the L1 data cache load times is greater than the third threshold, and the IPC is less than the fourth threshold, the process to be identified is configured as a target acceleration process, and the target acceleration process information is generated.

4. The method according to claim 1, characterized in that: The target acceleration process is accelerated by a process boost program, and the operation flow of the process boost program includes: Receiving the target acceleration process information; Get the default LLC configuration; Initialize a partition size configuration variable, wherein the partition size configuration variable represents a variable for adjusting the size of the LLC partition; All small-core CPUs are assigned to the first cpuset, and all large-core CPUs are assigned to the second cpuset; Dispatching the target acceleration process to the second cpuset; Sampling the last level cache events of the target acceleration process within a fixed period to obtain sampling data; Acquire the number of cache references and the number of cache misses of the target acceleration process according to the sampled data; Calculating a first ratio of the number of cache references to the number of cache misses; Setting a first partition size configuration variable according to the first ratio; Allocating LLCs of different sizes to the first cpuset according to the first partition size configuration variable, and the second cpuset using a complete LLC, so that the target acceleration process is executed faster; When the target acceleration process is finished, the allocated LLC is restored to the default LLC configuration.

5. The method according to claim 3, characterized in that: The method further comprises: Acquire PMU information of the process to be identified within the fixed period; Compare the nice value in the PMU information with the first threshold to obtain a first comparison result, and if the first comparison result indicates that the nice value is greater than or equal to the first threshold, obtain the PMU information within a next fixed period; When the first comparison result indicates that the nice value is less than the first threshold, compare a second ratio of the number of L1 data cache loads and the number of data cache loads in the PMU information with the second threshold to obtain a second comparison result, and when the second comparison result indicates that the second ratio is less than or equal to the second threshold, obtain the PMU information within a next fixed period; When the second comparison result indicates that the second ratio is greater than the second threshold, compare the number of L1 data cache loads in the PMU information with the third threshold to obtain a third comparison result, and when the third comparison result indicates that the number of L1 data cache loads is less than or equal to the third threshold, obtain the PMU information within a next fixed period; When the third comparison result indicates that the number of L1 data cache loads is greater than the third threshold, compare the IPC in the PMU information with the fourth threshold to obtain a fourth comparison result, and when the fourth comparison result indicates that the IPC is greater than or equal to the fourth threshold, obtain the PMU information within the next fixed period; When the fourth comparison result indicates that the IPC is less than the fourth threshold, the process to be identified is configured as a target acceleration process.

6. The method according to claim 1, characterized in that The allocating LLCs of different sizes to the first cpuset according to the first ratio includes: When the first ratio is less than or equal to 2, one eighth of the LLC is allocated to the first cpuset; When the first ratio is greater than 2 and less than or equal to 4, allocating one quarter of the LLC to the first cpuset; When the first ratio is greater than 4 and less than or equal to 8, half of the LLC is allocated to the first cpuset.

7. The method according to claim 4, characterized in that After scheduling the target acceleration process to the second cpuset, the method further includes: Get confirmation information; In the case where the confirmation information indicates that the allocation of the LLC has started, sampling the last level cache events of the target acceleration process within a fixed period to obtain sampling data; When the confirmation information indicates that the allocation of the LLC is not started, comparing the size of the LLC partition of the first cpuset with the size of the entire LLC to obtain a fifth comparison result; When the fifth comparison result indicates that the LLC partition of the first cpuset is equal to the size of the entire LLC, terminating the process boost program; When the fifth comparison result indicates that the LLC partition of the first cpuset is not equal to the size of the entire LLC, the process boost program is terminated after the LLC is restored to the default LLC configuration.

8. A cache allocation system, characterized in that: include: The first module is used to obtain target acceleration process information; A second module is used to determine a target acceleration process according to the target acceleration process information, wherein the target acceleration process represents a bandwidth resource type process; The third module is used to divide all small-core CPUs into the first cpuset and all large-core CPUs into the second cpuset; A fourth module is used to schedule the target acceleration process to the second cpuset; A fifth module is used to sample the last level cache events of the target acceleration process at a fixed period to obtain sampled data; A sixth module is used to obtain the number of cache references and the number of cache misses of the target acceleration process according to the sampled data; A seventh module, configured to calculate a first ratio of the number of cache references to the number of cache misses; An eighth module is used to allocate LLCs of different sizes to the first cpuset according to the first ratio, and the second cpuset uses a complete LLC so that the target acceleration process is executed faster.

9. A computer device, wherein: The computer device comprises a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a program executable by a processor, characterized in that: The processor-executable program is used to perform the method according to any one of claims 1 to 7 when executed by the processor.

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