Display driving circuit and display device including the same

Abstract

The invention discloses a display driving circuit and a display device including the same. The display driving circuit includes a control logic, a source amplifier, a first switching element, and a second switching element. The source amplifier includes a first input terminal, a second input terminal, and an output terminal, and amplifies a pixel voltage for displaying an image on the display panel, and supplies the amplified pixel voltage to the pixels through the data lines. A first switching element is connected between the first input terminal and the output terminal, and a second switching element is connected between the first input terminal and the sense line. The control logic controls the first switching element and the second switching element such that the source amplifier compares a sampled voltage input to the first input terminal through the sense line with a comparison voltage input to the second input terminal, and outputs comparison data based on the comparison.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0083771 filed on June 28, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Embodiments consistent with the present disclosure relate to semiconductor devices, and more particularly, to display driver circuits and display devices. More particularly, embodiments consistent with the present disclosure relate to display driver circuits and display devices for determining whether an error has occurred in a pixel by using a source amplifier. Background Art

[0003] Recently, the use of organic light emitting diode (OLED) display panels has increased, in which each of a plurality of pixels of a pixel array includes an OLED. As the resolution of a display device increases, the number of pixels of the display device increases, and each pixel may include a plurality of elements. In order for the display device to display an image normally, a test operation for identifying whether an error has occurred in a pixel is required. Performing a test operation on a large number of pixels may take a lot of time and cost.

[0004] Therefore, techniques are needed for reducing the time and cost spent performing testing operations. Summary of the invention

[0005] On the one hand, a display driving circuit and a display device are provided, in which a source amplifier for amplifying a pixel voltage to display an image on a display panel operates as a comparator to compare a sampled voltage with a comparison voltage, thereby reducing the cost and time spent on identifying whether an error has occurred in a pixel.

[0006] According to an aspect of one or more embodiments, a display driving circuit for driving a display panel is provided, wherein the display panel includes a data line, a sensing line, and pixels connected to the data line and the sensing line, and the display driving circuit includes: a control logic for controlling the operation of the display driving circuit; a source amplifier including a first input terminal, a second input terminal, and an output terminal, the source amplifier amplifying a pixel voltage for displaying an image on the display panel, and providing the amplified pixel voltage to the pixel through the data line; a first switching element connected between the first input terminal and the output terminal; and a second switching element connected between the first input terminal and the sensing line, wherein the control logic controls the first switching element and the second switching element so that the source amplifier compares a sampling voltage input to the first input terminal through the sensing line with a comparison voltage input to the second input terminal, and outputs comparison data based on the comparison.

[0007] According to another aspect of one or more embodiments, a display driving circuit for driving a display panel is provided, wherein the display panel includes a plurality of data lines, a plurality of sensing lines, and a plurality of pixels connected to the plurality of data lines and the plurality of sensing lines, and the display driving circuit includes: a plurality of decoders corresponding to the plurality of data lines, each decoder converts the pixel data of the corresponding data line and outputs a pixel voltage; a plurality of source amplifiers corresponding to the plurality of decoders, each source amplifier including a first input terminal, a second input terminal, and an output terminal, and each source amplifier amplifies the corresponding pixel voltage and provides the amplified pixel voltage to the corresponding pixel through the corresponding data line; a plurality of first switching elements corresponding to the plurality of source amplifiers, each first switching element is connected between the first input terminal and the output terminal of the corresponding source amplifier; and a plurality of second switching elements corresponding to the plurality of source amplifiers, each second switching element is connected between the first input terminal of the corresponding source amplifier and the corresponding sensing line. Each of the multiple source amplifiers amplifies the corresponding pixel voltage to be output to the corresponding data line in the first operating mode, and compares the sampling voltage input to the first input terminal through the corresponding sensing line with the comparison voltage input to the second input terminal based on the operation of the first switching element and the second switching element in the second operating mode, and outputs comparison data.

[0008] According to another aspect of one or more embodiments, a display device is provided, the display device comprising: a display panel including a data line, a sensing line, and pixels connected to the data line and the sensing line; and a display driving circuit driving the display panel so that an image is displayed on the display panel. The display driving circuit comprises: a source amplifier including a first input terminal, a second input terminal, and an output terminal, the source amplifier amplifies a pixel voltage for displaying an image on the display panel, and provides the amplified pixel voltage to the pixel through the data line; a first switching element connected between the first input terminal and the output terminal of the source amplifier; and a second switching element connected between the first input terminal of the source amplifier and the sensing line. The source amplifier compares the sampling voltage input to the first input terminal of the source amplifier through the sensing line with the comparison voltage input to the second input terminal of the source amplifier based on the operation of the first switching element and the second switching element, and outputs the comparison data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various embodiments will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram showing a display device according to an embodiment;

[0011] Figure 2is a diagram for describing a display driving circuit according to an embodiment;

[0012] Figure 3 is a circuit diagram showing an example of a pixel according to the embodiment;

[0013] Figure 4 is a circuit diagram showing an example of a pixel according to the embodiment;

[0014] Figure 5 is a circuit diagram showing an example of a pixel according to the embodiment;

[0015] Fig. 6A is a diagram for describing a reset period according to an embodiment;

[0016] Figure 6B is a diagram for describing a programming period according to an embodiment;

[0017] Figure 6C is a diagram for describing a comparison period according to an embodiment;

[0018] Figure 7 is a timing diagram showing a plurality of signals for controlling a pixel and a display driving circuit according to an embodiment;

[0019] Fig. 8A is a diagram for describing a reset period according to an embodiment;

[0020] Figure 8B is a diagram for describing a programming period according to an embodiment;

[0021] Figure 8C is a diagram for describing a comparison period according to an embodiment;

[0022] Fig. 9 is a timing diagram showing a plurality of signals for controlling a pixel and a display driving circuit according to an embodiment;

[0023] Fig. 10A is a diagram for describing an offset correction period according to an embodiment;

[0024] Fig. 10B is a diagram for describing a comparison period after an offset correction period according to an embodiment;

[0025] Fig.11 is a timing diagram showing a plurality of signals for controlling a pixel and a display driving circuit according to an embodiment;

[0026] Fig. 12A is a diagram for describing a light emitting reset period according to an embodiment;

[0027] Fig. 12Bis a diagram for describing a light emitting programming period according to an embodiment;

[0028] Fig. 12C is a diagram for describing a light emission comparison period according to an embodiment;

[0029] Fig.13 is a timing diagram showing a plurality of signals for controlling a pixel and a display driving circuit according to an embodiment;

[0030] Fig.14 is a diagram for describing a method by which a display driving circuit determines whether an error has occurred in a pixel according to an embodiment;

[0031] Fig.15A is a diagram for describing a method by which a display driving circuit determines that an error has occurred in a pixel according to an embodiment;

[0032] Fig. 15B is a diagram for describing a method by which a display driving circuit determines that an error has occurred in a pixel according to an embodiment; and

[0033] Fig.16 is a diagram illustrating a display device according to an embodiment. DETAILED DESCRIPTION

[0034] The display device may include a display panel that displays an image and a display driving circuit that drives the display panel. The display driving circuit may drive the display panel by receiving image data from the outside and applying an image signal corresponding to the received image data to a data line of the display panel. As described above, recently, the use of organic light emitting diode (OLED) display panels has increased, in which each of a plurality of pixels of a pixel array includes an OLED.

[0035] The display device may include a plurality of pixels. The plurality of pixels may be arranged in rows and columns. The rows of the plurality of pixels may be connected to a scan driver, and the columns of the plurality of pixels may be connected to a data driver. The scan driver may control the timing of selecting each row of the plurality of pixels. The data driver may adjust the brightness of the pixels in the selected row.

[0036] As described above, as the resolution of the display device increases, the number of pixels of the display device increases, and each pixel may include multiple elements. In order for the display device to display an image normally, a test operation for identifying whether an error has occurred in the pixel is required. Performing a test operation on a large number of pixels can take a lot of time and cost.

[0037] Various embodiments provide a display driving circuit and a display device in which a source amplifier for amplifying a pixel voltage to display an image on a display panel operates as a comparator to compare a sampled voltage with a comparison voltage, thereby reducing the cost and time spent on identifying whether an error has occurred in a pixel.

[0038] Hereinafter, various embodiments will be described in detail so that those skilled in the art can easily implement the embodiments. Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. In the following description and drawings, the same reference numerals will represent the same elements, and for the sake of brevity, their redundant descriptions will be omitted.

[0039] Figure 1 is a block diagram showing a display device according to an embodiment.

[0040] Reference Figure 1 The display device 10 may include a display driving circuit 100 (also referred to as a display driving integrated circuit) and a display panel 200 .

[0041] In one embodiment, the display device 10 may be installed on an electronic device having an image display function. For example, the electronic device may include a smart phone, a tablet personal computer, a portable multimedia player (PMP), a camera, a wearable device, a television, a digital video disk (DVD) player, a refrigerator, an air conditioner, an air purifier, a set-top box, a robot, a drone, various medical devices, a navigation device, an augmented reality (AR) device, a virtual reality (VR) device, a global positioning system (GPS) receiver, an advanced driver assistance system (ADAS), a vehicle device, furniture, or various measuring devices.

[0042] In one embodiment, the electronic device may include AR glasses in the shape of glasses worn on the user's face or a head-mounted display (HMD) device, VR headset (VRH), or AR helmet worn on the user's head.

[0043] The display device 10 may display image data IDT received from a host (not shown). In one embodiment, the display device 10 may be a device in which the display driving circuit 100 and the display panel 200 are implemented as one module. For example, the display driving circuit 100 may be mounted on a substrate of the display panel 200, or the display driving circuit 100 and the display panel 200 may be electrically connected via a connecting member such as a flexible printed circuit board (FPCB).

[0044] The display panel 200 may be a display that actually displays an image, and may be a display device that receives an electrically transmitted image signal and displays a two-dimensional image (such as an organic light emitting diode (OLED) display, a thin film transistor-liquid crystal display (TFT-LCD), a field emission display, and a plasma display panel (PDP) display). Hereinafter, it is assumed that the display panel 200 is an OLED display panel in which each pixel includes an OLED. However, the embodiment is not limited thereto, and in some embodiments, the display panel 200 may be implemented as other types of flat panel displays or flexible display panels. In one embodiment, the display device 10 may include an OLED on silicon (OLEDoS).

[0045] The display driving circuit 100 may receive image data IDT from the host. The display driving circuit 100 may convert the image data IDT into a plurality of analog signals (e.g., a plurality of data voltages) for driving the display panel 200. The display driving circuit 100 may supply the plurality of analog signals to the display panel 200. Therefore, an image corresponding to the image data IDT may be displayed on the display panel 200.

[0046] The display driving circuit 100 may include a control logic 110, a data driver 120 (also referred to as a source driver), and a scan driver 130 (also referred to as a gate driver). The display driving circuit 100 may also include other components (such as an interface circuit, a memory, a voltage generator, a clock generator, etc.).

[0047] In one embodiment, the control logic 110, the data driver 120, and the scan driver 130 may be integrated into one semiconductor chip. However, the embodiment is not limited thereto, and in some embodiments, the control logic 110 and the data driver 120 may be formed in one semiconductor chip, and the scan driver 130 may be formed in the display panel 200.

[0048] The control logic 110 may control the overall operation of the display driving circuit 100. For example, the control logic 110 may control components of the display driving circuit 100 such as the data driver 120 and the scan driver 130 so that image data IDT received from an external device or host is displayed on the display panel 200.

[0049] The control logic 110 may perform image processing for brightness change, size change, format change, etc. on the received image data IDT, or may generate new image data to be displayed on the display panel 200 based on the received image data IDT, and transmit the pixel data DATA to the data driver 120. In this case, the control logic 110 may include an image processor (IP) for image processing.

[0050] The control logic 110 may provide a data driver control signal to the data driver 120. The control logic 110 may control the data driver 120 through the data driver control signal. The data driver control signal may be a first control signal CTRL1 for controlling the data driver 120. The control logic 110 may output the first control signal CTRL1 to the data driver 120.

[0051] The control logic 110 may provide a scan driver control signal to the scan driver 130. The control logic 110 may control the scan driver 130 through the scan driver control signal. Alternatively, the control logic 110 may control the operation timing of the scan driver 130 through the timing signal. The scan driver control signal may be a second control signal CTRL2 for controlling the scan driver 130. The control logic 110 may output the second control signal CTRL2 to the scan driver 130.

[0052] The data driver 120 may be connected to a plurality of columns of pixels PX through a plurality of data lines DL1 to DLm. The data driver 120 may receive pixel data DATA from the control logic 110. The pixel data DATA may include information about the brightness (or brightness) of a row of pixels. The data driver 120 may convert the received pixel data DATA into a plurality of image signals (e.g., a plurality of data voltages). The data driver 120 may output a plurality of data voltages to the display panel 200 through a plurality of data lines DL1 to DLm.

[0053] The data driver 120 may receive the pixel data DATA in units of line data, that is, in units of data corresponding to a plurality of pixels included in one horizontal line of the display panel 200. The data driver 120 may convert the line data received from the control logic 110 into a plurality of data voltages. The data driver 120 may provide a plurality of data voltages corresponding to brightness to the display panel 200 through a plurality of data lines DL1 to DLm.

[0054] The scan driver 130 may be connected to the plurality of scan lines SL1 to SLn of the display panel 200, and may sequentially drive the plurality of scan lines SL1 to SLn of the display panel 200. The scan driver 130 may sequentially provide a plurality of scan-on signals having an effective level (e.g., a logic high level) to the plurality of scan lines SL1 to SLn under the control of the control logic 110. Thus, the plurality of scan lines SL1 to SLn may be sequentially selected, and a plurality of data voltages may be applied to the pixels PX of the horizontal lines corresponding to the selected scan lines through the data lines DL1 to DLm.

[0055] In one embodiment, the display driving circuit 100 may obtain a sampling voltage from a pixel PX of the display panel 200. For example, in a test mode, the display driving circuit 100 may read a pixel voltage provided from the display panel 200 as a sampling voltage. The display panel 200 may further include a sensing line. Specifically, the data driver 120 may be connected to each pixel PX through each of the data lines DL1 to DLm and the sensing line. The data driver 120 may provide the pixel data DATA to the display panel 200 through the data lines DL1 to DLm, and receive the sampling voltage from the display panel 200 through the sensing line.

[0056] The display driving circuit 100 may receive the sampled voltage and generate comparison data for determining whether an error has occurred in each pixel PX based on the sampled voltage. Figure 2 A method by which the display driving circuit 100 generates comparison data is described in detail.

[0057] In some embodiments, the display panel 200 may include a plurality of scan lines SL1 to SLn, a plurality of data lines DL1 to DLm arranged in a direction intersecting the plurality of scan lines SL1 to SLn, and a plurality of pixels PX arranged in a region where the scan lines and the data lines intersect each other. For example, the display panel 200 may further include a plurality of sensing lines arranged in the same direction as the plurality of data lines DL1 to DLm. Each of the plurality of pixels PX may be connected to the scan line SL, the data line DL, and the sensing line corresponding thereto.

[0058] The display panel 200 may include a plurality of horizontal lines (or rows), and one horizontal line may include pixels PX connected to one scan line. For example, pixels PX of a first row connected to a first scan line SL1 may form a first horizontal line, and pixels PX of a second row connected to a second scan line SL2 may form a second horizontal line.

[0059] The pixels PX of one horizontal line may be driven during the horizontal line time, and the pixels PX of another horizontal line may be driven during the next horizontal line time. For example, the pixels PX of the first horizontal line corresponding to the first scan line SL1 may be driven during the first horizontal line time, and then the pixels PX of the second horizontal line corresponding to the second scan line SL2 may be driven during the second horizontal line time. In this way, the pixels PX of the display panel 200 may be driven during the first horizontal line time to the nth horizontal line time.

[0060] In one embodiment, the display panel 200 may be connected to the data driver 120 through the data lines DL1 to DLm and the sensing lines. The display panel 200 may provide the sampling voltage to the data driver 120 through the sensing lines connected to each pixel PX.

[0061] Each pixel PX may adjust its brightness in response to each of the control signals corresponding thereto. For example, each pixel PX may be selected in response to a corresponding scan signal among a plurality of scan signals S1 to Sn (or s1 to sn). Each of the selected pixels PX may emit light based on corresponding pixel data among the pixel data DATA. Each pixel PX may include a light emitting element (such as an OLED) and a transistor for controlling the light emitting element.

[0062] Each of the plurality of pixels PX may output light of a preset color, and two or more pixels PX (e.g., a red pixel, a blue pixel, and a green pixel) arranged adjacent to each other on the same line or adjacent lines and outputting light of different colors may constitute a unit pixel. In this case, two or more pixels PX constituting a unit pixel may be referred to as sub-pixels. The display panel 200 may have an RGB structure in which a red pixel, a blue pixel, and a green pixel constitute a unit pixel. However, the embodiment is not limited thereto, and the display panel 200 may have an RGBW structure in which the unit pixel further includes a white pixel for brightness improvement. Alternatively, the unit pixel of the display panel 200 may include a combination of pixels of other colors other than red, green, and blue.

[0063] Figure 2 is a diagram for describing a display driving circuit according to an embodiment. Figure 1 The description given of the display device 10 may be applied to Figure 2 Therefore, for the sake of brevity, redundant descriptions regarding the description given above will be omitted.

[0064] Reference Figure 2 , the display device 10 may include a display panel 200 and a display driving circuit 100 , and the display driving circuit 100 may include a control logic 110 and a data driver 120 .

[0065] The display panel 200 may include a plurality of signal lines (eg, a plurality of data lines DL1 to DLm), a plurality of sensing lines SSL1 to SSLm, and a plurality of scan lines (eg, Figure 1 The data driver 120 may be connected to the display panel 200 through a plurality of data lines DL1 to DLm. The data driver 120 may be connected to a plurality of columns of pixels PX through a plurality of data lines DL1 to DLm. The data driver 120 may be connected to the display panel 200 through a plurality of sensing lines SSL1 to SSLm. The data driver 120 may be connected to a plurality of columns of pixels PX through a plurality of sensing lines SSL1 to SSLm. Figure 2It is shown that the number of data lines and the number of sensing lines are equal to each other. However, the embodiment is not limited thereto, and in some embodiments, the number of data lines and the number of sensing lines may be different from each other.

[0066] In one embodiment, the display driver circuit 100 can operate in multiple operation modes. The control logic 110 can control the display driver circuit 100 to operate in multiple operation modes. The control logic 110 can control the data driver 120 to operate according to multiple operation modes. The control logic 110 can provide a control signal to the data driver 120 for the data driver 120 to operate according to multiple operation modes.

[0067] For example, the plurality of operation modes may include a first operation mode and a second operation mode. The first operation mode may refer to a display mode. In the first operation mode, the data driver 120 may store pixel data (e.g., Figure 1 The pixel data DATA) is converted into a data voltage and the data voltage is output to the display panel 200 through the data line. The second operation mode may refer to a test mode. In the second operation mode, the data driver 120 may receive a sampling voltage Vs from the pixel PX through the sensing line.

[0068] For example, the control logic 110 may control the switch element so that the data driver 120 operates in one of the first operation mode and the second operation mode. The data driver 120 may include a test switch element swt and a multiplexer (MUX) switch element swm. In the first operation mode, the test switch element swt may be disconnected and the MUX switch element swm may be turned on. Because the MUX switch element swm is turned on, the output of the source amplifier may be applied to the pixel PX through the data line.

[0069] In the second operation mode, the test switch element swt may be turned on and the MUX switch element swm may be turned off. Because the test switch element swt is turned on, the test voltage Vtest may be applied to the pixel PX through the data line. However, the method by which the control logic 110 controls the data driver 120 according to the operation mode is not limited to the above example, and the data driver 120 may be controlled according to the operation mode in various ways.

[0070] The data driver 120 may include a plurality of decoders and a plurality of source amplifiers. The plurality of source amplifiers may correspond to the plurality of decoders, respectively. The source amplifier corresponding to the decoder may refer to a source amplifier connected to the decoder. For example, the first source amplifier SA1 may correspond to the first decoder DEC1. Similarly, the mth source amplifier SAm may correspond to the mth decoder DECm.

[0071] Each of the plurality of source amplifiers may correspond to a data line. A source amplifier connected to a specific data line may be a source amplifier corresponding to the specific data line. For example, the first source amplifier SA1 may correspond to the first data line DL1. Similarly, the mth source amplifier SAm may correspond to the mth data line DLm. Each of the plurality of source amplifiers may correspond to a sensing line. A source amplifier connected to a specific sensing line may be a source amplifier corresponding to the specific sensing line. For example, the first source amplifier SA1 may correspond to the first sensing line SSL1. Similarly, the mth source amplifier SAm may correspond to the mth sensing line SSLm. Figure 2 The data lines and the sensing lines as well as the source amplifiers and the decoders are shown to correspond to each other one by one. However, the embodiments are not limited thereto.

[0072] Reference Figure 2 , the display driving circuit 100 may include a first switching element and a second switching element. The data driver 120 may include a first switching element and a second switching element. Figure 2 It is shown that the first switching element and the second switching element are included in the data driver 120. However, the embodiment is not limited thereto, and in some embodiments, the first switching element and the second switching element may be implemented as a switching circuit separate from the data driver 120.

[0073] The first switch element may be connected between the first input terminal and the output terminal of the corresponding source amplifier in the plurality of source amplifiers. In other words, in some embodiments, the first switch element may be provided for each of the plurality of source amplifiers. For example, the first switch element sw1_1 may be connected between the first input terminal and the output terminal of the first source amplifier SA1. Similarly, the first switch element sw1_m may be connected between the first input terminal and the output terminal of the mth source amplifier SAm. In some embodiments, the first input terminal of the source amplifier may be an inverting input terminal. However, the embodiments are not limited thereto, and in some embodiments, the first input terminal may be a non-inverting input terminal.

[0074] The second switch element may be connected between a first input terminal of a corresponding source amplifier among the plurality of source amplifiers and a sensing line corresponding to the corresponding source amplifier among the plurality of source amplifiers. In other words, in some embodiments, a second switch element may be provided for each of the plurality of source amplifiers. For example, the second switch element sw2_1 may be connected between a first input terminal of the first source amplifier SA1 and a first sensing line SSL1. Similarly, the second switch element sw2_m may be connected between a first input terminal of an mth source amplifier SAm and an mth sensing line SSLm.

[0075] In the first operation mode, the decoder may receive pixel data DATA. The decoder may receive pixel data DATA from the control logic 110. The decoder may convert the pixel data DATA and output a pixel voltage Vpx. The pixel data DATA provided to the decoder may be converted into a grayscale voltage by the decoder, and the pixel voltage Vpx corresponding to the pixel data DATA may be provided to the source amplifier. The pixel voltage Vpx may be provided to the second input terminal of the source amplifier. In some embodiments, the second input terminal of the source amplifier may be a non-inverting input terminal. However, the embodiment is not limited thereto, and in some embodiments, the second input terminal may be an inverting input terminal. For example, the first decoder DEC1 may select a grayscale voltage corresponding to the first pixel data corresponding to the first data line DL1, and output the selected grayscale voltage as the pixel voltage Vpx. The first decoder DEC1 may provide the pixel voltage Vpx corresponding to the first pixel data to the first source amplifier SA1. The first source amplifier SA1 may receive the pixel voltage Vpx through the second input terminal. Similarly, the mth decoder DECm may select a grayscale voltage corresponding to the first pixel data corresponding to the mth data line DLm, and output the selected grayscale voltage as the pixel voltage Vpx. The mth decoder DECm may provide a pixel voltage Vpx corresponding to the first pixel data to the mth source amplifier SAm. The mth source amplifier SAm may receive the pixel voltage Vpx through a second input terminal.

[0076] In the first operation mode, the source amplifier may amplify the pixel voltage Vpx. The source amplifier may amplify the grayscale voltage selected from the decoder. The source amplifier may also be referred to as a channel amplifier. A plurality of source amplifiers may respectively amplify the pixel voltages corresponding to a plurality of decoders, and respectively provide the amplified pixel voltages to a plurality of pixels through a plurality of data lines corresponding to the plurality of source amplifiers. For example, the first source amplifier SA1 may amplify the pixel voltage Vpx output from the first decoder DEC1. The amplified pixel voltage Vpx may be provided to the second pixel PX2 corresponding to the first data line DL1. Similarly, the mth source amplifier SAm may amplify the pixel voltage Vpx output from the mth decoder DECm. The amplified pixel voltage Vpx may be provided to the second pixel PX2 corresponding to the mth data line DLm.

[0077] The control logic 110 may control the first switch element sw1 (specifically, sw1_1, ..., sw1_m) and the second switch element sw2 (specifically, sw2_1, ..., sw2_m) according to the operation mode. The control logic 110 may control the operation of the first switch element sw1 and the second switch element sw2 in the first operation mode and the second operation mode.

[0078] In one embodiment, the control logic 110 may control the first switch element sw1 and the second switch element sw2 so that the corresponding source amplifier amplifies the pixel voltage Vpx. The control logic 110 may turn on the first switch element sw1 and turn off the second switch element sw2 in the first operation mode.

[0079] For example, in the first operation mode, the first switch element sw1_1 may be turned on to form a feedback loop connecting the first input terminal and the output terminal of the first source amplifier SA1, and the pixel voltage Vpx output from the first decoder DEC1 may be amplified. The second switch element sw2_1 may be turned off so that the sampling voltage Vs output from the sensing line is not transmitted to the first source amplifier SA1. The amplified pixel voltage Vpx may be applied to the pixel PX through the first data line DL1. Similarly, in the first operation mode, the mth switch element sw1_m may be turned on to form a feedback loop connecting the first input terminal and the output terminal of the mth source amplifier SAm, and the pixel voltage Vpx output from the mth decoder DECm may be amplified. The second switch element sw2_m may be turned off so that the sampling voltage Vs output from the sensing line is not transmitted to the mth source amplifier SAm. The amplified pixel voltage Vpx may be applied to the pixel PX through the mth data line DLm.

[0080] In the second operating mode, the source amplifier may receive a sampling voltage Vs from the pixel PX via the sensing line. The second operating mode may be a test mode for determining whether an error has occurred in the pixel PX. The second operating mode may include multiple operating periods. The second operating mode may include a reset period. The reset period may refer to a period during which the sampling voltage Vs of the pixel connected to the source amplifier is initialized. The second operating mode may include a programming period. The programming period may refer to a period during which the sampling voltage Vs is output via the sensing line. The sampling voltage may represent the electrical characteristics of the pixel connected to the sensing line. The second operating mode may include a comparison period. The comparison period may refer to a period during which the source amplifier performs a comparison operation. The following will refer to Fig. 6A The second operation mode is described in detail.

[0081] During the comparison period, the decoder may receive the test data DTC. For example, in some embodiments, the decoder may receive the test data DTC from the control logic 110. The decoder may convert the test data DTC and output a comparison voltage Vref. The test data DTC provided to the decoder may be converted into a grayscale voltage by the decoder, and the comparison voltage Vref corresponding to the test data DTC may be provided to the source amplifier. The comparison voltage Vref may be provided to the second input terminal of the source amplifier. For example, the first decoder DEC1 may provide the comparison voltage Vref corresponding to the test data DTC to the first source amplifier SA1. The first source amplifier SA1 may receive the comparison voltage Vref through its second input terminal. Similarly, the mth decoder DECm may provide the comparison voltage Vref corresponding to the test data DTC to the mth source amplifier SAm. The mth source amplifier SAm may receive the comparison voltage Vref through its second input terminal.

[0082] In the comparison period, the source amplifier may perform a comparison operation. The comparison operation may refer to an operation in which the source amplifier compares the sampling voltage Vs with the comparison voltage Vref and outputs the comparison data dc. The source amplifier may receive the comparison voltage Vref from the decoder. The comparison voltage Vref may be input to the second input terminal of the source amplifier. The source amplifier may receive the sampling voltage Vs output through the sensing line. The sampling voltage Vs may be input to the first input terminal.

[0083] The control logic 110 may control the operation of the first and second switching elements sw1 and sw2 in the second operation mode. In one embodiment, each of the source amplifiers may perform a comparison operation in a comparison period based on the operation of the first and second switching elements sw1 and sw2 corresponding to the source amplifier.

[0084] The control logic 110 may control the first switch element sw1 and the second switch element sw2 to output the comparison data dc by comparing the sampling voltage Vs input to the first input terminal through the sensing line with the comparison voltage Vref input to the second input terminal. The control logic 110 may turn off the first switch element sw1 and turn on the second switch element sw2 in the comparison period. For example, in the comparison period, the second switch element sw2_1 may be turned on so that the sampling voltage Vs output from the sensing line may be transmitted to the first source amplifier SA1. The sampling voltage Vs may be input to the first input terminal. The first switch element sw1_1 may be turned off so that the first source amplifier SA1 may perform a comparison operation of comparing the sampling voltage Vs with the comparison voltage Vref. The first source amplifier SA1 may output the comparison data dc. Similarly, in the comparison period, the second switch element sw2_m may be turned on so that the sampling voltage Vs output from the sensing line may be transmitted to the mth source amplifier SAm. The sampling voltage Vs may be input to the first input terminal. The first switch element sw1_m may be turned on so that the m-th source amplifier SAm may perform a comparison operation of comparing the sampling voltage Vs with the comparison voltage Vref. The m-th source amplifier SAm may output comparison data dc.

[0085] The display driving circuit 100 may further include a level shifter. The level shifter may shift the level of the comparison data dc. For example, the level shifter may be a level-down shifter. The level shifter may reduce the voltage level of the comparison data dc output from the source amplifier.

[0086] The display driving circuit 100 may include a level switch element sw1. The control logic 110 may control the operation of the level switch element sw1 in the second operation mode. The control logic 110 may turn on the level switch element sw1 in the comparison period. When the level switch element sw1 is turned on, the level converter may generate output data Dout by converting the level of the comparison data dc. For example, when the first level switch element sw11 is turned on, the first level converter LS1 may receive the comparison data dc from the first source amplifier SA1. The first level converter LS1 may reduce the voltage level of the comparison data dc to a logic level. Similarly, when the m-th level switch element sw1m is turned on, the m-th level converter LSm may receive the comparison data dc from the m-th source amplifier SAm. The m-th level converter LSm may reduce the voltage level of the comparison data dc to a logic level.

[0087] In one embodiment, based on the comparison data dc, the control logic 110 may determine whether an error has occurred in each pixel PX. The control logic 110 may receive the output data Dout generated by converting the level of the comparison data dc, and determine whether an error has occurred in each pixel PX based on the output data Dout. For example, based on the comparison data dc output from the first source amplifier SA1, the control logic 110 may determine whether an error has occurred in the second pixel PX2 connected to the first source amplifier SA1 through the data line DL1. Based on the output data Dout output from the first level converter LS1, the control logic 110 may determine whether an error has occurred in the second pixel PX2. Similarly, based on the comparison data dc output from the mth source amplifier SAm, the control logic 110 may determine whether an error has occurred in the second pixel PX2 connected to the mth source amplifier SAm through the mth data line DLm. Based on the output data Dout output from the mth level converter LSm, the control logic 110 may determine whether an error has occurred in the second pixel PX2.

[0088] With respect to the display driver circuit 100 and the display device 10 according to various embodiments, since a separate existing source amplifier can perform a comparison operation, even when a separate comparator is not added to the source amplifier, the display driver circuit 100 and the display device 10 can identify whether an error has occurred in a pixel. Therefore, the cost required for the test operation can be reduced, and the size of the display driver circuit 100 can be reduced. In other words, the display device according to the prior art requires a separate comparator in order to perform a test operation. In contrast, since the existing source amplifiers SA1, ..., SAm according to various embodiments can perform a comparison operation for a test operation, the display driver circuit 100 and the display device 10 can identify whether an error has occurred in a pixel.

[0089] Figure 3 is a circuit diagram showing an example of a pixel according to the embodiment. Figure 3 The pixel PXa can be Figure 1 and Figure 2 An example of a pixel PX. Figure 3 The pixel PXa can be applied to Figure 1 A display device 10 is provided.

[0090] The pixel PXa may include an OLED and a pixel circuit PXIRa. The pixel PXa may include a first scan line SL1 extending in a first direction D1, a second scan line SL2 extending in the first direction D1, a data line DL extending in a second direction D2 intersecting the first direction D1, a sensing line SSL extending in the second direction D2, a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor CS, and an OLED. For example, the first direction D1 may be an X-axis direction, and the second direction D2 may be a Y-axis direction. However, Figure 3 The configuration and structure of the pixel PXa are merely examples of a circuit of the pixel PXa, and the configuration and structure of the pixel PXa may be variously modified.

[0091] A first driving voltage may be applied to the pixel PXa from a first driving power source ELVDD, and a second driving voltage may be applied from a second driving power source ELVSS. The first driving power source ELVDD may be relatively higher than the second driving power source ELVSS. The pixel circuit PXIRa may include a first transistor T1 to a third transistor T3 and a storage capacitor CS. At least one of the first transistor T1 to the third transistor T3 may include an amorphous silicon (a-Si) thin film transistor (TFT), a polycrystalline silicon (poly-Si) TFT, an oxide TFT, an organic TFT, or the like. In one embodiment, at least one of the first transistor T1 to the third transistor T3 may be formed as an N-type transistor. However, the embodiment is not limited thereto, and at least one of the first transistor T1 to the third transistor T3 may be formed as a P-type transistor.

[0092] The first transistor T1 may be connected between the data line DL and the second node n2, and may operate in response to a scan signal s1 applied through the first scan line SL1. In a first operation mode, the first transistor T1 may be turned on by the scan signal s1 applied through the first scan line SL1 to provide the second node n2 with a signal from a data driver (e.g., Figure 1 The pixel voltage is supplied by the data driver 120.

[0093] The second transistor T2 may be connected between the first driving power source ELVDD and the first node n1, and may operate in response to a voltage applied through the second node n2. In the first operation mode, the first driving voltage may be applied to the first terminal of the second transistor T2, and the amount of current flowing through the second transistor T2 may be determined based on a voltage difference between the first node n1 and the second node n2. The amount of current flowing through the second transistor T2 may be supplied to the OLED.

[0094] The third transistor T3 may be connected between the first node n1 and the sensing line SSL, and may operate in response to a scan signal s2 applied through the second scan line SL2. In a first operation mode, the third transistor T3 may be turned on by the scan signal s2 applied through the second scan line SL2 to provide an initialization voltage supplied from the data driver through the sensing line SSL to the first node n1. In one embodiment, in a second operation mode, the third transistor T3 may be turned on by a signal applied through the second scan line SL2 to provide a sampling voltage to the data driver. For example, in the second operation mode, the third transistor T3 may provide a voltage of the first node n1 to the data driver through the sensing line SSL.

[0095] The storage capacitor CS may store a difference between a voltage applied to the second node n2 through the first transistor T1 and a voltage applied to the first node n1 through the third transistor T3 .

[0096] The OLED may be connected to the second terminal of the second transistor T2, the first node n1, and the second driving power source ELVSS. The OLED may include an anode connected to the first node n1, a cathode to which the second driving power source ELVSS is applied, and an organic light emitting layer between the cathode and the anode. When current is supplied from the second transistor T2 to the OLED, the OLED may generate light in the organic light emitting layer. The intensity of the light may be proportional to the current.

[0097] Figure 4 is a circuit diagram showing an example of a pixel according to the embodiment. Figure 4 The pixel PXb can be Figure 1 The pixels PX and Figure 2 An example of a pixel PX. Figure 4 The pixel PXb can be applied to Figure 1 A display device 10 is provided.

[0098] The pixel PXb may include an OLED and a pixel circuit PXIRb. The pixel PXb may include six transistors. The pixel PXb may include a first scan line SL1, a second scan line SL2, a data line DL, a sensing line SSL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a storage capacitor CS, and an OLED. However, Figure 4 The configuration and structure of the pixel PXb are merely examples of the pixel circuit PXIRb, and in some embodiments, the configuration and structure of the pixel PXb may be variously modified.

[0099] A first driving voltage may be applied to the pixel PXb from a first driving power source ELVDD, and a second driving voltage may be applied from a second driving power source ELVSS. The pixel circuit PXIRb may include a first transistor T1 to a sixth transistor T6 and a storage capacitor CS. At least one of the first transistor T1 to the sixth transistor T6 may be implemented as an oxide semiconductor thin film transistor including an active layer including an oxide semiconductor, a low temperature polycrystalline silicon (LTPS) thin film transistor including an active layer including polycrystalline silicon, or a metal oxide semiconductor field effect transistor (MOSFET). In one embodiment, at least one of the first transistor T1 to the sixth transistor T6 may be formed as a P-type transistor. However, the embodiment is not limited thereto, and in some embodiments, at least one of the first transistor T1 to the sixth transistor T6 may be formed as an N-type transistor.

[0100] The gate electrode of the first transistor T1 may be connected to one end of the storage capacitor CS. The source electrode of the first transistor T1 may be connected to the fifth transistor T5 and the other end of the storage capacitor CS, and the drain electrode of the first transistor T1 may be connected to the sixth transistor T6. In the first operation mode, the first transistor T1 may receive a pixel voltage supplied through the data line DL according to a switching operation of the second transistor T2, and supply a driving current Id to the OLED.

[0101] A gate electrode of the second transistor T2 may be connected to the first scan line SL1, a source electrode of the second transistor T2 may be connected to the data line DL, and a drain electrode of the second transistor T2 may be connected to the first transistor T1 and the fifth transistor T5. The second transistor T2 may be turned on according to a scan signal received through the first scan line SL1 to transfer a pixel voltage supplied through the data line DL to the first transistor T1.

[0102] A gate electrode of the third transistor T3 may be connected to the first scan line SL1, a source electrode of the third transistor T3 may be connected to the first transistor T1, and a drain electrode of the third transistor T3 may be connected to the first transistor T1 and one end of the storage capacitor CS. The third transistor T3 may be turned on according to a scan signal received through the first scan line SL1 to connect the gate electrode and the drain electrode of the first transistor T1 to each other.

[0103] A gate electrode of the fourth transistor T4 may be connected to the second scan line SL2, a source electrode of the fourth transistor T4 may be connected to the sensing line SSL, and a drain electrode of the fourth transistor T4 may be connected to one end of the storage capacitor CS, the third transistor T3, and the first transistor T1. In one embodiment, the fourth transistor T4 may be turned on according to a scan signal received through the first scan line SL1 to provide an initialization voltage to the sensing line SSL. The fourth transistor T4 may be turned on according to a scan signal received through the first scan line SL1 to provide a sampling voltage to the data driver through the sensing line SSL.

[0104] A gate electrode of the fifth transistor T5 may be connected to the light emission control line EN, a source electrode of the fifth transistor T5 may be connected to the first driving power source ELVDD, and a drain electrode of the fifth transistor T5 may be connected to the first transistor T1.

[0105] A gate electrode of the sixth transistor T6 may be connected to a light emission control line EN, a source electrode of the sixth transistor T6 may be connected to the first transistor T1 and the third transistor T3, and a drain electrode of the sixth transistor T6 may be connected to the OLED. The fifth transistor T5 and the sixth transistor T6 may be turned on simultaneously according to a light emission control signal EM received through the light emission control line EN, and current may flow through the OLED.

[0106] One end of the storage capacitor CS may be connected to the first transistor T1 , and the other end may be connected to the first transistor T1 .

[0107] The OLED may be connected to the drain electrode of the sixth transistor T6. The OLED may include an anode connected to the drain electrode of the sixth transistor T6, a cathode to which the second driving power source ELVSS is applied, and an organic light emitting layer between the cathode and the anode. When current is supplied from the sixth transistor T6 to the OLED, the OLED may generate light in the organic light emitting layer.

[0108] Figure 5 is a circuit diagram showing an example of a pixel according to the embodiment. Figure 5 The pixel PXc can be Figure 1 The pixels PX and Figure 2 An example of a pixel PX. Figure 5 The pixel PXc can be applied to Figure 1 The display device 10. Figure 4 Compared with the pixel PXb, Figure 5 The pixel PXc may further include a seventh transistor T7. For the sake of brevity, the above reference will be omitted. Figure 4 Redundant description of the given description.

[0109] The pixel PXc may include seven transistors. The pixel PXc may include a first scan line SL1, a second scan line SL2, a data line DL, a sensing line SSL, first to seventh transistors T1 to T7, a storage capacitor CS, and an OLED. However, Figure 5 The configuration and structure of the pixel PXc are merely examples of the pixel circuit PXIRc, and in some embodiments, the configuration and structure of the pixel PXc may be variously modified.

[0110] At least one of the first to seventh transistors T1 to T7 may be implemented as an oxide semiconductor thin film transistor including an active layer including an oxide semiconductor, an LTPS thin film transistor including an active layer including polysilicon, or a MOSFET. In one embodiment, at least one of the first to seventh transistors T1 to T7 may be formed as a P-type transistor. However, the embodiment is not limited thereto, and in some embodiments, at least one of the first to seventh transistors T1 to T7 may be formed as an N-type transistor.

[0111] The seventh transistor T7 may be connected between the third transistor T3 and the fourth transistor T4. The seventh transistor T7 may operate in response to the control signal EXT. In response to the control signal EXT, the seventh transistor T7 may be turned on. The seventh transistor T7 may be turned on so that the third transistor T3 and the sensing line SSL are electrically connected to each other. Figures 3 to 5 The described pixels are operable in a first mode of operation and a second mode of operation. In the following, the operation of the pixels and the display drive circuit in the second mode of operation will be described.

[0112] Fig. 6A is a diagram for describing a reset period RESET according to an embodiment. Figure 6B is a diagram for describing a program period PROGRAM according to an embodiment. Figure 6C is a diagram for describing a comparison period COMPARISON according to an embodiment. Figure 7 is a timing diagram showing a plurality of signals for controlling a pixel and a display driving circuit according to an embodiment.

[0113] For ease of description, Fig. 6A , Figure 6B and Figure 6C 1 and 2 show at least a portion of the display driving circuit 100 and at least one pixel PX. FIG. 6A to FIG. 6C The description is not limited to FIG. 6A to FIG. 6C In some embodiments, a test mode as a second operating mode may be performed before depositing the OLED. Because the operation of the pixel and the display driving circuit in the second operating mode will be described below, the OLED is omitted from the pixel PXa for ease of description and simplicity.

[0114] FIG. 6A to FIG. 6C The pixel PXa is shown to include three transistors. However, the embodiment is not limited thereto, and in some embodiments, the pixel PXa may include various numbers of transistors, and FIG. 6A to FIG. 6C The description of can be applied to pixels PXa having various structures. Fig. 6A and Figure 7 .in addition, FIG. 6A to FIG. 6C The operation is described with respect to a single source amplifier SA. It will be appreciated that similar operation applies to the other ones of the source amplifiers.

[0115] Reference Fig. 6A and Figure 7 , the second operation mode may include a reset period. The reset period may be from the first time t1 to the second time t2. The reset period may refer to a period during which the sampling voltage Vs of the pixel PXa connected to the source amplifier SA is initialized. During the reset period, a test voltage Vtest for determining an error in the pixel PXa may be applied to the pixel PXa through the data line DL. In one embodiment, the control logic (e.g., Figure 1 The control logic 110) may apply the test voltage Vtest to the pixel PXa through the data line DL.

[0116] The control logic may control the test switch element swt and the MUX switch element swm. The control logic may output a control signal Sswt for controlling the test switch element swt and a control signal Sswm for controlling the MUX switch element swm. The test switch element swt may operate in response to the control signal Sswt. The MUX switch element swm may operate in response to the control signal Sswm.

[0117] In the reset period, the control signal Sswt may have an effective level (e.g., a high level or a first level), and the control signal Sswm may have an ineffective level (e.g., a low level or a second level). The test switch element swt may be turned on based on the control signal Sswt of the effective level. The MUX switch element swm may be turned off based on the control signal Sswm of the ineffective level. In the reset period, the test switch element swt may be turned on and the MUX switch element swm may be turned off, so that the test voltage Vtest may be applied to the data line DL.

[0118] In the reset period, the first transistor T1 may be turned on. The first scan signal s1 may have an active level. In response to the first scan signal s1 of the active level, the first transistor T1 may be turned on and may transmit the test voltage Vtest provided through the data line DL to the second node n2.

[0119] In the reset period, an initialization voltage Vint for initializing the sampling voltage Vs of the sensing line SSL output to the pixel PXa may be applied to the pixel PXa through the sensing line SSL. In one embodiment, the control logic may apply the initialization voltage Vint to the pixel PXa through the sensing line SSL. The initialization voltage Vint may be provided from an initialization power supply EVINT.

[0120] In one embodiment, the display driving circuit 100 may include a third switch element sw3 connected between the initialization power source EVINT and the sensing line SSL. FIG. 6A to FIG. 6C As shown in . The control logic may control the third switch element sw3. The control logic may output a control signal Ssw3 for controlling the third switch element sw3. The third switch element sw3 may operate in response to the control signal Ssw3.

[0121] The display driving circuit 100 may include a first switching element sw1 and a second switching element sw2. The first switching element sw1 may be connected between an output terminal and a first input terminal of a source amplifier SA. The second switching element sw2 may be connected between a sensing line SSL and a first input terminal of the source amplifier SA. The control logic may control the first switching element sw1 and the second switching element sw2. The control logic may output a control signal Ssw1 for controlling the first switching element sw1 and a control signal Ssw2 for controlling the second switching element sw2. The first switching element sw1 may operate in response to the control signal Ssw1. The second switching element sw2 may operate in response to the control signal Ssw2.

[0122] In the reset period, the control signal Ssw1 may have an active level, and the control signal Ssw2 may have an inactive level. The first switching element sw1 may be turned on based on the active level of the control signal Ssw1, and the second switching element sw2 may be turned off based on the inactive level of the control signal Ssw2.

[0123] In the reset period, the control signal Ssw3 may have an effective level. The third switch element sw3 may be turned on based on the control signal Ssw3 of the effective level. In some embodiments, in the reset period, the control logic may turn on the first switch element sw1 and the third switch element sw3 and turn off the second switch element sw2 to apply the initialization voltage Vint to the pixel PXa through the third switch element sw3 and the sensing line SSL.

[0124] In the reset period, the third transistor T3 may be turned on. The second scan signal s2 may have an effective level. In response to the second scan signal s2 of the effective level, the third transistor T3 may be turned on and the third transistor T3 may transmit the initialization voltage Vint provided through the sensing line SSL to the first node n1. The storage capacitor CS may store the difference between the test voltage Vtest and the initialization voltage Vint.

[0125] In one embodiment, the display driving circuit 100 may include a level switch element sw1. In a reset period, the control logic may control the level switch element sw1. The control logic may output a control signal Ssw1 to control the level switch element sw1. The level switch element sw1 may operate in response to the control signal Ssw1. In a reset period, the control signal Ssw1 may have an invalid level. The level switch element sw1 may be disconnected based on the control signal Ssw1 of the invalid level.

[0126] In the reset period, the decoder DEC may receive the test data DTC. The control logic may provide the first test data DTC1. In the reset period, the first test data DTC1 may be provided to the decoder DEC, and the first comparison voltage Vref1 corresponding to the first test data DTC1 may be provided to the source amplifier SA. The first comparison voltage Vref1 of a level corresponding to the first test data DTC1 may be provided to the source amplifier SA. Figure 7 It is shown that the first test data DTC1 is provided in the reset period. However, the embodiment is not limited thereto, and in some embodiments, the second test data DTC2 may be provided in the reset period, or the test data DTC may not be provided in the reset period. Since the initialization voltage Vint is applied through the sensing line SSL, the sampling voltage Vs may be the initialization voltage Vint.

[0127] Figure 6B is a diagram for describing a programming period according to an embodiment. Fig. 6A Redundant description of the given description.

[0128] Reference Figure 6B and Figure 7 , the second operation mode may include a programming period. The programming period may be from the second time t2 to the third time t3. The programming period may refer to a period during which the sampling voltage Vs is output through the sensing line SSL. The programming period may be after the reset period.

[0129] In the programming period, the control signal Sswt may have an effective level, and the control signal Sswm may have an ineffective level. The test switch element swt may maintain a conductive state based on the control signal Sswt based on the effective level. The MUX switch element swm may maintain a disconnected state based on the control signal Sswm of the ineffective level. In the programming period, the test switch element swt and the MUX switch element swm may maintain the state of the reset period. The test voltage Vtest may continue to be applied to the data line DL.

[0130] The first transistor T1 may maintain a turned-on state in the programming period. In the programming period, since the first scan signal s1 continues to have an active level, the first transistor T1 may maintain a turned-on state in the reset period in response to the first scan signal s1 of an active level.

[0131] In the programming period, the control signal Ssw1 may have an active level, and the control signal Ssw2 may have an inactive level. Since the control signal Ssw1 continues to have an active level, the first switch element sw1 may maintain an on state. Since the control signal Ssw2 continues to have an inactive level, the second switch element sw2 may maintain an off state.

[0132] In the programming period, the sampling voltage Vs may be output through the sensing line SSL. In the programming period, the control logic may control the third switch element sw3. In the programming period, the control signal Ssw3 may have an invalid level. At the second time t2, the control signal Ssw3 may be changed from the valid level to the invalid level. In the programming period, the third switch element sw3 may be turned off based on the control signal Ssw3 of the invalid level. In the programming period, the control logic may turn off the third switch element sw3 so that the sampling voltage Vs may be output through the sensing line SSL.

[0133] In the programming period, the third transistor T3 may maintain a turned-on state. In response to the second scan signal s2 of an active level, the third transistor T3 may be turned on and may provide the voltage of the first node n1 as a sampling voltage Vs through the sensing line SSL.

[0134] In the programming period, the control logic may control the level switch element swl. In the programming period, the control signal Sswl may maintain an inactive level. The level switch element swl may maintain an off state based on the control signal Sswl of the inactive level.

[0135] In the programming period, the first comparison voltage Vref1 of a level corresponding to the first test data DTC1 may be provided to the source amplifier SA. Figure 7It is shown that the first test data DTC1 is provided in the programming period. However, the embodiment is not limited thereto, and in some embodiments, the second test data DTC2 may be provided in the programming period, or the test data DTC may not be provided in the programming period. The sampling voltage Vs may be output through the sensing line SSL.

[0136] Figure 6C is a diagram for describing a comparison period according to an embodiment. For the sake of brevity, redundant descriptions regarding the description given above will be omitted.

[0137] Reference Figure 6C and Figure 7 , the second operation mode may include a comparison period. The comparison period may be from the third time t3 to the fifth time t5. The comparison period may refer to a period in which the source amplifier SA performs a comparison operation. The comparison period may be after the programming period.

[0138] In one embodiment, the comparison period may include a first comparison period COM1 and a second comparison period COM2. In some embodiments, the first comparison period COM1 may refer to a period in which the source amplifier SA performs a comparison operation based on the first comparison voltage Vref1, and the second comparison period COM2 may refer to a period in which the source amplifier SA performs a comparison operation based on the second comparison voltage Vref2. The second comparison period COM2 may be after the first comparison period COM1. For example, the first comparison period COM1 may be from the third time t3 to the fourth time t4, and the second comparison period COM2 may be from the fourth time t4 to the fifth time t5. However, the embodiment is not limited thereto, and in some embodiments, the second comparison period COM2 may be before the first comparison period COM1.

[0139] In the comparison period, the control signal Sswt may have an effective level, and the control signal Sswm may have an ineffective level. The test switch element swt may maintain an on state based on the control signal Sswt of the effective level. The MUX switch element swm may maintain an off state based on the control signal Sswm of the ineffective level.

[0140] In the comparison period, the first transistor T1 may maintain a turned-on state. The first transistor T1 may be turned on in response to the first scan signal s1 of an active level.

[0141] In the comparison period, the third switch element sw3 may maintain an off state. In response to the control signal Ssw3 of the inactive level, the third switch element sw3 may maintain an off state.

[0142] In one embodiment, during the comparison period, the first switch element sw1 and the second switch element sw2 may be controlled. The control logic may control the first switch element sw1 and the second switch element sw2. The first switch element sw1 may operate in response to the control signal Ssw1. The second switch element sw2 may operate in response to the control signal Ssw2.

[0143] In the comparison period, the control signal Ssw1 may have an invalid level. At the third time t3, the control signal Ssw1 may be changed from the valid level to the invalid level. In the comparison period, the first switch element sw1 may be turned off based on the control signal Ssw1 of the invalid level. Because the first switch element sw1 is turned off, the first input terminal and the output terminal of the source amplifier SA may not be connected to each other, and the source amplifier SA may operate as a comparator.

[0144] In the comparison period, the control signal Ssw2 may have an effective level. At the third time t3, the control signal Ssw2 may be changed from an ineffective level to an effective level. In the comparison period, the second switch element sw2 may be turned on based on the control signal Ssw2 of the effective level. Because the second switch element sw2 is turned on, the first input terminal of the source amplifier SA and the sensing line SSL may be connected to each other, and the sampling voltage Vs may be provided to the first input terminal of the source amplifier SA.

[0145] In the comparison period, the control logic may provide a comparison voltage Vref. In some embodiments, the control logic may provide different comparison voltages Vref in the first comparison period COM1 and the second comparison period COM2. In one embodiment, the control logic may provide the first comparison voltage Vref1 to the source amplifier SA in the first comparison period COM1. Specifically, in the first comparison period COM1, the control logic may provide the first test data DTC1 to the decoder DEC. The decoder DEC may output the first comparison voltage Vref1 corresponding to the first test data DTC1. The first comparison voltage Vref1 corresponding to the first test data DTC1 may be provided to the source amplifier SA. The first comparison voltage Vref1 of a level corresponding to the first test data DTC1 may be provided to the second input terminal of the source amplifier SA.

[0146] In the comparison period, the source amplifier SA may output comparison data dc by comparing the sampling voltage Vs input to the first input terminal with the comparison voltage Vref input to the second input terminal. In one embodiment, in the first comparison period COM1, the source amplifier SA may output first comparison data by comparing the sampling voltage Vs with the first comparison voltage Vref1.

[0147] In one embodiment, the control logic may provide the second comparison voltage Vref2 to the source amplifier SA in the second comparison period COM2. Specifically, in the second comparison period COM2, the control logic may provide the second test data DTC2 to the decoder DEC. The decoder DEC may output the second comparison voltage Vref2 corresponding to the second test data DTC2. For example, in some embodiments, the level of the second comparison voltage Vref2 may be greater than the level of the first comparison voltage Vref1. The second comparison voltage Vref2 corresponding to the second test data DTC2 may be provided to the source amplifier SA. The second comparison voltage Vref2 of the level corresponding to the second test data DTC2 may be provided to the second input terminal of the source amplifier SA. In the second comparison period COM2, the source amplifier SA may output the second comparison data by comparing the sampling voltage Vs with the second comparison voltage Vref2.

[0148] In the comparison period, the control signal Sswl may have an effective level. At the third time t3, the control signal Sswl may be changed from an invalid level to an effective level. In the comparison period, the level switch element swl may be turned on based on the control signal Sswl of the effective level. Because the level switch element swl is turned on, the output of the source amplifier SA may be provided to the level converter. In the comparison period, the comparison data dc may be provided to the level converter. For example, in some embodiments, the first comparison data may be provided to the level converter in the first comparison period COM1, and the second comparison data may be provided to the level converter in the second comparison period COM2. In the normal operation period ( FIG. 6A to FIG. 6C and Figure 7 In the embodiment shown in Figure 1, the control signal Sswt may have an invalid level, and the control signal Sswm may have an effective level. The test switch element swt may be in an off state based on the control signal Sswt of the invalid level. The MUX switch element swm may be in an on state based on the control signal Sswm of the effective level. In this way, the display drive circuit 100 can operate in a normal (non-test) operation mode / normal (non-test) period in which the source amplifier SA performs amplification instead of comparison.

[0149] In one embodiment, the display driving circuit 100 may determine whether an error has occurred in at least a portion of the pixel PXa. The control logic may determine whether an error has occurred in the pixel PXa based on the first comparison data and the second comparison data. Specifically, the control logic may receive the first output data obtained by converting the first comparison data and the second output data obtained by converting the second comparison data from the level converter. The control logic may determine whether an error has occurred in the pixel PXa based on the first output data and the second output data. In some embodiments, the control logic may be configured to output an error signal indicating whether an error has occurred in the pixel PXa. For example, in some embodiments, the error signal may be a flag. In some embodiments, an action may be taken based on the error signal to correct the pixel PXa in which an error has occurred. For example, the display panel 200 may be wired during manufacturing to perform a correction action for repairing (fix) or replacing the pixel PXa. However, the embodiment is not limited to the control logic determining whether an error has occurred. In some embodiments, a test device outside the display device may receive the first output data and the second output data, and may determine whether an error has occurred in a portion of the pixel PXa based on the first output data and the second output data. Since the source amplifier SA operates as a comparator to output comparison data dc, and determines whether an error has occurred in the pixel PXa based on the comparison data dc, an accurate determination can be made at a low cost.

[0150] Fig. 8A is a diagram for describing a reset period RESET according to an embodiment. Figure 8B is a diagram for describing a program period PROGRAM according to an embodiment. Figure 8C is a diagram for describing a comparison period COMPARISON according to an embodiment. Fig. 9 is a timing diagram showing a plurality of signals for controlling a pixel and a display driving circuit according to an embodiment. FIG. 8A to FIG. 9 An embodiment in which the source amplifier SA applies the initialization voltage Vint is shown. For the sake of brevity, redundant descriptions regarding the description given above will be omitted.

[0151] FIG. 8A to FIG. 8C Pixel PXb is shown to include six transistors. However, embodiments are not limited thereto, and in some embodiments, pixel PXb may include various numbers of transistors, and FIG. 8A to FIG. 8C The description of can be applied to pixels PXb having various structures. Fig. 8A and Fig. 9 .

[0152] Reference Fig. 8A and Fig. 9, the second operation mode may include a reset period. The reset period may be from the first time t1 to the second time t2. In one embodiment, the control logic (e.g., Figure 1 The control logic 110) may apply the test voltage Vtest to the pixel PXb through the data line DL.

[0153] In the reset period, the control signal Sswt may have an active level and the control signal Sswm may have an inactive level. In the reset period, the test switch element swt may be turned on and the MUX switch element swm may be turned off so that the test voltage Vtest may be applied to the data line DL.

[0154] In the reset period, the second transistor T2 may be turned on. The first scan signal s1 may have an inactive level. In response to the first scan signal s1 of the inactive level, the second transistor T2 may be turned on, and the second transistor T2 may transmit the test voltage Vtest provided through the data line DL to the first transistor T1. In the reset period, the third transistor T3 may be turned on. The third transistor T3 may be turned on in response to the first scan signal s1 of the inactive level.

[0155] In the reset period, the fifth transistor T5 and the sixth transistor T6 may be turned off. The fifth transistor T5 and the sixth transistor T6 may operate in response to the light emission control signal EM applied through the light emission control line EN. In the reset period, the light emission control signal EM may have an effective level. The fifth transistor T5 and the sixth transistor T6 may be turned off in response to the light emission control signal EM of the effective level.

[0156] In the reset period, the initialization voltage Vint may be applied to the pixel PXb. In one embodiment, the control logic may apply the initialization voltage Vint to the pixel PXb through the source amplifier SA. The initialization voltage Vint may be provided from the source amplifier SA.

[0157] In one embodiment, the display driving circuit 100 may include a fourth switch element sw4 connected between an output terminal of the source amplifier SA and the sensing line SSL. The control logic may control the fourth switch element sw4. The control logic may output a control signal Ssw4 for controlling the fourth switch element sw4. The fourth switch element sw4 may operate in response to the control signal Ssw4.

[0158] In the reset period, the control signal Ssw1 may have an active level, and the control signal Ssw2 may have an inactive level. The first switching element sw1 may be turned on based on the active level of the control signal Ssw1, and the second switching element sw2 may be turned off based on the inactive level of the control signal Ssw2.

[0159] In the reset period, the control signal Ssw4 may have an effective level. The fourth switch element sw4 may be turned on based on the control signal Ssw4 of the effective level. In the reset period, the control logic may turn on the first switch element sw1 and the fourth switch element sw4 to apply the initialization voltage Vint to the pixel PXb from the output terminal of the source amplifier SA through the fourth switch element sw4. The control logic may turn off the second switch element sw2 so as not to connect the first input terminal of the source amplifier SA to the sensing line SSL.

[0160] In the reset period, the fourth transistor T4 may be turned on. The second scan signal s2 may have an inactive level. In response to the second scan signal s2 of the inactive level, the fourth transistor T4 may be turned on and may transmit the initialization voltage Vint provided from the source amplifier SA to the first node n1.

[0161] In the reset period, the control signal Ssw3 for controlling the third switch element sw3 may have an invalid level. The third switch element sw3 may be turned off based on the control signal Ssw3 of the invalid level. The control signal Ssw1 may have an invalid level. The level switch element sw1 may be turned off based on the control signal Ssw1 of the invalid level.

[0162] In the reset period, the decoder DEC may receive initialization data Dint. The control logic may provide the initialization data Dint. In the reset period, the initialization data Dint may be provided to the decoder DEC, and the decoder voltage Vd may be output. The output voltage Vd corresponding to the initialization data Dint may be provided to the source amplifier SA. The output voltage Vd corresponding to the initialization data Dint may be a preliminary initialization voltage Vpint, and the preliminary initialization voltage Vpint may be provided to the second input terminal of the source amplifier SA. The source amplifier SA may amplify the preliminary initialization voltage Vpint and output the initialization voltage Vint.

[0163] Since the display driving circuit 100 according to the embodiment can directly apply the initialization voltage Vint to the pixel PXb by using the source amplifier SA, the initialization voltage Vint can be quickly applied. Therefore, the test operation can be quickly performed.

[0164] Figure 8B is a diagram for describing a programming period according to an embodiment. Fig. 8A Redundant description of the given description.

[0165] Reference Figure 8B and Fig. 9, the second operation mode may include a programming period. The programming period may be from the second time t2 to the third time t3. In the programming period, because the control signal Sswt has a valid level and the control signal Sswm has an invalid level, the test switch element swt may maintain a turned-on state, and the MUX switch element swm may maintain a turned-off state.

[0166] In the programming period, because the first scan signal s1 has an invalid level, the second transistor T2 and the third transistor T3 may maintain a turned-on state. In the programming period, because the light emitting control signal EM has an effective level, the fifth transistor T5 and the sixth transistor T6 may maintain a turned-off state. In the programming period, the control signal Ssw1 may have an effective level, and the control signal Ssw2 may have an invalid level. The first switching element sw1 may be in a turned-on state, and the second switching element sw2 may be in a turned-off state.

[0167] In one embodiment, during the programming period, the control logic may control the fourth switch element sw4. During the programming period, the control signal Ssw4 may have an invalid level. At the second time t2, the control signal Ssw4 may be changed from the valid level to the invalid level. The fourth switch element sw4 may be disconnected based on the control signal Ssw4 of the invalid level. During the programming period, the control logic may disconnect the fourth switch element sw4 so that the sampling voltage Vs of the pixel PXb can be output through the sensing line SSL.

[0168] In the programming period, because the second scan signal s2 has an invalid level, the fourth transistor T4 can maintain a turned-on state. The fourth transistor T4 can provide the voltage of the first node n1 as a sampling voltage Vs through the sensing line SSL. In one embodiment, the sampling voltage Vs can be the difference between the test voltage Vtest and the threshold voltage VTH of the first transistor T1.

[0169] In the programming period, the level switching element swl may maintain a turned-off state based on the control signal Sswl of the invalid level.

[0170] In the programming period, the first comparison voltage Vref1 of a level corresponding to the first test data DTC1 may be provided to the source amplifier SA. In the programming period, the first test data DTC1 may be provided to the decoder DEC, and the first comparison voltage Vref1 may be output as the decoder voltage Vd. The first comparison voltage Vref1 may be provided to the second input terminal of the source amplifier SA. Fig. 9 It is shown that the first test data DTC1 is provided in the programming period. However, the embodiment is not limited thereto, and in some embodiments, the second test data DTC2 may be provided in the programming period, or the test data DTC may not be provided in the programming period. The sampling voltage Vs may be output through the sensing line SSL.

[0171] Figure 8C is a diagram for describing a comparison period according to an embodiment. For the sake of brevity, redundant descriptions regarding the description given above will be omitted.

[0172] Reference Figure 8C and Fig. 9 , the second operation mode may include a comparison period. The comparison period may be from the third time t3 to the fifth time t5. The comparison period may include a first comparison period COM1 and a second comparison period COM2.

[0173] In the comparison period, the test switch element swt may maintain a turned-on state based on the control signal Sswt of the active level, and the MUX switch element swm may maintain a turned-off state based on the control signal Sswm of the inactive level.

[0174] In the comparison period, the fifth transistor T5 and the sixth transistor T6 may maintain an off state in response to the light emitting control signal EM of the effective level. In the comparison period, the second transistor T2 and the third transistor T3 may maintain an on state in response to the first scan signal s1 of the invalid level. In the comparison period, the fourth transistor T4 may maintain an on state in response to the second scan signal s2 of the invalid level.

[0175] In the comparison period, the third switch element sw3 may maintain an off state in response to the control signal Ssw3 of an inactive level. In the comparison period, the fourth switch element sw4 may maintain an off state in response to the control signal Ssw4 of an inactive level.

[0176] In one embodiment, during the comparison period, the first switch element sw1 and the second switch element sw2 may be controlled. During the comparison period, the control signal Ssw1 may have an invalid level. At the third time t3, the control signal Ssw1 may be changed from the valid level to the invalid level. During the comparison period, the first switch element sw1 may be disconnected based on the control signal Ssw1 of the invalid level. During the comparison period, the control signal Ssw2 may have an effective level. At the third time t3, the control signal Ssw2 may be changed from the invalid level to the effective level. During the comparison period, the second switch element sw2 may be turned on based on the control signal Ssw2 of the effective level. The sampling voltage Vs may be provided to the first input terminal of the source amplifier SA.

[0177] In one embodiment, the control logic may provide the first comparison voltage Vref1 to the source amplifier SA in the first comparison period COM1. In the first comparison period COM1, the source amplifier SA may output first comparison data by comparing the sampling voltage Vs with the first comparison voltage Vref1.

[0178] In one embodiment, the control logic may provide the second comparison voltage Vref2 to the source amplifier SA in the second comparison period COM2. In the second comparison period COM2, the source amplifier SA may output second comparison data by comparing the sampling voltage Vs with the second comparison voltage Vref2.

[0179] In the comparison period, the control signal Sswl may have an effective level. At the third time t3, the control signal Sswl may be changed from an ineffective level to an effective level. Because the level switch element swl is turned on, the output of the source amplifier SA may be provided to the level converter. The first comparison data may be provided to the level converter in the first comparison period COM1, and the second comparison data may be provided to the level converter in the second comparison period COM2.

[0180] Fig. 10A is a diagram for describing an offset correction period according to an embodiment. Fig. 10B is a diagram for describing a comparison period after an offset correction period according to an embodiment. Fig.11 1 is a timing diagram showing a plurality of signals for controlling a pixel and a display driving circuit according to an embodiment. For the sake of brevity, redundant descriptions regarding the description given above will be omitted.

[0181] Fig. 10A and Fig. 10B Pixel PXb is shown to include six transistors. However, embodiments are not limited thereto, and in some embodiments, pixel PXb may include various numbers of transistors, and FIG. 10A to FIG. 11 The description of can be applied to pixels PXb having various structures. Fig. 10A and Fig.11 .

[0182] Reference Fig. 10A and Fig.11 In the reset period and the programming period, the pixel PXb and the display driving circuit 100 can be the same as those described above. FIG. 6A to FIG. 9 The described pixel PXb and display driving circuit 100 operate similarly. The second operation mode may include an offset correction period. The offset correction period may refer to a period for correcting the offset of the source amplifier SA. The offset correction period may be after the programming period.

[0183] In one embodiment, the offset correction period may include a first offset correction period OC1 and a second offset correction period OC2. The first offset correction period OC1 may correspond to and precede the first comparison period COM1, and the second offset correction period OC2 may correspond to and precede the second comparison period COM2. For example, the first offset correction period OC1 may be from the third time t3 to the fourth time t4, the first comparison period COM1 may be from the fourth time t4 to the fifth time t5, the second offset correction period OC2 may be from the fifth time t5 to the sixth time t6, and the second comparison period COM2 may be from the sixth time t6 to the seventh time t7. Hereinafter, the offset correction period may refer to at least one of the first offset correction period OC1 and the second offset correction period OC2.

[0184] The display driving circuit 100 may include a compensation capacitor CSp for stabilizing the source amplifier SA when the source amplifier SA amplifies the pixel voltage. In the first operation mode, the compensation capacitor CSp may stabilize the source amplifier SA. The compensation capacitor CSp may be connected between the first input terminal of the source amplifier SA and the second switching element sw2.

[0185] In one embodiment, in the second operation mode, the compensation capacitor CSp may store the offset of the source amplifier SA. In the offset correction period, the compensation capacitor CSp may store the offset of the source amplifier SA.

[0186] The display driving circuit 100 may include a fifth switching element sw5. The fifth switching element sw5 may be connected between the compensation capacitor CSp and the initialization power supply EVINT. The control logic may control the fifth switching element sw5. The control logic may output a control signal Ssw5 for controlling the fifth switching element sw5. The fifth switching element sw5 may operate in response to the control signal Ssw5.

[0187] In one embodiment, the control logic may control the first switch element sw1 and the fifth switch element sw5 so that the offset voltage of the source amplifier SA is stored in the compensation capacitor CSp. In the offset correction period, the control signal Ssw1 may have an effective level. The first switch element sw1 may be turned on based on the control signal Ssw1 of the effective level. Because the output terminal and the first input terminal of the source amplifier SA are connected through the first switch element sw1, a feedback loop may be formed. In the offset correction period, the control signal Ssw5 may have an effective level. The fifth switch element sw5 may be turned on based on the control signal Ssw5 of the effective level. The fifth switch element sw5 may be turned on to store the offset voltage in the compensation capacitor CSp.

[0188] In the first offset correction period OC1, the control signal Ssw1 and the control signal Ssw5 may have an effective level. At the third time t3, the control signal Ssw5 may transition from an inactive level to an active level. In the second offset correction period OC2, the control signal Ssw1 and the control signal Ssw5 may have an effective level. At the fifth time t5, the control signal Ssw5 may transition from an inactive level to an active level. At the fifth time t5, the control signal Ssw1 may transition from an inactive level to an active level.

[0189] In the first offset correction period OC1 and the second offset correction period OC2, the test switch element swt may be turned on in response to the control signal Sswt of the effective level, and the MUX switch element swm may be turned off in response to the control signal Sswm of the invalid level. The fifth transistor T5 and the sixth transistor T6 may be turned off in response to the light emitting control signal EM of the effective level. The second transistor T2 and the third transistor T3 may be turned on in response to the first scan signal s1 of the invalid level. The fourth transistor T4 may be turned on in response to the second scan signal s2 of the invalid level. The second switch element sw2 may be turned off in response to the control signal Ssw2 of the invalid level. The third switch element sw3 may be turned off in response to the control signal Ssw3 of the invalid level. The level switch element swl may be turned off in response to the control signal Sswl of the invalid level.

[0190] In the offset correction period, test data may be provided. In the first offset correction period OC1, the decoder DEC may receive the first test data DTC1. The first comparison voltage Vref1 of a level corresponding to the first test data DTC1 may be provided to the source amplifier SA. In the first offset correction period OC1, the first test data DTC1 may be provided to the decoder DEC, and the first comparison voltage Vref1 may be output as the decoder voltage Vd. The first comparison voltage Vref1 may be provided to the second input terminal of the source amplifier SA.

[0191] In the second offset correction period OC2, the decoder DEC may receive the second test data DTC2. A second comparison voltage Vref2 of a level corresponding to the second test data DTC2 may be provided to the source amplifier SA. In the second offset correction period OC2, the second test data DTC2 may be provided to the decoder DEC, and the second comparison voltage Vref2 may be output as the decoder voltage Vd. The second comparison voltage Vref2 may be provided to the second input terminal of the source amplifier SA.

[0192] Fig. 10B is a diagram for describing a comparison period after an offset correction period according to an embodiment. For the sake of brevity, redundant descriptions regarding the description given above will be omitted.

[0193] Reference Fig. 10B and Fig.11 During the comparison period, the pixel PXb and the display driving circuit 100 may be the same as that described above. FIG. 6A to FIG. 9 The pixel PXb and the display driving circuit described operate similarly. A first comparison period COM1 may be performed after the first offset correction period OC1. In the first comparison period COM1, the offset of the source amplifier SA stored in the first offset correction period OC1 may be removed. A second comparison period COM2 may be performed after the second offset correction period OC2. In the second comparison period COM2, the offset of the source amplifier SA stored in the second offset correction period OC2 may be removed.

[0194] In one embodiment, in the first comparison period COM1, the first switch element sw1 and the second switch element sw2 may be controlled. In the first comparison period COM1, the control signal Ssw1 may have an invalid level. At the fourth time t4, the control signal Ssw1 may be changed from the valid level to the invalid level. In the first comparison period COM1, the first switch element sw1 may be turned off based on the control signal Ssw1 of the invalid level. In the first comparison period COM1, the control signal Ssw2 may have an effective level. At the fourth time t4, the control signal Ssw2 may be changed from the invalid level to the effective level. In the first comparison period COM1, the second switch element sw2 may be turned on based on the control signal Ssw2 of the effective level. The sampling voltage Vs may be provided to the compensation capacitor CSp.

[0195] In the first comparison period COM1, the control signal Ssw5 may have an invalid level. At the fourth time t4, the control signal Ssw5 may be changed from the valid level to the invalid level. In the first comparison period COM1, the fifth switch element sw5 may be turned off based on the control signal Ssw5 of the invalid level. In the first comparison period COM1, since the offset voltage of the source amplifier SA stored in the compensation capacitor CSp is added to the sampling voltage Vs, even when there is an offset voltage of the source amplifier SA, the first comparison data obtained by removing the offset voltage of the source amplifier SA can be output.

[0196] In one embodiment, in the second comparison period COM2, the first switch element sw1 and the second switch element sw2 may be controlled. In the second comparison period COM2, the control signal Ssw1 may have an invalid level. At the sixth time t6, the control signal Ssw1 may be changed from the invalid level to the valid level. In the second comparison period COM2, the first switch element sw1 may be turned off based on the control signal Ssw1 of the invalid level. In the second comparison period COM2, the control signal Ssw2 may have an effective level. At the sixth time t6, the control signal Ssw2 may be changed from the invalid level to the effective level. In the second comparison period COM2, the second switch element sw2 may be turned on based on the control signal Ssw2 of the effective level. The sampling voltage Vs may be provided to the compensation capacitor CSp.

[0197] In the second comparison period COM2, the control signal Ssw5 may have an invalid level. At the sixth time t6, the control signal Ssw5 may be changed from the valid level to the invalid level. In the second comparison period COM2, the fifth switch element sw5 may be disconnected based on the control signal Ssw5 of the invalid level. In the second comparison period COM2, since the offset voltage of the source amplifier SA stored in the compensation capacitor CSp is added to the sampling voltage Vs, even when there is an offset voltage of the source amplifier SA, the second comparison data obtained by removing the offset voltage of the source amplifier SA can also be output.

[0198] Fig. 12A is a diagram for describing a light emitting reset period according to an embodiment. Fig. 12B is a diagram for describing a light emitting programming period according to an embodiment. Fig. 12C is a diagram for describing a light emission comparison period according to an embodiment. Fig.13 1 is a timing diagram showing a plurality of signals for controlling a pixel and a display driving circuit according to an embodiment. For the sake of brevity, redundant descriptions regarding the description given above will be omitted.

[0199] Reference Fig. 12A and Fig. 12B , the pixel PXb may include a fifth transistor T5. The fifth transistor T5 may operate in response to the light emission control signal EM. A gate electrode of the fifth transistor T5 may be connected to the light emission control line EN, a source electrode of the fifth transistor T5 may be connected to the first driving power source ELVDD, and a drain electrode of the fifth transistor T5 may be connected to the first transistor T1. The fifth transistor T5 may also be referred to as a light emission switching element. FIG. 12A to FIG. 12C Pixel PXb is shown to include six transistors. However, embodiments are not limited thereto, and in some embodiments, pixel PXb may include various numbers of transistors, and FIG. 12A to FIG. 12C The description can be applied to pixels PXb having various structures.

[0200] Figures 12A to 12C and Fig.13 An embodiment of determining whether an error has occurred in a light emitting switching element is shown. In a second operating mode, an error in a pixel PXb may be determined, and an error in a light emitting switching element may be determined. The second operating mode may include at least one of a reset period, a programming period, a comparison period, and an offset correction period for determining an error in the pixel PXb. The second operating mode may include at least one of a light emitting reset period, a light emitting programming period, and a light emitting comparison period for determining an error in the light emitting switching element. In the second operating mode, an error in the light emitting switching element may be determined after determining an error in the pixel PXb. However, the embodiments are not limited thereto, and in some embodiments, an error in the pixel PXb may be determined after determining an error in the light emitting switching element.

[0201] Reference Fig. 12A and Fig.13 , the second operation mode may include a light emitting reset period ERESET. The light emitting reset period ERESET may be from the first time t1 to the second time t2. The light emitting reset period ERESET may refer to a period in which the light emitting switch element is initialized. In the light emitting reset period ERESET, a first driving voltage for determining an error in the fifth transistor T5 may be applied to the fifth transistor T5. The test voltage Vtest may not be applied to the pixel PXb. The test voltage Vtest may not be applied to the pixel PXb through the data line DL.

[0202] In one embodiment, the control logic (e.g., Figure 1 The control logic 110 of the control logic 110 may not apply the test voltage Vtest to the pixel PXb through the data line DL. In the light emission reset period ERESET, the control signal Sswt and the control signal Sswm may have an invalid level. In the light emission reset period ERESET, the test switch element swt may be turned off, and the MUX switch element swm may be turned off, so that the test voltage Vtest may not be applied to the data line DL.

[0203] In the light emission reset period ERESET, the fifth transistor T5 may be turned on. The fifth transistor T5 may operate in response to the light emission control signal EM applied through the light emission control line EN. In the light emission reset period ERESET, the light emission control signal EM may have an invalid level. The fifth transistor T5 may be turned on in response to the light emission control signal EM of the invalid level. The fifth transistor T5 may be turned on so that the first driving voltage may be applied to the pixel PXb from the first driving power supply ELVDD.

[0204] In the emission reset period ERESET, the second transistor T2 may be turned on in response to the first scan signal s1 of the inactive level, and the third transistor T2 may be turned on in response to the first scan signal s1 of the inactive level. In the emission reset period ERESET, the sixth transistor T6 may be turned on in response to the emission control signal EM of the inactive level.

[0205] In the light emitting reset period ERESET, the initialization voltage Vint may be applied to the pixel PXb. The display driving circuit 100 may include a fourth switching element sw4 connected between the output terminal of the source amplifier SA and the sensing line SSL. The control logic may control the fourth switching element sw4. The control logic may output a control signal Ssw4 for controlling the fourth switching element sw4. The fourth switching element sw4 may operate in response to the control signal Ssw4.

[0206] In the emission reset period ERESET, the control signal Ssw1 may have an active level and the control signal Ssw2 may have an inactive level. The first switching element sw1 may be turned on based on the active level of the control signal Ssw1 and the second switching element sw2 may be turned off based on the inactive level of the control signal Ssw2.

[0207] In the light emission reset period ERESET, the fourth switch element sw4 may be turned on based on the control signal Ssw4 of the effective level. The control logic may turn on the first switch element sw1 and the fourth switch element sw4 to apply the initialization voltage Vint to the pixel PXb from the output terminal of the source amplifier SA through the fourth switch element sw4. The control logic may turn off the second switch element sw2 to not connect the first input terminal of the source amplifier SA to the sensing line SSL.

[0208] In the light emission reset period ERESET, in response to the second scan signal s2 of the invalid level, the fourth transistor T4 may be turned on, and the fourth transistor T4 may transmit the initialization voltage Vint provided from the source amplifier SA to the first node n1. The third switching element sw3 may be turned off based on the control signal Ssw3 of the invalid level. The level switching element sw1 may be turned off based on the control signal Sswl of the invalid level.

[0209] In the light emitting reset period ERESET, the decoder DEC may receive initialization data Dint. In the light emitting reset period ERESET, the initialization data Dint may be provided to the decoder DEC and the decoder voltage Vd may be output. The output voltage Vd corresponding to the initialization data Dint may be a preliminary initialization voltage Vpint, and the preliminary initialization voltage Vpint may be provided to the second input terminal of the source amplifier SA. The source amplifier SA may amplify the preliminary initialization voltage Vpint and output the initialization voltage Vint.

[0210] Fig. 12B is a diagram for describing the light emitting programming period according to an embodiment. Fig. 12A Redundant description of the given description.

[0211] Reference Fig. 12B and Fig.13 , the second operation mode may include a light emission programming period EPROGRAM. The light emission programming period EPROGRAM may be from the second time t2 to the third time t3. In the light emission programming period EPROGRAM, because the control signal Sswt and the control signal Sswm have an invalid level, the test switch element swt and the MUX switch element swm may maintain a disconnected state.

[0212] In the light emitting programming period EPROGRAM, because the first scan signal s1 has an invalid level, the second transistor T2 and the third transistor T3 may maintain a turned-on state. In the light emitting programming period EPROGRAM, because the light emitting control signal EM has an invalid level, the fifth transistor T5 and the sixth transistor T6 may maintain a turned-on state. In the light emitting programming period EPROGRAM, the control signal Ssw1 may have an effective level, and the control signal Ssw2 may have an invalid level. The first switching element sw1 may be in a turned-on state, and the second switching element sw2 may be in a turned-off state.

[0213] In the light emitting programming period EPROGRAM, the control signal Ssw4 may have an invalid level. At the second time t2, the control signal Ssw4 may be changed from the valid level to the invalid level. The fourth switch element sw4 may be turned on based on the control signal Ssw4 of the invalid level. In the light emitting programming period EPROGRAM, the control logic may turn off the fourth switch element sw4 so that the sampling voltage Vs of the pixel PXb can be output through the sensing line SSL.

[0214] In the light emitting programming period EPROGRAM, because the second scan signal s2 has an invalid level, the fourth transistor T4 may maintain a turned-on state. The fourth transistor T4 may provide the voltage of the first node n1 as a sampling voltage Vs through the sensing line SSL. For example, the sampling voltage Vs may be a difference between the first driving voltage ELVDD and the threshold voltage VTH of the first transistor T1. In the light emitting programming period EPROGRAM, the level switch element swl may maintain a turned-off state based on the control signal Sswl of the invalid level.

[0215] Fig. 12C is a diagram for describing a light emission comparison period according to an embodiment. For the sake of brevity, redundant descriptions regarding the description given above will be omitted.

[0216] Reference Fig. 12C and Fig.13 , the second operation mode may include a light emission comparison period ECOMPARISON. The light emission comparison period ECOMPARISON may be from the third time t3 to the fifth time t5. The light emission comparison period ECOMPARISON may include a first light emission comparison period ECOM1 and a second light emission comparison period ECOM2. The first light emission comparison period ECOM1 and the second light emission comparison period ECOM2 may respectively operate similarly to the pixel PXb and the display driving circuit 100 in the above-mentioned first comparison period and the second comparison period.

[0217] In the first light emitting comparison period ECOM1, the source amplifier SA may output first light emitting comparison data by comparing the sampling voltage Vs with the first comparison voltage Vref1. In the second light emitting comparison period ECOM2, the source amplifier SA may output second light emitting comparison data by comparing the sampling voltage Vs with the second comparison voltage Vref2. In the first light emitting comparison period ECOM1, the first light emitting comparison data may be provided to the level converter, and the first light emitting output data may be output. In the second light emitting comparison period ECOM2, the second light emitting comparison data may be provided to the level converter, and the second light emitting output data may be output.

[0218] In one embodiment, the display driving circuit 100 may determine whether an error has occurred in at least a portion of the pixel PXb including the light emitting switching element. In other words, the display driving circuit 100 may determine whether an error has occurred in the fifth transistor T5. The control logic may determine whether an error has occurred in the fifth transistor T5 based on the first light emitting comparison data and the second light emitting comparison data. Specifically, the control logic may receive the first light emitting output data and the second light emitting output data, and determine whether an error has occurred in the fifth transistor T5 based on the first light emitting output data and the second light emitting output data. In some embodiments, the control logic may be configured to output an error signal indicating whether an error has occurred in the fifth transistor T5. For example, in some embodiments, the error signal may be a flag. In some embodiments, an action may be taken based on the error signal to correct the transistor T5 in which an error has occurred. For example, the display panel 200 may be wired during manufacturing to perform a correction action for repairing or replacing the fifth transistor T5 of the pixel PXb. However, the embodiment is not limited to the control logic determining whether an error has occurred. However, the embodiment is not limited thereto, and in some embodiments, a test device outside the display device may receive the first light emitting output data and the second light emitting output data, and may determine whether an error has occurred in the portion of the pixel PXb including the fifth transistor T5 based on the first light emitting output data and the second light emitting output data. Since it is determined whether an error has occurred in at least a portion of the pixel PXb including the light emitting switching element, it may be accurately determined in detail whether an error has occurred in the pixel PXb.

[0219] Fig.14 is a diagram for describing a method by which a display driving circuit determines whether an error has occurred in a pixel according to an embodiment. Fig.14 A case where no error occurs in a pixel is shown. Fig.14 A method of determining whether an error has occurred in a pixel based on comparison data output in a comparison period is shown. However, Fig.14 The description of can also be similarly applied to a method of determining whether an error has occurred in a portion of a pixel including a light emitting switching element based on light emitting comparison data output in a light emitting comparison period.

[0220] In one embodiment, based on the comparison data dc, the control logic (eg, Figure 1 The control logic 110 of the control logic 110 may determine whether an error has occurred in each pixel PX. The first comparison data dc1 may be output in the first comparison period COM1, and the second comparison data dc2 may be output in the second comparison period COM2.

[0221] The source amplifier may output first comparison data dc1 and second comparison data dc2. In the first comparison period COM1, the source amplifier may receive a first comparison voltage Vref1 and a sampling voltage Vs. The first comparison voltage Vref1 may be input to the second input terminal of the source amplifier, and the sampling voltage Vs may be input to the first input terminal of the source amplifier.

[0222] In the first comparison period COM1, the source amplifier (eg, Figure 2 The source amplifier SA may compare the first comparison voltage Vref1 with the sampling voltage Vs and generate the first comparison data dc1. When the first comparison voltage Vref1 is lower than the sampling voltage Vs, the source amplifier may output the first comparison data dc1 of an invalid level (eg, a low level or a first level).

[0223] In the second comparison period COM2, the source amplifier may receive the second comparison voltage Vref2 and the sampling voltage Vs. The second comparison voltage Vref2 may be input to the second input terminal of the source amplifier, and the sampling voltage Vs may be input to the first input terminal of the source amplifier.

[0224] In the second comparison period COM2, the source amplifier may compare the second comparison voltage Vref2 with the sampling voltage Vs and generate second comparison data dc2. When the second comparison voltage Vref2 is higher than the sampling voltage Vs, the source amplifier may output the second comparison data dc2 of a valid level (eg, a high level or a second level).

[0225] The level converter may generate the first output data do1 by converting the level of the first comparison data dc1, and generate the second output data do2 by converting the level of the second comparison data dc2. For example, the level converter may generate the second output data do2 by lowering the level of the second comparison data dc2.

[0226] The control logic may determine whether an error has occurred in the pixel based on the first comparison data dc1 and the second comparison data dc2. The control logic may determine whether an error has occurred in the pixel based on the first output data do1 and the second output data do2. In one embodiment, when the logic level of the first output data do1 corresponds to a first logic level (e.g., a logic low level, a first level, or an invalid level) and the logic level of the second output data do2 corresponds to a second logic level (e.g., a logic high level, a second level, or an effective level), the control logic may determine that no error has occurred in the pixel. When the sampling voltage Vs is higher than the first comparison voltage Vref1 and lower than the second comparison voltage Vref2, the logic level of the first output data do1 may be the first logic level, and the logic level of the second output data do2 may be the second logic level. Therefore, when the logic level of the first output data do1 is the first logic level and the logic level of the second output data do2 is the second logic level, because the sampling voltage Vs is between the first comparison voltage Vref1 and the second comparison voltage Vref2, the control logic may determine that no error has occurred in the pixel.

[0227] Fig.15A is a diagram for describing a method by which a display driving circuit determines that an error has occurred in a pixel according to an embodiment. Fig.15A For the sake of brevity, the above reference will be omitted. Fig.14 Redundant description of the given description.

[0228] In the first comparison period COM1 , when the first comparison voltage Vref1 is lower than the sampling voltage Vs, the source amplifier may output the first comparison data dc1 of an invalid level (eg, a low level or a first level).

[0229] In the second comparison period COM2 , because the second comparison voltage Vref2 is lower than the sampling voltage Vs, the source amplifier may output the second comparison data dc2 of an invalid level (eg, a low level or a first level).

[0230] The level converter may generate the first output data do1 of an inactive level by converting the level of the first comparison data dc1 , and generate the second output data do2 of an inactive level by converting the level of the second comparison data dc2 .

[0231] In one embodiment, when the logic level of the first output data do1 corresponds to the first logic level and the logic level of the second output data do2 corresponds to the second logic level, the control logic may determine that no error has occurred in the pixel (ie, as described above with reference to FIG. 1 ). Fig.14Because the logic level of the first output data do1 corresponds to the first logic level and the logic level of the second output data do2 corresponds to the first logic level, the control logic may determine that an error has occurred in the pixel.

[0232] When the logic levels of the first output data do1 and the second output data do2 are the first logic level, the control logic may determine that an error has occurred in the pixel because the sampling voltage Vs is higher than the second comparison voltage Vref2 .

[0233] Fig. 15B is a diagram for describing a method by which a display driving circuit determines that an error has occurred in a pixel according to an embodiment. Fig.15A compared to, Fig. 15B A case where the first comparison data dc1 and the second comparison data dc2 have a valid level is shown. For the sake of brevity, redundant descriptions regarding the description given above will be omitted.

[0234] In the first comparison period COM1 , since the first comparison voltage Vref1 is higher than the sampling voltage Vs, the source amplifier may output the first comparison data dc1 of a valid level.

[0235] In the second comparison period COM2 , since the second comparison voltage Vref2 is higher than the sampling voltage Vs, the source amplifier may output the second comparison data dc2 of a valid level.

[0236] The level converter may generate first output data do1 of a valid level by converting a level of the first comparison data dc1 , and generate second output data do2 of a valid level by converting a level of the second comparison data dc2 .

[0237] In one embodiment, when the logic level of the first output data do1 corresponds to the first logic level and the logic level of the second output data do2 corresponds to the second logic level, the control logic may determine that no error has occurred in the pixel (ie, as described above with respect to Fig.14 Because the logic level of the second output data do2 corresponds to the second logic level and the logic level of the first output data do1 corresponds to the second logic level, the control logic may determine that an error has occurred in the pixel.

[0238] When each of the logic levels of the first output data do1 and the second output data do2 has the second logic level, the control logic may determine that an error has occurred in the pixel because the sampling voltage Vs is lower than the first comparison voltage Vref1 .

[0239] Fig.16 is a diagram illustrating a display device according to an embodiment. Fig.16The display device 1600 may be a device including a medium to large-sized display panel 1620 and may be applied to, for example, a television, a monitor, and the like.

[0240] Reference Fig.16 , the display device 1600 may include a source driver (SDIC) 1611 , a timing controller (TCON IC) 1612 , a gate driver (GDIC) 1613 , and a display panel 1620 .

[0241] The timing controller (TCON IC) 1612 may include one or more integrated circuits (ICs) or modules. The timing controller 1612 may communicate with a plurality of source driver ICs SDIC and a plurality of gate driver ICs GDIC through a provided interface.

[0242] The timing controller (TCON IC) 1612 may generate a control signal for controlling driving timings of the plurality of source driver ICs SDIC and the plurality of gate driver ICs GDIC, and provide the control signal to the plurality of source driver ICs SDIC and the plurality of gate driver ICs GDIC.

[0243] The source driver 1611 may include a plurality of source driver ICs SDIC, which may be mounted on a circuit film such as a tape carrier package (TCP), a chip on film (COF), or a flexible printed circuit (FPC) and may be attached to the display panel 1620 by a tape automated bonding (TAB) method, or may be mounted on a non-display area of ​​the display panel 1620 by a chip on glass (COG) method.

[0244] The gate driver 1613 may include a plurality of gate driver ICs GDIC, and the plurality of gate driver ICs GDIC may be mounted on a circuit film and attached to the display panel 1620 by a TAB method, or may be mounted on a non-display region of the display panel 1620 by a COG method. Alternatively, the gate driver 1613 may be directly formed on a lower substrate of the display panel 1620 by a gate driver in panel (GIP) method. The gate driver 1413 may be formed in a non-display region outside a pixel array forming pixels in the display panel 1620, and may be formed by the same TFT process as the pixels.

[0245] As mentioned above Figures 1 to 15BAs described, the display device 1600 may include a first switching element and a second switching element, and the first switching element and the second switching element are controlled so that the source amplifier outputs comparison data by comparing a sampling voltage input to the first input terminal through a sensing line with a comparison voltage input to the second input terminal. Therefore, the source amplifier may operate as a comparator to compare the sampling voltage with the comparison voltage, thereby reducing the cost required to determine whether an error has occurred in a pixel.

[0246] Although various embodiments have been particularly shown and described with reference to the drawings, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A display driving circuit for driving a display panel, the display panel comprising a data line, a sensing line, and pixels connected to the data line and the sensing line, the display driving circuit comprising: control logic to control the operation of the display driving circuit; A source amplifier, comprising a first input terminal, a second input terminal and an output terminal, the source amplifier amplifies a pixel voltage for displaying an image on the display panel, and provides the amplified pixel voltage to the pixel through a data line; A first switch element connected between the first input terminal and the output terminal; as well as a second switch element, the second switch element being connected between the first input terminal and the sensing line, The control logic controls the first switch element and the second switch element so that the source amplifier compares the sampling voltage input to the first input terminal through the sensing line with the comparison voltage input to the second input terminal, and outputs comparison data based on the comparison.

2. The display driving circuit according to claim 1, further comprising: A third switch element is connected between the initialization power supply and the sensing line, The control logic turns on the first switching element and the third switching element and turns off the second switching element in a reset period to apply an initialization voltage from an initialization power source to the pixel through the third switching element and the sensing line.

3. The display driving circuit according to claim 2, wherein: During the reset period, the control logic applies a test voltage to the pixel through the data line.

4. The display driving circuit according to claim 3, wherein: In a programming period after the reset period, the control logic turns off the third switching element so that the sampling voltage is output through the sensing line.

5. The display driving circuit according to claim 4, wherein: In a comparison period after the programming period, the control logic turns off the first switch element and turns on the second switch element, so that the source amplifier compares the sampling voltage input to the first input terminal of the source amplifier with the comparison voltage input to the second input terminal and outputs comparison data.

6. The display driving circuit according to claim 5, wherein: The comparison period includes a first comparison period and a second comparison period. The control logic applies a first comparison voltage to the second input terminal of the source amplifier in a first comparison period, and applies a second comparison voltage higher than the first comparison voltage to the second input terminal in a second comparison period, and The source amplifier compares the sampling voltage with the first comparison voltage in a first comparison period and outputs first comparison data based on the comparison, and compares the sampling voltage with the second comparison voltage in a second comparison period and outputs second comparison data based on the comparison.

7. The display driving circuit according to claim 6, wherein: The control logic determines whether an error has occurred in the pixel based on the first comparison data and the second comparison data.

8. The display driving circuit according to claim 1, further comprising: a fourth switch element connected between the sensing line and the output terminal, In the reset period, the control logic turns on the first switch element and the fourth switch element to apply the initialization voltage from the output terminal of the source amplifier to the pixel through the fourth switch element.

9. The display driving circuit according to claim 8, wherein: In the reset period, the control logic applies a test voltage to the pixel through the data line.

10. The display driving circuit according to claim 9, wherein: In the reset period, the control logic applies a preliminary initialization voltage to the second input terminal of the source amplifier so that the initialization voltage is output from the output terminal of the source amplifier.

11. The display driving circuit according to claim 9, wherein: In a programming period after the reset period, the control logic turns off the fourth switching element so that the sampling voltage of the pixel is output through the sensing line.

12. The display driving circuit according to claim 1, further comprising: a compensation capacitor to stabilize the source amplifier when the source amplifier amplifies the pixel voltage; as well as a fifth switching element connected between the compensation capacitor and the initialization power supply, In the offset correction period, the control logic controls the first switching element and the fifth switching element so that the offset voltage of the source amplifier is stored in the compensation capacitor.

13. The display driving circuit according to claim 12, wherein: In the offset correction period, the control logic turns on the first switching element to form a feedback loop connecting the first input terminal of the source amplifier to the output terminal of the source amplifier, and turns on the fifth switching element to store the offset voltage in the compensation capacitor.

14. The display driving circuit according to any one of claims 1 to 13, wherein: The pixel includes a light emitting switching element connected to a driving power source, and The control logic applies a driving voltage from a driving power source to the pixel through the light emitting switching element, and applies an initialization voltage to the pixel.

15. The display driving circuit according to any one of claims 1 to 13, further comprising: The level converter converts the level of the comparison data.

16. A display driving circuit for driving a display panel, the display panel comprising a plurality of data lines, a plurality of sensing lines, and a plurality of pixels connected to the plurality of data lines and the plurality of sensing lines, the display driving circuit comprising: A plurality of decoders, corresponding to the plurality of data lines respectively, each decoder converting pixel data of a corresponding data line and outputting a pixel voltage; a plurality of source amplifiers, corresponding to the plurality of decoders respectively, each source amplifier comprising a first input terminal, a second input terminal and an output terminal, and each source amplifier amplifies a corresponding pixel voltage and provides the amplified pixel voltage to a corresponding pixel through a corresponding data line; a plurality of first switch elements, corresponding to the plurality of source amplifiers respectively, each first switch element being connected between a first input terminal and an output terminal of a corresponding source amplifier; as well as A plurality of second switch elements, respectively corresponding to the plurality of source amplifiers, each second switch element being connected between a first input terminal of a corresponding source amplifier and a corresponding sensing line, Wherein, each of the plurality of source amplifiers is configured as: In a first operation mode, amplifying a corresponding pixel voltage to be output to a corresponding data line, In the second operation mode, based on operations of the first switching element and the second switching element, a sampling voltage input to the first input terminal through a corresponding sensing line is compared with a comparison voltage input to the second input terminal, and comparison data is output.

17. The display driving circuit according to claim 16, wherein: In the second operation mode, after each of the plurality of first switching elements is turned on and each of the plurality of second switching elements is turned off, each of the plurality of first switching elements is turned off and each of the plurality of second switching elements is turned on.

18. The display driving circuit according to claim 16, wherein: In the first operation mode, the corresponding pixel voltage is applied to the corresponding data line, and In the second operation mode, a corresponding test voltage is applied to each data line.

19. The display driving circuit according to claim 18, wherein: Each decoder outputs a first comparison voltage corresponding to the first test data and a second comparison voltage corresponding to the second test data, and When each of the plurality of first switching elements is turned off and each of the plurality of second switching elements is turned on, each of the plurality of source amplifiers compares the corresponding sampling voltage with the first comparison voltage and outputs first comparison data, and compares the corresponding sampling voltage with the second comparison voltage and outputs second comparison data.

20. A display device, comprising: A display panel including data lines, sensing lines, and pixels connected to the data lines and the sensing lines; as well as a display driving circuit, driving the display panel so that an image is displayed on the display panel, Wherein, the display driving circuit comprises: A source amplifier, comprising a first input terminal, a second input terminal and an output terminal, the source amplifier amplifies a pixel voltage for displaying an image on the display panel, and provides the amplified pixel voltage to the pixel through a data line; A first switch element connected between the first input terminal and the output terminal of the source amplifier; and A second switch element is connected between the first input terminal of the source amplifier and the sensing line, The source amplifier compares a sampling voltage input to a first input terminal of the source amplifier through a sensing line with a comparison voltage input to a second input terminal of the source amplifier based on operations of the first switching element and the second switching element, and outputs comparison data.

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