Array substrate, display device and driving method

Abstract

The present disclosure relates to the field of display, and discloses an array substrate, a display device, and a driving method. The array substrate comprises: each sub-pixel row defined by the intersection of multiple rows of gate lines and multiple columns of data lines comprises a pixel electrode and a transistor, the side of the pixel electrode extending along the gate line is larger than the side extending along the data line, two adjacent sub-pixel rows of the same color form a row unit, two shift registers are adjacently arranged or there are M-1 shift registers between the two shift registers, one register group corresponds to one row unit, the first shift register in the register group is connected to the first sub-pixel row in the corresponding row unit, and the second shift register is connected to the second sub-pixel row in the corresponding row unit. When the array substrate operates in a first mode, the clock signals on the clock signal lines connected to the same register group are the same, which effectively improves the display effect of the picture, reduces costs, and improves the charging rate of the array substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology and provides an array substrate, a display device, and a driving method. Background Art

[0002] Using a triple-gate pixel architecture can reduce the number of data lines by two-thirds, and accordingly, the number of data driver chips used can also be reduced by two-thirds, thereby reducing the cost of the display panel. DLG technology can double the refresh rate. However, under the triple-gate pixel architecture design, the colors of two adjacent sub-pixels connected to the same data line are different. In DLG mode, the problem of displaying multiple colors simultaneously can occur, resulting in abnormal color on the display screen. That is, in DLG mode with a doubled refresh rate, the sub-pixels will show two different colors within the corresponding display time. Summary of the Invention

[0003] The embodiments of the present disclosure provide an array substrate, a display device, and a driving method for improving the display effect of a picture, while reducing costs and increasing the charging rate of the array substrate.

[0004] The specific technical solutions provided by this disclosure are as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0006] A display area and a non-display area, wherein the display area includes a plurality of rows of gate lines and a plurality of columns of data lines, wherein the plurality of rows of gate lines and the plurality of columns of data lines intersect to define a plurality of sub-pixel rows, wherein the sub-pixel rows include pixel electrodes and transistors, and the sides of the pixel electrodes extending along the gate lines are larger than the sides extending along the data lines;

[0007] The non-display area includes a plurality of cascaded shift registers;

[0008] The display area includes a plurality of row groups repeatedly arranged along a column direction, each row group including: M sub-pixel rows of different colors arranged along the column direction, and sub-pixels in the same sub-pixel row having the same color;

[0009] Two sub-pixel rows of the same color in two adjacent row groups constitute a row unit;

[0010] The plurality of cascaded shift registers include a plurality of register groups, each register group includes two shift registers, the two shift registers are arranged adjacent to each other or there are M-1 shift registers between the two shift registers;

[0011] One register group corresponds to one row unit;

[0012] The first shift register in the register group is connected to the first sub-pixel row in the corresponding row unit, and the second shift register is connected to the second sub-pixel row in the corresponding row unit;

[0013] The array substrate further includes a plurality of clock signal lines, and each shift register is connected to a clock signal line;

[0014] When the array substrate operates in the first mode, the clock signals on the clock signal lines connected to the same register group are the same, and the clock signals on the clock signal lines connected to two adjacent register groups have a first phase difference (2H).

[0015] Optionally, the operating mode of the array substrate further includes a second mode;

[0016] When the array substrate operates in the second mode, clock signals on clock signal lines connected to the same register group have a second phase difference, and clock signals on clock signal lines connected to two adjacent register groups have a second phase difference.

[0017] Optionally, the first phase difference is twice the second phase difference.

[0018] Optionally, the width of the data signal loaded into the same row of units is 2H, where H is the charging time of a row of sub-pixels.

[0019] Optionally, each row group includes: a first color sub-pixel row, a second color sub-pixel row, and a third color sub-pixel row arranged along a column direction;

[0020] When the array substrate operates in the first mode, the timing of the clock signal corresponding to the shift register connected to the first color sub-pixel row is earlier than the timing of the clock signal corresponding to the shift register connected to the second color sub-pixel row, and the timing of the clock signal corresponding to the shift register connected to the second color sub-pixel row is earlier than the timing of the clock signal corresponding to the shift register connected to the third color sub-pixel row.

[0021] Optionally, the connection relationship between the shift register and the clock signal line is as follows:

[0022] The 12k-11th stage shift register is connected to the first clock signal line of the plurality of clock signal lines;

[0023] The 12k-10th stage shift register is connected to the second clock signal line among the multiple clock signal lines;

[0024] The 12k-9th stage shift register is connected to the third clock signal line among the multiple clock signal lines;

[0025] The 12k-8th stage shift register is connected to the fourth clock signal line of the plurality of clock signal lines;

[0026] The 12k-7th stage shift register is connected to the fifth clock signal line among the multiple clock signal lines;

[0027] The 12k-6th stage shift register is connected to the 6th clock signal line among the multiple clock signal lines;

[0028] The 12k-5 stage shift register is connected to the 7th clock signal line among the multiple clock signal lines;

[0029] The 12k-4 stage shift register is connected to the 8th clock signal line among the multiple clock signal lines;

[0030] The 12k-3 stage shift register is connected to the 9th clock signal line among the multiple clock signal lines;

[0031] The 12k-2 stage shift register is connected to the 10th clock signal line among the multiple clock signal lines;

[0032] The 12k-1 stage shift register is connected to the 11th clock signal line among the multiple clock signal lines;

[0033] The 12k-th stage shift register is connected to the 12th clock signal line among the multiple clock signal lines, where k is a positive integer.

[0034] Optionally, the array substrate includes at least two gate driving circuits, and the gate driving circuit includes a plurality of cascaded shift registers;

[0035] The input signal terminal of the first stage shift register is configured to be coupled to the frame start signal terminal;

[0036] In every adjacent six shift registers, the input signal end of the 6M-level shift register is configured to be coupled to the output end of the 6M-5-level shift register, and the reset signal end of the 6M-5-level shift register is configured to be coupled to the output end of the 6M+N-level shift register, where M is a positive integer and N is a positive integer.

[0037] Optionally, the array substrate further includes a first start signal line coupled to the frame start signal terminal;

[0038] The input signal terminals of the 1st-stage shift register to the 2M-stage shift register are connected to the first start signal line.

[0039] Optionally, the array substrate further includes a second start signal line and a third start signal line, the second start signal line is coupled to the first frame start signal terminal, and the third start signal line is coupled to the second frame start signal terminal;

[0040] The input signal end of the 1st stage shift register to the Mth stage shift register is connected to the second start signal line, and the input signal end of the Mth stage shift register to the 2Mth stage shift register is connected to the third start signal line.

[0041] Optionally, sub-pixels located in different rows and connected to the same data line are arranged on both sides of the same data line.

[0042] Optionally, sub-pixels located in different rows and connected to the same data line are arranged on the same side of the same data line.

[0043] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising: the above-mentioned array substrate.

[0044] In a third aspect, the present disclosure further provides a driving method, including:

[0045] In the first mode, the same clock signal is loaded onto the clock signal lines connected to the same register group, and clock signals with a first phase difference are loaded onto the clock signal lines connected to two adjacent register groups.

[0046] The beneficial effects of the present disclosure are as follows:

[0047] In summary, in an embodiment of the present disclosure, an array substrate, a display device, and a driving method are provided, wherein the array substrate comprises: a display area and a non-display area, the display area comprises a plurality of rows of gate lines and a plurality of columns of data lines, the plurality of rows of gate lines and the plurality of columns of data lines intersecting to define a plurality of sub-pixel rows, the sub-pixel rows comprising pixel electrodes and transistors, the sides of the pixel electrodes extending along the gate lines being larger than the sides extending along the data lines, the non-display area comprises a plurality of cascaded shift registers, the display area comprises a plurality of row groups repeatedly arranged along a column direction, each row group comprises: M sub-pixel rows of different colors arranged along a column direction, the sub-pixels in the same sub-pixel row having the same color, two sub-pixel rows of the same color in two adjacent row groups being a row unit, the plurality of cascaded shift registers comprising a plurality of register groups, each register group comprising two shift registers, the two shift registers being adjacently arranged or the two shift registers being spaced apart. There are M-1 shift registers between the registers, one register group corresponds to one row unit, the first shift register in the register group is connected to the first sub-pixel row in the corresponding row unit, and the second shift register is connected to the second sub-pixel row in the corresponding row unit. The array substrate also includes multiple clock signal lines, each shift register is connected to a clock signal line. When the array substrate works in the first mode, the clock signals on the clock signal lines connected to the same register group are the same, and the clock signals on the clock signal lines connected to two adjacent register groups have a first phase difference. The above-mentioned sub-pixel rows of the same color are connected in sequence by the same data line and driven by the same clock signal, which effectively improves the display effect of the picture, reduces the cost, and improves the charging rate of the array substrate.

[0048] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. The purposes and other advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0050] Figure 1 This is a schematic diagram of the connection of the array substrate in an embodiment of the present disclosure;

[0051] Figure 2 Schematic diagram of the first triple gate pixel architecture in an embodiment of the present disclosure;

[0052] Figure 3Schematic diagram of a second triple-gate pixel architecture in an embodiment of the present disclosure;

[0053] Figure 4 Schematic diagram of the connection relationship between the output of the shift register in the non-display area and each sub-pixel in the display area in the first embodiment of the present disclosure;

[0054] Figure 5 This is a schematic diagram of data signal input when the array substrate is in the first mode in the first embodiment of the present disclosure;

[0055] Figure 6 This is a schematic diagram of data signal input when the array substrate is in the second mode in the first embodiment of the present disclosure;

[0056] Figure 7 A connection diagram of the cascade relationship of the shift registers in the first embodiment of the present disclosure;

[0057] Figure 8 This is a schematic diagram of driving timing input when the array substrate is in the first mode in the first embodiment of the present disclosure;

[0058] Figure 9 This is a schematic diagram of driving timing input when the array substrate is in the second mode in the first embodiment of the present disclosure;

[0059] Figure 10 Schematic diagram of the connection relationship between the output of the shift register in the non-display area and each sub-pixel in the display area in the second embodiment of the present disclosure;

[0060] Figure 11 This is a schematic diagram of driving timing input when the array substrate is in the first mode in the second embodiment of the present disclosure;

[0061] Figure 12 This is a schematic diagram of driving timing input when the array substrate is in the second mode in the first embodiment of the present disclosure;

[0062] Figure 13 This is a schematic diagram of data signal input when the array substrate is in the first mode in the first embodiment of the present disclosure;

[0063] Figure 14 This is a schematic diagram of data signal input when the array substrate is in the second mode in the first embodiment of the present disclosure;

[0064] Figure 15 A connection diagram of a cascade relationship of shift registers in a second embodiment of the present disclosure;

[0065] Figure 16 This is a connection diagram of another cascade relationship of shift registers in the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the technical solutions of the present disclosure, but not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments described in this disclosure without making any creative efforts shall fall within the scope of protection of the technical solutions of the present disclosure.

[0067] The terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be practiced using orders other than those illustrated or described herein.

[0068] The preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0069] An array substrate proposed in the embodiment of the present disclosure, referring to Figure 1 As shown, it includes: a display area and a non-display area, the display area includes multiple rows of gate lines and multiple columns of data lines, the multiple rows of gate lines and the multiple columns of data lines cross to define multiple sub-pixel rows, the sub-pixel rows include pixel electrodes and transistors, and the side of the pixel electrode extending along the gate line is larger than the side of the data line extending.

[0070] First of all, it should be explained that the peripheral circuit of the array substrate usually includes a system-on-chip (SOC), a timing controller and a data driver chip. Of course, in actual applications, the implementation method of the SOC can be determined according to the needs of the actual application and is not limited here. The above-mentioned timing controller can store an overdrive relationship table, etc., and perform display control during the display process of the display panel. The number of the above-mentioned data driver chips is usually multiple, and each data driver chip is used to provide data voltages for the sub-pixels in the display area to achieve color display of the picture.

[0071] In the embodiment of the present application, the array substrate includes a display area and a non-display area. The display area primarily displays images through multiple sub-pixel rows. The display area includes multiple rows of gate lines and multiple columns of data lines. The multiple rows of gate lines and multiple columns of data lines intersect to define multiple sub-pixel rows, and each sub-pixel is controlled by the gate lines and data lines. The sub-pixel rows include pixel electrodes and transistors. During the display process, the gate lines control the conduction of the transistors through gate signals, and the data lines provide data signals to the pixel electrodes through the conductive transistors.

[0072] It should be noted that the array substrate in the embodiment of the present application has a triple-gate pixel architecture, and the side of the pixel electrode extending along the gate line is greater than the side extending along the data line, that is, the horizontal side length of the array substrate in the embodiment of the present application is greater than the vertical side length. It should be noted that when the pixel electrode is a plate-shaped electrode, the side of the pixel electrode extending along the gate line is greater than the side extending along the data line. When the pixel electrode has a structure with a slit and branch electrodes, the edge connection line of the pixel electrode composed of multiple branch electrodes serves as the side of the pixel electrode extending along the gate line.

[0073] The non-display area includes a plurality of cascaded shift registers GOA.

[0074] In an embodiment of the present application, optionally, multiple shift registers are evenly distributed on both sides of the display area, and the gate signals in the above-mentioned gate lines are provided by corresponding GOAs, or the shift registers are set on one side of the non-display area, which is not limited here.

[0075] The display area is described in detail below. The display area includes multiple row groups repeatedly arranged along the column direction. Each row group includes: M sub-pixel rows with different colors arranged along the column direction. The sub-pixels in the same sub-pixel row have the same color.

[0076] In the embodiment of the present application, the sub-pixels included in the display area are first divided into row groups. That is, in units of columns, a row of M sub-pixels with different red, green, and blue colors arranged along the column direction is called a group. The value of M is usually at least three. In the rows of sub-pixels including red, green, blue, and white, the minimum value of M is usually four. In the above row group, the sub-pixels in the same sub-pixel row have the same color, that is, at least three or four sub-pixel rows with different colors in a column constitute a row group.

[0077] Two sub-pixel rows of the same color in the two adjacent row groups constitute a row unit.

[0078] Considering that sub-pixels of different colors are arranged sequentially in a row group, in the embodiment of the present application, two sub-pixels of the same color are found in two adjacent row groups, and the above two sub-pixels are called a row unit.

[0079] Since the shift registers correspond to the sub-pixel rows one by one, the multiple cascaded shift registers include multiple register groups, each register group includes two shift registers, and the two shift registers are adjacently arranged or there are M-1 shift registers between the two shift registers.

[0080] One register group corresponds to one row unit.

[0081] The first shift register in the register group is connected to the first sub-pixel row in the corresponding row unit, and the second shift register is connected to the second sub-pixel row in the corresponding row unit.

[0082] In an embodiment of the present application, after two adjacent row groups are divided into a row unit, each shift register is also divided, that is, two shift registers are divided into a register group. In this way, one register group corresponds to one row unit, and each shift register in the register group corresponds to one sub-pixel row.

[0083] In order to achieve simultaneous charging of sub-pixels of the same color connected to the same data line, two schemes are provided in the embodiments of the present application: Scheme 1, two shift registers are arranged adjacent to each other, that is, the two adjacent shift registers are divided into a register group; there are M-1 shift registers between the two shift registers, that is, the two shift registers corresponding to two sub-pixel rows of the same color are divided into a register group.

[0084] In order to display the image normally, the array substrate further includes a plurality of clock signal lines. Each shift register is connected to one clock signal line, that is, the shift register is started under the driving control of the clock signal line.

[0085] When the array substrate operates in the first mode, the clock signals on the clock signal lines connected to the same register group are the same, and the clock signals on the clock signal lines connected to two adjacent register groups have a first phase difference.

[0086] It should be noted that the first mode described above is the DLG mode. In this first mode, the clock signals on the clock signal lines connected to the two shift registers within the same register group are identical. This ensures that the gate lines of the two shift registers within the same register group can simultaneously provide drive signals to the two sub-pixel rows of the same color included in the corresponding row unit. To ensure normal operation of the entire array substrate, the clock signals on the clock signal lines connected to the two adjacent register groups have a first phase difference. In this way, the two adjacent registers can time-share the drive signals to the two adjacent sub-pixel rows of different colors, thereby ensuring row-by-row driving of each sub-pixel row.

[0087] In addition, there are two ways to arrange the sub-pixels and the connected data lines in the embodiment of the present application. The first way is to refer to Figure 2 As shown, the sub-pixels in different rows connected to the same data line are arranged on both sides of the same data line. Figure 2 The three sub-pixels enclosed by the dotted lines from top to bottom may be sub-pixels corresponding to red, green, and blue, respectively. The sub-pixels in the same row correspond to the same color.

[0088] In the embodiment of the present application, sub-pixels located in different rows and the data lines connected thereto are arranged in a zigzag pattern, that is, sub-pixels located in different rows connected to the same data line are arranged on both sides of the same data line.

[0089] The second method see Figure 3 As shown, sub-pixels located in different rows and connected to the same data line are arranged on the same side of the same data line.

[0090] In the embodiment of the present application, sub-pixels located in different rows and the data lines connected thereto are arranged in a straight line, that is, sub-pixels located in different rows connected to the same data line are arranged on the same side of the same data line. Figure 2 In the second method, since the sub-pixels driven simultaneously are located on the same side of the same data line, the color display is more uniform and the display effect is better.

[0091] After introducing the basic structure of the array substrate in the embodiment of the present application, the following describes in detail the two solutions provided in the embodiment of the present application, such as Figure 4 As shown, in solution 1, two shift registers are set adjacent to each other, see Figure 10 As shown, there are M-1 shift registers between the two shift registers in Scheme 2. Both Scheme 1 and Scheme 2 can realize that two sub-pixels of the same color corresponding to the same register group are turned on and charged at the same time, that is, at the same moment, the gate line controls the two sub-pixel rows of the same color to be turned on at the same time and the same data signal is charged into the above two sub-pixels by the data line.

[0092] See Figure 4 As shown in FIG, the specific approach of the first solution is to change the connection relationship between the output of the shift register in the non-display area and each sub-pixel in the display area, so as to Figure 4 As shown, six sub-pixels including red, green and blue are arranged along the column direction. The first sub-pixel has the same color as the fourth sub-pixel, the second sub-pixel has the same color as the fifth sub-pixel, and the third sub-pixel has the same color as the sixth sub-pixel. The first sub-pixel and the fourth sub-pixel form a row unit, the second sub-pixel and the fifth sub-pixel form a row unit, and the third sub-pixel and the sixth sub-pixel form a row unit.

[0093] Correspondingly, in order to correspond to the row unit, the shift register connected to the first sub-pixel and the shift register connected to the fourth sub-pixel in the non-display area are a register group, the shift register connected to the second sub-pixel and the shift register connected to the fifth sub-pixel are a register group, and the shift register connected to the third sub-pixel and the shift register connected to the sixth sub-pixel are a register group. Each register group is connected as follows: Figure 4The lines shown are connected to the sub-pixel rows in the corresponding row units.

[0094] See Figure 5 As shown, it should be noted that, in the first mode of the first solution, the width of the data signal loaded into the same row of units is 2H, where H is the charging time of a row of sub-pixels. Figure 5 , Gout1 and Gout4 are opened at the same time as a group, and then Gout2 and Gout5, Gout3 and Gout6, and so on are opened in sequence, and the details are not repeated here.

[0095] During implementation, the width of the time for writing the data signal into the sub-pixel row is 2H. That is, the driving method at this time can increase the charging time of the pixel row, which is suitable for high-resolution products.

[0096] See Figure 6 As shown, it should be noted that, in the second mode of the first solution, the second mode generally refers to the non-DLG mode, and the width of the data signal loaded into a row of sub-pixels is 1H. Figure 6 The order in which the gate lines are opened is Gout1, Gout4, Gout2, Gout5, Gout3, and Gout6. The phase difference in the timing of opening adjacent gate lines is 1H, that is, Gout4 is opened 1H later than Gout1, Gout2 is opened 1H later than Gout4, and so on.

[0097] For details, see Figure 7 As shown, the operating mode of the array substrate also includes a second mode.

[0098] When the array substrate operates in the second mode, clock signals on clock signal lines connected to the same register group have a second phase difference, and clock signals on clock signal lines connected to two adjacent register groups have a second phase difference.

[0099] During implementation, when the array substrate operates in non-DLG mode, the clock signals on the clock signal lines connected to the two shift registers within the same register group have a second phase difference. This ensures that the gate lines of the two shift registers within the same register group can provide drive signals to the two sub-pixel rows of the same color included in the corresponding row unit at equal time intervals. To achieve a more uniform display across the entire array substrate, the clock signals on the clock signal lines connected to two adjacent register groups also have a second phase difference. This allows the two adjacent registers to provide drive signals to the two adjacent sub-pixel rows of different colors at equal time intervals, thereby ensuring row-by-row driving of each sub-pixel row.

[0100] Since the refresh rate is doubled in the DLG mode, the first phase difference is twice the second phase difference.

[0101] Still using two register groups including six sub-pixel rows of red, green and blue to explain, Figure 7 It can be seen that in the first scheme, the cascade relationship between the shift registers is: the cascade output signal Out_C of the first shift register is connected to the input terminal Input of the seventh shift register, and the cascade output signal Out_C of the second shift register is connected to the input terminal Input of the eighth shift register. In this scheme, a cascade output terminal Out_C and a gate signal output terminal Gout are optionally provided, wherein the cascade output terminal Out_C is used to transmit the cascade carry and reset signals, and the gate signal output terminal Gout is used to achieve electrical connection with the gate line of the display area and transmit the gate start signal. Of course, this scheme can also be provided with only the gate signal output terminal Gout, that is, the gate signal output terminal Gout is used to transmit the cascade carry and reset signals and transmit the display area gate line start signal. Figure 7 In this case, the cascade output of the GOA (GOAN) at stage N provides a signal to the input of GOAN+6, the cascade output of GOA N+8 provides a reset signal to GOAN, and so on for subsequent registers. At the same time, the output signals of the shift registers after the sixth shift register are connected to the reset terminal of the first shift register, the output signals of the shift registers after the seventh shift register are connected to the reset terminal of the second shift register, and so on.

[0102] For specific clock signals corresponding to each sub-pixel row in the first mode in the embodiment of the present application, see Figure 8 As shown, in the DLG mode, the clock signal corresponding to the sub-pixels in the next row of adjacent rows is 2H later than the clock signal corresponding to the sub-pixels in the previous row. Figure 8 During implementation, in DLG mode, no special adjustment of the clock signal is required. Only the correspondence between the output of the GOA and the gate line needs to be adjusted (i.e., CLK1 and CLK2 can be turned on at the same time, and the second GOA corresponding to CLK2 is electrically connected to the fourth gate line of the display panel) to realize the DLG function of triple gate, which ensures cost reduction and improves the charging rate of the display panel.

[0103] For specific clock signals corresponding to each sub-pixel row in the second mode in the embodiment of the present application, see Figure 9 As shown, in the DLG mode, the clock signal corresponding to the sub-pixels in the next row of adjacent rows is sequentially 1H later than the clock signal corresponding to the sub-pixels in the previous row.

[0104] After introducing Solution 1, Solution 2 in the embodiment of this application will be introduced in detail.

[0105] See Figure 10As shown in FIG, the difference from the first solution is that the connection relationship between the output of the shift register in the non-display area and each sub-pixel in the display area does not change. Figure 1 As shown, six sub-pixels including red, green and blue are arranged along the column direction. The first sub-pixel has the same color as the fourth sub-pixel, the second sub-pixel has the same color as the fifth sub-pixel, and the third sub-pixel has the same color as the sixth sub-pixel. The first sub-pixel and the fourth sub-pixel form a row unit, the second sub-pixel and the fifth sub-pixel form a row unit, and the third sub-pixel and the sixth sub-pixel form a row unit.

[0106] In the non-display area, the shift register connected to the first sub-pixel and the shift register connected to the fourth sub-pixel form a register group, the shift register connected to the second sub-pixel and the shift register connected to the fifth sub-pixel form a register group, and the shift register connected to the third sub-pixel and the shift register connected to the sixth sub-pixel form a register group. Each register group is connected as follows: Figure 10 The lines shown are connected to the sub-pixel rows in the corresponding row units, ie, the shift registers are connected to the sub-pixel rows in a one-to-one correspondence.

[0107] In the embodiment of the present application, the connection relationship between the shift register and the clock signal line is as follows:

[0108] The 12k-11th stage shift register is connected to the first clock signal line of the plurality of clock signal lines;

[0109] The 12k-10th stage shift register is connected to the second clock signal line among the multiple clock signal lines;

[0110] The 12k-9th stage shift register is connected to the third clock signal line among the multiple clock signal lines;

[0111] The 12k-8th stage shift register is connected to the fourth clock signal line of the plurality of clock signal lines;

[0112] The 12k-7th stage shift register is connected to the fifth clock signal line among the multiple clock signal lines;

[0113] The 12k-6th stage shift register is connected to the 6th clock signal line among the multiple clock signal lines;

[0114] The 12k-5 stage shift register is connected to the 7th clock signal line among the multiple clock signal lines;

[0115] The 12k-4 stage shift register is connected to the 8th clock signal line among the multiple clock signal lines;

[0116] The 12k-3 stage shift register is connected to the 9th clock signal line among the multiple clock signal lines;

[0117] The 12k-2 stage shift register is connected to the 10th clock signal line among the multiple clock signal lines;

[0118] The 12k-1 stage shift register is connected to the 11th clock signal line among the multiple clock signal lines;

[0119] The 12k-th stage shift register is connected to the 12th clock signal line among the multiple clock signal lines, where k is a positive integer.

[0120] During implementation, assuming that k is 1, the first-stage shift register in Solution 2 is connected to the first clock signal line among the multiple clock signal lines, the second-stage shift register is connected to the second clock signal line among the multiple clock signal lines, and so on.

[0121] See Figure 11 As shown, in the embodiment of the present application, Figure 10 The driving timing of CLK is changed based on the connection relationship of Figure 11 As shown, the case of 12 sub-pixel rows is used for illustration. The first row of sub-pixel rows has the same color as the fourth row of sub-pixel rows, and the timing of the clock signals corresponding to the shift registers connected to these two sub-pixel rows is the same. The second row of sub-pixel rows has the same color as the fifth row of sub-pixel rows, and the timing of the clock signals corresponding to the shift registers connected to these two sub-pixel rows is the same, and so on.

[0122] Specifically, each row group includes: a first color sub-pixel row, a second color sub-pixel row, and a third color sub-pixel row arranged along a column direction.

[0123] When the array substrate operates in the first mode, the timing of the clock signal corresponding to the shift register connected to the first color sub-pixel row is earlier than the timing of the clock signal corresponding to the shift register connected to the second color sub-pixel row, and the timing of the clock signal corresponding to the shift register connected to the second color sub-pixel row is earlier than the timing of the clock signal corresponding to the shift register connected to the third color sub-pixel row.

[0124] During implementation, when the array substrate operates in DLG mode, the timing of the clock signal corresponding to the shift register connected to the first color sub-pixel row, the clock signal corresponding to the shift register connected to the second color sub-pixel row, and the clock signal corresponding to the shift register connected to the third color sub-pixel row are successively increased by 2H.

[0125] It should be supplemented that the sub-pixel color of the first color sub-pixel row is red, the sub-pixel color of the second color sub-pixel row is green, and the sub-pixel color of the first color sub-pixel row is blue;

[0126] Alternatively, the sub-pixel color of the first color sub-pixel row is green, the sub-pixel color of the second color sub-pixel row is blue, and the sub-pixel color of the first color sub-pixel row is red;

[0127] Alternatively, the sub-pixel color of the first color sub-pixel row is blue, the sub-pixel color of the second color sub-pixel row is red, and the sub-pixel color of the first color sub-pixel row is green;

[0128] Alternatively, the sub-pixel color of the first color sub-pixel row is red, the sub-pixel color of the second color sub-pixel row is blue, and the sub-pixel color of the first color sub-pixel row is green;

[0129] Alternatively, the sub-pixel color of the first color sub-pixel row is green, the sub-pixel color of the second color sub-pixel row is red, and the sub-pixel color of the first color sub-pixel row is blue;

[0130] Alternatively, the sub-pixel color of the first color sub-pixel row is blue, the sub-pixel color of the second color sub-pixel row is green, and the sub-pixel color of the first color sub-pixel row is red.

[0131] That is, during implementation, the sub-pixel colors of the first color sub-pixel row, the sub-pixel colors of the second color sub-pixel row, and the sub-pixel colors of the third color sub-pixel row are random, and the colors corresponding to the sub-pixels are not specifically limited.

[0132] See Figure 12 As shown, during the implementation process, when the array substrate operates in non-DLG mode, the timing of the clock signal corresponding to the shift register connected to the first color sub-pixel row, the clock signal corresponding to the shift register connected to the second color sub-pixel row, and the clock signal corresponding to the shift register connected to the third color sub-pixel row are successively increased by 1H.

[0133] See Figure 13 As shown, in order to charge the same data signal to the data lines corresponding to two sub-pixel rows of the same color, in an embodiment of the present application, when the array substrate operates in DLG mode, the data signal on the data line is first input to the first row of sub-pixel rows corresponding to the first shift register and the fourth row of sub-pixel rows corresponding to the fourth shift register, then to the first row of sub-pixel rows corresponding to the second shift register and the fifth row of sub-pixel rows corresponding to the fifth shift register, and then to the third row of sub-pixel rows corresponding to the third shift register and the sixth row of sub-pixel rows corresponding to the sixth shift register. During implementation, the time width for writing a data signal to a sub-pixel row is 2H.

[0134] See Figure 14As shown, when the array substrate operates in the non-DLG mode, in order to charge the same data signal to the data lines corresponding to two sub-pixel rows of the same color, in an embodiment of the present application, the data signals on the data lines will be written in the order of arrangement of the shift registers, that is, the first shift register, the second shift register, the third shift register... In the order of writing, in the non-DLG mode, the time width for writing the data signal to the sub-pixel row corresponding to a shift register is 1H.

[0135] The following describes the cascade relationship of the shift registers in the second solution. Figure 15 As shown, the array substrate includes at least two gate driving circuits, and the gate driving circuit includes a plurality of cascaded shift registers.

[0136] The input signal terminals of the first six stages of shift registers are configured to be coupled to the frame start signal terminal, so as to provide an initial signal to the input terminal of the initial stage of the shift register.

[0137] In every adjacent six shift registers, the input signal end of the N+6th stage shift register is configured to be coupled to the cascade output end of the Nth stage shift register, and the reset signal end of the Nth stage shift register is configured to be coupled to the cascade output end of the N+6th stage shift register, where N is a positive integer.

[0138] During implementation, taking the change in the connection relationship between the shift register and the clock signal line as an example for explanation, the cascade relationship of the shift registers is as follows: the signal from the cascade output terminal of the first-stage shift register is provided to the input signal terminal of the seventh-stage shift register, the signal from the cascade output terminal of the second-stage shift register is provided to the input signal terminal of the eighth-stage shift register, and so on. The signal from the cascade output terminal of the seventh-stage shift register is provided to the reset signal terminal of the first-stage shift register, the signal from the cascade output terminal of the eighth-stage shift register is provided to the reset signal terminal of the second-stage shift register, and so on.

[0139] In some embodiments, the frame start signal terminal can be provided by a start signal line. Figure 15 As shown, the array substrate further includes a first start signal line, which is coupled to the frame start signal terminal.

[0140] The input signal terminals of the 1st-stage shift register to the 2M-stage shift register are connected to the first start signal line.

[0141] That is, the frame start signal ends of the 2M shift registers in the embodiment of the present application are all provided by the signal in the first start signal line.

[0142] In some other embodiments, the frame start signal terminal may be provided by two start signal lines. Figure 16As shown, in one embodiment, the array substrate further includes a second start signal line and a third start signal line, the second start signal line is coupled to the first frame start signal terminal, and the third start signal line is coupled to the second frame start signal terminal; Figure 16 The two start signal lines are STV1A and STV1B. The input signal ends of the first three levels of GOA are controlled by the start signal STV1A, and the input signal ends of the fourth, fifth and sixth levels of GOA are controlled by the start signal STV1B. This design can control the GOA to be half on and half off, which is used for PDF (pattern detect) function, etc.

[0143] The input signal end of the 1st stage shift register to the Mth stage shift register is connected to the second start signal line, and the input signal end of the Mth stage shift register to the 2Mth stage shift register is connected to the third start signal line.

[0144] That is, the frame start signal end of the first M shift registers in the embodiment of the present application is provided by the signal in the second start signal line, and the frame start signal end of the last M shift registers in the embodiment of the present application is provided by the signal in the third start signal line.

[0145] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, comprising: any one of the above array substrates.

[0146] In the embodiments of the present invention, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described in detail herein, nor should they be construed as limiting the present invention.

[0147] Based on the same inventive concept, an embodiment of the present disclosure provides a driving method, including:

[0148] In the first mode, the same clock signal is loaded onto the clock signal lines connected to the same register group, and clock signals with a first phase difference are loaded onto the clock signal lines connected to two adjacent register groups.

[0149] In an embodiment of the present application, when the array substrate operates in the DLG mode, in order to prevent interference in the color display of two sub-pixels of the same color corresponding to the same register group, the same clock signal is loaded on the clock signal line connected to the same register group. In the specific implementation process, in one way, the connection relationship between the output of the shift register in the non-display area and the sub-pixels in the display area is changed, so that the clock signals on the clock signal line connected to the two shift registers in the same register group can be the same, thereby ensuring that the gate lines of the two shift registers in the same register group can simultaneously provide driving signals to the two sub-pixel rows of the same color included in the corresponding row units; in another way, the connection relationship between the output of the shift register in the non-display area and the sub-pixels in the display area is not changed, and the driving timing of CLK is changed, so that the gate lines of the two shift registers in the same register group can simultaneously provide driving signals to the two sub-pixel rows of the same color included in the corresponding row units.

[0150] In summary, in the embodiments of the present disclosure, an array substrate, a display device, and a driving method are provided. The array substrate includes: a display area and a non-display area. The display area includes multiple rows of gate lines and multiple columns of data lines. The multiple rows of gate lines and the multiple columns of data lines intersect to define multiple sub-pixel rows. The sub-pixel rows include pixel electrodes and transistors. The sides of the pixel electrodes extending along the gate lines are larger than the sides extending along the data lines. The non-display area includes multiple cascaded shift registers. The display area includes multiple row groups repeatedly arranged along the column direction. Each row group includes: M sub-pixel rows of different colors arranged along the column direction. The sub-pixels in the same sub-pixel row have the same color. Two sub-pixel rows of the same color in two adjacent row groups are a row unit. The multiple cascaded shift registers include multiple register groups. Each register group includes two shift registers. The two shift registers are adjacently arranged or the two shift registers are arranged adjacently. There are M-1 shift registers between the registers, one register group corresponds to one row unit, the first shift register in the register group is connected to the first sub-pixel row in the corresponding row unit, and the second shift register is connected to the second sub-pixel row in the corresponding row unit. The array substrate also includes multiple clock signal lines, each shift register is connected to a clock signal line. When the array substrate works in the first mode, the clock signals on the clock signal lines connected to the same register group are the same, and the clock signals on the clock signal lines connected to two adjacent register groups have a first phase difference. The above-mentioned sub-pixel rows of the same color that are opened in sequence by the same data line are connected and driven by the same clock signal, which effectively improves the display effect of the picture, reduces the cost, and improves the charging rate of the array substrate.

[0151] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program product systems. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0152] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present disclosure. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0153] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0154] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0155] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. An array substrate, wherein: include: a display area and a non-display area, wherein the display area includes a plurality of rows of gate lines and a plurality of columns of data lines, wherein the plurality of rows of gate lines and the plurality of columns of data lines intersect to define a plurality of sub-pixel rows, wherein the sub-pixel rows include pixel electrodes and transistors, and the sides of the pixel electrodes extending along the gate lines are larger than the sides extending along the data lines; The non-display area includes a plurality of cascaded shift registers; The display area includes a plurality of row groups repeatedly arranged along a column direction, each row group including: M sub-pixel rows of different colors arranged along the column direction, and sub-pixels in the same sub-pixel row have the same color; Two sub-pixel rows of the same color in two adjacent row groups constitute a row unit; The plurality of cascaded shift registers include a plurality of register groups, each register group includes two shift registers, the two shift registers are arranged adjacent to each other or there is M-1 shift registers between the two shift registers; One register group corresponds to one row unit; The first shift register in the register group is connected to the first sub-pixel row in the corresponding row unit, and the second shift register is connected to the second sub-pixel row in the corresponding row unit; The array substrate further includes a plurality of clock signal lines, and each shift register is connected to a clock signal line; When the array substrate operates in the first mode, the clock signals on the clock signal lines connected to the same register group are the same, and the clock signals on the clock signal lines connected to two adjacent register groups have a first phase difference; The operating mode of the array substrate further includes a second mode; When the array substrate operates in the second mode, clock signals on the clock signal line connected to the same register group have a second phase difference, and clock signals on the clock signal lines connected to two adjacent register groups also have the second phase difference.

2. The array substrate according to claim 1, wherein: The first phase difference is twice the second phase difference.

3. The array substrate according to claim 1, wherein: The width of the data signal loaded into the same row unit is 2H, wherein H is the charging time of one row of sub-pixels.

4. The array substrate according to claim 1 or 2, wherein: Each row group includes: a first color sub-pixel row, a second color sub-pixel row, and a third color sub-pixel row arranged along a column direction; When the array substrate operates in the first mode, the timing of the clock signal corresponding to the shift register connected to the first color sub-pixel row is earlier than the timing of the clock signal corresponding to the shift register connected to the second color sub-pixel row, and the timing of the clock signal corresponding to the shift register connected to the second color sub-pixel row is earlier than the timing of the clock signal corresponding to the shift register connected to the third color sub-pixel row.

5. The array substrate according to claim 4, wherein: The connection relationship between the shift register and the clock signal line is as follows: The 12k-11th stage shift register is connected to the first clock signal line among the plurality of clock signal lines; The 12k-10th stage shift register is connected to the second clock signal line among the plurality of clock signal lines; The 12k-9th stage shift register is connected to the third clock signal line among the multiple clock signal lines; The 12k-8th stage shift register is connected to the fourth clock signal line among the plurality of clock signal lines; The 12k-7th stage shift register is connected to the fifth clock signal line among the plurality of clock signal lines; The 12k-6th stage shift register is connected to the sixth clock signal line among the plurality of clock signal lines; The 12k-5th stage shift register is connected to the 7th clock signal line among the multiple clock signal lines; The 12k-4th stage shift register is connected to the 8th clock signal line among the multiple clock signal lines; The 12k-3 stage shift register is connected to the 9th clock signal line among the multiple clock signal lines; The 12k-2 stage shift register is connected to the 10th clock signal line among the multiple clock signal lines; The 12k-1th stage shift register is connected to the 11th clock signal line among the plurality of clock signal lines; The 12k-th stage shift register is connected to the 12th clock signal line among the multiple clock signal lines, where k is a positive integer.

6. The array substrate according to claim 4, wherein: The array substrate includes at least two gate driving circuits, and the gate driving circuit includes the plurality of cascaded shift registers; The input signal terminal of the first stage shift register is configured to be coupled to the frame start signal terminal; In every adjacent six shift registers, the input signal end of the 6M-level shift register is configured to be coupled to the output end of the 6M-5-level shift register, and the reset signal end of the 6M-5-level shift register is configured to be coupled to the output end of the 6M+N-level shift register, where M is a positive integer and N is a positive integer.

7. The array substrate according to claim 6, wherein: The array substrate further includes a first start signal line coupled to the frame start signal terminal; The input signal terminals of the 1st-stage shift register to the 2M-stage shift register are connected to the first start signal line.

8. The array substrate according to claim 6, wherein: The array substrate further includes a second start signal line and a third start signal line, the second start signal line is coupled to the first frame start signal terminal, and the third start signal line is coupled to the second frame start signal terminal; The input signal ends of the 1st to Mth stage shift registers are connected to the second start signal line, and the input signal ends of the Mth to 2Mth stage shift registers are connected to the third start signal line.

9. The array substrate according to claim 6, wherein: The sub-pixels in different rows connected to the same data line are arranged on both sides of the same data line.

10. The array substrate according to claim 6, wherein: Sub-pixels located in different rows and connected to the same data line are arranged on the same side of the same data line.

11. A display device, wherein: The invention comprises the array substrate according to any one of claims 1 to 10.

12. A driving method applied to the array substrate according to any one of claims 1 to 10, wherein: include: In the first mode, the same clock signal is loaded onto the clock signal lines connected to the same register group, and clock signals with a first phase difference are loaded onto the clock signal lines connected to two adjacent register groups; In the second mode, a clock signal with a second phase difference is loaded onto the clock signal lines connected to the same register group, and a clock signal with the second phase difference is loaded onto the clock signal lines connected to two adjacent register groups.

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