Display device, display system, and driving method of display device

Abstract

A display device, a display system, and a driving method of the display device are provided. The display device includes: a pixel array including a pixel including a light emitting diode and a first transistor including a source terminal to which a pixel driving voltage is applied and a gate terminal to which a data signal is applied, the first transistor outputs a driving current generated based on a voltage difference between a gate terminal and a source terminal to the light emitting diode; and a display driver IC that generates a data signal based on the pixel driving voltage.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0084176 filed in the Korean Intellectual Property Office on June 29, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device, a display system, and a driving method of the display device. Background Art

[0003] In order to keep up with the development of information and communication technology, electronic devices such as automotive devices, smart phones and artificial reality systems include display devices for conveying information about images to users. As the amount of data that needs to be processed to provide information about images increases, high-performance display devices are required.

[0004] A display device may use various elements to generate and emit light. Such a display device may perform various operations to improve the quality of an image to be displayed by the display device. Summary of the invention

[0005] The present disclosure attempts to disclose a display device, a display system, and a driving method of the display device that are capable of displaying a brightness level corresponding to a grayscale level in order to prevent an image to be displayed from being changed according to a change in a power supply voltage supplied to a pixel.

[0006] In general, aspects of the subject matter described in this specification can be implemented in a display device, comprising: a pixel array, including pixels, the pixels including light-emitting diodes and a first transistor, the first transistor including: a source terminal, a pixel driving voltage is applied to the source terminal, and a gate terminal, a data signal is applied to the gate terminal, and the first transistor outputs a driving current generated based on a voltage difference between the gate terminal and the source terminal to the light-emitting diode, and a display driver IC, which generates a data signal based on the pixel driving voltage.

[0007] Another general aspect can be implemented in a device comprising: a power supply that supplies a pixel driving voltage and a circuit driving voltage, a processor that generates first image data and second image data, a first display device comprising: a first display driver IC that generates a first data signal based on the first image data, the pixel driving voltage and the circuit driving voltage, and a first pixel array that displays a first image to one of two eyes based on the pixel driving voltage and the first data signal, and a second display device comprising: a second display driver IC that generates a second data signal based on the second image data, the pixel driving voltage and the circuit driving voltage, and a second pixel array that displays a second image to the other of the two eyes based on the pixel driving voltage and the second data signal.

[0008] Another general aspect can be implemented in a driving method of a display device, which includes: applying an input voltage to a display driver IC; and applying a pixel driving voltage to the display driver IC and a display panel; a step of generating a data signal based on the input voltage and the pixel driving voltage by the display driver IC; and a step of displaying an image based on the data signal and the pixel driving voltage by the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic block diagram of an example of a display device.

[0010] Figure 2 yes Figure 1 A block diagram of an example of a reference voltage generator for a display device.

[0011] Figure 3 yes Figure 1 A circuit diagram of an example of a gamma voltage generator of a display device.

[0012] Figure 4 is a block diagram for explaining the operation of an example of a display panel.

[0013] Figure 5 is a schematic circuit diagram of an example of a pixel.

[0014] Figure 6 , Figure 7 , Figure 8 and Fig. 9 is a block diagram for explaining an example of the operation of the display system.

[0015] Fig.10 is a flowchart of an example of a method for driving a display device.

[0016] Fig.11 is a graph for explaining an example of the operation of the display device.

[0017] Fig.12 is a graph for explaining an example of the operation of the display device.

[0018] Fig.13 is a block diagram for explaining an example of a semiconductor system.

[0019] Fig.14 is a block diagram for explaining an example of a display system. DETAILED DESCRIPTION

[0020] In the following detailed description, only specific examples of the present disclosure are shown and described by way of illustration. As those skilled in the art will appreciate, the described examples can be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0021] Therefore, the drawings and descriptions are to be considered as illustrative and non-restrictive in nature. Throughout the specification, the same reference numerals represent the same elements. In the flow charts described with reference to the drawings, the order of the operations may be changed, and some operations may be combined, and the operations may be divided, and some operations may not be performed.

[0022] In addition, unless an explicit expression (such as "one" or "single") is used, an expression written in the singular may be understood as a singular form or a plural form. Terms including ordinal numbers (such as first and second) are used to describe various constituent elements, but the constituent elements are not limited by the terms. The terms are only used to distinguish one constituent element from other constituent elements.

[0023] Figure 1 is a schematic block diagram of a display device.

[0024] Reference Figure 1 , the display device 10 may include a timing controller 110, a gate driver 120, a reference voltage generator 130, a gamma voltage generator 140, a source driver 150, a display panel 160, a first power source (POWER 1) 180, and a second power source (POWER 2) 182. The timing controller 110, the gate driver 120, the reference voltage generator 130, the gamma voltage generator 140, and the source driver 150 may also be referred to as a display driver integrated circuit (IC). The gate driver 120 and the gate line GL may also be referred to as a scan driver and a scan line, respectively, and the source driver 150 and the source line SL may also be referred to as a data driver and a data line, respectively.

[0025] In some embodiments, Figure 1 As shown in , the reference voltage generator 130 and the gamma voltage generator 140 may be implemented as independent driving devices outside the source driver 150. In some embodiments, the reference voltage generator 130 and the gamma voltage generator 140 may be implemented inside the source driver 150. In some embodiments, the reference voltage generator 130 may be implemented inside the first power supply 180.

[0026] The timing controller 110 may receive an input image signal DATA and an input control signal CONT from an image source such as an external graphics device. The input control signal CONT may be a signal for controlling the display of the input image signal DATA and includes a main clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, etc.

[0027] The input image signal DATA may include brightness information about the plurality of pixels (PX) 170 of the display panel 160, and the brightness may have a predetermined number of gray levels (eg, 1024 (=2 10 )、256(=2 8 ) or 64(=2 6 ) gray levels). The display panel 160 may receive a gate signal from the gate driver 120 through a plurality of gate lines GL in order to display an image. The gate signal may be composed of a combination of a scan-on voltage for allowing a data signal to be applied to the pixel 170 and a scan-off voltage for prohibiting the application of the data signal. The vertical synchronization signal of the input control signal CONT may indicate a start field of a frame of an image to which a scan-on voltage is to be applied, and the horizontal synchronization signal may indicate a start portion of a gate line GL of the display panel 160 to which a scan-on voltage is to be applied. One cycle of the vertical synchronization signal is a frame cycle, and one cycle of the horizontal synchronization signal and the data enable signal is a horizontal cycle. One frame cycle may include a plurality of horizontal cycles.

[0028] The timing controller 110 may generate control signals CTRL1, CTRL2, and CTRL3 based on the input image signal DATA and the input control signal CONT. The timing controller 110 may control the reference voltage generator 130, the source driver 150, and the gate driver 120 using the control signals CTRL1, CTRL2, and CTRL3.

[0029] The reference voltage generator 130 may receive a control signal CTRL1 from the timing controller 110. In addition, the reference voltage generator 130 may receive a first pixel driving voltage PVDD from a first power supply 180, and an input voltage (e.g., a circuit driving voltage) VIN from a second power supply 182. The first power supply 180 and the second power supply 182 are shown as separate integrated circuits; however, in some embodiments, the first power supply 180 and the second power supply 182 may be implemented as one power module so as to be able to output the first pixel driving voltage PVDD and the input voltage VIN. In addition, Figure 1 , it is shown that the first power supply 180 outputs the input voltage VIN and the first pixel driving voltage PVDD to the reference voltage generator 130; however, the present disclosure is not necessarily limited to this, and a direct current (DC) to DC converter, etc. may be implemented to output at least one of the input voltage VIN and the first pixel driving voltage PVDD to the reference voltage generator 130.

[0030] The reference voltage generator 130 may generate a maximum gamma voltage VG_TOP and a minimum gamma voltage VG_BOT using an input voltage VIN and a first pixel driving voltage PVDD in response to a control signal CTRL1. The reference voltage generator 130 may include a resistor string, a decoder, a gamma amplifier, etc., so as to generate a maximum gamma voltage VG_TOP and a minimum gamma voltage VG_BOT. The maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT may be voltages for generating a plurality of gamma voltages VG, which are used to determine the brightness level of each pixel of the display panel 160. The reference voltage generator 130 may output the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT to the gamma voltage generator 140. The gamma voltage generator 140 may generate a plurality of gamma voltages VG based on the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT. For example, the gamma voltage generator 140 may include a resistor string and output a plurality of gamma voltages VG from the resistor string.

[0031] The timing controller 110 may output a control signal CTRL2 to the source driver 150 based on the input image signal DATA. The control signal CTRL2 may include image data satisfying an operating condition of the display panel 160.

[0032] The source driver 150 may generate data signals regarding image data using a plurality of gamma voltages VG in response to a control signal CTRL2 and provide the data signals to the display panel 160 through a plurality of source lines SL. The source driver 150 may include a decoder and a source amplifier for generating data signals from the plurality of gamma voltages VG.

[0033] The display panel 160 may receive a first pixel driving voltage PVDD and a second pixel driving voltage PVSS from the first power supply 180 and display an image according to a plurality of data signals. The first pixel driving voltage PVDD and the second pixel driving voltage PVSS may be voltages for driving the plurality of pixels 170. The first pixel driving voltage PVDD may be higher than the second pixel driving voltage PVSS. In some embodiments, the second pixel driving voltage PVSS may be a ground voltage.

[0034] The display panel 160 may include a plurality of pixels 170. The display panel 160 may be a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an inorganic light emitting diode (ILED) display, a micro light emitting diode (μLED) display, an active matrix OLED display (AMOLED), a transparent OLED (TOLED) display, or a combination thereof. The display panel 160 may be connected to the gate driver 120 through a plurality of gate lines GL, and may be connected to the source driver 150 through a plurality of source lines SL. In this case, the number of source lines SL may be p, and the number of gate lines GL may be q. p and q may be integers greater than 1. Since each of the plurality of pixels 170 is connected to a corresponding gate line of the plurality of gate lines GL and a corresponding source line of the plurality of source lines SL, the display panel 160 may include p×q pixels 170. The display panel 160 may include a conductive line for delivering a first pixel driving voltage PVDD to the plurality of pixels 170.

[0035] The gate driver 120 may provide a gate signal to the display panel 160 through a plurality of gate lines GL in response to a control signal CTRL3. Each gate signal may be composed of a combination of a scan-on voltage and a scan-off voltage. The control signal CTRL3 may include a scan start signal, a clock signal, etc. The scan start signal may be a signal that causes a first gate signal for displaying an image of one frame to be generated. The clock signal may be a synchronization signal for sequentially applying a gate signal to a plurality of gate lines GL.

[0036] Typically, when noise (e.g., ripple) occurs in the first pixel driving voltage PVDD, a data signal to be provided to the pixel 170 is generated based on the input voltage VIN. Therefore, even if some pixels 170 receive data signals corresponding to the same grayscale, one or more driving transistors of the pixel operate differently due to the difference between the gate voltage and the source voltage (or drain voltage). Therefore, although some pixels 170 receive data signals corresponding to the same grayscale, the current flowing in the light-emitting element of the pixel depends on the change of the first pixel driving voltage PVDD. Therefore, although some pixels 170 receive data signals corresponding to the same grayscale, the pixels emit light with different brightness levels.

[0037] To solve this problem, the reference voltage generator 130 may also receive the first pixel driving voltage PVDD (input to the display panel 160), and use the input voltage VIN and the first pixel driving voltage PVDD to generate the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT. Therefore, when the first pixel driving voltage PVDD is changed, the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT may also be changed according to the change of the first pixel driving voltage PVDD. Similarly, since the gamma voltage generator 140 generates a plurality of gamma voltages VG based on the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT, and the source driver 150 passes the data signal to the pixel 170 based on the plurality of gamma voltages VG, when the first pixel driving voltage PVDD is changed, the plurality of gamma voltages VG and the data signal generated from the plurality of gamma voltages VG may also be changed. In other words, since the data signal to be input to the pixel 170 is reflected in the voltage change occurring in the first pixel driving voltage PVDD, when some pixels 170 receive the data signal corresponding to the same gray level, the difference between the gate voltage and the source voltage (or drain voltage) of the driving transistor of the pixel can be substantially constant. Therefore, even if the first pixel driving voltage PVDD changes, the current flowing in the light emitting element of the pixel 170 receiving the data signal corresponding to the same gray level is constant. As a result, the pixels 170 receiving the data signal corresponding to the same gray level emit light having substantially the same brightness level, whereby the display panel 160 can display a high-quality image.

[0038] Figure 2 yes Figure 1 A block diagram of a reference voltage generator of a display device 10, Figure 3 is a circuit diagram of a gamma voltage generator.

[0039] Reference Figure 2 , the reference voltage generator 130 may include a voltage generator (VGEN) 131 , a first reference voltage generator ( RVGEN1 ) 132 , and a second reference voltage generator ( RVGEN2 ) 133 .

[0040] The voltage generator 131 may generate a voltage (e.g., an initial voltage) VOGN based on an input voltage VIN and a first pixel driving voltage PVDD. For example, the voltage generator 131 may include at least an amplifier, a resistor string, a decoder, and other suitable components for generating the voltage VOGN. Here, the magnitude of the voltage VOGN may be equal to or greater than the magnitude of the first pixel driving voltage PVDD. In addition, the magnitude of the voltage VOGN may be equal to or less than the magnitude of the input voltage VIN. In other words, the voltage generator 131 may generate a voltage VOGN between the first pixel driving voltage PVDD and the input voltage VIN. The voltage generator 131 may output the voltage VOGN by changing the resistance value of the resistor string or causing the decoder to select a voltage in response to a control signal CTRL1. The decoder may be connected to the resistor string and select a voltage from a plurality of voltages of the resistor string in response to the control signal CTRL1. For example, the voltage generator 131 may be a bandgap reference (BRG) circuit that outputs a constant voltage regardless of changes in the external environment (such as, temperature).

[0041] The first reference voltage generator 132 may generate a maximum gamma voltage VG_TOP based on the voltage VOGN, the input voltage VIN, and the first pixel driving voltage PVDD. For example, the first reference voltage generator 132 may include a first input terminal receiving the voltage VOGN, a second input terminal receiving the input voltage VIN, a third input terminal receiving the first pixel driving voltage PVDD, and an output terminal outputting the maximum gamma voltage VG_TOP.

[0042] The first reference voltage generator 132 may include an amplifier, a transistor, a resistor string, a buffer, etc. The first reference voltage generator 132 may turn off the transistor or change the resistance value of the resistor string in response to the control signal CTRL1 to generate the maximum gamma voltage VG_TOP. The transistor may receive the control signal CTRL1 through the gate terminal to be turned on.

[0043] The second reference voltage generator 133 may generate the minimum gamma voltage VG_BOT based on the voltage VOGN, the first pixel driving voltage PVDD, and the driving reference voltage GVSS. In some embodiments, the driving reference voltage GVSS may be used as the ground voltage GVSS.

[0044] In some embodiments, the driving reference voltage GVSS may be equal to the second pixel driving voltage PVSS. The structure of the second reference voltage generator 133 may be the same as that of the first reference voltage generator 132. For example, the second reference voltage generator 133 may include a fourth input terminal receiving the voltage VOGN, a fifth input terminal receiving the first pixel driving voltage PVDD, a sixth input terminal receiving the driving reference voltage GVSS, and an output terminal outputting the minimum gamma voltage VG_BOT. The fourth to sixth input terminals of the second reference voltage generator 133 correspond to the first to third input terminals of the first reference voltage generator 132, respectively.

[0045] The second reference voltage generator 133 may include an amplifier, a transistor, a resistor string, a buffer, etc. The second reference voltage generator 133 may turn off the transistor or change the resistance value of the resistor string in response to the control signal CTRL1 to generate the minimum gamma voltage VG_BOT. The transistor may receive the control signal CTRL1 through the gate terminal to be turned on.

[0046] The first reference voltage generator 132 may output the maximum gamma voltage VG_TOP to the gamma voltage generator 140, and the second reference voltage generator 133 may output the minimum gamma voltage VG_BOT to the gamma voltage generator 140. For example, the first reference voltage generator 132 may output the maximum gamma voltage VG_TOP to one of the input terminals of the gamma voltage generator 140, and the second reference voltage generator 133 may output the minimum gamma voltage VG_BOT to the other input terminal of the gamma voltage generator 140.

[0047] The gamma voltage generator 140 may generate a plurality of gamma voltages VG associated with a plurality of gray levels based on a maximum gamma voltage VG_TOP and a minimum gamma voltage VG_BOT, and output the gamma voltages to the source driver 150. For example, the gamma voltage generator 140 may generate a plurality of gamma voltages VG by dividing a voltage between the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT. The maximum gamma voltage VG_TOP may be the highest voltage among the plurality of gamma voltages VG, and the minimum gamma voltage VG_BOT may be the lowest voltage among the plurality of gamma voltages VG. In some embodiments, the plurality of gamma voltages VG may not include the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT.

[0048] Refer to Figure 3, the gamma voltage generator 140 may include a plurality of resistors R0 to RN (wherein N is an integer greater than 1). The plurality of resistors R0 to RN may be connected in series to form a resistor string. The gamma voltage generator 140 may divide the voltage between the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT to generate the first gamma voltage VG_1 to the Nth gamma voltage VG_N. The gamma voltage generator 140 may generate the first gamma voltage VG_1 to the Nth gamma voltage VG_N by dividing the voltage between the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT via the plurality of resistors R0 to RN, and output the first gamma voltage to the Nth gamma voltage together with the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT as a plurality of gamma voltages VG. For example, the resistor string may generate a plurality of gamma voltages VG by receiving the maximum gamma voltage VG_TOP at the first end and the minimum gamma voltage VG_BOT at the second end.

[0049] Figure 4 is a block diagram for explaining the operation of an example of a display panel, and Figure 5 is a schematic circuit diagram of an example of a pixel.

[0050] Reference Figure 4 , the display panel 160 may include a pixel array in which a plurality of pixels (PX) are arranged. The plurality of pixels (PX) may be connected to the gate driver 120 and the source driver 150 through a plurality of gate lines GL1 to GLh and a plurality of source lines SLj to SLj+8, respectively. Figure 4 In the figure, for ease of explanation, some gate lines and some source lines are shown, and a portion of the display panel 160 in which these gate lines and source lines are connected is shown. The plurality of gate lines GL1 to GLh may include a first gate line GL1, a kth gate line GLk to a (k+5)th gate line GLk+5 (where k is an integer greater than 1), an ith gate line GLi to a (i+3)th gate line GLi+3 (where i is an integer greater than 6), and an hth gate line GLh (where h is an integer greater than 9). The plurality of source lines SLj to SLj+8 may include a jth source line SLj to a (j+8)th source line SLj+8 (where j is an integer greater than 0).

[0051] The gate driver 120 may receive a first control signal (e.g., CTRL3 described above) from the timing controller, and drive the plurality of gate lines GL1 to GLh in response to the first control signal. In some embodiments, the first control signal may include information about the gate lines, and the gate driver 120 may output different gate signals to the plurality of gate lines GL1 to GLh in response to the first control signal.

[0052] The source driver 150 may receive a second control signal (e.g., CTRL2 described above) from the timing controller, and drive the plurality of source lines SLj to SLj+8 in response to the second control signal. The source driver 150 may generate data signals to be output to the plurality of source lines SLj to SLj+8 based on the plurality of gamma voltages VG. For example, the source driver 150 may include an amplifier, a switch, etc. In some embodiments, the second control signal may include information about the source line, and the source driver 150 may output different data signals to the plurality of source lines SLj to SLj+8 in response to the second control signal.

[0053] A plurality of pixels (PX) may display an image based on a gate signal input through a plurality of gate lines GL1 to GLh, a data signal input through a plurality of source lines SLj to SLj+8, a first pixel driving voltage PVDD, and a second pixel driving voltage PVSS. In this case, since the data signal input through a plurality of source lines SLj to SLj+8 is generated based on the first pixel driving voltage PVDD, even if the first pixel driving voltage PVDD changes, the plurality of pixels (PX) may emit light having a constant brightness level. In other words, a constant current flows in the light emitting diodes of the plurality of pixels (PX), and thus the display panel 160 displays a stable image.

[0054] Reference Figure 5 , the pixel 200 may include a transistor 210, a transistor 220, a capacitor 230, and a light emitting diode 240. The light emitting diode 240 may operate based on a current IED flowing according to operations of the transistor 210, the transistor 220, and the capacitor 230.

[0055] The transistor 210 may be connected to a source line SLp connected to a source driver at a node N1, and to a gate line GLq connected to a gate driver at a node N2. The source terminal of the transistor 210 may be connected to the source line SLp, the gate terminal may be connected to the gate line GLq, and the drain terminal may be connected to the gate terminal of the transistor 220. The source line SLp and the gate line GLq may represent any source line (e.g., the pth source line) among a plurality of source lines and any gate line (e.g., the qth gate line) among a plurality of gate lines, respectively. The transistor 210 may receive a voltage VSLp as a data signal from the source line SLp through the node N1, and receive a voltage VGLq as a scan-on voltage from the gate line GLq through the node N2. The transistor 210 may be connected to the gate of the transistor 220 at a node N3. The transistor 210 may be turned on in response to the voltage VGLq, thereby transmitting the voltage VSLp to the transistor 220.

[0056] One of both ends of the capacitor 230 may be connected to the node N3, and the other end may be connected to the node N4. The capacitor 230 may be charged based on the voltage difference between the node N3 and the node N4. The transistor 220 may operate using the voltage of the charged capacitor 230.

[0057] The transistor 220 may receive a voltage VSLp from a node N3 through a gate terminal. The transistor 220 may receive a first pixel driving voltage PVDD from a node N4 through a source terminal. A current IED generated based on the difference between a voltage VSLp of a node N3 and a voltage of a node N4 (e.g., a first pixel driving voltage PVDD) may flow from a drain terminal of the transistor 220 to the light emitting diode 240. The light emitting diode 240 may be connected to the transistor 220 at a node N5 as one end of the light emitting diode, and receive the current IED, and emit light based on the current IED. A second pixel driving voltage PVSS may be applied to the other end of the light emitting diode 240. The second pixel driving voltage PVSS may be a ground voltage. In this case, even if the first pixel driving voltage PVDD is changed, the voltage VSLp also changes in response to the changed voltage of the first pixel driving voltage PVDD, the difference between the two voltages PVDD and VSLp may be constant, and a current IED having a constant magnitude may flow.

[0058] exist Figure 5 , the pixel 200 is shown to include two transistors 210 and 220; however, the pixel 200 is not necessarily limited thereto, and the pixel 200 may also include additional transistors and capacitors.

[0059] In addition, Figure 5 , the transistors 210 and 220 are illustrated as being P-channel metal oxide semiconductors (PMOS); however, the transistors are not necessarily limited thereto, and the transistors 210 and 220 may be implemented in various types such as N-channel metal oxide semiconductors (NMOS).

[0060] Figures 6 to 9 is a block diagram for explaining the operation of an example of a display system.

[0061] Reference Figure 6 The display system 1000 may provide an artificial reality system (such as a virtual reality (VR) system, an augmented reality (AR) system, a mixed reality (MR) system, a hybrid reality system, or a combination of some of them, and / or their derivative systems). The artificial reality system may be implemented on various platforms including a head mounted display (HMD), a mobile device, a computing system, or other hardware platforms capable of providing artificial reality content to one or more viewers.

[0062] The display system 1000 may include a first display device 1100, a second display device 1200, a power supply 1300, and a processor 1400. The first display device 1100 and the second display device 1200 may display images to both eyes of a user, respectively. For example, the first display device 1100 may display an image to the left eye of the user, and the second display device 1200 may display an image to the right eye of the user. In some embodiments, the image displayed by the first display device 1100 and the image displayed by the second display device 1200 may be the same or different.

[0063] The first display device 1100 may include a pixel array 1110 and a display driver IC (DDIC) 1120. The pixel array 1110 may receive a voltage PVDD1 from a first power source 1310 and display an image based on a gate signal and a data signal output from the display driver IC 1120. The pixel array 1110 may include a plurality of pixels.

[0064] The display driver IC 1120 may generate a gate signal and a data signal in response to an instruction from the processor 1400. For example, the processor 1400 may send image data, a clock signal, etc. to the display driver IC 1120, and the display driver IC 1120 may generate a gate signal and a data signal based on the image data and the clock signal. The processor 1400 may process data received through the communication module or data read from a storage device to generate image data. For example, the processor 1400 may perform encoding, conversion, or rendering on the received data.

[0065] The display driver IC 1120 may receive a voltage PVDD1 from the first power source 1310, and a voltage VIN1 from the second power source 1320. The display driver IC 1120 may generate a data signal based on the voltages PVDD1 and VIN1, and output the data signal to the pixel array 1110. Since the display driver IC 1120 generates the data signal using the voltage PVDD1, even if noise occurs in the voltage PVDD1, the data signal uniformly contains the noise, and in the pixel array 1110, the potential difference between the source terminal and the gate terminal of the driving transistor of the pixel is constant. In other words, a constant current flows in the light emitting diode of the pixel array 1110, whereby the first display device 1100 may stably display an image.

[0066] The second display device 1200 may include a pixel array 1210 and a display driver IC 1220. The second display device 1200 may operate similarly to the first display device 1100. Therefore, a redundant description will be omitted.

[0067] The power supply 1300 may include a first power supply 1310 that outputs voltages PVDD1 and PVDD2 and a second power supply 1320 that outputs voltages VIN1 and VIN2. In some embodiments, the voltage PVDD1 may be equal to the voltage PVDD2. The voltage VIN1 may be equal to the voltage VIN2. In some embodiments, the power supply 1300 may further include an additional power supply for supplying power to components of the display system 1000.

[0068] The processor 1400 may be a host for controlling the operations of the first display device 1100, the second display device 1200, and the power supply 1300. The processor 1400 may transmit the first image data to the first display device 1100 and the second image data to the second display device 1200. The processor 1400 may transmit the same clock signal to the first display device 1100 and the second display device 1200. Therefore, the first display device 1100 and the second display device 1200 may display images at the same time. The processor 1400 may control the power supply 1300 so that the power supply 1300 outputs the voltages VIN1, VIN2, PVDD1, and PVDD2.

[0069] Reference Figure 7 , the processor 1400 may monitor the voltages of the pixel arrays 1110 and 1210. For example, the processor 1400 may monitor the voltage output from the display driver IC 1120 to the pixel array 1110 and the voltage output from the display driver IC 1220 to the pixel array 1210. The processor 1400 may perform the monitoring by comparing the signal MDS1 received from the pixel array 1110 with the signal MDS2 received from the pixel array 1210. The signal MDS1 may be a signal output from the pixel array 1110 (e.g., a source line of the pixel array 1110) when a data signal generated by the display driver IC 1120 using the voltages PVDD1 and VIN1 is input to the pixel array. Likewise, the signal MDS2 may be a signal output from the pixel array 1210 (e.g., a source line of the pixel array 1210) when a data signal generated by the display driver IC 1220 using the voltages PVDD2 and VIN2 is input to the pixel array. When the signal MDS1 and the signal MDS2 are consistent with each other, the processor 1400 may determine that the display system 1000 is operating normally.

[0070] When the signal MDS1 and the signal MDS2 are inconsistent with each other, the processor 1400 may determine that an error has occurred in the display system 1000. For example, the potential of the signal MDS1 may be lower than the potential of the signal MDS2. The processor 1400 may detect that the potential of the signal MDS1 is lower than the potential of the signal MDS2, and determine that an error has occurred in the first display device 1100 (for example, determine that the first display device 1100 is abnormal). In some embodiments, the processor 1400 may compare the signals MDS1 and MDS2 with a reference potential range (for example, a reference potential value within the reference potential range). In other words, when the potentials of the signals MDS1 and MDS2 are inconsistent with the reference potential range within a tolerance, the processor 1400 may determine that an error has occurred.

[0071] In some embodiments, the processor 1400 may monitor the reference voltages of the display driver ICs 1120 and 1220. For example, the display driver IC 1120 may generate a reference voltage based on the voltages VIN1 and PVDD1, and the display driver IC 1220 may generate a reference voltage based on the voltages VIN2 and PVDD2, and the display driver IC may generate a data signal based on the reference voltages. The processor 1400 may compare the reference voltage of the display driver IC 1120 with the reference voltage of the display driver IC 1220.

[0072] Reference Figure 7 and Figure 8 , when it is determined that an error has occurred in the first display device 1100, the processor 1400 may generate an error correction signal EMOD1 based on the potential difference between the signals MDS1 and MDS2. In some embodiments, the processor 1400 may generate the error correction signal EMOD1 based on the difference between the signal MDS1 and the reference potential range. The processor 1400 may send the error correction signal EMOD1 to the display driver IC 1120 of the first display device 1100.

[0073] The display driver IC 1120 may change the data signal to be output to the pixel array 1110 based on the error correction signal EMOD1. For example, the display driver IC 1120 may amplify the data signal by a predetermined level. Since the pixel array 1110 outputs an image based on the amplified data signal, the first display device 1100 and the second display device 1200 may display images with the same quality.

[0074] Reference Figure 7 and Fig. 9When it is determined that an error has occurred in the first display device 1100, the processor 1400 may generate an error correction signal EMOD2 based on the potential difference between the signal MDS1 and the signal MDS2. In some embodiments, the processor 1400 may generate the error correction signal EMOD2 based on the difference between the signal MDS1 and the reference potential range. The processor 1400 may send the error correction signal EMOD2 to the second power supply 1320.

[0075] The second power supply 1320 may output a voltage VIN3 based on the error correction signal EMOD2. For example, the second power supply 1320 may amplify the voltage VIN1 by a predetermined level to generate the voltage VIN3. The display driver IC 1120 may generate a data signal based on the voltages PVDD1 and VIN3, and output the data signal to the pixel array 1110. The data signal generated based on the voltages PVDD1 and VIN3 may have a higher potential than the data signal generated based on the voltages PVDD1 and VIN1. Since the pixel array 1110 outputs an image based on the data signal having a higher potential, the first display device 1100 and the second display device 1200 may display an image having the same quality.

[0076] Figures 6 to 9 The description of explains what happens when the first display device 1100 has an error. A similar description may be applied when the second display device 1200 has an error. For example, the processor 1400 may determine that the second display device 1200 is abnormal based on the potential of the signal MDS1 being higher than the potential of the signal MDS2. For example, the processor 1400 may determine that the first display device 1100 is abnormal based on the potential of the signal MDS1 being lower than the reference potential value, and determine that the second display device 1200 is abnormal based on the potential of the signal MDS2 being lower than the reference potential value.

[0077] Fig.10 is a flow chart of a method for driving a display device.

[0078] Reference Fig.10 The driving method may be performed by a display device. The display device may include a display driver IC and a display panel. The display panel may display an image based on a gate signal and a data signal output from the display driver IC.

[0079] The display device may apply an input voltage VIN and a pixel driving voltage PVDD (S1010). For example, the display device may include a first power supply that generates the input voltage VIN and a second power supply that generates the pixel driving voltage PVDD. In some embodiments, the first power supply and the second power supply may be combined into one power supply. In some embodiments, the display device may receive the input voltage VIN and the pixel driving voltage PVDD from the outside. The display device may apply the input voltage VIN to the display driver IC and apply the pixel driving voltage PVDD to the display driver IC and the display panel.

[0080] The display driver IC may generate a voltage VOGN using an input voltage VIN and a pixel driving voltage PVDD (S1020). For example, the display driver IC may include a bandgap reference circuit and use the bandgap reference circuit to generate a voltage VOGN that is lower than the input voltage VIN and higher than the pixel driving voltage PVDD. In some embodiments, the display driver IC may generate a voltage VOGN having a first potential level higher than a first potential level of the pixel driving voltage PVDD.

[0081] The display driver IC may generate a maximum gamma voltage VG_TOP using a voltage VOGN, an input voltage VIN, and a pixel driving voltage PVDD (S1030). The display driver IC may include a first reference voltage generator for generating the maximum gamma voltage VG_TOP. The first reference voltage generator may generate the maximum gamma voltage VG_TOP by amplifying the voltage VOGN based on the input voltage VIN and the pixel driving voltage PVDD. The first reference voltage generator may include an amplifier, a transistor, a resistor string, a buffer, etc. for generating the maximum gamma voltage VG_TOP.

[0082] The display driver IC may generate a minimum gamma voltage VG_BOT using a voltage VOGN and a pixel driving voltage PVDD (S1040). The display driver IC may include a second reference voltage generator for generating the minimum gamma voltage VG_BOT. The second reference voltage generator may generate the minimum gamma voltage VG_BOT by amplifying the voltage VOGN based on the pixel driving voltage PVDD and the ground voltage. The second reference voltage generator may include an amplifier, a transistor, a resistor string, a buffer, etc. for generating the minimum gamma voltage VG_BOT. The first reference voltage generator and the second reference voltage generator may have the same structure. The node to which the pixel driving voltage PVDD is applied in the first reference voltage generator may correspond to the node to which the ground voltage is applied in the second reference voltage generator.

[0083] The display driver IC may generate a plurality of gamma voltages VG based on a maximum gamma voltage VG_TOP and a minimum gamma voltage VG_BOT (S1050). The display driver IC may include a gamma voltage generator composed of a resistor string. The display driver IC may output a plurality of gamma voltages VG at a node on the resistor string. The display driver IC may output the plurality of gamma voltages VG to a source driver, and the source driver may generate a data signal based on the plurality of gamma voltages VG, and output the data signal to a display panel.

[0084] Fig.11 is a graph for explaining an example of the operation of the display device.

[0085] Reference Fig.11 The display device may include a display driver IC and a display panel. The display driver IC may output a gate signal and a data signal to the display panel, and the display panel may display an image based on the gate signal and the data signal.

[0086] The display panel and the display driver IC may receive a pixel driving voltage PVDD. For example, the display device may receive the pixel driving voltage PVDD from an external power source, or may include a power source for generating the pixel driving voltage PVDD. The pixel driving voltage PVDD may have a variation as large as the voltage VNS, and its voltage value may fluctuate within a range from V1 to V2. For example, the display driver IC may generate a data signal having a variation corresponding to the variation of the pixel driving voltage PVDD.

[0087] The display driver IC may generate a voltage VSOURCE corresponding to the data signal based on the pixel drive voltage PVDD. For example, the display driver IC may include an amplifier, a resistor string, a decoder, etc. Therefore, similar to the pixel drive voltage PVDD, the voltage VSOURCE generated by the display driver IC may have a change as large as the voltage VNS. The voltage VSOURCE may fluctuate within a range from V3 to V4. The display driver IC may apply the voltage VSOURCE to the pixels of the display panel through the source line. The pixel may display an image based on the pixel drive voltage PVDD and the voltage VSOURCE.

[0088] Each pixel may include a plurality of transistors and a light emitting diode. Among the plurality of transistors, the driving transistor may receive a pixel driving voltage PVDD through its source terminal and receive a voltage VSOURCE through its gate terminal. The driving transistor may cause a current to flow to a drain terminal based on a voltage difference VGS between the source terminal and the gate terminal. The voltage difference VGS may be the difference between the pixel driving voltage PVDD and the voltage VSOURCE. Since the pixel driving voltage PVDD and the voltage VSOURCE have the same variation as VNS, the noise may be offset, and the voltage difference VGS between these voltages may have a constant value V5. Therefore, a constant current flows from the driving transistor to the light emitting diode, whereby the light emitting diode may emit light with a constant brightness.

[0089] Fig.12 is a graph for explaining an example of the operation of the display device.

[0090] Reference Fig.12 The display device may include a display driver IC and a display panel. The display driver IC may output a gate signal and a data signal to the display panel, and the display panel may display an image based on the gate signal and the data signal.

[0091] The display panel and the display driver IC may receive a pixel driving voltage PVDD. For example, the display device may receive the pixel driving voltage PVDD from an external power source, or may include a power source for generating the pixel driving voltage PVDD. The pixel driving voltage PVDD may have noises VNS1 to VNS5 at different time points, whereby the voltage value may fluctuate within a range from V1 to V5.

[0092] The display driver IC may generate a voltage VSOURCE corresponding to the data signal based on the pixel drive voltage PVDD. For example, the display driver IC may include an amplifier, a resistor string, a decoder, or a combination thereof. Therefore, similar to the pixel drive voltage PVDD, the voltage VSOURCE generated by the display driver IC may have noise VNS1 to VNS5. The voltage VSOURCE may fluctuate within a range from V6 to V10. In other words, the voltage VSOURCE and the pixel drive voltage PVDD may have the same noise at the same time point. The display driver IC may apply the voltage VSOURCE to the pixels of the display panel through the source line. The pixel may display an image based on the pixel drive voltage PVDD and the voltage VSOURCE.

[0093] Each pixel may include a plurality of transistors and a light emitting diode. Among the plurality of transistors, the driving transistor may receive a pixel driving voltage PVDD through its source terminal and receive a voltage VSOURCE through its gate terminal. The driving transistor may cause a current to flow to a drain terminal based on a voltage difference VGS between a source terminal and a gate terminal. The voltage difference VGS may be a difference between a pixel driving voltage PVDD and a voltage VSOURCE. Since the pixel driving voltage PVDD and the voltage VSOURCE have noises VNS1 to VNS5 at the same time point, the noises may be offset, and the voltage difference VGS between these voltages may have a constant value V11. Therefore, a constant current flows from the driving transistor to the light emitting diode, whereby the light emitting diode may emit light with a constant brightness.

[0094] Fig.13 is a block diagram of an example of a semiconductor system.

[0095] Reference Fig.13 , the semiconductor system 2000 may include a processor 2010 , a memory 2020 , a display device 2030 , and a peripheral device 2040 that are electrically connected through a system bus 2050 .

[0096] The processor 2010 may control data input and output of the memory 2020 , the display device 2030 , and the peripheral device 2040 , and perform image processing on image data transmitted between the corresponding devices.

[0097] The display device 2030 may include a display driver IC (DDI) 2031 and a display panel (DP) 2032, and stores image data input through the system bus 2050 in a frame memory included in the DDI 2031, and displays an image on the display panel 2032. In the display device 2030, referring to Figures 1 to 12 Any of the display devices described may be included. In other words, the display device 2030 may apply a pixel driving voltage to the DDI 2031 and the DP 2032, and the DDI 2031 may generate a data signal using the pixel driving voltage. The DDI 2031 may send a data signal to the DP 2032, and the DP 2032 may display an image based on the pixel driving voltage and the data signal. When the pixel driving voltage includes noise, the data signal also includes a noise component, which is offset in the driving transistor of the pixel, and a constant current flows in the light emitting diode of the pixel. Therefore, the display device 2030 may display a stable image.

[0098] The peripheral device 2040 may be a device (such as a camera, a scanner, or a webcam) for converting a video, a still image, etc. into an electrical signal. The image data acquired by the peripheral device 2040 may be stored in the memory 2020 or may be displayed on the display panel 2032 in real time.

[0099] The memory 2020 may include a volatile memory such as a dynamic random access memory (DRAM) and / or a non-volatile memory such as a flash memory. The memory 2020 may be composed of a DRAM, a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), a NOR flash memory, a NAND flash memory, a fusion flash memory (e.g., a memory including a static random access memory (SRAM) buffer, a NAND flash memory, and a NOR interface logic), etc. The memory 2020 may store image data acquired from the peripheral device 2040, or may store an image signal processed by the processor 2010.

[0100] The semiconductor system 2000 may be provided in a mobile electronic product such as a smart phone; but is not limited thereto, and may be provided in various electronic products that display an image.

[0101] Fig.14 is a block diagram showing an example of a system.

[0102] Reference Fig.14 The display system 3000 may provide an artificial reality system (such as a virtual reality (VR) system, an augmented reality (AR) system, a mixed reality (MR) system, a hybrid reality system, or a combination of some of them, and / or their derivative systems). The artificial reality system may be implemented on various platforms including a head mounted display (HMD), a mobile device, a computing system, or other hardware platforms capable of providing artificial reality content to one or more viewers.

[0103] The display system 3000 may include a display device 3100 and a host device 3200. The display device 3100 may receive image data IS transmitted from the host device 3200 and display an image according to the image data IS. The display device 3100 may display a two-dimensional or three-dimensional image to a user. The display device 3100 may include a display panel 3110, an optical system 3120, and an eye tracking sensor 3130. In some embodiments, the display device 3100 may further include a power supply circuit (such as a DC to DC converter) that supplies a driving voltage to the display panel 3110, the optical system 3120, and the eye tracking sensor 3130.

[0104] In some embodiments, the display panel 3110 may display an image to the user according to the image data IS received from the host device 3200. In some embodiments, the number of the display panels 3110 may be one or two or more. For example, two display panels 3110 may provide images to the user's eyes, respectively. The display panel 3110 may be a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an inorganic light emitting diode (ILED) display, a micro light emitting diode (μLED) display, an active matrix OLED display (AMOLED), a transparent OLED (TOLED) display, etc.

[0105] In some embodiments, the display panel 3110 may include a pixel array 3111 and a driver circuit 3112. The display panel 3110 may have a backplane structure in which the pixel array 3111 and the driver circuit 3112 are disposed on a silicon substrate (silicon semiconductor substrate). For example, the display panel 3110 may include a pixel array 3111 and a driver circuit 3112 on a complementary metal oxide semiconductor (CMOS) wafer.

[0106] The pixel array 3111 may include a plurality of pixels and a plurality of gate lines and a plurality of source lines respectively connected to the plurality of pixels. In some embodiments, the plurality of pixels may emit light of a primary color such as red, green, blue, white, or yellow.

[0107] The driver circuit 3112 may generate a signal for driving the pixel array 3111 based on the image data IS received from the host device 3200 .

[0108] The signal for driving the pixel array 3111 can be sent to multiple pixels through multiple gate lines and multiple source lines. In some embodiments, the driver circuit 3112 can generate a data signal and a gate signal for driving multiple pixels included in the pixel array 3111, and provide the data signal and the gate signal to multiple pixels. Multiple pixels included in the pixel array 3111 can emit image light based on the signal provided by the driver circuit 3112. The pixel array 3111 and the driver circuit 3112 can receive the same pixel drive voltage. The driver circuit 3112 can generate a data signal based on the pixel drive voltage. When the pixel drive voltage contains noise, the data signal also contains a noise component, which is offset in the driving transistor of the pixel, and a constant current flows in the light emitting diode of the pixel. Therefore, the display panel 3110 can display a stable image.

[0109] The image displayed on the display panel 3110 may be visually recognized by the user's eyes through the optical system 3120. In some embodiments, the optical system 3120 may optically display image content or amplify image light received from the display panel 3110, correct optical errors associated with the image light, and provide the corrected image light to the user. For example, the optical system 3120 may include a substrate, an optical waveguide, an aperture, a Fresnel lens, a convex lens, a concave lens, an optical filter, an input / output connector, or other suitable optical elements that may affect the image light emitted from the display panel 3110.

[0110] The eye tracking sensor 3130 may track the position and movement of the user's eyes. Eye tracking may refer to determining the position of the eyes relative to the display device 3100 (including the orientation and position of the eyes). In some embodiments, the eye tracking system may include an imaging system for imaging one or more eyes. In some embodiments, the eye tracking system may include a light emitter that generates light directed toward the eyes so that light reflected by the eyes can be captured by the imaging system. The eye tracking sensor 3130 may send eye tracking data ED to the host device 3200.

[0111] The host device 3200 may be a computing device or system that controls the display device 3100 from the outside so that an image desired by a user is displayed on the pixel array 3111. The host device 3200 may send image data IS according to the content to be presented to the user to the display device 3100. In some embodiments, the host device 3200 may render the content generated during the execution of the application into image data IS including a plurality of regions with different display qualities. For example, an image according to the image data IS may include a first region and a second region, and the first region may be rendered in a first quality (e.g., high definition), and a second region around the first region may be rendered in a second quality (e.g., low definition).

[0112] The host device 3200 may include an image processor 3210 that generates image data IS. In some embodiments, the image processor 3210 may generate image data IS having a plurality of regions with different display qualities. In some embodiments, the image processor 3210 may perform rendering of the image data IS based on eye tracking data ED received from the display device 3100. The image processor 3210 may receive the eye tracking data ED from the eye tracking sensor 3130 and determine the position of the user's eyes based on the eye tracking data. For example, the image processor 3210 may render a first region corresponding to the position of the user's eyes at a first quality, and render a second region surrounding the first region at a second quality.

[0113] The host device 3200 may send a driving control signal CTRL to the display device 3100. The driving control signal CTRL may include control information, setting data, etc. for controlling the driver circuit 3112 and the optical system 3120. In some embodiments, the driving control signal CTRL may include region indication data indicating a plurality of regions of an image according to the image data IS. In some embodiments, the region indication data may include information about the number of regions and / or coordinate data indicating the positions of a plurality of regions in the image represented by the image data IS, function data, etc. For example, when the image represented by the image data IS is divided into a first region and a second region and the first region is a rectangle, the region indication data may include coordinate values ​​of four vertices of the first region.

[0114] The display device 3100 can drive multiple regions of an image represented by the image data IS in multiple ways. The multiple regions can be rendered in multiple qualities. For example, the driver circuit 3112 can drive a first region rendered in a first quality and a second region rendered in a second quality in different ways.

[0115] In some embodiments, reference Figures 1 to 14 Each of the described components or a combination of two or more components may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), or the like.

[0116] Although the present disclosure includes many specific implementation details, these should not be interpreted as limitations on the scope of protection that can be claimed. Specific features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the above features may be described as working in a specific combination and even initially claimed as such, one or more features from the combination may be removed from the combination in some cases, and the combination may involve a sub-combination or a variation of the sub-combination.

[0117] While the invention has been described in conjunction with what are presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, comprising: A pixel array includes pixels, each pixel includes a light emitting diode and a first transistor, and the first transistor includes: a source terminal to which a pixel driving voltage is configured to be applied, and a gate terminal, the data signal being configured to be applied to the gate terminal, wherein the first transistor is configured to: output a driving current generated based on a voltage difference between a gate terminal and a source terminal to the light emitting diode; and The display driver integrated circuit IC is configured to generate a data signal based on the pixel driving voltage.

2. The display device according to claim 1, wherein: The display driver IC is configured to generate a data signal having a variation corresponding to a variation of a pixel driving voltage.

3. The display device according to claim 1, wherein: The pixel further includes: a second transistor, the second transistor including: A drain terminal configured to receive a data signal, and A source terminal is connected to the gate terminal of the first transistor and is configured to transmit the data signal to the first transistor.

4. The display device according to claim 3, wherein: The display driver IC is configured to generate a gate signal and apply the gate signal to a gate terminal of the second transistor, and The second transistor is configured to be turned on based on the gate signal and send the data signal to the first transistor.

5. The display device according to any one of claims 1 to 4, wherein: Display driver IC includes: a reference voltage generator configured to generate a maximum gamma voltage and a minimum gamma voltage based on a pixel driving voltage and a circuit driving voltage; a gamma voltage generator configured to generate a plurality of gamma voltages based on a maximum gamma voltage and a minimum gamma voltage; and The source driver is configured to generate a data signal based on the plurality of gamma voltages.

6. The display device according to claim 5, wherein: The reference voltage generator includes: a voltage generator configured to generate an initial voltage based on a pixel driving voltage and a circuit driving voltage; a first reference voltage generator configured to generate a maximum gamma voltage based on an initial voltage, a pixel driving voltage, and a circuit driving voltage; and The second reference voltage generator is configured to generate a minimum gamma voltage based on the initial voltage, the pixel driving voltage and the ground voltage.

7. The display device according to claim 6, wherein: The voltage generator is configured to generate an initial voltage that is higher than a pixel driving voltage and lower than a circuit driving voltage.

8. The display device according to claim 6, wherein: The first reference voltage generator comprises: The first input terminal is configured to: receive an initial voltage, The second input terminal is configured to: receive a circuit driving voltage, and The third input terminal is configured to: receive a pixel driving voltage, and Wherein, the second reference voltage generator comprises: The fourth input terminal is configured to: receive an initial voltage, A fifth input terminal is configured to: receive a pixel driving voltage, and a sixth input terminal configured to receive a ground voltage, and Among them, the first input terminal corresponds to the fourth input terminal, the second input terminal corresponds to the fifth input terminal, and the third input terminal corresponds to the sixth input terminal.

9. The display device according to claim 5, wherein: The gamma voltage generator includes: a resistor string including a plurality of resistors, and The resistor string is configured to generate the plurality of gamma voltages by receiving a maximum gamma voltage at a first end and a minimum gamma voltage at a second end.

10. A display system, comprising: A power supply configured to: supply a pixel driving voltage and a circuit driving voltage; A processor configured to: generate first image data and second image data; The first display device comprises: a first display driver integrated circuit IC configured to generate a first data signal based on first image data, a pixel driving voltage and a circuit driving voltage, and a first pixel array configured to display a first image to a first eye of two eyes of a user based on a pixel driving voltage and a first data signal; and The second display device comprises: a second display driver IC configured to generate a second data signal based on the second image data, the pixel driving voltage and the circuit driving voltage, and The second pixel array is configured to display a second image to a second eye of the two eyes of the user based on a pixel driving voltage and a second data signal.

11. The display system according to claim 10, wherein: The processor is configured to receive a first signal from the first pixel array, receive a second signal from the second pixel array, and determine whether the display system is operating normally by comparing the first signal and the second signal.

12. The display system according to claim 11, wherein: The first signal is a signal output from a source line of the first pixel array based on the first data signal being input to the source line of the first pixel array, and The second signal is a signal output from the source line of the second pixel array based on the second data signal being input to the source line of the second pixel array.

13. The display system according to claim 11, wherein: The processor is configured as: determining that the first display device is abnormal based on the potential of the first signal being lower than the potential of the second signal, and Based on the potential of the first signal being higher than the potential of the second signal, it is determined that the second display device is abnormal.

14. The display system according to claim 11, wherein: The processor is configured as: Based on the first signal being lower than a reference value, determining that the first display device is abnormal, and Based on the second signal being lower than a reference value, it is determined that the second display device is abnormal.

15. The display system according to any one of claims 11 to 14, wherein: The processor is configured to: send an error correction signal to the abnormal display device, and The abnormal display device is configured to output an amplified data signal based on the error correction signal.

16. The display system according to any one of claims 11 to 14, wherein: The processor is configured to: send an error correction signal to the power supply, and The power supply is configured to amplify the circuit driving voltage based on the error correction signal and output the amplified circuit driving voltage to the abnormal display device.

17. A method for driving a display device, the method comprising: applying an input voltage to a display driver integrated circuit IC; applying pixel drive voltages to the display driver IC and the display panel; Using a display driver IC, generating a data signal based on an input voltage and a pixel driving voltage; as well as Using the display panel, an image is displayed based on a data signal and a pixel driving voltage.

18. The method for driving a display device according to claim 17, wherein: The steps of generating a data signal include: Using a display driver IC, generating an initial voltage based on an input voltage and a pixel driving voltage; and Using the display driver IC, a data signal is generated based on an initial voltage, an input voltage, and a pixel driving voltage.

19. The method for driving a display device according to claim 18, wherein: The steps to generate the initial voltage include: A display driver IC is used to generate an initial voltage that is lower than the input voltage and higher than the pixel driving voltage.

20. The method for driving a display device according to claim 18, wherein: The step of generating a data signal based on an initial voltage, an input voltage and a pixel driving voltage includes: Using a display driver IC, generating a maximum gamma voltage based on an initial voltage, an input voltage, and a pixel driving voltage; Using a display driver IC, generating a minimum gamma voltage based on an initial voltage, a pixel driving voltage, and a ground voltage; generating a plurality of gamma voltages based on a maximum gamma voltage and a minimum gamma voltage using a display driver IC; and Using the display driver IC, a data signal is generated based on the plurality of gamma voltages.

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