Display device and driving method thereof

Abstract

A display device and a driving method thereof are disclosed. There is provided a display device including a plurality of pixels, and each of the plurality of pixels includes: a first switching transistor operating according to a scan signal; a second switching transistor operated according to the sensing signal; a driving transistor including a gate connected to the first node, a source connected to the second node, and a drain connected to a low potential voltage line; a light emitting device including an anode connected to the high potential voltage line and a cathode connected to the second node; and a storage capacitor connected between the first node and the second node.

Description

Technical Field

[0001] The present disclosure relates to a display device and a driving method thereof. Background Art

[0002] In addition to the display screen of a television or monitor, the display device is widely used as a notebook computer, a tablet computer, a smart phone, a portable display device, and a portable information device display screen. Recently, light-emitting diode display devices using micro light-emitting diodes have been studied and developed, and light-emitting diode display devices have become the focus of next-generation displays due to their high definition and high reliability. In addition, since the light-emitting diode display device can omit the backlight unit, a transparent display device capable of recognizing an object located on the lower surface of the display device has also been studied.

[0003] The light emitting diode display device can display an image by driving a thin film transistor to adjust the amount of current flowing through the light emitting diode. Summary of the invention

[0004] The inventors have recognized that since the driving transistor receives the driving voltage as a DC voltage, the threshold voltage characteristics of the driving transistor may change due to degradation. The present disclosure provides a display device and a method for driving the display device, which can compensate for changes in device performance while improving transparency, etc.

[0005] According to one aspect of the present disclosure, a display device includes: a display panel, on which a gate line, a scan line, a data line and a plurality of pixels are arranged, wherein each of the plurality of pixels includes: a first switching transistor, which operates according to a scan signal applied through the gate line; a second switching transistor, which operates according to a sensing signal applied through the sensing line; a driving transistor, which includes a gate connected to a first node, a source connected to a second node and a drain connected to a low potential voltage line providing a low potential voltage; a light-emitting device, which includes an anode connected to a high potential voltage line providing a high potential voltage and a cathode connected to the second node; and a storage capacitor, which is connected between the first node and the second node.

[0006] In addition, according to one aspect of the present disclosure, a method for driving a display device is provided. The display device includes a display panel, on which a gate line, a sensing line, a data line, and a plurality of pixels are arranged. The method includes: during a first period, turning on a first switching transistor and a second switching transistor to initialize a voltage stored in a storage capacitor by applying an initialization voltage to the data line; during a second period, sensing a threshold voltage of a driving transistor; during a third period, applying a data voltage to the data line; during a fourth period, compensating for the threshold voltage of the driving transistor; and during a fifth period, emitting light by a light-emitting element. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0008] Figure 2 is a circuit diagram of one pixel according to an embodiment of the present disclosure.

[0009] Figure 3 is a diagram of a waveform of a signal applied to a pixel according to an embodiment of the present disclosure.

[0010] Figure 4 is a circuit diagram illustrating driving of a pixel in a first period according to an embodiment of the present disclosure.

[0011] Figure 5 is a circuit diagram illustrating driving of a pixel in a second period according to an embodiment of the present disclosure.

[0012] Figure 6 is a circuit diagram illustrating driving of a pixel in a third period according to an embodiment of the present disclosure.

[0013] Figure 7 is a circuit diagram illustrating driving of a pixel in a fourth period according to an embodiment of the present disclosure.

[0014] Figure 8 is a circuit diagram illustrating driving of a pixel in a fifth period according to an embodiment of the present disclosure.

[0015] Fig. 9 is a block diagram of a plurality of pixels according to the first embodiment of the present disclosure and the second embodiment of the present disclosure.

[0016] Fig.10 is a diagram of waveforms of a signal in a first horizontal period and a second horizontal period according to the first embodiment of the present disclosure.

[0017] Fig.11 is a diagram of waveforms of a signal in a first horizontal period and a second horizontal period according to a second embodiment of the present disclosure.

[0018] Fig.12 is a block diagram of a plurality of pixels according to a third embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The advantages and characteristics of the present disclosure and methods for implementing the same will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0020] The shapes, sizes, ratios, angles and quantities disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details shown. Throughout the specification, the same reference numerals refer to the same elements. In the following description, when a detailed description of a related known function or configuration is determined to be unnecessary to obscure the focus of the present disclosure, the detailed description will be omitted. In the case of using "including", "having" and "comprising" described in the present disclosure, another part may be added unless "only" is used. Unless otherwise specified, a term in the singular may include a plural form.

[0021] When constructing an element, the element is interpreted as including an error band even though not explicitly described.

[0022] In describing a positional relationship, for example, when the positional relationship is described as “on,” “over,” “below,” and “beside,” one or more parts may be disposed between two other parts unless “immediately” or “directly” is used.

[0023] It should be understood that although the terms "first", "second", etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0024] As those skilled in the art can fully understand, the features of the various embodiments of the present disclosure can be partially or entirely connected or combined with each other, and can interoperate and technically drive each other differently. The embodiments of the present disclosure can be performed independently of each other, or can be performed together in a mutually dependent relationship.

[0025] Hereinafter, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0027] Reference Figure 1 , a display device according to an embodiment of the present disclosure may include a display panel 100 , a gate driver 200 , a data driver 300 , a sensing driver 400 , and a timing controller 500 .

[0028] The display panel 100 may be a flat panel or a flexible display panel. The substrate of the display panel 100 may be formed of glass, plastic or a plastic film, but is not limited thereto. In addition, when the display device is a transparent display device, the substrate of the display panel 100 may be formed of a transparent material.

[0029] The display panel 100 may include a pixel array in which a plurality of pixels P are arranged in a matrix form. Each of the plurality of pixels P may include a plurality of sub-pixels each including a light-emitting element. Each pixel may be composed of three color sub-pixels or four color sub-pixels among a red sub-pixel emitting red light, a green sub-pixel emitting green light, a blue sub-pixel emitting blue light, and a white sub-pixel emitting white light, or may be composed of two color sub-pixels. In addition, when the display device is a transparent display device, each of the plurality of pixels P may include a transparent area.

[0030] Each of the plurality of pixels P is connected to a plurality of signal lines including a gate line driven by a gate driver 200, a data line driven by a data driver 300, a sensing line driven by a sensing driver 400, and a power supply line providing a power supply voltage. In addition, each of the plurality of pixels P can be independently driven by each pixel circuit.

[0031] The micro light emitting diode may be applied to a light emitting device disposed in a plurality of pixels P, but is not limited thereto.

[0032] The gate driver 200 may receive a plurality of gate control signals from the timing controller 500 and then individually drive the gate lines GL of the display panel 100 .

[0033] The data driver 300 may receive a plurality of data control signals from the timing controller 500 and then individually drive the data lines DL of the display panel 100 .

[0034] The sensing driver 400 may receive a plurality of sensing control signals from the timing controller 500 and then individually drive the sensing lines SL of the display panel 100 .

[0035] The timing controller 500 may rearrange digital video data input from the outside and provide the rearranged digital video data to the data driver 300. The timing controller 500 may control operation timings of the gate driver 200, the data driver 300, and the sense driver 400 using timing signals such as a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal input from the outside.

[0036] Figure 2 is a circuit diagram of a pixel P according to an embodiment of the present disclosure.

[0037] The pixel P may include a plurality of thin film transistors DT, ST1 and ST2, a light emitting element LED and a storage capacitor Cst. The plurality of thin film transistors DT, ST1 and ST2 may include a driving transistor DT, a first switching transistor ST1 and a second switching transistor ST2. In this case, each of the driving transistor DT, the first switching transistor ST1 and the second switching transistor ST2 may be formed by a PMOS transistor.

[0038] A gate of the first switching transistor ST1 may be connected to the gate line GL, a source of the first switching transistor ST1 may be connected to the data line DL, and a drain of the first switching transistor ST1 may be connected to the first node n1. The first switching transistor ST1 may operate according to a scan signal Scan applied through the gate line GL. The first switching transistor ST1 may provide an initialization voltage Vinit or a data voltage Vdata applied through the data line DL to the first node n1.

[0039] The gate of the second switch transistor ST2 may be connected to the sensing line SL, the source of the second switch transistor ST2 may be connected to the third node n3, and the drain of the second switch transistor ST2 may be connected to the second node n2. The second switch transistor ST2 may operate according to a sensing signal Sense applied through the sensing line SL.

[0040] The gate of the driving transistor DT may be connected to the first node n1, the source of the driving transistor DT may be connected to the second node n2, and the drain of the driving transistor DT may be connected to the low potential voltage line EVSSL. The driving transistor DT may control the magnitude of the driving current I flowing to the light emitting element LED.

[0041] The anode of the light emitting element LED may be connected to the third node N3, and the cathode of the light emitting element LED may be connected to the second node N2. The anode of the light emitting element LED may be connected to the source of the second switching transistor ST2 through the third node N3, and the cathode may be connected to the drain of the second switching transistor ST2 through the second node N2. In addition, the light emitting element LED may be a micro light emitting diode, but is not limited thereto. The light emitting element LED may emit light according to the driving current I.

[0042] The storage capacitor Cst may be connected to the first node N1 and the second node N2. The storage capacitor Cst may maintain the data voltage Vdata applied to the first node N1 for a predetermined period.

[0043] Figure 3 is a diagram of a waveform of a signal applied to a pixel P according to an embodiment of the present disclosure. A plurality of pixels P may be driven according to a first period T1, a second period T2, a third period T3, a fourth period T4, and a fifth period T5. The first period T1 to the fifth period T5 (T1, T2, T3, T4, and T5) do not overlap with each other, but may be continuous or uninterrupted with each other. In this case, the first horizontal period H1 may include the first period T1 to the fourth period T4. Referring to Figures 4 to 8 , the driving process of the pixel P will be described in detail.

[0044] Figure 4 is a circuit diagram illustrating driving of a pixel in a first period T1 according to an embodiment of the present disclosure. The first period T1 may be a reset period.

[0045] In the first period T1, the scan signal Scan and the sensing signal Sense in the low voltage state are applied, so the first switch transistor ST1 and the second switch transistor ST2 can be in the on state. The initialization voltage Vinit applied to the data line DL through the first switch transistor ST1 can be applied to the first node n1. In addition, the high potential voltage EVDD can be applied to the second node n2 through the second switch transistor ST2. Since the first terminals of the storage capacitor Cst are respectively connected to the first node n1, the first terminals of the storage capacitor Cst can be initialized to the initialization voltage Vinit. In addition, since the second terminals of the storage capacitor Cst are respectively connected to the second node n2, the second terminals of the storage capacitor Cst can be initialized to the high potential voltage EVDD.

[0046] Therefore, the storage capacitor Cst can be initialized to a differential voltage between the initialization voltage Vinit and the high potential voltage EVDD. For example, by initializing the storage capacitor Cst via the initialization voltage Vinit provided through the data line DL and the high potential voltage EVDD provided through the high potential voltage line EVDDL, a wiring for providing a reference voltage may not be used separately. Therefore, the number of wirings in the pixel circuit can be reduced, thereby improving the transmittance.

[0047] In addition, in the first period T1, the driving transistor DT may be turned on by the initialization voltage Vinit applied to the first node N1 and the high potential voltage EVDD applied to the second node n2. In addition, the anode and cathode of the light emitting element LED may be short-circuited. The current provided from the high potential voltage line EVDDL may flow through the high potential voltage line EVDDL, the second switching transistor ST2, the driving transistor DT, the first switching transistor ST1, and the data line DL. Since no current flows through the light emitting element LED, the light emitting element LED may not emit light in the first period T1.

[0048] Figure 5 is a circuit diagram illustrating driving of a pixel in a second period T2 according to an embodiment of the present disclosure. The second period T2 may be a sensing period.

[0049] In the second period T2, the scan signal Scan provided to the first switch transistor ST1 may maintain a low voltage state, and the sensing signal Sense provided to the second switch transistor ST2 may change from a low voltage state to a high voltage state. Therefore, the first switch transistor ST1 may maintain a turned-on state, and the second switch transistor ST2 may change from a turned-on state to a turned-off state.

[0050] The second switch transistor ST2 becomes a cut-off state, and the driving transistor DT can operate as a source follower. For example, the voltage of the second node n2 connected to the source of the driving transistor DT can be discharged through the low potential voltage line EVSSL. In addition, the first node n1 connected to the gate of the driving transistor DT can maintain the initialization voltage Vinit.

[0051] Since the voltage of the gate of the driving transistor DT is maintained and the voltage of the source of the driving transistor DT is reduced, the gate-source voltage Vgs of the driving transistor DT can be reduced. When the gate-source voltage Vgs of the driving transistor DT is reduced to the threshold voltage Vth of the driving transistor DT, the driving transistor DT can be turned off. In addition, since the storage capacitor Cst stores a differential voltage, that is, a voltage difference between the first terminal of the storage capacitor Cst and the second terminal of the storage capacitor Cst, the storage capacitor Cst can store a threshold voltage Vth as the gate-source voltage Vgs of the driving transistor DT.

[0052] In the second period T2, the magnitude of the gate voltage of the driving transistor DT may be Vinit. Also, the magnitude of the source voltage of the driving transistor DT may be Vinit+|Vth|. Also, the magnitude of the voltage potential stored in the storage capacitor Cst may be |Vth|. In the second period T2, the sensing threshold voltage Vth is sensed by the voltage potential stored in the storage capacitor Cst.

[0053] Even in the second period T2, the light emitting diode LED may not emit light.

[0054] Figure 6 is a circuit diagram showing driving of a pixel in a third period T3 according to an embodiment of the present disclosure. The third period T3 may be a data conversion period.

[0055] In the third period T3, the scan signal Scan supplied to the first switch transistor ST1 may be changed from a low voltage state to a high voltage state, and the sensing signal Sense supplied to the second switch transistor ST2 may maintain a high voltage state. Therefore, the first switch transistor ST1 may be changed from an on state to an off state, and the second switch transistor ST2 may maintain an off state. Since the gate-source voltage Vgs of the driving transistor DT does not change, the storage capacitor Cst may maintain a state in which the threshold voltage Vth of the driving transistor DT is stored.

[0056] In addition, in the third period T3, the voltage applied to the data line DL may be changed from the initialization voltage Vinit to the data voltage Vdata. By providing both the initialization voltage Vinit and the data voltage Vdata via the data line DL, the initialization voltage Vinit and the data voltage Vdata may not be provided through different wires. Therefore, the number of wires may be reduced. In this case, the amplitude of the data voltage Vdata may be smaller than the amplitude of the initialization voltage Vinit.

[0057] Figure 7is a circuit diagram showing driving of a pixel in a fourth period T4 according to an embodiment of the present disclosure. The fourth period T4 may be a writing period.

[0058] In the fourth period T4, the scan signal Scan supplied to the first switching transistor ST1 may be changed from a high voltage state to a low voltage state, and the sensing signal Sense supplied to the second switching transistor ST2 may maintain a high voltage state. The first switching transistor ST1 may be changed from an off state to an on state, and the second switching transistor ST2 may maintain an off state. The fourth period T4 may be shorter than the first period T1 or the third period T3.

[0059] Since the first switch transistor ST1 is in the on state, the data voltage Vdata applied to the data line DL can be applied to the first node n1 through the first switch transistor ST1. Therefore, both the initialization voltage Vinit and the data voltage Vdata can be provided through the first switch transistor ST1, and the initialization voltage Vinit and the data voltage Vdata may not be provided through different switch transistors. Therefore, the number of transistors in the pixel circuit can be reduced, and thus the transmittance can be improved.

[0060] In addition, the data voltage Vdata is applied to the first node n1 through the first switching transistor ST1, and the gate voltage of the driving transistor DT connected to the first node n1 may decrease from the initialization voltage Vinit to the data voltage Vdata. For example, the voltage of the first node n1 may decrease by "Vinit-Vdata".

[0061] The voltage change amount of the first node n1 may be reflected in the second node n2 through the storage capacitor Cst, and "Vinit-Vdata" as the voltage change amount of the first node n1 may be reflected in the second node n2. In this case, since the second node n2 is connected between the storage capacitor Cst and the light emitting element LED, the voltage of the second node n2 may be reduced by a portion of "Vinit-Vdata" due to a coupling effect. Specifically, the voltage change amount may be reflected in the second node n2 at a ratio of α as shown in the following equation 1. In equation 1, C1 may be the capacitance of the storage capacitor Cst, and C2 may be the capacitance of the light emitting element LED.

[0062] Equation 1:

[0063] Therefore, the voltage of the second node n2 decreases by α(Vinit-Vdata), and thus the voltage of the second node n2 may be "Vinit+|Vth|-α(Vinit-Vdata)". Finally, the magnitude of the gate-source voltage Vgs of the driving transistor DT is as shown in the following equation 2. In this case, β may be 1-α. β may be The gate-source voltage Vgs of the following Equation 2 may be stored in the storage capacitor Cst.

[0064] Equation 2: Vgs = Vth + β (Vinit - Vdata)

[0065] Therefore, the threshold voltage Vth of the driving transistor is compensated by an amount of β(Vinit-Vdata).

[0066] Figure 8 is a circuit diagram showing driving of a pixel in a fifth period according to an embodiment of the present disclosure. The fifth period T5 may be a light emitting period.

[0067] In the fifth period T5, the scan signal Scan supplied to the first switching transistor ST1 may change from a low voltage state to a high voltage state, and the sensing signal Sense supplied to the second switching transistor ST2 may maintain a high voltage state. The first switching transistor ST1 may change from an on state to an off state, and the second switching transistor ST2 may maintain an off state.

[0068] Since the first switching transistor ST1 and the second switching transistor ST2 are in the off state, a current I corresponding to the gate-source voltage Vgs of the driving transistor DT may flow through the light emitting diode LED. The light emitting diode LED may emit light. The gate-source voltage Vgs of the driving transistor DT may be maintained for 1 frame by the storage capacitor Cst.

[0069] In addition, the current I provided to the LED by the driving transistor DT is shown in the following equation 3. In the following equation 3, k may be a proportionality coefficient determined by the structure and physical characteristics of the driving transistor DT. The proportionality coefficient may be determined by the electron mobility, channel width, channel length, etc. of the driving transistor DT.

[0070] Equation 3: I = k(Vgs-Vth) 2

[0071] When the gate-source voltage Vgs derived from the above Equation 2 is reflected in Equation 3, the following Equation 4 can be derived.

[0072] Equation 4: I = k{β(Vinit - Vdata)} 2

[0073] Referring to Equation 4, the current I provided to the light emitting element LED of the driving transistor DT may not be affected by the threshold voltage Vth and may be determined by the capacitance C1 of the storage capacitor Cst, the initialization voltage Vinit, and the data voltage Vdata. By adjusting the capacitance C1 of the storage capacitor Cst, the initialization voltage Vinit, or the data voltage Vdata, the threshold voltage Vth of the driving transistor DT may be compensated at a predetermined ratio.

[0074] As described herein, even if the characteristic of the threshold voltage Vth of the driving transistor DT changes due to degradation, the deviation of the current I supplied to the light emitting diode LED of the driving transistor DT can be prevented. Therefore, the degradation of image quality due to the change in the characteristic of the threshold voltage Vth can be prevented.

[0075] As described above, the present disclosure has the effect of improving light transmittance by reducing the number of transistors and the number of wirings while preventing degradation of image quality due to changes in the characteristics of the threshold voltage Vth.

[0076] Fig. 9 is a block diagram of a plurality of pixels according to the first embodiment of the present disclosure and the second embodiment of the present disclosure.

[0077] refer to Fig. 9 , Fig. 9 A first pixel P1, a second pixel P2, a third pixel P3, and a fourth pixel P4 among a plurality of pixels are shown. In this case, a plurality of pixels may be arranged in a matrix form. Specifically, the first pixel P1 and the second pixel P2 may be arranged in the same row, and the third pixel P3 and the fourth pixel P4 may be arranged in the same row. In addition, the first pixel P1 and the third pixel P3 may be arranged in the same column, and the second pixel P2 and the fourth pixel P4 may be arranged in the same column.

[0078] The first scan signal Scan1 may be applied to the first pixel P1 and the second pixel P2 through the first gate line GL1, and the second scan signal Scan2 may be applied to the third pixel P3 and the fourth pixel P4 through the second gate line GL2. In addition, the first sensing signal Sense1 may be applied to the first pixel P1 and the second pixel P2 through the first sensing line SL1, and the second sensing signal Sense2 may be applied to the third pixel P3 and the fourth pixel P4 through the second sensing line SL2. One gate line GL may apply the scan signal Scan to pixels arranged in the same row, and one sensing line SL may apply the sensing signal Sense to pixels arranged in the same row.

[0079] Fig.10 is a diagram of waveforms of a signal in a first horizontal period and a second horizontal period according to the first embodiment of the present disclosure.

[0080] refer to Fig.10 , each of the first horizontal period H1 and the second horizontal period H2 may include Figures 3 to 8 . As described above, each of the first to fourth periods T1 to T4 may be a reset period, a sensing period, a data conversion period, and a write period. In addition, the second horizontal period H2 may not overlap or be spaced apart from the first horizontal period H1, but may be continuous or uninterrupted with the first horizontal period H1.

[0081] In the first horizontal period H1, the voltage states of the first scanning signal Scan1 and the first sensing signal Sense1 may change. Specifically, the first sensing signal Sense1 may be in a low voltage state in the first period T1, and may be in a high voltage state in the second period T2 to the fourth period T4. In addition, the first scanning signal Scan1 may be in a low voltage state in the first period T1, the second period T2, and the fourth period T4, and may be in a high voltage state in the third period T3. In addition, in the first horizontal period H1, the second scanning signal Scan2 and the second sensing signal Sense2 may maintain a high voltage state. In the first horizontal period H1, the first pixel P1 and the second pixel P2 may be driven according to the voltage states of the first scanning signal Scan1 and the first sensing signal Sense1, and the third pixel P3 and the fourth pixel P4 may not be driven.

[0082] In addition, in the second horizontal period H2, the voltage states of the second scanning signal Scan2 and the second sensing signal Sense2 may change. Specifically, the second sensing signal Sense2 may be in a low voltage state in the first period T1, and may be in a high voltage state in the second period T2 to the fourth period T4. In addition, the second scanning signal Scan2 may be in a low voltage state in the first period T1, the second period T2, and the fourth period T4, and may be in a high voltage state in the third period T3. In addition, in the second horizontal period H2, the first scanning signal Scan1 and the first sensing signal Sense1 may maintain a high voltage state. In the second horizontal period H2, the third pixel P3 and the fourth pixel P4 may be driven according to the voltage states of the second scanning signal Scan2 and the second sensing signal Sense2, and the first pixel P1 and the second pixel P2 may not be driven.

[0083] Therefore, the pixels arranged in the same row may be driven according to the first to fourth periods T1 to T4 in one horizontal period. Therefore, the pixels arranged in the same row may perform the sensing period and the writing period in one horizontal period.

[0084] Fig.11is a diagram of waveforms of a signal in a first horizontal period and a second horizontal period according to a second embodiment of the present disclosure.

[0085] refer to Fig.11 , the first horizontal period H1 may include a first period T1 and a second period T2, and the second horizontal period H2 may include a second period T2 to a fourth period T4. In addition, the third period T3 includes a 3-1 period T3-1 and a 3-2 period T3-2, and the fourth period T4 may include a 4-1 period T4-1 and a 4-2 period T4-2. As described above, each of the first period T1 to the fourth period T4 may be a reset period, a sensing period, a data conversion period, and a write period.

[0086] Furthermore, the second horizontal period H2 may not overlap or be spaced apart from the first horizontal period H1 but may be continuous or uninterrupted with the first horizontal period H1. The second period T2 of the first horizontal period H1 and the second period T2 of the second horizontal period H2 may be continuous or uninterrupted with each other.

[0087] In the first horizontal period H1, the voltage states of the first scan signal Scan1 and the second scan signal Scan2 and the voltage states of the first sensing signal Sense1 and the second sensing signal Sense2 may change. Specifically, the first sensing signal Sense1 and the second sensing signal Sense2 may be in a low voltage state in the first period T1, and may be in a high voltage state in the second period T2. In addition, the first scan signal Scan1 and the second scan signal Scan2 may be in a low voltage state in the first horizontal period H1.

[0088] In the first horizontal period H1, since the voltage states of the first and second scan signals Scan1 and Scan2 and the first and second sensing signals Sense1 and Sense2 are equally changed, the first to fourth pixels P1 to P4 may be driven simultaneously. Therefore, in the first horizontal period H1, the first to fourth pixels P1 to P4 may perform the sensing period simultaneously.

[0089] In addition, the voltage states of the first scan signal Scan1 and the second scan signal Scan2 may be changed in the second horizontal period H2. In detail, the first scan signal Scan1 may be in a low voltage state in the second period T2 and the 4-1 period T4-1, and may be in a high voltage state in the 3-1 period T3-1, the 3-2 period T3-2, and the 4-2 period T4-2. In addition, the second scan signal Scan2 may be in a low voltage state in the second period T2 and the 4-2 period T4-2, and may be in a high voltage state in the 3-1 period T3-1, the 4-1 period T4-1, and the 3-2 period T3-2. In addition, in the second horizontal period H2, the first sensing signal Sense1 and the second sensing signal Sense2 may maintain a high voltage state.

[0090] As in the first horizontal period H1, in the second horizontal period H2, the first pixel P1 to the fourth pixel P4 can simultaneously perform the sensing period. In this case, since the first horizontal period H1 and the second horizontal period H2 are continuous, the sensing period can also be continuously performed. In addition, the first pixel P1 and the second pixel P2 can perform the writing period in the 4-1 period T4-1, and the third pixel P3 and the fourth pixel P4 can perform the writing period in the 4-2 period T4-2.

[0091] In a second embodiment, after simultaneously executing the sensing period of the first pixel P1 to the fourth pixel P4, the writing period of the first pixel P1 and the second pixel P2 connected to the first scanning signal Scan1 and the first sensing signal Sense1 and the writing period of the third pixel P3 and the fourth pixel P4 connected to the second scanning signal Scan2 and the second sensing signal Sense2 can be executed sequentially.

[0092] Compared with the first embodiment, the second embodiment can increase the length of the sensing period of the first pixel P1 to the fourth pixel P4 by continuously performing the sensing period in the first horizontal period H1 and the second horizontal period H2. Fig.11 The sensing period is shown to last for two horizontal periods, but is not limited thereto. For example, the sensing period may last for three or more horizontal periods.

[0093] In addition, as mentioned above Fig.11 As described in the second embodiment, the voltage states of the first sensing signal Sense1 and the second sensing signal Sense2 may be changed equally during the first horizontal period H1 and the second horizontal period H2. Fig.12 As shown, the structure of the sensing line SL may be changed.

[0094] In detail, Fig.12 is a block diagram of a plurality of pixels according to a third embodiment of the present disclosure. Fig.12 , the first sensing signal Sense1 may be omitted, and the second sensing signal Sense2 may be applied to all the first to fourth pixels P1 to P4. In this case, the third pixel P3 and the fourth pixel P4 may directly receive the second sensing signal Sense2 from the second sensing line SL2, and the first pixel P1 and the second pixel P2 may receive the second sensing signal Sense2 through the wiring connected to the second sensing line SL2 in the panel.

[0095] Therefore, compared with the first and second embodiments, the third embodiment can further improve the light transmittance of the pixel by reducing the number of sensing lines SL.

[0096] According to the present disclosure, the following advantageous effects can be obtained.

[0097] According to the present disclosure, a plurality of light conversion layers may be formed, so that light efficiency may be improved and reflection due to external light may be reduced.

[0098] It will be apparent to those skilled in the art that the disclosure described above is not limited to the above-mentioned embodiments and drawings, and that various substitutions, modifications and changes may be made in the disclosure without departing from the spirit or scope of the disclosure. Therefore, the scope of the disclosure includes the scope of the appended claims, and it is intended that all changes or modifications derived from the meaning, scope and equivalent concepts of the claims fall within the scope of the disclosure.

[0099] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts from the various embodiments to provide further embodiments.

[0100] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

[0101] CROSS-REFERENCE TO RELATED APPLICATIONS

[0102] This application claims the benefit of Korean Patent Application No. 10-2023-0085161, filed on Jun. 30, 2023, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A display device, comprising: A display panel is provided with a gate line, a sensing line, a data line and a plurality of pixels, and Wherein, each pixel of the plurality of pixels comprises: a first switching transistor configured to operate based on a scan signal applied through the gate line; a second switching transistor configured to operate based on a sensing signal applied through the sensing line; a driving transistor including a gate connected to the first node, a source connected to the second node, and a drain connected to a low potential voltage line configured to provide a low potential voltage; a light emitting device including an anode connected to a high potential voltage line configured to provide a high potential voltage and a cathode connected to the second node; and A storage capacitor is connected between the first node and the second node.

2. The display device according to claim 1, wherein: The first switch transistor includes a gate connected to the gate line, a source connected to the data line, and a drain connected to the first node, and The second switch transistor includes a gate connected to the sensing line, a source connected to the high potential voltage line, and a drain connected to the second node.

3. The display device according to claim 2, wherein: The first switch transistor is configured to provide a data voltage or an initialization voltage to the first node, The data line is configured to receive the data voltage or the initialization voltage.

4. The display device according to claim 3, wherein: The amplitude of the data voltage is smaller than the amplitude of the initialization voltage.

5. A method for driving a display device, the display device comprising a display panel, on which a gate line, a sensing line, a data line and a plurality of pixels are arranged, the method comprising the following steps: During a first period, turning on the first switching transistor and the second switching transistor to initialize a voltage stored in the storage capacitor by an initialization voltage applied to the data line; During a second period, sensing a threshold voltage of the drive transistor; During a third period, applying a data voltage to the data line; During a fourth period, compensating the threshold voltage of the driving transistor; as well as During the fifth period, light is emitted by the light emitting element.

6. The method for driving a display device according to claim 5, wherein: In the first period, the initialization voltage applied to the data line is provided to the gate of the driving transistor through the first switching transistor, a high potential voltage is provided to the source of the driving transistor through the second switching transistor, and the storage capacitor is initialized to a differential voltage between the initialization voltage and the high potential voltage.

7. The method for driving a display device according to claim 5, wherein: In the second period, the first switching transistor maintains an on state, the second switching transistor changes from an on state to an off state, the voltage of the gate of the driving transistor is maintained, and the voltage of the source of the driving transistor decreases.

8. The method for driving a display device according to claim 7, wherein: In the second period, the magnitude of the gate-source voltage of the driving transistor is equal to the magnitude of the threshold voltage of the driving transistor.

9. The method for driving a display device according to claim 7, wherein: In the second period, the storage capacitor stores the threshold voltage of the driving transistor.

10. The method for driving a display device according to claim 5, wherein: In the third period, the first switching transistor changes from the on state to the off state, the second switching transistor maintains the off state, and the data voltage different from the initialization voltage is applied to the data line.

11. The method for driving a display device according to claim 5, wherein: In the fourth period, the first switching transistor changes from an off state to an on state, the second switching transistor maintains an off state, and the data voltage applied to the data line is supplied to the gate of the driving transistor through the first switching transistor.

12. The method for driving a display device according to claim 5, wherein: In the fifth period, the first switching transistor changes from the on state to the off state, the second switching transistor maintains the off state, and the light emitting element emits light according to a current having a current value based on the initialization voltage and the data voltage.

13. The method for driving a display device according to claim 5, wherein: The first period, the second period, the third period, and the fourth period are included in each of the first horizontal period and the second horizontal period, and The first horizontal period and the second horizontal period are continuous.

14. The method for driving a display device according to claim 13, wherein: The first time period, the second time period, the third time period and the fourth time period are continuous.

15. The method for driving a display device according to claim 13, wherein: The plurality of pixels include a first pixel, a second pixel, a third pixel and a fourth pixel, The gate line includes a first gate line and a second gate line, The sensing line includes a first sensing line and a second sensing line, The first gate line and the first sensing line provide signals to the first pixel and the second pixel in the first horizontal period, and The second gate line and the second sensing line provide signals to the third pixel and the fourth pixel in the second horizontal period.

16. The method for driving a display device according to claim 5, wherein: The first period and the second period are included in a first horizontal period, The second period, the third period, and the fourth period are included in a second horizontal period, and The first horizontal period and the second horizontal period are continuous.

17. The method for driving a display device according to claim 16, wherein: The plurality of pixels include a first pixel, a second pixel, a third pixel and a fourth pixel, The gate lines include a first gate line and a second gate line, and The sensing line includes a first sensing line and a second sensing line, In the first horizontal period, the first gate line and the first sensing line provide signals to the first pixel and the second pixel, and the second gate line and the second sensing line provide signals to the third pixel and the fourth pixel.

18. The method for driving a display device according to claim 17, wherein: In the first horizontal period, the first gate line and the second gate line provide the same signal, and The first sensing line and the second sensing line provide the same signal.

19. The method for driving a display device according to claim 15, wherein: In the second horizontal period, the third period includes a 3-1 period and a 3-2 period, In the second horizontal period, the fourth period includes a 4-1 period and a 4-2 period, The first gate line and the first sensing line provide a signal to the first pixel and the second pixel in each of the 3-1 period and the 4-1 period, The second gate line and the second sensing line provide signals to the third pixel and the fourth pixel in each of the 3-2 period and the 4-2 period.

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