A high-reliability and high-heat dissipation packaging method for high-power chips

Abstract

The present invention belongs to the technical field of integrated circuit packaging, and particularly relates to a high-reliability and high-heat dissipation packaging method for high-power chips. The method comprises the following steps: providing a silicon wafer, etching a pattern on the front side of the silicon wafer using a photolithography process, and then etching a cavity using a dry etching process; providing a heterogeneous chip, loading the heterogeneous chip into the cavity using a high-precision chip mounter, and using a dry film material to fill the gap between the heterogeneous chip and the cavity; using a rewiring process on the front side of the silicon wafer to form a passivation layer, a metal rewiring layer and a conductive through hole; using a dicing process to scribe the silicon wafer along a dicing path. The present invention covers the front and back sides and the surrounding sides of the package to ensure the reliability of the package. At the same time, by making a metal heat dissipation layer with a high thermal conductivity on the back side of the chip as a heat dissipation path, the problem that the chip cannot effectively dissipate heat when buried in the package is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit packaging, and in particular relates to a high-reliability and high-heat dissipation packaging method for a high-power chip. Background Art

[0002] With the rapid development of science and technology, large-size, high-power chips are increasingly used in high-performance computers, data centers, artificial intelligence and other fields. These chips have higher power consumption and heat generation due to their high performance and large-scale integration. If the heat cannot be dissipated in a timely and effective manner, the chip performance will be reduced or even damaged.

[0003] Traditional heat dissipation materials, such as heat sinks and fans, can reduce chip temperature to a certain extent, but these traditional methods are often inadequate when faced with extremely high power consumption chips. Therefore, as products continue to develop towards high integration and thinness, the heat dissipation problem of products has become an urgent problem to be solved in the current scientific and technological community. Summary of the invention

[0004] The object of the present invention is to provide a high-reliability and high-heat dissipation packaging method for a high-power chip, so as to solve the heat dissipation problem of the above-mentioned high-power chip.

[0005] In order to solve the above technical problems, the present invention provides a high-reliability and high-heat dissipation packaging method for a high-power chip, comprising the following steps:

[0006] Step 1: providing a silicon wafer, photolithography a pattern on the front side of the silicon wafer using a photolithography process, and then etching a cavity using a dry etching process;

[0007] Step 2: providing a heterogeneous chip, loading the heterogeneous chip into the cavity using a high-precision chip mounter, and filling the gap between the heterogeneous chip and the cavity with a dry film material;

[0008] Step 3: forming a passivation layer, a metal rewiring layer and a conductive via on the front side of the silicon wafer using a rewiring process;

[0009] Step 4: using a dicing process to diced the silicon wafer along dicing lanes to form a single package;

[0010] Step 5: Arrange a plurality of the single package bodies in an array as required, and encapsulate them with a plastic encapsulation material to form a plastic encapsulation carrier; the plastic encapsulation carrier uses a resin-based round sheet or a resin-based square sheet as a resin base;

[0011] Step 6: Using a thinning process, thinning the back side of the plastic package carrier to expose the back side of the heterogeneous chip;

[0012] Step 7: Making a metal heat dissipation layer with high thermal conductivity on the back side of the heterogeneous chip;

[0013] Step eight: solder balls are implanted on the conductive through holes exposed on the front side of the plastic package carrier using a ball implantation process; finally, the plastic package carrier is diced along dicing lines using a dicing process to form a final package.

[0014] Preferably, in step one, the size of the silicon wafer is 6 inches, 8 inches or 12 inches, the number of the cavities is multiple, the size of the cavities is determined according to the size of the heterogeneous chip, and the depth is above 10 μm.

[0015] Preferably, in step 2, the heterogeneous chip is loaded into the cavity by a high-precision chip mounter, with the pad of the heterogeneous chip facing outwards. After the heterogeneous chip is buried, the height of the heterogeneous chip has an error of no more than 5 μm with respect to the height of the front side of the silicon wafer as a reference plane.

[0016] Preferably, in the step three, a passivation layer, a metal rewiring layer and a conductive via are formed by photolithography, sputtering and electroplating processes; wherein the passivation layer is a polyimide material with a thickness of more than 5 μm, and the metal rewiring layer is one or more layers with a thickness of more than 3 μm.

[0017] Preferably, the dry film material in step 2 and the plastic packaging material in step 5 are both polymer materials including resins and polyimides.

[0018] Preferably, in step seven, the material of the metal heat dissipation layer with high thermal conductivity is one or more of nano silver paste, nano copper paste, solder, solder sheet or conductive glue.

[0019] Preferably, in step eight, the material of the solder ball is CuSn, CuNiSn, CuNiSnAg, SnPb or SnAgCu.

[0020] The present invention also provides a high-reliability and high-heat dissipation packaging structure of a high-power chip, which is manufactured by using the high-reliability and high-heat dissipation packaging method of a high-power chip as described above.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. The present invention buries the chip in the package body, and the heat is easily concentrated inside the packaging material. By making a metal heat dissipation layer with a high thermal conductivity on the back of the chip as a heat dissipation path, the heat dissipation efficiency of the chip is increased, and the heat dissipation capacity of the high-power chip package is greatly improved.

[0023] 2. The present invention also adopts resin injection molding or silicon cavity fan-out packaging process methods, which avoids the warping problem in the resin-based packaging process that leads to high processing difficulty and low yield. At the same time, the passivation layer on the surface of the package body is coated with resin to ensure the reliability of the package body.

[0024] 3. The front, back and surrounding sides of the chip of the present invention are all covered, which can effectively protect the chip. The packaged chip is not easily scratched, collided or damaged during cutting, and the yield rate is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of silicon-based multi-cavity etching in the method of the present invention.

[0026] Figure 2 It is a schematic diagram of silicon-based fan-out multi-chip loading in the method of the present invention.

[0027] Figure 3 It is a schematic diagram of a wafer-level multi-layer wiring layer structure in the method of the present invention.

[0028] Figure 4 It is a schematic diagram of completing the six-sided plastic sealing in the method of the present invention.

[0029] Figure 5 It is a schematic diagram of the back surface after thinning in the method of the present invention.

[0030] Figure 6 It is a schematic diagram of coating a highly heat-dissipating conductive material in the method of the present invention.

[0031] Figure 7 It is a schematic diagram after ball implantation is completed in the method of the present invention.

[0032] In the figure: 101-silicon wafer, 102-cavity, 103-heterogeneous chip, 104-dry film material, 105-passivation layer, 106-metal redistribution layer, 107-conductive via, 108-plastic encapsulation carrier, 109-metal heat dissipation layer, 110-solder ball. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0034] like Figure 1 to Figure 7 As shown, the embodiment of the present invention specifically provides a high-reliability and high-heat dissipation packaging method for a high-power chip, comprising the following steps:

[0035] 1) Provide a silicon wafer 101, photolithography a pattern on the front side of the silicon wafer 101 by using a photolithography process, and then use a dry etching process to etch a cavity 102, such as Figure 1 As shown; specifically, the size of the silicon wafer 101 is 6 inches, 8 inches or 12 inches, the number of the cavities 102 is multiple, the size of the cavities 102 is determined according to the chip size, and the depth is above 10μm.

[0036] 2) Providing a heterogeneous chip 103, loading the heterogeneous chip 103 into the cavity 102 using a high-precision chip mounter, and filling it with a dry film material 104, such as Figure 2 As shown; specifically, the pad surface of the heterogeneous chip 103 faces outward, and the height of the chip formed after the chip is buried has an error of no more than 5μm with the height of the front silicon base plane of the silicon wafer 101; wherein the dry film material 104 is a polymer material including resins and polyimides.

[0037] 3) On the front side of the silicon wafer 101, a rewiring process is used to form a passivation layer 105, a metal rewiring layer 106 and a conductive via 107, such as Figure 3 As shown, the method of forming the passivation layer 105, the metal rewiring layer 106 and the conductive via 107 specifically includes photolithography, sputtering and electroplating processes. The passivation layer is a polyimide material with a thickness of more than 5μm, and the rewiring layer is one or more layers with a thickness of more than 3μm.

[0038] 4) Using a dicing process, the silicon wafer 101 is diced along dicing lanes into individual packages.

[0039] 5) Arrange a plurality of single package bodies in an array as required, and encapsulate them by encapsulating them with a plastic encapsulation material to form a resin-based round sheet or a resin-based square sheet as a resin base, and finally obtain a plastic encapsulation carrier 108, such as Figure 4 The plastic packaging material is a polymer material including resin and polyimide.

[0040] 6) Using a thinning process, thin the back side of the plastic package carrier 108 to expose the back side of the heterogeneous chip 103, such as Figure 5 As shown;

[0041] 7) A metal heat dissipation layer 109 with high thermal conductivity is fabricated on the back of the heterogeneous chip 103, such as Figure 6 The material of the metal heat dissipation layer 109 with high thermal conductivity is one or more of nano silver paste, nano copper paste, solder, solder sheet or conductive glue.

[0042] 8) Using a ball planting process, solder balls 110 are planted on the conductive through holes 107 exposed on the front side of the plastic package carrier 108; the material of the solder balls 110 is CuSn, CuNiSn, CuNiSnAg, SnPb or SnAgCu. Finally, using a dicing process, the plastic package carrier 108 is diced along the dicing path to form a final package body, such as Figure 7 shown.

[0043] In summary, the present invention etches a plurality of cavities on the front side of a silicon wafer, mounts the functional side of a heterogeneous high-power chip into the cavity in a certain arrangement with the functional side facing upward, and fills the gap between the chip and the cavity with a dry film material. The chip signal is led out by rewiring, and at least one or more layers of rewiring are made. The silicon wafer is diced and cut to obtain a single product. Several single products are molded with a resin molding compound to form a plastic encapsulation carrier, the back of the plastic encapsulation carrier exposes the back of the chip, and a high heat dissipation layer is set on the back of the chip. Using a wafer-level ball planting process, balls are planted at the metal layer under the balls of the multi-layer wiring on the front side of the silicon wafer; finally, the wafer is diced to form a final package. The present invention simultaneously adopts resin injection molding and silicon cavity fan-out packaging process methods, and the front, back and surrounding sides of the package are all covered to ensure the reliability of the package. At the same time, a metal heat dissipation layer with a high thermal conductivity is made on the back of the chip as a heat dissipation path, which solves the problem that the chip buried in the package cannot effectively dissipate heat.

[0044] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high-reliability and high-heat dissipation packaging method for high-power chips, characterized in that: The steps include: Step 1: providing a silicon wafer, photolithography a pattern on the front side of the silicon wafer using a photolithography process, and then etching a cavity using a dry etching process; Step 2: providing a heterogeneous chip, loading the heterogeneous chip into the cavity using a high-precision chip mounter, and filling the gap between the heterogeneous chip and the cavity with a dry film material; Step 3: forming a passivation layer, a metal rewiring layer and a conductive via on the front side of the silicon wafer using a rewiring process; Step 4: using a dicing process to diced the silicon wafer along dicing lanes to form a single package; Step 5: Arrange a plurality of the single package bodies in an array as required, and encapsulate them with a plastic encapsulation material to form a plastic encapsulation carrier; the plastic encapsulation carrier uses a resin-based round sheet or a resin-based square sheet as a resin base; Step 6: Using a thinning process, thinning the back side of the plastic package carrier to expose the back side of the heterogeneous chip; Step 7: Making a metal heat dissipation layer with high thermal conductivity on the back side of the heterogeneous chip; Step 8: solder balls are implanted on the conductive through holes exposed on the front side of the plastic package carrier using a ball implantation process; finally, the plastic package carrier is diced along dicing paths using a dicing process to form a final package; In the step 3, a passivation layer, a metal rewiring layer and a conductive via are formed by photolithography, sputtering and electroplating processes; wherein the passivation layer is a polyimide material with a thickness of 5 μm or more, and the metal rewiring layer is one or more layers with a thickness of 3 μm or more; The dry film material in step 2 and the plastic packaging material in step 5 are both polymer materials including resins and polyimides.

2. A high-reliability and high-heat dissipation packaging method for a high-power chip as claimed in claim 1, characterized in that: In the step 1, the size of the silicon wafer is 6 inches, 8 inches or 12 inches, the number of the cavities is multiple, the size of the cavity is determined according to the size of the heterogeneous chip, and the depth is above 10 μm.

3. A high-reliability and high-heat dissipation packaging method for a high-power chip as claimed in claim 1, characterized in that: In the step 2, the heterogeneous chip is loaded into the cavity by a high-precision chip mounter, with the pad of the heterogeneous chip facing outward. After the heterogeneous chip is buried, the height of the heterogeneous chip has an error of no more than 5 μm with respect to the height of the front side of the silicon wafer as a reference plane.

4. A high-reliability and high-heat dissipation packaging method for a high-power chip as claimed in claim 1, characterized in that: In the step seven, the material of the metal heat dissipation layer with high thermal conductivity is one or more of nano silver paste, nano copper paste, solder, solder sheet or conductive glue.

5. A high-reliability and high-heat dissipation packaging method for a high-power chip as claimed in claim 1, characterized in that: In the step eight, the material of the solder ball is CuSn, CuNiSn, CuNiSnAg, SnPb or SnAgCu.

6. A high-reliability and high-heat dissipation packaging structure for a high-power chip, characterized in that: The high-power chip is manufactured by adopting a high-reliability and high-heat dissipation packaging method as described in any one of claims 1 to 5.

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