An integrated longitudinal device SOI semiconductor structure and method of manufacturing the same

Abstract

The application relates to an SOI semiconductor structure integrated with longitudinal devices and a manufacturing method thereof, the method comprising the following steps: obtaining a wafer, the wafer comprising a substrate, a buried dielectric region on the substrate and a top semiconductor layer on the buried dielectric region; patterning the wafer to expose the substrate of a longitudinal device region; forming a first insulating isolation part on the side of the longitudinal device region; epitaxially forming a first conductive type region outside the longitudinal device region; forming a CMOS device main body in the first device region and a first well region and a first source region in the longitudinal device region through a CMOS process; the first well region is formed in the first conductive type region, and the first source region is formed in the first well region; and forming a first drain region at the bottom of the substrate. The depletion region of the second conductive type can optimize the electric field of the longitudinal device, the area of the depletion region is reduced, and the chip area is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to an SOI semiconductor structure with integrated vertical devices, and also to a method for manufacturing an SOI semiconductor structure with integrated vertical devices. Background Technology

[0002] BCD (Bipolar-CMOS-DMOS) technology is a monolithic integration process that enables the fabrication of bipolar transistors, CMOS (metal-oxide-semiconductor field-effect transistors), and DMOS (double-diffused metal-oxide-semiconductor field-effect transistors) devices on a single chip. Devices fabricated using this process combine the high transconductance and strong load driving capability of bipolar devices with the high integration density and low power consumption of CMOS. Simultaneously, DMOS can handle higher voltages and operates with extremely low power consumption in switching mode, delivering high power to the load without the need for expensive packaging and cooling systems. This technology has been widely applied in automotive electronics, power management, lighting, and radio frequency communications. The DMOS, responsible for the power section, is the core of these circuits because it needs to handle relatively large currents and voltages, often occupying 30%-90% of the total area, making it crucial to the entire integrated circuit.

[0003] In the exemplary BCD process, the DMOS used is a lateral channel LDMOS (laterally diffused metal-oxide-semiconductor field-effect transistor). For LDMOS, the drift region needs to withstand the voltage, so for devices with high voltage withstand requirements, the drift region needs to be long enough to withstand the voltage, resulting in a larger device size. Summary of the Invention

[0004] Therefore, it is necessary to provide an SOI semiconductor structure with integrated vertical devices and its manufacturing method.

[0005] An SOI semiconductor structure integrating vertical devices includes: a substrate having a first conductivity type; a buried dielectric region disposed on the substrate; a first conductivity type region disposed in a region on the substrate without the buried dielectric region; a second conductivity type region disposed on the buried dielectric region, wherein the first conductivity type and the second conductivity type are opposite conductivity types; a first device body disposed on the buried dielectric region; the vertical device body including a first well region, a first source region, a first drain region, and a first gate, wherein the first well region has a second conductivity type and is disposed in the first conductivity type region, the first source region is disposed in the first well region, and the first drain region is disposed at the bottom of the substrate; and an isolation structure including a first insulating isolation portion and a depletion region, wherein the depletion region is located between the second conductivity type region and the first conductivity type region, the bottom of the first insulating isolation portion reaches the buried dielectric region, the depletion region and the first conductivity type region are separated by the first insulating isolation portion, the depletion region is located between the first insulating isolation portion and the second conductivity type region, and the depletion region has a second conductivity type.

[0006] The aforementioned SOI semiconductor structure integrating vertical devices integrates relatively small vertical devices (for reference, VDMOS has a smaller area than LDMOS), thus enabling devices with higher power density. The isolation structure between the first device and the vertical devices employs a structure where a depletion region of a second conductivity type cooperates with a first insulating isolation portion. The depletion region of the second conductivity type can optimize the electric field of the vertical devices, thereby reducing the area of ​​the depletion region and shrinking the chip area.

[0007] In one embodiment, the withstand voltage of the longitudinal device is greater than that of the first device.

[0008] In one embodiment, the longitudinal device is a high-voltage device, and the first device is a low-voltage device.

[0009] In one embodiment, the isolation structure further includes a second insulating isolation portion, the depletion region being located between the first insulating isolation portion and the second insulating isolation portion, the bottom of the second insulating isolation portion reaching the buried medium region.

[0010] In one embodiment, the first insulating isolation portion is disposed near the first conductivity type region, and the second insulating isolation portion is disposed near the second conductivity type region.

[0011] In one embodiment, the vertical device is a VDMOS device, the first source region and the first drain region have a first conductivity type, and the doping concentration of the first drain region is greater than the doping concentration of the substrate.

[0012] In one embodiment, the first device body is the body of a CMOS device, and the first device body includes: a CMOS well region having a second conductivity type and disposed above the buried dielectric region; a CMOS source region having a first conductivity type and disposed in the CMOS well region; a CMOS drain region having a first conductivity type and disposed in the CMOS well region; and a CMOS gate disposed on the CMOS well region between the CMOS source region and the CMOS drain region.

[0013] In one embodiment, the CMOS source region, the CMOS drain region, and the first source region are located on the same horizontal plane in the SOI semiconductor structure.

[0014] In one embodiment, the second insulating isolation portion is a closed ring structure that surrounds the second conductivity type region in the lateral direction.

[0015] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0016] A method for manufacturing an SOI semiconductor structure with integrated vertical devices includes: obtaining a wafer, the wafer including a substrate, a buried dielectric region on the substrate, and a top semiconductor layer on the buried dielectric region; the substrate having a first conductivity type, the top semiconductor layer having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; patterning the wafer to remove the top semiconductor layer and the buried dielectric region of the vertical device region to expose the substrate of the vertical device region; forming a first insulating isolation portion on the side of the vertical device region; epitaxially forming a first conductivity type region on the vertical device region; forming a CMOS device body on the top semiconductor layer and forming a first well region and a first source region on the vertical device region using a CMOS process; the first well region being formed in the first conductivity type region, the first well region having a second conductivity type, and the first source region being formed in the first well region; in the top semiconductor layer, the portion located between the first insulating isolation portion and the CMOS device body serving as a depletion region; and forming a first drain region on the bottom of the substrate.

[0017] The aforementioned method for manufacturing an SOI semiconductor structure with integrated vertical devices enables the integration of relatively small vertical devices, thereby achieving devices with higher power density. The depletion region of the second conductivity type optimizes the electric field of the vertical devices, thereby reducing the area of ​​the depletion region and shrinking the chip area.

[0018] In one embodiment, the step of patterning the wafer further includes forming an isolation trench that divides the top semiconductor layer into a first device region and a depletion region, the depletion region being located between the isolation trench and the first insulating isolation portion; the step of forming the first insulating isolation portion on the side of the vertical device region includes depositing an insulating dielectric material on the front side of the wafer, thereby filling the isolation trench with the insulating dielectric material to form a second insulating isolation portion, and forming the first insulating isolation portion on the side of the vertical device region; the step of forming a CMOS device body on the top semiconductor layer using a CMOS process is to form the CMOS device body in the first device region.

[0019] In one embodiment, the wafer acquisition step further includes a dielectric layer on the top semiconductor layer; after the step of epitaxially forming a first conductivity type region in the vertical device region and before forming the CMOS device body, the step further includes removing the dielectric layer.

[0020] In one embodiment, the critical dimension of the isolation groove is 0.8 to 2 micrometers.

[0021] In one embodiment, the step of forming a CMOS device body in the first device region using a CMOS process includes: forming a CMOS well region, a CMOS source region, a CMOS drain region, and a CMOS gate using a CMOS process; the CMOS well region has a second conductivity type and is formed above the buried dielectric region; the CMOS source region and the CMOS drain region have a first conductivity type and are formed in the CMOS well region; the CMOS gate is formed on the CMOS well region between the CMOS source region and the CMOS drain region; the first source region and the first drain region have a first conductivity type, and the doping concentration of the first drain region is greater than the doping concentration of the substrate.

[0022] In one embodiment, the step of patterning the wafer, removing the top semiconductor layer and buried dielectric region of the vertical device region to expose the substrate of the vertical device region, and simultaneously forming an isolation trench that separates the first device region from the vertical device region, wherein the top semiconductor layer between the isolation trench and the vertical device region serves as a depletion region, is performed by removing the top semiconductor layer and buried dielectric region of the vertical device region and forming the isolation trench through photolithography and etching. Furthermore, the photolithography and etching of the vertical device region and the isolation trench are performed using the same photomask and in the same etching step.

[0023] In one embodiment, the step of filling the isolation trench with insulating dielectric material includes depositing the insulating dielectric material on the front side of the wafer, the deposition forming a second insulating isolation portion on both sides of the longitudinal device region.

[0024] In one embodiment, the voltage withstand capability of the vertical device is greater than that of the CMOS device.

[0025] In one embodiment, the vertical device is a VDMOS device, the first source region and the first drain region have a first conductivity type, and the doping concentration of the first drain region is greater than the doping concentration of the substrate.

[0026] In one embodiment, the second trench has a closed loop structure.

[0027] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type. Attached Figure Description

[0028] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0029] Figure 1 This is a flowchart of a method for manufacturing an SOI semiconductor structure with integrated vertical devices according to an embodiment of this application;

[0030] Figures 2a to 2d It is based on Figure 1 A cross-sectional schematic diagram of the device during the manufacturing process shown in the diagram;

[0031] Figure 3 This is a cross-sectional schematic diagram of an SOI semiconductor structure integrating vertical devices in one embodiment of this application;

[0032] Figure 4 This is a flowchart of a method for manufacturing an SOI semiconductor structure with integrated vertical devices according to another embodiment of this application;

[0033] Figures 5a to 5e It is based on Figure 4 A cross-sectional schematic diagram of the device during the manufacturing process shown in the diagram;

[0034] Figure 6 This is a cross-sectional schematic diagram of an SOI semiconductor structure integrating vertical devices in another embodiment of this application. Detailed Implementation

[0035] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] It should be understood that when a component or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers. The term "connection" in this specification, if referring to the transmission of electrical signals or data between connected circuits, modules, units, etc., should be understood as "electrical connection," "communication connection," etc. It should be understood that although the terms first, second, third, etc., may be used to describe various components, parts, areas, layers, and / or portions, these components, parts, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one component, part, area, layer, or portion from another component, part, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer or portion discussed below may be represented as a second element, component, region, layer or portion.

[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be understood that “at least one” means one or more, and “a plurality” means two or more. “At least a portion of an element” means part or all of an element. It should also be understood that the terms “compose” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0041] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0042] With the widespread application of very large-scale integrated circuits (VLSI) in various fields, the requirements for high-voltage, high-power semiconductor devices are becoming increasingly stringent. Integrated high-voltage devices utilizing silicon-on-insulator (SOI) technology combine the advantages of SOI technology and the devices themselves, offering high operating speed, low parasitic effects, high breakdown voltage, simple fabrication, and convenient integration, thus attracting widespread research and application. This application proposes a process method for integrating vertically diffused double-diffused metal-oxide-semiconductor (VDMOS) devices on an SOI substrate. This method integrates VDMOS devices with low on-resistance, small area, and high breakdown voltage into a BCD process platform, achieving higher power density DMOS. Furthermore, because VDMOS can be packaged together with integrated CMOS, complex circuits can be further miniaturized.

[0043] Figure 1 This is a flowchart of a method for manufacturing an SOI semiconductor structure with integrated vertical devices according to an embodiment of this application, including the following steps:

[0044] S110, acquire wafer.

[0045] See Figure 2a The wafer includes a substrate 12, a buried dielectric region 20 on the substrate 12, and a top semiconductor layer 14 on the buried dielectric region 20. The substrate 12 has a first conductivity type, and the top semiconductor layer 14 has a second conductivity type. In one embodiment of this application, the first conductivity type is N-type, the second conductivity type is P-type, and the top semiconductor layer 14 is a P+ region. In other embodiments of this application, the first conductivity type may be P-type, and the second conductivity type may be N-type. In one embodiment of this application, the thickness of the top semiconductor layer 14 is 1 to 5 micrometers.

[0046] In one embodiment of this application, the substrate 12 is a silicon substrate with a high doping concentration. In an SOI semiconductor structure, the isolation region between adjacent devices is depleted from the device end towards the substrate 12. Using a substrate 12 with a high doping concentration results in a narrower depletion region, thus allowing the distance between two adjacent devices to be closer (i.e., a narrower isolation region), and consequently, a smaller device area. In one embodiment of this application, the doping concentration of the substrate 12 is controlled to achieve a resistivity of 8 to 45 Ω×cm.

[0047] In one embodiment of this application, the buried medium region 20 is a buried oxide layer, which may be made of silicon oxide, such as silicon dioxide. In one embodiment of this application, the thickness of the buried medium region 20 is 0.5 to 3 micrometers.

[0048] exist Figure 2aIn the illustrated embodiment, the wafer further includes a dielectric layer 22 on the top semiconductor layer 14. In one embodiment of this application, the dielectric layer 22 may be made of silicon oxide, such as silicon dioxide.

[0049] S120, a patterned wafer, exposes the substrate in the vertical device area.

[0050] The top semiconductor layer 14 and buried dielectric region 20 of the vertical device region are removed, thereby exposing the substrate 12 of the vertical device region.

[0051] See Figure 2a and Figure 2b The patterning in step S120 is formed by photolithography and etching. Specifically, photoresist is coated on the front side of the wafer, and then exposed using a photomask. After development, a photoresist layer 94 is formed. Then, using the photoresist layer 94 as an etching barrier layer, the dielectric layer 22, the top semiconductor layer 14, and the buried dielectric region 20 are etched away. The dielectric layer 22, the top semiconductor layer 14, and the buried dielectric region 20 above the substrate 12 of the vertical device region are etched away, thereby exposing the substrate 12.

[0052] S130, a first insulating isolation portion is formed on the side of the longitudinal device area.

[0053] In one embodiment of this application, step S130 includes depositing an insulating dielectric material on the front side of the wafer after removing the photoresist layer 94. In one embodiment of this application, the deposition of the insulating dielectric material in step S130 is performed using a low-pressure chemical vapor deposition (LPCVD) process with TEOS (tetraethyl orthosilicate) as the reactant.

[0054] In one embodiment of this application, after depositing the insulating dielectric material, it is necessary to remove the insulating dielectric material on the upper surface of the substrate 12 in the vertical device region to expose the substrate 12. In one embodiment of this application, the insulating dielectric material on the upper surface of the substrate 12 is removed by etching (i.e., etching directly without photolithography). After deposition and etching, the insulating dielectric material remaining on both sides of the vertical device region serves as the first insulating isolation portion 26, see [link to relevant documentation]. Figure 2c .

[0055] S140, a first conductivity type region is epitaxially formed on the longitudinal device region.

[0056] exist Figure 2d In the embodiment shown, a first conductivity type epitaxial layer (i.e., first conductivity type region 16) is grown in the longitudinal device region by selective epitaxy.

[0057] In the embodiment where a dielectric layer 22 is formed on the top semiconductor layer 14 in the preceding steps, the dielectric layer 22 will prevent the formation of a silicon epitaxial layer during selective epitaxy. Therefore, the epitaxial layer will only be formed on the substrate 12 at the location not covered by the buried dielectric region 20, the first insulating isolation portion 26 and the second insulating isolation portion 24, and will not be formed on the top semiconductor layer 14 covered by the dielectric layer 22.

[0058] S150 is formed by CMOS process to form the CMOS device body, first well region and first source region.

[0059] The vertical device is a high-voltage device, which is isolated from the CMOS device by a first insulating isolation portion 26. In one embodiment of this application, the vertical device is a VDMOS device, and the first well region 44 and the first source region 46 are the well region and source region of the VDMOS device.

[0060] Specifically, after removing the dielectric layer 22 on the front side of the wafer, a CMOS device body is formed in the first device region using CMOS technology, and a first well region 44 and a first source region 46 are formed in the vertical device region. The first well region 44 is formed in the first conductivity type region 16 and has a second conductivity type, and the first source region 46 is formed in the first well region 44.

[0061] Reference Figure 3 A CMOS well region 54, a CMOS source region 562, a CMOS drain region 564, and a CMOS gate 58 can be formed in the first device region using conventional CMOS processes. Simultaneously, a first well region 44 and a first source region 46 are formed in the vertical device region. The first well region 44 has a second conductivity type and is formed in a first conductivity type region 16. The first source region 46 is formed in the first well region 44. The CMOS well region 54 has a second conductivity type and is formed in the top semiconductor layer 14 (second conductivity type region), above the buried dielectric region 20. The CMOS source region 562 and the CMOS drain region 564 have a first conductivity type and are formed in the CMOS well region 54. The CMOS gate 58 is formed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564.

[0062] In an SOI structure, the electric field lines on the high-voltage side penetrate into the silicon on the other side of the isolation trench, forming a depletion region. This depletion region can affect the performance of other devices. Figure 3In the illustrated embodiment, the CMOS well region 54 occupies only a portion of the top semiconductor layer 14 laterally, and the top semiconductor layer 14 outside the CMOS well region 54 serves as a depletion region. For example, amplified isolation rules can be used to avoid the effects of the depletion region. One approach is to move other devices away from the isolation trench boundary, but this increases the chip area; another is to increase the number and width of the isolation trenches, but the more isolation trenches are etched, the higher the wafer warpage, and the wafer may crack due to increased stress.

[0063] After etching away the buried dielectric region 20 of the vertical device region, this application regenerates a first conductivity type region 16 in the vertical device region that has a different conductivity type than the top semiconductor layer 14. This can optimize the electric field of the vertical device and reduce the area of ​​the depletion region, thereby reducing the chip area. It also eliminates the need for a wider isolation trench between the first device region and the vertical device region, avoiding the increased stress on the wafer caused by a larger isolation trench size, which could lead to wafer warping or even cracking.

[0064] S160, a first drain region is formed at the bottom of the substrate.

[0065] A first drain region 42 is formed on the bottom surface of substrate 12 using an ion implantation process. The doping concentration of the first drain region 42 is greater than that of the substrate 12.

[0066] The aforementioned method for manufacturing SOI semiconductor structures with integrated vertical devices enables the integration of relatively small vertical devices into a process platform, resulting in devices with higher power density. The depletion region of the second conductivity type optimizes the electric field of the vertical devices, thereby reducing the area of ​​the depletion region and shrinking the chip area.

[0067] In one embodiment of this application, the aforementioned SOI semiconductor structure employs the BCD process platform. In another embodiment of this application, the vertical device may also be an IGBT (Insulated Gate Bipolar Transistor) device, an SGT (Shielded Gate Trench) device, or the like.

[0068] This application correspondingly provides an SOI semiconductor structure integrating vertical devices. (Refer to...) Figure 3The semiconductor structure includes a substrate 12, a buried dielectric region 20, a first conductivity type region 16, a top semiconductor layer 14, a first device body, a vertical device body, and a first insulating isolation portion 26. The substrate 12 has a first conductivity type. The buried dielectric region 20 is disposed on the substrate 12. The first conductivity type region 16 is disposed in a region of the substrate 12 without the buried dielectric region 20. The top semiconductor layer 14 is disposed on the buried dielectric region 20 and includes a second conductivity type region located in the first device region, and a depletion region located between the second conductivity type region and the first conductivity type region 16. The top semiconductor layer 14 has a second conductivity type. The first device body is disposed on the buried dielectric region 20 and located in the first device region. The vertical device body includes a first well region 44, a first source region 46, a first drain region 42, and a first gate 48. The first well region 44 has a second conductivity type and is disposed in the first conductivity type region 16. The first source region 46 is disposed in the first well region 44, and the first drain region 42 is disposed at the bottom of the substrate 12. The isolation structure includes a first insulating isolation portion 26 and a depletion region. The depletion region is located between the second conductivity type region and the first conductivity type region 16. The bottom of the first insulating isolation portion 26 reaches the buried medium region 20. The depletion region and the first conductivity type region 16 are separated by the first insulating isolation portion 26, and the depletion region is located between the first insulating isolation portion 26 and the second conductivity type region. In one embodiment of this application, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments of this application, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0069] The aforementioned SOI semiconductor structure with integrated vertical devices integrates relatively small vertical devices, thus enabling devices with higher power density. The isolation structure between the first device and the vertical devices employs a structure in which a depletion region of a second conductivity type cooperates with a first insulating isolation portion. The depletion region of the second conductivity type can optimize the electric field of the vertical devices, thereby reducing the area of ​​the depletion region and shrinking the chip area.

[0070] In one embodiment of this application, the substrate 12 is a silicon substrate with a high doping concentration. In an SOI semiconductor structure, the isolation region between adjacent devices is depleted from the device end of the substrate 12. Using a substrate with a high doping concentration results in a narrower depletion region, thus allowing the distance between two adjacent devices to be closer (i.e., a narrower isolation region), and consequently, a smaller device area. In one embodiment of this application, the doping concentration of the substrate 12 is controlled to achieve a resistivity of 8 to 45 Ω×cm.

[0071] In one embodiment of this application, the isolation structure further includes a second insulating isolation portion 24. The depletion region is located between the first insulating isolation portion 26 and the second insulating isolation portion 24. The bottom of the second insulating isolation portion 24 reaches the buried medium region 20. The first insulating isolation portion 26 is disposed near the first conductivity type region 16, and the second insulating isolation portion 24 is disposed near the second conductivity type region.

[0072] In one embodiment of this application, the first device is a low-voltage device (e.g., a CMOS device), and the vertical device is a high-voltage device (e.g., a VDMOS device). The low-voltage device and the high-voltage device are isolated by an isolation structure consisting of a first insulating isolation portion 26, a second insulating isolation portion 24, and a depletion region. The first source region 46 and the first drain region 42 have a first conductivity type, and the doping concentration of the first drain region 42 is greater than the doping concentration of the substrate 12.

[0073] In one embodiment of this application, the first device body includes a CMOS well region 54, a CMOS source region 562, a CMOS drain region 564, and a CMOS gate 58. The CMOS well region 54 has a second conductivity type and is formed in the second conductivity type region above the buried dielectric region 20. The CMOS source region 562 and the CMOS drain region 564 have a first conductivity type and are formed in the CMOS well region 54. The CMOS gate 58 is formed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564.

[0074] exist Figure 3 In the embodiment shown, the first source region 46, the CMOS source region 562, and the CMOS drain region 564 are located on the same horizontal plane in the SOI semiconductor structure.

[0075] In one embodiment of this application, the aforementioned SOI semiconductor structure employs a thin-top silicon and thin-buried oxide layer structure. The thickness of the top semiconductor layer 14 is 1-5 micrometers. The thickness of the buried dielectric region 20 is 0.5 to 3 micrometers.

[0076] Figure 4 This is a flowchart of a method for manufacturing an SOI semiconductor structure with integrated vertical devices according to another embodiment of this application, including the following steps:

[0077] S410, acquire wafer.

[0078] See Figure 5aThe wafer includes a substrate 12, a buried dielectric region 20 on the substrate 12, and a top semiconductor layer 14 on the buried dielectric region 20. The substrate 12 has a first conductivity type, and the top semiconductor layer 14 has a second conductivity type. In one embodiment of this application, the first conductivity type is N-type, the second conductivity type is P-type, and the top semiconductor layer 14 is a P+ region. In other embodiments of this application, the first conductivity type may be P-type, and the second conductivity type may be N-type. In one embodiment of this application, the thickness of the top semiconductor layer 14 is 1 to 5 micrometers.

[0079] In one embodiment of this application, the substrate 12 is a silicon substrate with a high doping concentration. In an SOI semiconductor structure, the isolation region between adjacent devices is depleted from the device end towards the substrate 12. Using a substrate 12 with a high doping concentration results in a narrower depletion region, thus allowing the distance between two adjacent devices to be closer (i.e., a narrower isolation region), and consequently, a smaller device area. In one embodiment of this application, the doping concentration of the substrate 12 is controlled to achieve a resistivity of 8 to 45 Ω×cm.

[0080] In one embodiment of this application, the buried medium region 20 is a buried oxide layer, which may be made of silicon oxide, such as silicon dioxide. In one embodiment of this application, the thickness of the buried medium region 20 is 0.5 to 3 micrometers.

[0081] exist Figure 5a In the illustrated embodiment, the wafer further includes a dielectric layer 22 on the top semiconductor layer 14. In one embodiment of this application, the dielectric layer 22 may be made of silicon oxide, such as silicon dioxide.

[0082] S420, a patterned wafer, exposes the substrate of the vertical device region while forming isolation trenches and depletion regions.

[0083] The top semiconductor layer 14 and buried dielectric region 20 of the vertical device region are removed, thereby exposing the substrate 12 of the vertical device region. Simultaneously with the removal of the top semiconductor layer 14 and buried dielectric region 20 of the vertical device region, isolation trenches 13 are patterned and formed. The isolation trenches 13 separate the first device region from the vertical device region, and the top semiconductor layer 14 between the isolation trenches 13 and the vertical device region serves as a depletion region 14a.

[0084] See Figure 5a and Figure 5bThe patterning in step S420 is achieved through photolithography and etching. Specifically, photoresist is coated on the front side of the wafer, then exposed using a photomask, and after development, a photoresist layer 94 is formed. Then, using the photoresist layer 94 as an etching barrier layer, the dielectric layer 22, the top semiconductor layer 14, and the buried dielectric region 20 are etched to form an isolation trench 13. Simultaneously, the dielectric layer 22, the top semiconductor layer 14, and the buried dielectric region 20 above the substrate 12 in the vertical device region are etched away, thereby exposing the substrate 12. The photolithography and etching of the vertical device region and the isolation trench 13 are performed using the same photomask in the same etching step.

[0085] In one embodiment of this application, the critical dimension (CD) of the isolation groove 13 is 0.8 to 2 micrometers.

[0086] In one embodiment of this application, the isolation groove 13 surrounds the first device region laterally. In another embodiment of this application, the isolation groove 13 is a closed ring structure, which may be a circular ring, a square ring, or other shaped closed ring.

[0087] S430, fill the isolation groove with insulating medium material.

[0088] In one embodiment of this application, the insulating dielectric material is an oxide of silicon, such as silicon dioxide. The insulating dielectric material filled in the isolation trench 13 serves as the second insulating isolation portion 24. In one embodiment of this application, step S430 includes depositing the insulating dielectric material on the front side of the wafer after removing the photoresist layer 94. After deposition, the first insulating isolation portions 26 are formed on both sides of the vertical device region, see [link to relevant documentation]. Figure 5c .

[0089] In one embodiment of this application, step S430, which involves depositing the insulating dielectric material, is a low-pressure chemical vapor deposition (LPCVD) process using TEOS (tetraethyl orthosilicate) as the reactant.

[0090] In one embodiment of this application, after depositing the insulating dielectric material, it is necessary to remove the insulating dielectric material from the upper surface of the substrate 12 in the vertical device region, thereby exposing the substrate 12, as shown below. Figure 5d In one embodiment of this application, the insulating dielectric material on the upper surface of the substrate 12 is removed by photolithography (i.e., etching directly without photolithography).

[0091] S440, a first conductivity type region is epitaxially formed on the longitudinal device region.

[0092] exist Figure 5e In the embodiment shown, a first conductivity type epitaxial layer (i.e., first conductivity type region 16) is grown in the longitudinal device region by selective epitaxy.

[0093] In the embodiment where a dielectric layer 22 is formed on the top semiconductor layer 14 in the preceding steps, the dielectric layer 22 will prevent the formation of a silicon epitaxial layer during selective epitaxy. Therefore, the epitaxial layer will only be formed on the substrate 12 at the location not covered by the buried dielectric region 20, the first insulating isolation portion 26 and the second insulating isolation portion 24, and will not be formed on the top semiconductor layer 14 covered by the dielectric layer 22.

[0094] In SOI structures, electric field lines from the high-voltage side penetrate into the silicon on the other side of the isolation trench, forming a depletion region. This depletion region can affect the performance of other devices. For example, the effects of the depletion region can be avoided by amplifying isolation rules: one approach is to move other devices away from the isolation trench boundary, but this increases the chip area; another is to increase the number and width of the isolation trenches, but the more isolation trenches are etched, the higher the wafer warpage, which can lead to wafer cracking due to increased stress.

[0095] After etching away the buried dielectric region 20 of the vertical device region, this application regenerates a first conductivity type region 16 in the vertical device region that has a different conductivity type than the top semiconductor layer 14. This can optimize the electric field of the vertical device and reduce the area of ​​the depletion region 14a. This also eliminates the need for a wider isolation trench 13 between the first device region and the vertical device region, thus avoiding increased wafer stress due to a larger isolation trench size, which could lead to wafer warping or even cracking.

[0096] The S450 uses CMOS technology to form the CMOS device body, first well region, and first source region.

[0097] The vertical device is a high-voltage device, which is isolated from the CMOS device by an isolation structure consisting of a first insulating isolation portion 26, a second insulating isolation portion 24, and a depletion region 14a. In one embodiment of this application, the vertical device is a VDMOS device, and the first well region 44 and the first source region 46 are the well region and source region of the VDMOS device.

[0098] Specifically, after removing the dielectric layer 22 on the front side of the wafer, a CMOS device body is formed in the first device region using CMOS technology, and a first well region 44 and a first source region 46 are formed in the vertical device region. The first well region 44 is formed in the first conductivity type region 16 and has a second conductivity type, and the first source region 46 is formed in the first well region 44.

[0099] Reference Figure 6A CMOS well region 54, a CMOS source region 562, a CMOS drain region 564, and a CMOS gate 58 can be formed in the first device region using conventional CMOS processes. Simultaneously, a first well region 44 and a first source region 46 are formed in the vertical device region. The first well region 44 has a second conductivity type and is formed in a first conductivity type region 16. The first source region 46 is formed in the first well region 44. The CMOS well region 54 has a second conductivity type and is formed in the top semiconductor layer 14 (second conductivity type region), above the buried dielectric region 20. The CMOS source region 562 and the CMOS drain region 564 have a first conductivity type and are formed in the CMOS well region 54. The CMOS gate 58 is formed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564.

[0100] S460 forms the first drain region at the bottom of the substrate.

[0101] A first drain region 42 is formed on the bottom surface of substrate 12 using an ion implantation process. The doping concentration of the first drain region 42 is greater than that of the substrate 12.

[0102] The aforementioned method for manufacturing an SOI semiconductor structure with integrated vertical devices enables the integration of relatively small vertical devices, thereby achieving devices with higher power density. The depletion region of the second conductivity type optimizes the electric field of the vertical devices, thereby reducing the area of ​​the depletion region and shrinking the chip area.

[0103] This application correspondingly provides an SOI semiconductor structure integrating vertical devices. (Refer to...) Figure 6 The semiconductor structure includes a substrate 12, a buried dielectric region 20, a first conductivity type region 16, a second conductivity type region (i.e., a portion of the top semiconductor layer 14), a first device body, a vertical device body, and an isolation structure. The substrate 12 has a first conductivity type. The buried dielectric region 20 is disposed on the substrate 12. The first conductivity type region 16 is disposed in a region of the substrate 12 without the buried dielectric region 20. The second conductivity type region is disposed on the buried dielectric region 20. The first device body is disposed on the buried dielectric region 20 and located within the first device region. The vertical device body includes a first well region 44, a first source region 46, a first drain region 42, and a first gate region 48. The first well region 44 has a second conductivity type and is disposed within the first conductivity type region 16. The first source region 46 is disposed within the first well region 44, and the first drain region 42 is disposed at the bottom of the substrate 12. The isolation structure includes a first insulating isolation portion 26, a second insulating isolation portion 24, and a depletion region 14a, the depletion region 14a being located within the second conductivity type region (…). Figure 6Between the top semiconductor layer 14 and the first conductivity type region 16, the bottoms of the first insulating isolation portion 26 and the second insulating isolation portion 24 reach the buried dielectric region 20. The depletion region 14a and the second conductivity type region are separated by the second insulating isolation portion 24, and the depletion region 14a and the first conductivity type region 16 are separated by the first insulating isolation portion 26. The depletion region 14a has a second conductivity type. In one embodiment of this application, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments of this application, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0104] The aforementioned SOI semiconductor structure integrating vertical devices enables the integration of relatively small vertical devices within a process platform, resulting in devices with higher power density. The isolation structure between the first device and the vertical devices employs a structure where a depletion region of a second conductivity type cooperates with the first insulating isolation portion 26 and the second insulating isolation portion 24. The depletion region of the second conductivity type can optimize the electric field of the vertical devices, thereby reducing the area of ​​the depletion region and shrinking the chip area.

[0105] In one embodiment of this application, the substrate 12 is a silicon substrate with a high doping concentration. In an SOI semiconductor structure, the isolation region between adjacent devices is depleted from the device end of the substrate 12. Using a substrate with a high doping concentration results in a narrower depletion region, thus allowing the distance between two adjacent devices to be closer (i.e., a narrower isolation region), and consequently, a smaller device area. In one embodiment of this application, the doping concentration of the substrate 12 is controlled to achieve a resistivity of 8 to 45 Ω×cm.

[0106] In one embodiment of this application, the first device is a low-voltage device (e.g., a CMOS device), and the vertical device is a high-voltage device (e.g., a VDMOS device). The low-voltage device and the high-voltage device are isolated by an isolation structure consisting of a first insulating isolation portion 26, a second insulating isolation portion 24, and a depletion region 14a. The first source region 46 and the first drain region 42 have a first conductivity type, and the doping concentration of the first drain region 42 is greater than the doping concentration of the substrate 12.

[0107] In one embodiment of this application, the second insulating isolation portion 24 laterally surrounds the second conductivity type region (i.e., the top semiconductor layer 14 of the first device region). In another embodiment of this application, the second insulating isolation portion 24 is a closed ring structure that surrounds the second conductivity type region to provide insulation isolation for the first device. This ring structure can be a circular ring, a square ring, or other shaped closed ring.

[0108] In one embodiment of this application, the first device body includes a CMOS well region 54, a CMOS source region 562, a CMOS drain region 564, and a CMOS gate 58. The CMOS well region 54 has a second conductivity type and is formed in the second conductivity type region above the buried dielectric region 20. The CMOS source region 562 and the CMOS drain region 564 have a first conductivity type and are formed in the CMOS well region 54. The CMOS gate 58 is formed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564.

[0109] exist Figure 6 In the embodiment shown, the first source region 46, the CMOS source region 562, and the CMOS drain region 564 are located on the same horizontal plane in the SOI semiconductor structure.

[0110] In one embodiment of this application, the aforementioned SOI semiconductor structure employs a thin-top silicon and thin-buried oxide layer structure. The thickness of the top semiconductor layer 14 is 1-5 micrometers. The thickness of the buried dielectric region 20 is 0.5 to 3 micrometers.

[0111] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0112] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0113] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for manufacturing an SOI semiconductor structure with integrated vertical devices, comprising: Obtain a wafer, the wafer comprising a substrate, a buried dielectric region on the substrate, and a top semiconductor layer on the buried dielectric region; The substrate has a first conductivity type, and the top semiconductor layer has a second conductivity type. The first conductivity type and the second conductivity type are opposite conductivity types, the first conductivity type is N-type, and the second conductivity type is P-type. The wafer is patterned to remove the top semiconductor layer and buried dielectric region of the vertical device region, thereby exposing the substrate of the vertical device region. A first insulating isolation portion is formed on the side of the longitudinal device region; A first conductivity type region is epitaxially formed outside the vertical device region; the first conductivity type region and the top semiconductor layer are separated by the first insulating isolation portion; A CMOS device body is formed in the top semiconductor layer using CMOS technology, and a first well region and a first source region are formed in the vertical device region; the first well region is formed in the first conductivity type region, the first well region has a second conductivity type, and the first source region is formed in the first well region; In the top semiconductor layer, the portion located between the first insulating isolation portion and the CMOS device body is a depletion region; A first drain region is formed at the bottom of the substrate.

2. The method for manufacturing an SOI semiconductor structure with integrated vertical devices according to claim 1, characterized in that, The step of patterning the wafer further includes forming an isolation trench that divides the top semiconductor layer into a first device region and a depletion region, the depletion region being located between the isolation trench and the first insulating isolation portion; The step of forming a first insulating isolation portion on the side of the longitudinal device region includes depositing an insulating dielectric material on the front side of the wafer, thereby filling the isolation trench with the insulating dielectric material to form a second insulating isolation portion, and forming the first insulating isolation portion on the side of the longitudinal device region; The CMOS device body is formed on the top semiconductor layer using CMOS technology, which means that the CMOS device body is formed in the first device region.

3. The method for manufacturing an SOI semiconductor structure with integrated vertical devices according to claim 1, characterized in that, In the step of obtaining a wafer, the obtained wafer further includes a dielectric layer on the top semiconductor layer; After the step of epitaxially forming the first conductivity type region in the vertical device region and before the step of forming the CMOS device body, the method further includes a step of removing the dielectric layer.

4. The method for manufacturing an SOI semiconductor structure with integrated vertical devices according to claim 2, characterized in that, The step of forming a CMOS device body in the first device region using CMOS technology includes: forming a CMOS well region, a CMOS source region, a CMOS drain region, and a CMOS gate using CMOS technology; the CMOS well region has a second conductivity type and is formed above the buried dielectric region; the CMOS source region and the CMOS drain region have a first conductivity type and are formed in the CMOS well region; the CMOS gate is formed on the CMOS well region between the CMOS source region and the CMOS drain region; the first source region and the first drain region have a first conductivity type, and the doping concentration of the first drain region is greater than the doping concentration of the substrate.

5. An SOI semiconductor structure integrating vertical devices, characterized in that, The SOI semiconductor structure is manufactured according to the manufacturing method of claim 1, and comprises: The substrate has a first type of conductivity; A buried medium region is disposed on the substrate; The first conductivity type region is located in the area on the substrate where the buried dielectric region is not present. A second conductivity type region is provided on the buried medium region, wherein the first conductivity type and the second conductivity type are opposite conductivity types; The main body of the first device is disposed on the buried medium area; The vertical device body includes a first well region, a first source region, a first drain region, and a first gate. The first well region has a second conductivity type and is disposed in the first conductivity type region. The first source region is disposed in the first well region, and the first drain region is disposed at the bottom of the substrate. An isolation structure includes a first insulating isolation portion and a depletion region, the depletion region being located between a second conductivity type region and a first conductivity type region, the bottom of the first insulating isolation portion reaching the buried medium region, the depletion region and the first conductivity type region being separated by the first insulating isolation portion, the depletion region being located between the first insulating isolation portion and the second conductivity type region, and the depletion region having a second conductivity type.

6. The SOI semiconductor structure with integrated vertical devices according to claim 5, characterized in that, The isolation structure further includes a second insulating isolation portion, the depletion region is located between the first insulating isolation portion and the second insulating isolation portion, the bottom of the second insulating isolation portion reaches the buried medium region, the first insulating isolation portion is disposed near the first conductivity type region, and the second insulating isolation portion is disposed near the second conductivity type region.

7. The SOI semiconductor structure with integrated vertical devices according to claim 5, characterized in that, The vertical device is a VDMOS device, the first source region and the first drain region have a first conductivity type, and the doping concentration of the first drain region is greater than the doping concentration of the substrate.

8. The SOI semiconductor structure with integrated vertical devices according to claim 5, characterized in that, The first device body is the body of a CMOS device, and the first device body includes: A CMOS well region, having a second conductivity type, is disposed above the buried dielectric region; The CMOS source region, having a first conductivity type, is located in the CMOS well region; The CMOS drain region, having a first conductivity type, is located in the CMOS well region; The CMOS gate is located on the CMOS well region between the CMOS source region and the CMOS drain region.

9. The SOI semiconductor structure with integrated vertical devices according to claim 8, characterized in that, The CMOS source region, CMOS drain region, and first source region are located on the same horizontal plane in the SOI semiconductor structure.

10. The SOI semiconductor structure with integrated vertical devices according to claim 6, characterized in that, The second insulating isolation part is a closed ring structure that surrounds the second conductivity type region in the lateral direction.

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