Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device, the array substrate comprises a substrate, a thin film transistor, a pixel electrode, a common electrode, a conductive pattern and a plurality of grid lines, the thin film transistor is located on the substrate, and the thin film transistor comprises a source electrode, a drain electrode and a grid electrode; the pixel electrode is electrically connected with the drain electrode; the common electrode is configured to form an electric field with the pixel electrode; the conductive pattern and the common electrode are positioned on different layers; the grid line is electrically connected with the grid electrode of the thin film transistor, the conductive pattern is electrically connected with the common electrode, and the orthographic projection of the grid line on the substrate and the orthographic projection of the conductive pattern on the substrate are at least partially overlapped. According to the embodiment of the invention, the conductive pattern electrically connected with the common electrode is arranged, and the conductive pattern and the grid line are overlapped in the direction perpendicular to the substrate, so that the uniformity of a common electrode signal during diffusion is good, and a relatively large pixel aperture ratio is ensured, thereby facilitating display.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to an array substrate, a display panel, and a display device. Background Art

[0002] With the development of science and technology, the demand for image quality of self-media and film and television workers is getting higher and higher. For example, in 2017, radio and television stations have switched from 1080P display rate to 4K ultra-high-definition TV production and transmission, and mobile phone apps have gradually acquired 4K ultra-high-definition video bitstreams. At the same time, camera technology is also constantly improving, and some camera products have 6K / 8K video recording capabilities. At present, medium and large-sized display products have a trend towards higher resolution. How to improve the resolution of the product while meeting the product size requirements and having good display performance has become a difficult problem that R&D personnel in the display field need to constantly overcome. Summary of the invention

[0003] At least one embodiment of the present disclosure provides an array substrate, a display panel, and a display device.

[0004] At least one embodiment of the present disclosure provides an array substrate, including a base substrate, a thin film transistor, a pixel electrode, a common electrode, a conductive pattern and a plurality of gate lines, wherein the thin film transistor is located on the base substrate, and the thin film transistor includes a source, a drain and a gate; the pixel electrode is electrically connected to the drain; the common electrode is configured to form an electric field with the pixel electrode; the conductive pattern and the common electrode are located in different layers; the plurality of gate lines extend along a first direction, the plurality of gate lines are spaced apart along a second direction, the gate lines are electrically connected to the gates of the thin film transistors, the first direction and the second direction are both parallel to the base substrate, and the first direction intersects with the second direction, wherein the conductive pattern is electrically connected to the common electrode, and the orthographic projection of the gate line on the base substrate at least partially overlaps with the orthographic projection of the conductive pattern on the base substrate.

[0005] For example, according to at least one embodiment of the present disclosure, an array substrate is provided, which also includes an active pattern, which is respectively connected to the source and the drain of the thin film transistor and at least partially overlaps with the gate, wherein the orthographic projection of the active pattern on the base substrate overlaps at least partially with the orthographic projection of the conductive pattern on the base substrate.

[0006] For example, according to the array substrate provided by at least one embodiment of the present disclosure, there is a gap between the orthographic projection of the active pattern on the base substrate and the orthographic projection of the conductive pattern on the base substrate.

[0007] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the conductive pattern includes a plurality of conductive pattern units, and at least a portion of the orthographic projection of the conductive pattern units on the base substrate surrounds the orthographic projection of the active pattern on the base substrate.

[0008] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the orthographic projection of at least part of the conductive pattern unit on the base substrate is in the shape of a closed ring, or an open ring.

[0009] For example, according to the array substrate provided by at least one embodiment of the present disclosure, in the first direction, at least parts of the adjacent conductive pattern units are connected to each other.

[0010] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the conductive pattern further includes a plurality of connecting portions, the connecting portions extend along the second direction, and two ends of the connecting portions are respectively connected to two adjacent conductive pattern units in the second direction.

[0011] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the array substrate also includes a plurality of data lines, the data lines extend along the second direction, and the data lines are electrically connected to the source, wherein the orthographic projection of the connecting portion on the base substrate falls within the orthographic projection of a portion of the data line located between the two conductive pattern units connected by the connecting portion on the base substrate.

[0012] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the width of the conductive pattern is greater than or equal to 3 μm.

[0013] For example, according to the array substrate provided by at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the conductive pattern is located on a side of the common electrode away from the base substrate.

[0014] For example, according to the array substrate provided by at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the common electrode is closer to the base substrate than the pixel electrode, and the conductive pattern is located between the common electrode and the pixel electrode.

[0015] For example, according to the array substrate provided by at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the common electrode is farther away from the base substrate than the pixel electrode.

[0016] At least one embodiment of the present disclosure further provides a display panel, comprising the array substrate described in any of the above embodiments and an opposing substrate, wherein the opposing substrate is arranged opposite to the array substrate to form a box.

[0017] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the array substrate also includes a shading pattern, and the orthographic projection of the conductive pattern on the base substrate, the orthographic projection of the data line on the base substrate, and the orthographic projection of the gate line on the base substrate all fall into the orthographic projection of the shading pattern on the base substrate.

[0018] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the shading pattern includes a plurality of openings, at least a portion of the pixel electrode is located in the opening, the array substrate also includes a flat layer, the flat layer is located on a side of the pixel electrode close to the conductive pattern, the drain is electrically connected to the pixel electrode through a via hole penetrating the flat layer, and the orthographic projection of the via hole on the base substrate does not overlap with the orthographic projection of the conductive pattern unit on the base substrate.

[0019] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the minimum distance between the orthographic projection of the via hole on the base substrate and the orthographic projection of the conductive pattern unit on the base substrate is greater than or equal to 3.25 μm.

[0020] For example, according to the array substrate provided by at least one embodiment of the present disclosure, in the second direction, the distance that the edge of the orthographic projection of the shading pattern on the base substrate exceeds the edge of the orthographic projection of the gate line on the base substrate is greater than or equal to 0.5 μm.

[0021] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the minimum distance between the edge of the orthographic projection of the data line on the base substrate and the edge of the orthographic projection of the light shielding pattern on the base substrate is greater than or equal to 0.5 μm.

[0022] For example, according to at least one embodiment of the present disclosure, the array substrate is provided, wherein the display panel further includes a plurality of supporting structures, and the supporting structures are located between the array substrate and the base substrate to support the cell thickness.

[0023] For example, in a display panel provided according to at least one embodiment of the present disclosure, the array substrate includes a top insulating layer, the top insulating layer is located on a side of the conductive pattern away from the base substrate, the top insulating layer includes a first insulating portion and a second insulating portion connected to each other, the first insulating portion covers the conductive pattern, the orthographic projection of the second insulating portion on the base substrate does not overlap with at least a portion of the orthographic projection of the conductive pattern on the base substrate, in a direction perpendicular to the base substrate, the positions where the first insulating portion and the second insulating portion are connected to each other have a step difference, the surface of the first insulating portion away from the conductive pattern is farther from the base substrate than the surface of the second insulating portion away from the conductive pattern, and the orthographic projection of the support structure on the base substrate falls into the orthographic projection of the second insulating portion on the base substrate.

[0024] For example, according to the display panel provided by at least one embodiment of the present disclosure, at least a portion of the orthographic projection of the conductive pattern on the base substrate surrounds the orthographic projection of the support structure on the base substrate.

[0025] For example, according to the display panel provided by at least one embodiment of the present disclosure, in the second direction, portions of the conductive pattern located on both sides of the same supporting structure in the second direction are connected to each other.

[0026] For example, according to the display panel provided by at least one embodiment of the present disclosure, in the first direction, at least parts of the conductive pattern located between two adjacent support structures are disconnected from each other.

[0027] For example, according to the display panel provided by at least one embodiment of the present disclosure, in the second direction, the orthographic projection areas of the portions of the conductive pattern located on both sides of the same supporting structure on the base substrate are different.

[0028] For example, according to the display panel provided by at least one embodiment of the present disclosure, the array substrate has a first alignment layer, the opposing substrate has a second alignment layer, the multiple supporting structures are arranged on the opposing substrate, and the first alignment layer has a recess in the area surrounded by at least part of the conductive pattern to limit the position of the supporting structure.

[0029] For example, according to the display panel provided by at least one embodiment of the present disclosure, the orthographic projection of the support structure on the base substrate at least partially overlaps with the orthographic projection of the recess on the base substrate.

[0030] For example, according to the display panel provided by at least one embodiment of the present disclosure, the orthographic projection of the supporting structure on the base substrate falls into the orthographic projection of the recess on the base substrate.

[0031] At least one embodiment of the present disclosure further provides a display device, comprising the display panel described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0033] Figure 1 It is a schematic diagram of a partial structure of an array substrate provided by at least one embodiment of the present disclosure.

[0034] Figure 2 yes Figure 1 A schematic cross-sectional view of the array substrate taken along line AA' in FIG.

[0035] Figure 3 yes Figure 1 A schematic cross-sectional view of the array substrate taken along line BB' in FIG.

[0036] Figure 4 yes Figure 1 A schematic cross-sectional view of the array substrate taken along line CC' in FIG.

[0037] Figure 5 yes Figure 1 A schematic cross-sectional view of the array substrate taken along line DD' in FIG.

[0038] Figure 6 yes Figure 1 A schematic cross-sectional view of the array substrate taken along line EE' in FIG.

[0039] Figure 7 It is a schematic diagram of the partial structure of another array substrate provided by at least one embodiment of the present disclosure.

[0040] Figure 8 It is a structural schematic diagram of a display panel.

[0041] Fig. 9 is a schematic diagram of the structure of a display panel provided by at least one embodiment of the present disclosure.

[0042] Fig.10 for Fig. 9 A partial cross-sectional view of a display panel in FIG.

[0043] Fig.11 for Fig.10 Schematic diagram of the local structure of the conductive pattern in FIG.

[0044] Fig.12 A schematic diagram of the local structure of another conductive pattern.

[0045] Fig.13 A schematic diagram of a partial structure of another conductive pattern.

[0046] Fig.14 A schematic diagram of a partial structure of another conductive pattern.

[0047] Fig.15 A schematic diagram of a partial structure of another conductive pattern.

[0048] Fig.16 A partial cross-sectional schematic diagram of another display panel provided in an embodiment of the present disclosure.

[0049] Fig.17 A schematic diagram of a partial structure of another conductive pattern.

[0050] Fig.18 A schematic diagram of a partial structure of another conductive pattern.

[0051] Fig.19 A schematic diagram of a partial structure of another conductive pattern.

[0052] Fig. 20 A schematic diagram of a partial structure of another conductive pattern.

[0053] Fig.21 A schematic diagram of the connection between the display area and the peripheral area of ​​the display panel provided in an embodiment of the present disclosure.

[0054] Fig. 22 for Fig.21 A schematic diagram of the local structure of the display area.

[0055] Fig.23 for Fig. 22 Enlarged view of the local area.

[0056] Fig.24 yes Fig.21 Schematic diagram of a cross section of the array substrate taken along line M1-M1'.

[0057] Fig.25 yes Fig.21 Schematic cross-sectional view of the array substrate taken along line M2-M2'.

[0058] Fig.26 yes Fig.21 Schematic diagram of a cross-section of the array substrate taken along line M3-M3'.

[0059] Fig. 27 yes Fig.21 Schematic diagram of a cross section of the array substrate taken along line M4-M4'.

[0060] Fig.28 yes Fig.21Schematic diagram of a cross section of the array substrate taken along line M5-M5'. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0062] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The words "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0063] The features such as "perpendicular", "parallel" and "same" used in the embodiments of the present disclosure include the features such as "perpendicular", "parallel" and "same" in a strict sense, as well as the cases where "approximately perpendicular", "approximately parallel" and "approximately the same" contain certain errors, taking into account the errors associated with the measurement of specific quantities (that is, the limitations of the measurement system), indicating that the acceptable deviation range for a specific value is determined by ordinary technicians in this field. The "center" in the embodiments of the present disclosure can include a position strictly located at the geometric center and a position approximately centered within a small area around the geometric center.

[0064] With the rapid development of imaging technology, there is a market demand for display products with larger sizes and higher resolutions. At the same time, with the rapid transmission of information on the Internet, users are becoming more and more familiar with the display industry and are paying more attention to their own visual experience.

[0065] However, in the research, the inventors of the present disclosure found that: for medium and large-sized display products (for example, liquid crystal display products), the display panel generally includes an array substrate and an opposing substrate arranged relatively to each other, and the array substrate may be provided with pixel electrodes and common electrodes. An electric field can be formed between the pixel electrode and the common electrode to drive the liquid crystal molecules located between the array substrate and the opposing substrate to rotate, thereby realizing display. When the uniformity of the signal diffusion of the common electrode is poor, crosstalk and other display defects may occur. For example, for medium and large-sized high-resolution products, due to the limitation of the square resistance of the common electrode, the signal uniformity of the common electrode is not good. When the product is running (for example, when reloading the screen), there may be a Crosstalk problem when using Excel documents, affecting the user's visual experience when working with Excel. Of course, the above crosstalk problem is not limited to the scene when using Excel documents. For example, the aspect ratio of the display screen of the above-mentioned medium and large-sized display products can be 16:9, for example, the size of the display screen can be 597.6mm×336.15mm, but is not limited to this.

[0066] Therefore, it is urgent to reduce the square resistance of the common electrode in the array substrate to improve the uniformity of signal transmission. At the same time, the technical solution for reducing the square resistance of the common electrode should also have a small impact on the pixel aperture ratio of the product to facilitate display.

[0067] At least one embodiment of the present disclosure provides an array substrate, a display panel, and a display device.

[0068] At least one embodiment of the present disclosure provides an array substrate including a base substrate, a thin film transistor, a pixel electrode, a common electrode, a conductive pattern and a plurality of gate lines. The thin film transistor is located on the base substrate, and the thin film transistor includes a source, a drain and a gate. The pixel electrode is electrically connected to the drain. The common electrode is configured to form an electric field with the pixel electrode. The conductive pattern and the common electrode are located in different layers. The gate line extends along a first direction, and a plurality of gate lines are arranged at intervals along a second direction. The gate line is electrically connected to the gate of the thin film transistor. The first direction and the second direction are both parallel to the base substrate, and the first direction intersects with the second direction. The conductive pattern is electrically connected to the common electrode, and the orthographic projection of the gate line on the base substrate at least partially overlaps with the orthographic projection of the conductive pattern on the base substrate.

[0069] The array substrate provided in the embodiment of the present disclosure can effectively reduce the square resistance of the common electrode and improve the uniformity of the common electrode signal when it is diffused by adding a conductive pattern electrically connected to the common electrode, thereby reducing the probability of crosstalk in the display product and improving the display effect; at the same time, by at least partially overlapping the orthographic projection of the gate line on the base substrate with the orthographic projection of the conductive pattern on the base substrate, the layout area occupied by the conductive pattern can be reduced, and the pixel opening ratio can be made larger to facilitate display.

[0070] The array substrate, display panel and display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0071] Figure 1 is a schematic diagram of a partial structure of an array substrate provided by at least one embodiment of the present disclosure; Figure 2 yes Figure 1 A schematic cross-sectional view of the array substrate taken along line AA' in FIG.

[0072] like Figure 1 and Figure 2 As shown, the array substrate 10 includes a base substrate 100, a thin film transistor 200, a pixel electrode 300 and a common electrode 400. The thin film transistor 200 is located on the base substrate 100, and the thin film transistor 200 includes a source electrode 201, a drain electrode 202 and a gate electrode 203. The pixel electrode 300 is electrically connected to the drain electrode 202 of the thin film transistor 200, and the common electrode 400 is configured to form an electric field with the pixel electrode 300. For example, a liquid crystal layer (not shown in the figure) may be provided on one side of the array substrate 10, and the electric field formed between the pixel electrode 300 and the common electrode 400 can drive the liquid crystal molecules to deflect for display.

[0073] like Figure 1 and Figure 2 As shown, the array substrate 10 further includes a conductive pattern 500, which is electrically connected to the common electrode 400 and is located at a different layer from the common electrode 400. Figure 2 As shown, the conductive pattern 500 and the common electrode 400 may be in direct contact to facilitate the transmission of electrical signals therebetween, but the present invention is not limited thereto. For example, in some embodiments, an insulating layer may be provided between the conductive pattern 500 and the common electrode 400, and the insulating layer may have a via hole, so that the common electrode 400 and the conductive pattern 500 are electrically connected through the via hole, and the embodiments of the present disclosure are not limited thereto.

[0074] like Figure 1 and Figure 2 As shown, the array substrate 10 further includes a plurality of gate lines 600. The gate lines 600 extend along a first direction X, and the plurality of gate lines 600 are arranged at intervals along a second direction Y. The gate lines 600 are electrically connected to the gate electrode 203 of the thin film transistor 200 to control the conduction between the source electrode 201 and the drain electrode 202 of the thin film transistor 200. The orthographic projection of the gate line 600 on the base substrate 100 at least partially overlaps with the orthographic projection of the conductive pattern 500 on the base substrate 100.

[0075] For example, in Figure 1 A counter substrate (for example, see Figure 8-Figure 9). The opposing substrate includes a shading pattern 800, and the shading pattern 800 has an opening 810, and the pixel electrode 300 is located in the opening 810. For example, the opening of the shading pattern 800 can define a pixel area to control the pixel light-emitting area. The portion of the shading pattern 800 other than the opening 810 can shield the structure in the array substrate 10 to reduce the risk of light leakage and the like. For example, the shading pattern 800 can cover each signal line in the array substrate 10, such as the gate line 600, the conductive pattern 500, the data line, etc., but is not limited thereto. Therefore, when the orthographic projection of the conductive pattern 500 on the base substrate 100 overlaps at least partially with the orthographic projection of the gate line 600 on the base substrate 100, the effect of setting the conductive pattern 500 on the pixel aperture ratio can be minimized, for example, after the conductive pattern 500 is set, the pixel aperture ratio of the array substrate 10 remains substantially unchanged to facilitate display. That is, the orthographic projection of the conductive pattern 500 on the base substrate 100 at least partially overlaps with the orthographic projection of the gate line 600 on the base substrate 100 , so that the pixel aperture ratio is not reduced due to the provision of the conductive pattern 500 .

[0076] like Figure 1 and Figure 2 As shown, the first direction X and the second direction Y are both parallel to the base substrate 100 , and the first direction X intersects the second direction Y. For example, the first direction X may be perpendicular to the second direction Y.

[0077] like Figure 1 and Figure 2 As shown, the array substrate 10 provided in the embodiment of the present disclosure can effectively reduce the square resistance of the common electrode 400 and improve the uniformity of the common electrode 400 signal diffusion by adding a conductive pattern 500 electrically connected to the common electrode 400, thereby reducing the probability of crosstalk in the display product to enhance the display effect; at the same time, by at least partially overlapping the orthographic projection of the gate line 600 on the base substrate 100 with the orthographic projection of the conductive pattern 500 on the base substrate 10, the layout area occupied by the conductive pattern 500 can be reduced, and the pixel aperture ratio can be made larger to facilitate display.

[0078] For example, Figure 1 As shown, in the second direction Y, the edge of the orthographic projection of the conductive pattern 500 on the substrate 100 may exceed the edge of the orthographic projection of the gate line 600 on the substrate 100, for example, the distance of the excess is greater than or equal to 0.5 μm. For example, a portion of the orthographic projection of the gate line 600 on the substrate 100 is covered by the orthographic projection of the conductive pattern 500 on the substrate 100. For example, in the first direction X, the orthographic projection of the portion of the conductive pattern 500 located between two adjacent thin film transistors 200 and extending along the first direction X on the substrate 100 covers at least a portion of the gate line 600.

[0079] For example, Figure 1 As shown, in the second direction Y, the size of the portion where the orthographic projection of the conductive pattern 500 on the base substrate 100 overlaps with the orthographic projection of the gate line 600 on the base substrate 100 is 30% to 90% of the size of the gate line 600, for example, it can be at least one of 30% to 70%, 40% to 60%, 450% to 75%, and 50% to 60%, but is not limited thereto. For example, in order to reduce the size of the conductive pattern 500 in the second direction Y, the overlapping area between the conductive pattern 500 and the gate line 600 can be increased as much as possible, so as to facilitate obtaining a larger pixel aperture ratio, which is beneficial to display.

[0080] For example, Figure 1 As shown, the array substrate 10 further includes an active pattern 250. The active pattern 250 is respectively connected to the source 201 and the drain 202 of the thin film transistor 200, and at least partially overlaps with the gate 203. For example, in the first direction X, the source 201 and the drain 202 are respectively arranged on both sides of the active pattern 250. For example, the source 201 and the drain 202 may be located in the same layer, and an insulating layer may be arranged between the same layer and the active pattern 250, and the source 201 and the drain 202 may be respectively connected to the active pattern 250 through vias penetrating the insulating layer, but is not limited thereto.

[0081] For example, in an embodiment of the present disclosure, the active pattern 250 is made of a semiconductor material, such as amorphous silicon, low temperature polysilicon or oxide semiconductor material, but is not limited thereto.

[0082] For example, Figure 1 As shown, the orthographic projection of the active pattern 250 on the substrate 100 overlaps with the orthographic projection of the conductive pattern 500 on the substrate 100 at least partially. That is, the orthographic projection of the active pattern 250 on the substrate 100 does not overlap with the orthographic projection of the conductive pattern 500 on the substrate 100 at least partially, or does not overlap at all. For example, the conductive pattern 500 may include a plurality of hollow portions 501, and at least a portion of the orthographic projection of the active pattern 250 on the substrate 100 may be located in a region surrounded by the orthographic projection of the hollow portions 501 on the substrate 100, so that along a direction perpendicular to the substrate 10 (the third direction Z), the active pattern 250 is not completely covered by the conductive pattern 500, so that at least a portion of the active pattern 250 is exposed through the hollow portions 501.

[0083] Such an arrangement can ensure that the active pattern 250 or at least part of the structure connected to the active pattern 250 is not covered by the conductive pattern 500, so as to facilitate observation of the working state of the thin film transistor 200 (for example, observation can be performed through a microscope) and to facilitate inspection and maintenance when a failure occurs in the thin film transistor 200.

[0084] In the embodiment of the present disclosure, the third direction Z is perpendicular to the first direction X, and perpendicular to the second direction Y.

[0085] For example, Figure 1 As shown, there is a gap between the orthographic projection of the active pattern 250 on the base substrate 100 and the orthographic projection of the conductive pattern 500 on the base substrate 100. For example, the orthographic projection of the active pattern 250 on the base substrate 100 may be completely located in the area surrounded by the orthographic projection of the hollow portion 501 of the conductive pattern 500 on the base substrate, so as to facilitate observation of the working state of the thin film transistor 200.

[0086] For example, Figure 1 As shown, the conductive pattern 500 includes a plurality of conductive pattern units 510. At least part of the orthographic projection of the conductive pattern unit 510 on the base substrate 100 surrounds the orthographic projection of the active pattern 250 on the base substrate 100. For example, the plurality of conductive pattern units 510 may correspond to the plurality of thin film transistors 200 one by one, and the number of the conductive pattern units 510 in the array substrate 10 may be equal to the number of the thin film transistors 200, but is not limited thereto. For example, at least part of the orthographic projection of the thin film transistor 200 on the base substrate 100 may not be covered by the orthographic projection of the conductive pattern 500 on the base substrate 100, so as to facilitate observation of its working state.

[0087] For example, Figure 1 As shown, the orthographic projection of at least part of the conductive pattern unit 510 on the base substrate 100 is a closed ring. For example, the ring is not limited to a circular ring, for example, it can be a polygon, an ellipse, a triangle, etc., and the embodiments of the present disclosure are not limited to this. For example, the orthographic projection of at least part of the conductive pattern unit 510 on the base substrate 100 can be an octagonal ring, but is not limited thereto.

[0088] For example, Figure 1 As shown, the orthographic projection of at least part of the conductive pattern unit 510 on the base substrate 100 may also be an open ring, for example, a ring with a gap, such as a semicircle, so that a part of the conductive pattern unit 510 is arranged around the thin film transistor 200 .

[0089] For example, Figure 1 As shown, in the first direction X, at least parts of adjacent conductive pattern units 510 are connected to each other, so that the overall square resistance of the conductive pattern 500 can be reduced, so as to make the signal transmitted by the common electrode 400 uniform.

[0090] For example, Figure 1 As shown, the conductive pattern 500 further includes a plurality of connecting portions. For example, the plurality of connecting portions may be Figure 1The first connection portion 520 shown. For example, the first connection portion 520 extends along the second direction Y, and the two ends of the first connection portion 520 are respectively connected to two adjacent conductive pattern units 510 in the second direction Y, so that the overall square resistance of the conductive pattern 500 can be further reduced, so as to facilitate the uniformity of the signal transmitted by the common electrode 400. For example, the conductive pattern 500 can be an integral "mesh" structure, so that the signal transmitted by the common electrode 400 can be transmitted in all directions, which is conducive to making the signal uniform, but is not limited to this. For example, a pixel electrode 300 is arranged between two adjacent first connection portions 520, and the greater the distance between the two adjacent first connection portions 520 in the first direction X, the more conducive it is to increase the pixel aperture ratio.

[0091] Figure 3 yes Figure 1 A schematic cross-sectional view of the array substrate taken along line BB' in FIG.

[0092] For example, Figure 1 and Figure 3 As shown, the array substrate 10 further includes a plurality of data lines 700, the data lines 700 extend along the second direction Y, and the data lines 700 are electrically connected to the source electrode 201 of the thin film transistor 200. The orthographic projection of the first connecting portion 520 on the base substrate 100 falls into the orthographic projection of the portion of the data line 700 located between the two conductive pattern units 510 connected by the first connecting portion 520 on the base substrate 100.

[0093] For example, Figure 1 and Figure 3 As shown, in the second direction Y, the data line 700 and the first connection portion 520 between two adjacent conductive pattern units 510 have substantially the same trend, and the width of the first connection portion 520 is substantially the same as the width of the data line 700, thereby reducing the influence of the first connection portion 520 on the pixel aperture ratio.

[0094] For example, Figure 1 and Figure 3 As shown, the minimum distance L1 between the edge of the orthographic projection of the data line 700 on the substrate 100 and the edge of the orthographic projection of the conductive pattern 500 on the substrate 100 is greater than or equal to 0.5 μm. For example, the width of the orthographic projection of the conductive pattern 500 on the substrate 100 is smaller than the width of the orthographic projection of the data line 700 on the substrate 100, thereby facilitating the increase of the pixel aperture ratio. For example, the minimum distance L1 may be at least one of 0.5 μm to 0.9 μm, 0.5 μm to 0.8 μm, 0.6 μm to 0.7 μm, and 0.55 μm to 0.75 μm, but is not limited thereto.

[0095] For example, Figure 1As shown, the orthographic projection of the conductive pattern 500 on the base substrate 100 , the orthographic projection of the data line 700 on the base substrate 100 , and the orthographic projection of the gate line 600 on the base substrate 100 all fall into the orthographic projection of the shading pattern 800 on the base substrate 100 to reduce interference with pixel display.

[0096] For example, Figure 1 As shown, the distance L2 that the edge of the orthographic projection of the shading pattern 800 on the base substrate 100 exceeds the edge of the orthographic projection of the gate line 600 on the base substrate 100 is greater than or equal to 0.5μm, for example, it can be at least one of 0.5μm to 0.9μm, 0.5μm to 0.8μm, 0.6μm to 0.7μm and 0.55μm to 0.75μm, but is not limited to this.

[0097] For example, Figure 1 As shown, the width L3 of the conductive pattern 500 is greater than or equal to 3 μm, for example, it can be at least one of 3.1 μm to 3.5 μm, 3.2 μm to 3.6 μm, 3.3 μm to 3.7 μm, and 3.4 μm to 3.8 μm, thereby reducing the overall square resistance of the conductive pattern 500, which is beneficial to the uniformity of the signal transmitted by the common electrode 400, while making the pixel aperture ratio larger.

[0098] For example, Figure 1 and Figure 2 As shown, the array substrate 10 further includes a planar layer 910, which is located on a side of the pixel electrode 300 close to the conductive pattern 500, and the drain electrode 202 is electrically connected to the pixel electrode 300 through a via hole 950 penetrating the planar layer 910. Figure 1 As shown, the orthographic projection of the via hole 950 on the base substrate 100 does not overlap with the orthographic projection of the conductive pattern unit 510 on the base substrate 100. For example, the orthographic projection of the via hole 950 on the base substrate 100 is located in the area surrounded by the orthographic projection of the conductive pattern unit 510 on the base substrate 100, for example, it can be located in the above-mentioned hollow portion 501. Such a setting is conducive to detecting the connection between the drain 202 and the pixel electrode 300 at the via hole 950.

[0099] For example, Figure 1 As shown, the minimum distance L4 between the orthographic projection of the via hole 950 on the base substrate 100 and the orthographic projection of the conductive pattern unit 510 on the base substrate 100 is greater than or equal to 3.25 μm, so as to reduce the influence of the conductive pattern 510 on the connection condition at the via hole 950. For example, the minimum distance L4 can be at least one of 3.25 μm to 3.50 μm, 3.35 μm to 3.65 μm, 3.45 μm to 3.75 μm, and 3.55 μm to 3.85 μm, but is not limited thereto.

[0100] For example, Figure 1 and Figure 2 As shown, in the direction perpendicular to the substrate 100, that is, in Figure 2 In the third direction Z shown, a first insulating layer 911 is disposed on the base substrate 100, and the drain 202 and the source 201 of the thin film transistor 200 are disposed on the same layer and are both located on the first insulating layer 911. A planar layer 910 is disposed on the drain 202. A common electrode 400 is disposed on the planar layer 910, and for example, the common electrode 400 may be made of a transparent material, such as ITO (Indium tin oxide), but is not limited thereto.

[0101] For example, Figure 1 and Figure 2 As shown, the conductive pattern 500 is located on the side of the common electrode 400 away from the base substrate 100. For example, a second insulating layer 922 is further provided between the conductive pattern 500 and the pixel electrode 300. For example, in the third direction Z, the common electrode 400 is closer to the base substrate 100 than the pixel electrode 300, and the conductive pattern 500 is located between the common electrode 400 and the pixel electrode 300, but is not limited thereto. For example, the pixel electrode 300 may be made of a transparent conductive material, for example, the pixel electrode 300 may be made of the same material as the common electrode 400, but is not limited thereto.

[0102] For example, Figure 1 and Figure 3 As shown, the data line 700 can be located in the same layer as the drain 202 and the source 201 of the thin film transistor 200, and both are located on the first insulating layer 911, so as to facilitate the connection between the data line 700 and the source 201. For example, the data line 700, the source 201 and the drain 202 can be made of the same conductive material and formed by the same process, but is not limited thereto.

[0103] Figure 4 yes Figure 1 A schematic cross-sectional view of the array substrate taken along line CC' in FIG.

[0104] For example, Figure 1 and Figure 4 As shown, at the position cut by line CC', the first insulating layer 911, the data line 700, the planar layer 910, the common electrode 400, and the conductive pattern 500 are sequentially stacked on the base substrate 100. The second insulating layer 922 is disposed on the conductive pattern 500, and the thickness of the second insulating layer 922 is substantially uniform.

[0105] Figure 5 yes Figure 1 A schematic cross-sectional view of the array substrate taken along line DD' in FIG.

[0106] For example, Figure 1 and Figure 5 As shown, at the position intercepted by line D-D', the gate line 600, the first insulating layer 911, the flat layer 910, the common electrode 400, the conductive pattern 500 and the second insulating layer 922 are sequentially arranged. The orthographic projection of the gate line 600 on the base substrate 100 overlaps at least partially with the orthographic projection of the conductive pattern 500 on the base substrate 100 to reduce the influence of the conductive pattern 500 on the pixel aperture ratio. For example, in some embodiments of the present disclosure, the width of the conductive pattern 500 may be substantially equal to the width of the gate line 600, but is not limited thereto.

[0107] Figure 6 yes Figure 1 A schematic cross-sectional view of the array substrate taken along line EE' in FIG.

[0108] For example, Figure 1 and Figure 6 As shown, at the position cut by line EE', the first insulating layer 911, the flat layer 910, the common electrode 400, the conductive pattern 500 and the second insulating layer 922 are sequentially arranged on the base substrate 100. For example, at this position, the orthographic projection of the conductive pattern 500 on the base substrate 100 falls into the orthographic projection of the common electrode 400 on the base substrate 100, but is not limited thereto.

[0109] For example, Figure 1 As shown, in the array substrate 10, the film layer where the gate line 600 is located can be the first metal layer, and the data line 700 (such as Figure 4 As shown), the film layer where the source 201 and the drain 202 are located may be the second metal layer, and the film layer where the conductive pattern 500 is located may be the third metal layer, but is not limited thereto.

[0110] For example, in some embodiments of the present disclosure, in a direction perpendicular to the base substrate, the relative positions of the common electrode and the pixel electrode can be flexibly adjusted according to design requirements, as long as an electric field that drives the liquid crystal to deflect can be formed therebetween.

[0111] Figure 7 It is a schematic diagram of the partial structure of another array substrate provided by at least one embodiment of the present disclosure.

[0112] For example, in the array substrate 11 provided in some embodiments, referring to Figure 1 The structure of the array substrate 11 at the corresponding position is as follows: Figure 7 As shown, the common electrode 400 may be further away from the base substrate 100 than the pixel electrode 300. Figure 7The difference between the array substrate 11 shown and the array substrate 10 is that the relative position relationship between the common electrode 400 and the pixel electrode 300 is different. For the remaining structures, reference may be made to the relevant description of the above embodiment and will not be repeated here.

[0113] For example, Figure 7 As shown, in the third direction Z, the first insulating layer 931, the drain electrode 202, and the planar layer 910 are sequentially arranged. The pixel electrode 300 is arranged on the planar layer 910, and the second insulating layer 932 is arranged on the pixel electrode 300. The common electrode 400 and the conductive pattern 500 are sequentially arranged on the second insulating layer 932, and the third insulating layer 933 is arranged on the conductive pattern 500. For example, an electric field can be formed between the pixel electrode 300 and the common electrode 400 to drive the liquid crystal to deflect. For example, the pixel electrode 300 can be made of the same material as the common electrode 400, such as ITO, but not limited thereto. Compared to Figure 6 In the array substrate shown, the conductive pattern 500 in the array substrate 11 is further away from the base substrate 100. Such a configuration is, for example, conducive to flexibly configuring the structure of the conductive pattern 500 to meet more design requirements.

[0114] Figure 8 It is a structural schematic diagram of a display panel.

[0115] Usually, if Figure 8 As shown, in a display product of medium or large size and high resolution, an array substrate 10 and an opposing substrate 20 are provided, and the opposing substrate 20 is arranged opposite to the array substrate 10. For example, a plurality of supporting structures 15 may be provided on the opposing substrate 20 to support the array substrate 10 and the opposing substrate 20. For example, a layer of the array substrate 10 facing the opposing substrate 20 is usually an insulating layer, and the insulating layer can protect the array substrate 10. For example, the insulating layer can also be an alignment layer so that the liquid crystal can be arranged uniformly and stably. However, since the supporting structure 15 is in direct contact with the above-mentioned insulating layer or alignment layer, it is easy to shift during the process of the opposing substrate 20 and the array substrate 10 being arranged in a box, thereby scratching the surface of the above-mentioned insulating layer or the surface of the alignment layer, and then easily causing poor display such as Mura.

[0116] Fig. 9 is a schematic diagram of the structure of a display panel provided by at least one embodiment of the present disclosure.

[0117] Therefore, if Fig. 9As shown, the embodiment of the present disclosure further provides a display panel 1000. The display panel 1000 includes the array substrate 10 and the counter substrate 20 described in any of the above embodiments, and the counter substrate 20 is arranged opposite to the array substrate 10 to form a box. The display panel 1000 also includes a plurality of support structures 210, and the support structures 210 are located between the array substrate 10 and the counter substrate 20 to support the thickness of the box. For example, the array substrate in the following embodiments is Figure 1 The array substrate 10 shown is used for illustration, but is not limited thereto.

[0118] For example, Fig. 9 As shown, a liquid crystal layer 30 is provided in the box. The liquid crystal layer 30 includes a plurality of liquid crystal molecules 301. In some embodiments, a filter layer may be provided on the side of the counter substrate 20 facing the array substrate 10 to achieve color display. For example, the filter layer includes a plurality of filter units, each of which may correspond to a display electrode. For example, the plurality of filter units may include a plurality of red filter units, a plurality of green filter units, and a plurality of blue filter units, but is not limited thereto.

[0119] For example, Fig. 9 As shown, the array substrate 10 includes a top insulating layer 900, which is located on a side of the conductive pattern 500 away from the base substrate 100. For example, the top insulating layer 900 may be a film layer of the array substrate 10 that is closest to the counter substrate 20. Fig. 9 A conductive pattern 500 is also shown, and the conductive pattern 500 is located on a side of the top insulating layer 900 close to the base substrate 100. Fig. 9 It can be seen that the conductive pattern 500 is not laid in a whole layer, but has a pattern with a characteristic shape. Fig. 9 Some film layers are omitted in the array substrate.

[0120] For example, Figure 4 and Fig. 9 As shown, since the conductive pattern 500 is closer to the base substrate 100 than the top insulating layer 900, and the thickness of the top insulating layer 900 is relatively uniform, the top insulating layer 900 can include a first insulating portion 901 and a second insulating portion 902 connected to each other. Figure 4 As shown, the first insulating portion 901 covers the conductive pattern 500 , and the orthographic projection of the second insulating portion 902 on the base substrate 100 does not overlap with at least a portion of the orthographic projection of the conductive pattern 500 on the base substrate 100 .

[0121] For example, the first insulating layer 901 completely covers the conductive pattern 500 , so that the orthographic projection of the conductive pattern 500 on the base substrate 100 falls into the orthographic projection of the first insulating layer 901 on the base substrate 100 .

[0122] For example, Fig. 9 and Figure 4 As shown, in the third direction Z, the position where the first insulating portion 901 and the second insulating portion 902 are connected to each other has a step difference H. The surface of the first insulating portion 901 away from the conductive pattern 500 is farther away from the substrate 100 than the surface of the second insulating portion 902 away from the conductive pattern 500, and the orthographic projection of the support structure 210 on the substrate 100 falls into the orthographic projection of the second insulating portion 902 on the substrate 100. For example, the step difference H between the first insulating portion 901 and the second insulating portion 902 may be substantially equal to the thickness of the conductive pattern 500. For example, the step difference H may be 0.3 μm to 1 μm, for example, at least one of 0.3 μm to 0.5 μm, 0.5 μm to 0.8 μm, 0.6 μm to 0.9 μm, and 0.3 μm to 0.7 μm, but is not limited thereto.

[0123] So set up, such as Fig. 9 and Figure 4 As shown, the second insulating portion 902 can be recessed relative to the first insulating portion 901, and the supporting structure 210 can be located on the second insulating portion 902, so that the first insulating portion 901 can be used to limit the supporting structure 210 to limit the sliding of the supporting structure 210 on the surface of the second insulating portion 902, thereby reducing the risk of the supporting structure 210 scratching the top insulating layer 900, and further reducing the risk of display defects such as Mura.

[0124] For example, Fig. 9 As shown, the top insulating layer 900 in the above embodiment may be the first alignment layer 110, and the counter substrate 20 further has a second alignment layer 220. The second alignment layer 220 may be a film layer of the counter substrate 20 that is closest to the array substrate 10, and faces the first alignment layer 110 in the third direction Z. For example, the first alignment layer 110 and the second alignment layer 220 may jointly control the arrangement state of the liquid crystal molecules 301, so as to facilitate the orderly arrangement of the liquid crystal molecules 301.

[0125] For example, Fig. 9As shown, a plurality of support structures 210 are disposed on the counter substrate 20, and the first alignment layer 110 has a recess 205 in the area surrounded by at least a portion of the conductive pattern 500, so as to define the position of the support structure 210. For example, the orthographic projection of the support structure 210 on the base substrate 100 overlaps at least partially with the orthographic projection of the recess 205 on the base substrate 100, for example, the orthographic projection of the support structure 210 on the base substrate 100 can be made to fall into the orthographic projection of the recess 205 on the base substrate 100, so that the first alignment layer 110 can effectively limit the movement of the support structure 210 in a direction parallel to the base substrate 100 while controlling the arrangement state of the liquid crystal molecules 301, which is conducive to reducing the risk of the support structure 210 scratching the first alignment layer 110.

[0126] It should be noted that, in the embodiments of the present disclosure, Fig. 9 As shown, the metal structure 500 may not be in direct contact with the film layer of the array substrate 10 that is closest to the counter substrate 20 (for example, the top insulating layer or the first alignment layer 110 in the above embodiment). For example, a plurality of other film layers may be provided on the side of the metal structure 500 that is away from the base substrate 100, as long as the film layer of the array substrate 10 that is closest to the counter substrate 20 has a depression and the risk of the support structure 210 scratching the film layer of the array substrate 10 that is closest to the counter substrate 20 can be reduced.

[0127] Fig.10 for Fig. 9 A partial cross-sectional view of a display panel in FIG.

[0128] For example, Fig.10 As shown, at least part of the orthographic projection of the conductive pattern 500 on the base substrate 100 surrounds the orthographic projection of the support structure 210 on the base substrate 100. For example, the orthographic projection of the support structure 210 on the base substrate 100 may be any one of a polygon (e.g., an octagon), a circle, and an ellipse, which is not limited in the embodiments of the present disclosure. For example, the conductive pattern unit 510 (see FIG. 5 ) in the conductive pattern 500 may be a conductive pattern unit 510 (see FIG. 5 ) in the conductive pattern 500. Figure 1 ) on the substrate 100 may be a closed ring, so that the support structure 210 may be located in the ring. For example, in some embodiments of the present disclosure, the orthographic projection of the portion of the conductive pattern 500 surrounding the support structure 210 on the substrate 100 may also be an open ring, which is not limited to this.

[0129] For example, Figure 4 and Fig.10As shown, when the support structure 210 is at least partially surrounded by the conductive pattern 500, the portion of the conductive pattern 500 limits the movement of the support structure 210 in a direction parallel to the base substrate 100, thereby reducing the risk of the support structure 210 scratching the surface of the array substrate 10 (for example, the first alignment layer 110 in the array substrate 10).

[0130] Fig.11 for Fig.10 Schematic diagram of the local structure of the conductive pattern in FIG.

[0131] For example, Fig.11 As shown, in the second direction Y, the portions of the conductive pattern 500 located on both sides of the same support structure 210 in the second direction Y are connected to each other. For example, the conductive pattern 500 may include a second connection portion 530, and the main extension direction of the portions of the conductive pattern 500 located on both sides of the same support structure 210 in the second direction Y is the first direction X, and the two portions may be connected by the second connection portion 530, so that the orthographic projection of the portion of the conductive pattern 500 surrounding the same support structure 210 on the substrate 100 may be a closed ring. Under this arrangement, the support structure 210 is restricted by the conductive pattern 500 in the circumferential direction, so that the risk of movement of the support structure 210 in a direction parallel to the substrate 100 can be effectively reduced.

[0132] Fig.12 A schematic diagram of the local structure of another conductive pattern.

[0133] For example, Fig.12 The conductive pattern shown is Fig.11 The shapes of the conductive patterns are different, and the remaining features can refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0134] For example, Fig.10 and Fig.12 As shown, in the second direction Y, Fig.12 The portions of the conductive pattern located on both sides of the same support structure 210 include two corners opposite to each other, corresponding to the support structure 210 with a local protruding structure, but not limited thereto. For example, when the support structure 210 has various shapes according to design requirements, the shape and structure of the conductive pattern 500 can also be flexibly adjusted accordingly to better restrict the support structure 210 from moving in a direction parallel to the substrate.

[0135] Fig.13 A schematic diagram of a partial structure of another conductive pattern.

[0136] For example, Fig.13 The conductive pattern shown is Fig.11The shapes of the conductive patterns are different, and the remaining features can refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0137] For example, Fig.13 As shown, in the first direction X, at least parts of the conductive pattern 500 located between two adjacent support structures 210 are disconnected from each other. Fig.10 and Fig.13 As shown, the conductive pattern 500 may include a first conductive pattern portion 541 and a second conductive pattern portion 542 respectively located on both sides of the same support structure 210 in the second direction Y, and the first conductive pattern portion 541 and the second conductive pattern portion 542 are not connected to each other. For example, in the first direction X, the two first conductive pattern portions 541 located on the same side of two adjacent support structures 210 are connected to each other, and the two second conductive pattern portions 542 located on the same side of two adjacent support structures 210 are not connected to each other. For example, under this scheme, the probability of the portion of the support structure 210 not surrounded by the conductive pattern 500 sliding is relatively small. In this way, the movement of the support structure 210 can be limited by the first conductive pattern portion 541 and the second conductive pattern portion 542.

[0138] Fig.14 A schematic diagram of a partial structure of another conductive pattern.

[0139] For example, Fig.14 The conductive pattern shown is Fig.13 The shapes of the conductive patterns are different, and the remaining features can refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0140] For example, Fig.14 As shown, in the first direction X, at least parts of the conductive pattern 500 located between two adjacent support structures 210 are disconnected from each other. Fig.10 and Fig.14 As shown, the conductive pattern 500 may include a first conductive pattern portion 551 and a second conductive pattern portion 552 located on both sides of the same support structure 210 in the second direction Y, and the first conductive pattern portion 551 and the second conductive pattern portion 552 are not connected to each other, and the second conductive pattern portion 552 includes a first sub-conductive pattern portion 5521 and a second sub-conductive pattern portion 5522 that are spaced apart from each other. For example, in the first direction X, two first conductive pattern portions 541 located on the same side of two adjacent support structures 210 are connected to each other, and two second conductive pattern portions 542 located on the same side of two adjacent support structures 210 are not connected to each other. The first sub-conductive pattern portion 5521 and the second sub-conductive pattern portion 5522 surrounding the same support structure 210 are projected in an "eight" shape on the base substrate, thereby limiting the movement of the support structure 210.

[0141] Fig.15 A schematic diagram of a partial structure of another conductive pattern.

[0142] For example, Fig.10 and Fig.15 As shown, in order to better limit the movement of the support structure 210 according to design requirements, the structure of the conductive pattern 500 is not limited to the structure shown in the above embodiment. For example, in the second direction Y, the portions of the conductive pattern 500 located on both sides of the same support structure 210 have different orthographic projection areas on the substrate 100. For example, in some embodiments, the conductive pattern 500 may be provided only on one side of the support structure 210, thereby reducing the movement of the support structure 210 toward the support structure 210 close to the side, but is not limited thereto.

[0143] Fig.16 A partial cross-sectional schematic diagram of another display panel provided in an embodiment of the present disclosure.

[0144] For example, Fig.16 As shown, the display panel 1001 includes a plurality of pixel electrodes 300 and a plurality of support structures 210, the plurality of pixel electrodes 300 are arranged in an array along a first direction X and a second direction Y, the plurality of support structures 210 are arranged in an array along a first direction X and a second direction Y, and there is a gap between the orthographic projection of the pixel electrode 300 on the substrate and the orthographic projection of the support structure 210 on the substrate. For example, the orthographic projection of the support structure 210 on the substrate is substantially circular, and the orthographic projection area of ​​the support structure 210 on the substrate is smaller than the orthographic projection area of ​​the pixel electrode 300 on the substrate.

[0145] For example, Fig.16 As shown, the display panel 1001 also includes a conductive pattern 500, and at least part of the conductive pattern 500 surrounds the support structure 210. For example, the conductive pattern 500 includes a plurality of conductive pattern units 510, and the support structure 210 is located in the area surrounded by the conductive pattern units 510. In the first direction X, the portions of the conductive pattern 500 surrounding two adjacent support structures 210 are connected to each other. In the second direction Y, the portions of the conductive pattern 500 located on both sides of the same pixel electrode 300 are connected to each other. For example, the conductive pattern 500 can be an integrated structure, which is beneficial to reducing the square resistance of the conductive pattern 500, so as to facilitate the diffusion of the signal in all directions. At the same time, the support structure 210 can be slid in a direction parallel to the base substrate to reduce scratching the array substrate in the display panel 1001, which is beneficial to reduce the occurrence of crosstalk and display defects such as Mura.

[0146] Fig.17 is a schematic diagram of a partial structure of another conductive pattern; Fig.18 is a schematic diagram of a partial structure of another conductive pattern; Fig.19 is a schematic diagram of a partial structure of another conductive pattern; Fig. 20 A schematic diagram of a partial structure of another conductive pattern.

[0147] For example, Fig.17 As shown, the conductive pattern 500 may include a first conductive pattern portion 5011 and a second conductive pattern portion 5012, and the first conductive pattern portion 5011 and the second conductive pattern portion 5012 are arranged at intervals in the second direction Y. The first conductive pattern portion 5011 extends along the first direction X, and the extension direction of the first conductive pattern portion 5011 is substantially straight, and the extension direction of the second conductive pattern portion 5012 is curved. The orthographic projection of the second conductive pattern portion 5012 on the substrate substrate overlaps at least partially with the orthographic projection of the gate line 600 on the substrate substrate. For example, the orthographic projection of the portion of the second conductive pattern portion 5012 extending along the first direction X on the substrate substrate falls into the orthographic projection of the gate line 600 on the substrate substrate, thereby saving layout space and facilitating an increase in pixel aperture ratio. For example, the second conductive pattern portion 5012 includes a straight line segment portion extending along the first direction X between adjacent data lines, and the orthographic projection of the straight line segment portion on the substrate substrate falls into the orthographic projection of the gate line 600 on the substrate substrate.

[0148] For example, Fig.18 As shown, the conductive pattern 500 includes a first conductive pattern portion 5013 and a second conductive pattern portion 5014, the extension directions of the first conductive pattern portion 5013 and the second conductive pattern portion 5014 are both curved, and the first conductive pattern portion 5013 and the second conductive pattern portion 5014 are connected by a second connecting portion 530. The display panel includes a first gate line 6001 and a second gate line 6002, and the first gate line 6001 and the second gate line 6002 both extend along a first direction X. The orthographic projection of the first conductive pattern portion 5013 on the substrate substrate overlaps at least partially with the orthographic projection of the first gate line 6001 on the substrate substrate, and the orthographic projection of the second conductive pattern 5014 on the substrate substrate overlaps at least partially with the orthographic projection of the second gate line 6002 on the substrate substrate. The display panel includes a first pixel electrode 3001 and a second pixel electrode 3002 adjacent to each other in the first direction X, and a third pixel electrode 3003 and a fourth pixel electrode 3004 adjacent to each other in the first direction X. The first pixel electrode 3001 and the third pixel electrode 3003 are located in different rows in the second direction Y. For example, the drain electrode 202 adjacent to the gate electrode 203 connected to the first gate line 6001 is connected to the first pixel electrode 3001 through a via hole. For example, the drain electrode 202 adjacent to the gate electrode 203 connected to the second gate line 6002 is connected to the third pixel electrode 3003 through a via hole.

[0149] For example, Fig.19As shown, the conductive pattern 500 includes a plurality of openings 50010. For example, the conductive pattern 500 includes a plurality of conductive pattern units 510, and the positive projection of the conductive pattern unit 510 on the substrate is an open ring. At least a portion of the pixel electrode 300 is located in the ring area, so that the distance between adjacent pixel electrodes 300 in the second direction Y can be reduced to increase the pixel opening.

[0150] For example, Fig. 20 As shown, the conductive pattern 500 may include a first conductive pattern portion 5015 and a second conductive pattern portion 5016, the first conductive pattern portion 5015 and the second conductive pattern portion 5016 are spaced apart in the second direction Y, and the first conductive pattern portion 5015 and the second conductive pattern portion 5016 are connected by a second connecting portion 530. The extension directions of the first conductive pattern portion 5015 and the second conductive pattern portion 5016 are both curved. The display panel includes a first gate line 6003 and a second gate line 6004, and the first gate line 6003 and the second gate line 6004 are both extended along the first direction X. The orthographic projection of the first conductive pattern portion 5015 on the substrate substrate overlaps at least partially with the orthographic projection of the first gate line 6003 on the substrate substrate, and the orthographic projection of the second conductive pattern 5016 on the substrate substrate overlaps at least partially with the orthographic projection of the second gate line 6004 on the substrate substrate. For example, the pixel electrode 300 may be connected to the drain of the thin film transistor through the via hole 950, and at least a portion of the pixel electrode 300 may be connected to the common electrode line through the via hole 960 (for the arrangement of the common electrode line, please refer to the following embodiment about Figure 22-Figure 23 For example, there is a gap between the orthographic projection of via 950 on the substrate and the orthographic projection of via 960 on the substrate to reduce the risk of poor signal.

[0151] Fig.21 A schematic diagram of the connection between the display area and the peripheral area of ​​the display panel provided in the embodiment of the present disclosure; Fig. 22 for Fig.21 A local structural schematic diagram of the display area in; Fig.23 for Fig. 22 Enlarged view of the local area.

[0152] For example, Fig.21 As shown, the display panel includes a display area 1010 and a peripheral area 1020 . The peripheral area 1020 is located on at least one side of the display area 1010 . For example, the peripheral area 1020 may be disposed around the display area 1010 , but is not limited thereto.

[0153] For example, Fig. 22As shown, when viewed from one side of the array substrate of the display panel, a plurality of sub-pixels are arranged in the display area 1010, and the plurality of sub-pixels are arranged in an array along the first direction X and the second direction Y to form a plurality of pixel rows and a plurality of pixel columns. For example, the plurality of sub-pixels include a first sub-pixel 310, a second sub-pixel 320, and a third sub-pixel 330. For example, the first sub-pixel 310, the second sub-pixel 320, and the third sub-pixel 330 are sub-pixels that emit different colors, for example, one of the first sub-pixel 310 and the second sub-pixel 320 can be a red sub-pixel that emits red light, the other can be a blue sub-pixel that emits blue light, and the third sub-pixel 330 can be a green sub-pixel that emits green light. For example, the first sub-pixel 310 is a blue sub-pixel, and the second sub-pixel 320 is a red sub-pixel. Of course, the colors of the first sub-pixel 310, the second sub-pixel 320, and the third sub-pixel 330 can be interchangeable. Of course, the embodiments of the present disclosure are not limited thereto, and the size of the luminous area of ​​each color sub-pixel can be set according to actual product requirements.

[0154] For example, Fig. 22 and Fig.23 As shown, a conductive pattern 500 and a source 201 , a drain 202 and a gate 203 in the thin film transistor 200 are arranged between two adjacent rows of sub-pixels, and part of the structure of the thin film transistor 200 is not covered by the conductive pattern 500 to facilitate detection of the working state of the thin film transistor 200 .

[0155] For example, compared to Fig.11 The conductive pattern 500 shown, Fig.23 The number of second connection portions 530 in the conductive pattern 500 in the second direction Y can be reduced according to design requirements. For example, in the second direction Y, a second connection portion 530 is provided between two adjacent third sub-pixels 330, and the second connection portion 530 may not be provided between two adjacent second sub-pixels 320, so as to better adapt to the layout space. For example, in some embodiments, in the second direction Y, the second connection portion 530 may also be provided only between two adjacent first sub-pixels 310, and the second connection portion 530 may not be provided between two adjacent third sub-pixels 330, but is not limited thereto. For example, in some embodiments, the number and position of the second connection portion 530 can be flexibly adjusted according to the layout space.

[0156] For example, Fig.21 and Fig.23As shown, the display panel further includes a common electrode line 5000, and the common electrode line 5000 extends along the first direction X. For example, the common electrode line 5000 may be located at the same layer as the gate line 600. For example, the conductive pattern 500 may be located at a side of the common electrode line 5000 away from the base substrate, and the common electrode line 5000 may be electrically connected to the conductive pattern 500, thereby further reducing the common electrode 400 (such as Figure 4 The square resistance of the common electrode 400 is improved to improve the uniformity of the signal diffusion.

[0157] For example, Fig.23 As shown, the orthographic projection of the common electrode line 5000 on the base substrate does not overlap with the gate line 600 to reduce signal interference.

[0158] Fig.24 yes Fig.21 A schematic cross-sectional view of the array substrate taken along line M1-M1'; Fig.25 yes Fig.21 A schematic cross-sectional view of the array substrate taken along line M2-M2'; Fig.26 yes Fig.21 A schematic cross-sectional view of the array substrate taken along line M3-M3'; Fig. 27 yes Fig.21 A schematic cross-sectional view of the array substrate taken along line M4-M4'; Fig.28 yes Fig.21 Schematic diagram of a cross section of the array substrate taken along line M5-M5'.

[0159] For example, Fig.21 As shown, a portion of the signal lines in the display area 1010 are connected to the peripheral area 1020 , so as to apply a driving signal from the peripheral area 1020 to the display area 1010 .

[0160] For example, Fig.21 and Fig.24 As shown, at the position intercepted by line M1-M1', the first insulating layer 911, the planar layer 910, the connector 1400 located on the same layer as the common electrode 400, the connector 1500 located on the same layer as the conductive pattern 500, the second insulating layer 922 and the connector 1300 located on the same layer as the pixel electrode 300 are sequentially stacked on the base substrate 100.

[0161] For example, Fig.21 and Fig.25As shown, at the position intercepted by line M2-M2', a hollowed-out area of ​​the third metal layer (i.e., the film layer where the conductive pattern 500 is located) is located, and the connector 1601 located on the same layer as the gate line 600, the first insulating layer 911, the connector 1700 located on the same layer as the data line 700, the flat layer 910, the connector 1401 located on the same layer as the common electrode 400, the second insulating layer 922, and the connector 1301 located on the same layer as the pixel electrode 300 are sequentially stacked on the base substrate 100. For example, in the second direction Y, other connectors located on the same layer are also spaced apart on both sides of the connector 1601. For example, the connector 1601 can transmit a scan signal from the peripheral area 1020 to the display area 1010 to control the opening or closing of the thin film transistor 200 in the display area 1010.

[0162] For example, Fig.21 and Fig.26 As shown, the position cut by the line M3-M3' is located at the edge of the hollow area of ​​the third metal layer. At this position, the connecting member 1401 and the structure below it located at the same layer as the common electrode 400 are connected to the Fig.24 The structure shown in is substantially the same. A connecting member 1501 located on the same layer as the conductive pattern 500 is disposed on the connecting member 1401 , and the second insulating layer 922 and the connecting member 1301 located on the same layer as the pixel electrode 300 are disposed on the conductive pattern 500 .

[0163] For example, Fig.21 and Fig. 27 As shown, at the position cut by line M4-M4', the connecting member 1602, the first insulating layer 911, and the data line 700 (as shown in FIG. 1 ) located on the same layer as the gate line 600 are connected to the connecting member 1602, the first insulating layer 911, and the data line 700 (as shown in FIG. 1 ). Figure 4 A connector 1701 located on the same layer as the pixel electrode 300, a flat layer 910, a connector 1401 located on the same layer as the common electrode 400, and a connector 1502 located on the same layer as the conductive pattern 500 are arranged in sequence, a second insulating layer 922 is located on the connector 1502, and a connector 1302 located on the same layer as the pixel electrode 300 is located on the second insulating layer 922 and is connected to the connector 1502 through a via N1.

[0164] For example, Fig.21 and Fig.28 As shown, at the position cut by line M5-M5', the connecting member 1603, the first insulating layer 911, and the data line 700 (as shown in FIG. 1 ) located on the same layer as the gate line 600 are connected to the connecting member 1603, the first insulating layer 911, and the data line 700 (as shown in FIG. 1 ). Figure 4The connector 1702 and the planar layer 910 located on the same layer as the pixel electrode 300 are sequentially arranged, the second insulating layer 922 is located on the planar layer 910, and the connector 1303 located on the same layer as the pixel electrode 300 is located on the second insulating layer 922. The connector 1303 is connected to the connector 1702 through the via hole N2, and the connector 1303 is connected to the connector 1603 through the via hole N3.

[0165] In the embodiment of the present disclosure, for the thin film transistor 200, the source 201 and the drain 202 of the thin film transistor 200 are relatively interchangeable. Of course, one of the source 201 and the drain 202 of the thin film transistor 200 can also be called a first electrode, and the other of the source 201 and the drain 202 of the thin film transistor 200 can also be called a second electrode. The gate 203 of the thin film transistor 200 can be called a control electrode.

[0166] In the embodiment of the present disclosure, both the pixel electrode 300 and the common electrode 400 may be referred to as display electrodes. For example, one of the pixel electrode 300 and the common electrode 400 may be referred to as a first display electrode, and the other of the pixel electrode 300 and the common electrode 400 may be referred to as a second display electrode.

[0167] For example, the array substrate provided in the embodiment of the present disclosure may be manufactured using an oxide back channel etching (Oxide Back Channel Etch) technology.

[0168] For example, in the embodiment of the present disclosure, the support structure 15 may also be referred to as a spacer.

[0169] The embodiment of the present disclosure is described by taking the example that the pixel electrode 300 is located on the side of the common electrode 400 away from the substrate, that is, the pixel electrode 300 is formed after the common electrode 400, but is not limited thereto. The positions of the pixel electrode 300 and the common electrode 400 can be adjusted as needed. For example, in some embodiments, the common electrode 400 is located on the side of the pixel electrode 300 away from the substrate. In the embodiment of the present disclosure, one of the common electrode 400 and the pixel electrode 300 away from the substrate has a slit to facilitate the common electrode 400 and the pixel electrode 300 to form an electric field.

[0170] The embodiment of the present disclosure takes the conductive pattern 500 as being located on the common electrode 400, that is, the conductive pattern 500 is formed after the common electrode 400, but is not limited thereto. In other embodiments, the conductive pattern 500 may be formed first, and then the common electrode 400 may be formed, that is, the common electrode 400 is located on the conductive pattern 500.

[0171] In the embodiments of the present disclosure, the components located in the same layer may be formed by the same film layer through the same patterning process. For example, the components located in the same layer may be located on the surface of the same component away from the substrate.

[0172] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of the layer or region is exaggerated. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be an intermediate element.

[0173] In the embodiments of the present disclosure, the patterning or patterning process may include only the photolithography process, or include the photolithography process and the etching step, or may include other processes such as printing and inkjetting for forming a predetermined pattern. The photolithography process refers to a process including film formation, exposure, and development, and a pattern is formed using a photoresist, a mask, an exposure machine, etc. The corresponding patterning process can be selected according to the structure formed in the embodiments of the present disclosure.

[0174] In the embodiments of the present disclosure, components located at different layers are formed from different film layers through different patterning processes.

[0175] At least one embodiment of the present disclosure further provides a display device, and the display device includes the display panel described in any of the above embodiments. Therefore, the display device includes the above display panel, and therefore, the technical effects of the above display panel can also be embodied on the display device, which will not be repeated here.

[0176] There are a few points to note:

[0177] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0178] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0179] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure, which is determined by the appended claims.

Claims

1. An array substrate, comprising: substrate substrate; A thin film transistor, located on the substrate, comprising a source electrode, a drain electrode and a gate electrode; a pixel electrode, electrically connected to the drain electrode; a common electrode configured to form an electric field with the pixel electrode; A conductive pattern located at a different layer from the common electrode; a plurality of gate lines, the plurality of gate lines extending along a first direction, the plurality of gate lines being spaced apart along a second direction, the gate lines being electrically connected to the gate of the thin film transistor, the first direction and the second direction both being parallel to the substrate, and the first direction intersecting the second direction, The conductive pattern is electrically connected to the common electrode, and an orthographic projection of the gate line on the base substrate at least partially overlaps with an orthographic projection of the conductive pattern on the base substrate.

2. The array substrate according to claim 1, further comprising an active pattern connected to the source electrode and the drain electrode of the thin film transistor respectively and at least partially overlapping the gate electrode, in, An orthographic projection of the active pattern on the base substrate overlaps at least partially with an orthographic projection of the conductive pattern on the base substrate.

3. The array substrate according to claim 2, wherein: An orthographic projection of the active pattern on the base substrate has a space between an orthographic projection of the conductive pattern on the base substrate.

4. The array substrate according to claim 2, wherein: The conductive pattern includes a plurality of conductive pattern units, and at least a portion of an orthographic projection of the conductive pattern units on the base substrate surrounds an orthographic projection of the active pattern on the base substrate.

5. The array substrate according to claim 4, wherein: The orthographic projection of at least part of the conductive pattern unit on the base substrate is in the shape of a closed ring or an open ring.

6. The array substrate according to claim 4, wherein: In the first direction, at least parts of adjacent conductive pattern units are connected to each other.

7. The array substrate according to claim 4, wherein: The conductive pattern further includes a plurality of connecting portions, wherein the connecting portions extend along the second direction, and two ends of the connecting portions are respectively connected to two adjacent conductive pattern units in the second direction.

8. The array substrate according to claim 7, further comprising a plurality of data lines, the data lines extending along the second direction and the data lines being electrically connected to the source electrode, in, The orthographic projection of the connecting portion on the base substrate falls within the orthographic projection of a portion of the data line located between the two conductive pattern units connected by the connecting portion on the base substrate.

9. The array substrate according to any one of claims 1 to 8, wherein: The width of the conductive pattern is greater than or equal to 3 μm.

10. The array substrate according to any one of claims 1 to 8, wherein: In a direction perpendicular to the base substrate, the conductive pattern is located on a side of the common electrode away from the base substrate.

11. The array substrate according to claim 10, wherein: In a direction perpendicular to the base substrate, the common electrode is closer to the base substrate than the pixel electrode, and the conductive pattern is located between the common electrode and the pixel electrode.

12. The array substrate according to claim 10, wherein: In a direction perpendicular to the base substrate, the common electrode is farther away from the base substrate than the pixel electrode.

13. A display panel, comprising: The array substrate according to any one of claims 1 to 12; The counter substrate is arranged opposite to the array substrate to form a box.

14. According to the display panel of claim 13, the opposing substrate comprises a shading pattern, and the orthographic projection of the conductive pattern on the base substrate, the orthographic projection of the data line on the base substrate, and the orthographic projection of the gate line on the base substrate all fall into the orthographic projection of the shading pattern on the base substrate.

15. The display panel according to claim 14, wherein: The light shielding pattern includes a plurality of openings, and at least a portion of the pixel electrode is located in the openings. The array substrate also includes a flat layer, which is located on a side of the pixel electrode close to the conductive pattern. The drain is electrically connected to the pixel electrode through a via hole penetrating the flat layer. The orthographic projection of the via hole on the base substrate does not overlap with the orthographic projection of the conductive pattern unit on the base substrate. 16 . The display panel according to claim 15 , wherein a minimum distance between an orthographic projection of the via hole on the base substrate and an orthographic projection of the conductive pattern unit on the base substrate is greater than or equal to 3.25 μm.

17. The display panel according to claim 14, wherein: In the second direction, The distance that the edge of the orthographic projection of the light shielding pattern on the base substrate exceeds the edge of the orthographic projection of the gate line on the base substrate is greater than or equal to 0.5 μm.

18. The display panel according to claim 14, wherein: A minimum distance between an edge of an orthographic projection of the data line on the base substrate and an edge of an orthographic projection of the light shielding pattern on the base substrate is greater than or equal to 0.5 μm.

19. The display panel according to claim 13, wherein: The display panel further includes a plurality of supporting structures, and the supporting structures are located between the array substrate and the base substrate to support the cell thickness.

20. The display panel according to claim 13, wherein: The array substrate comprises a top insulating layer, wherein the top insulating layer is located on a side of the conductive pattern away from the base substrate. The top insulating layer includes a first insulating portion and a second insulating portion connected to each other, the first insulating portion covers the conductive pattern, and an orthographic projection of the second insulating portion on the base substrate does not overlap with at least a portion of an orthographic projection of the conductive pattern on the base substrate. In a direction perpendicular to the base substrate, the positions where the first insulating part and the second insulating part are connected to each other have a step difference, the surface of the first insulating part away from the conductive pattern is farther away from the base substrate than the surface of the second insulating part away from the conductive pattern, and the orthographic projection of the support structure on the base substrate falls into the orthographic projection of the second insulating part on the base substrate.

21. The display panel according to claim 19, wherein: At least a portion of an orthographic projection of the conductive pattern on the base substrate surrounds an orthographic projection of the support structure on the base substrate.

22. The display panel according to claim 19, wherein: In the second direction, portions of the conductive pattern located on both sides of the same support structure in the second direction are connected to each other.

23. The display panel according to claim 19, wherein: In the first direction, at least parts of the conductive pattern located between two adjacent support structures are disconnected from each other.

24. The display panel according to claim 19, wherein: In the second direction, the orthographic projection areas of the portions of the conductive pattern located on two sides of the same support structure on the base substrate are different.

25. The display panel according to any one of claims 19 to 24, wherein: The array substrate has a first alignment layer, the opposing substrate has a second alignment layer, the plurality of support structures are arranged on the opposing substrate, and the first alignment layer has a recess in an area at least partially surrounded by the conductive pattern to define the position of the support structure.

26. The display panel according to claim 25, wherein: An orthographic projection of the support structure on the base substrate at least partially overlaps with an orthographic projection of the recess on the base substrate.

27. The display panel according to claim 25, wherein: The orthographic projection of the support structure on the substrate falls into the orthographic projection of the recess on the substrate.

28. A display device comprising the display panel according to any one of claims 13 to 27.

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