Method and apparatus for multiphase clock generation

Abstract

An example apparatus includes: a first clock generation circuit (135) including: an interlock circuit (220) having terminals; a reference clock generation circuit (230) having a first terminal and a second terminal, the first terminal of the reference clock generation circuit (230) being coupled to the terminal of the interlock circuit (220); a first duty cycle copy circuit (240) having a first terminal and a second terminal, the first terminal of the first duty cycle copy circuit (240) being coupled to the second terminal of the reference clock generation circuit (230); and a snubber circuit (250) having a first terminal and a second terminal, the first terminal of the snubber circuit (250) being coupled to the second terminal of the first duty cycle copy circuit (240); and a second clock generation circuit (145) comprising: a detection circuit (310) having a first terminal and a second terminal, the first terminal of the detection circuit (310) being coupled to the second terminal of the buffer circuit (250); and a detection circuit (310) having a first terminal and a second terminal.

Description

Technical Field

[0001] The present specification relates generally to clock generation, and more particularly to methods and apparatus for multi-phase clock generation. Background Art

[0002] As circuits continue to become more complex, the incentive to create flexible clock generation circuits continues to increase. In some devices, clock generation circuits need to be able to generate multiple clock signals. Some such clock generation circuits generate each of the multiple clock signals with a different phase. Summary of the invention

[0003] For a method and apparatus for multi-phase clock generation, an example apparatus includes a first clock generation circuit and a second clock generation circuit, the first clock generation circuit including: an interlocking circuit having a terminal; a reference clock generation circuit having a first terminal and a second terminal, the first terminal of the reference clock generation circuit being coupled to a terminal of the interlocking circuit; a first duty cycle replica circuit having a first terminal and a second terminal, the first terminal of the first duty cycle replica circuit being coupled to a second terminal of the reference clock generation circuit; and a buffer circuit having a first terminal and a second terminal, the first terminal of the buffer circuit being coupled to a second terminal of the first duty cycle replica circuit; the second clock generation circuit including: a detection circuit having a first terminal and a second terminal, the first terminal of the detection circuit being coupled to a second terminal of the buffer circuit; a second detection circuit having a first terminal and a second terminal, the first terminal of the second detection circuit being coupled to a second terminal of the detection circuit; and a second duty cycle replica circuit having a terminal coupled to a second terminal of the second detection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of an example chain-linked power supply in which an example power converter circuit is powered using example primary and secondary clock generation circuits.

[0005] Figure 2 is configured to generate a clock signal Figure 1 A block diagram of an example of a primary clock generation circuit of FIG. 1 , which includes an example interlock circuit, an example reference clock generation circuit, and an example duty cycle replica circuit.

[0006] Figure 3 yes Figure 1 A block diagram of an example of a secondary clock generation circuit including an example duty cycle replica circuit to generate a phase-shifted clock signal.

[0007] Figure 4 yes Figure 2 Schematic diagram of an example implementation of an interlock circuit.

[0008] Figure 5 yes Figure 2 Schematic diagram of an example implementation of a reference clock generation circuit.

[0009] Figure 6 yes Figure 2 and Figure 3 Schematic diagram of an example implementation of a duty cycle replica circuit.

[0010] Figure 7 yes Figure 1-Figure 3 A timing diagram of an example operation of the primary and secondary clock generation circuits.

[0011] Fig. 8A and Figure 8B The formation expression can be Figure 1-Figure 3 Flowchart of example operations of primary and secondary clock generation circuits implemented, instantiated and / or performed to generate multiple clock signals of different phases.

[0012] The same reference numbers or other reference designators are used in the drawings to designate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0013] The drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and the specification refer to the same or similar parts. Although the drawings show areas with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, boundaries and / or lines may be invisible, blended, and / or irregular.

[0014] Methods for generating clock signals are constantly evolving. Some clock generation circuits utilize electrical properties of components such as resistors, capacitors, and / or crystals to generate clock signals. Some applications can use relatively simple clock generation methods, such as oscillation between resistors and capacitors. Other applications require more complex clock generation methods. Such applications include relatively high-speed processor circuits, security circuits, switching power supplies, etc.

[0015] As electronic devices continue to advance, designers are motivated to use increasingly complex clock generation circuits that are capable of generating multiple clock signals. Some instances of clock generation circuits require multiple clock signals. In such applications, designers typically use timing techniques, such as clock division or phase shifting, to generate multiple clock signals from a single clock signal. However, most timing techniques are not adjustable and require a device-specific design, such as a set amount of clock signals or a predetermined duty cycle.

[0016] Examples described herein include methods and apparatus for a multi-phase clock generation circuit capable of dynamically adjusting the duty cycle of a clock signal. In some described examples, a primary clock generation circuit is coupled in series with one or more instances of a secondary clock generation circuit, thereby creating a digital locked loop. The digital locked loop allows the clock generation circuit to modify the duty cycle of each clock signal to compensate for the number of secondary clock generation circuits. Each of the primary clock generation circuit and one or more instances of the secondary clock generation circuit generates a clock signal. The primary clock generation circuit modifies the duty cycle of the first clock signal to account for one or more instances of the secondary clock generation circuit. The secondary clock generation circuit generates a clock signal by copying the duty cycle of the first clock signal. In addition, the secondary clock generation circuit synchronizes the falling edge of the input clock signal with the rising edge of the output clock signal. Advantageously, the primary clock generation circuit adjusts the duty cycle of multiple clock signals to compensate for multiple secondary clock generation circuits.

[0017] Figure 1 is a block diagram of an example chained power supply 100 configured to provide power from an example power supply 105 to an example processor circuit 110. Figure 1 In the example of , the chain power supply 100 includes an example primary power circuit 115, a first example secondary power circuit 120, a second example secondary power circuit 125, and a third example secondary power circuit 130. The chain power supply 100 supplies continuous power to the processor circuit 110 using multi-phase clock generation.

[0018] exist Figure 1 In the examples, the processor circuit 110 is a programmable circuit that is configured to implement, instantiate and / or execute example machine-readable instructions and / or perform example operations. In some examples, the processor circuit 110 is configured to operate based on the amount of power supplied by the chain power supply 100. In such examples, the chain power supply circuit 100 is powered from all power circuits 115-130 to improve the performance of the processor circuit 100. In other examples, the chain power supply circuit 100 is powered using the primary power circuit 115 and one or more secondary power circuits 120-130. For example, one or more secondary power circuits are no longer operating. In such examples, the processor circuit 110 is still able to perform operations, but the processor circuit may be limited due to the reduction in power supplied by the chain power supply circuit 100. Although in Figure 1 In the example of FIG. 1 , the chain power supply 100 is configured to power the processor circuit 110 , but the chain power supply 100 may power alternative external circuits.

[0019] The primary power circuit 115 is coupled to the power source 105, the processor circuit 110, and the secondary power circuits 120-130. Figure 1In the example of , primary power circuit 115 includes an example primary clock generation circuit 135 and a first example power converter 140. Primary power circuit 115 converts and / or regulates power from power supply 105 based on a clock signal from primary clock generation circuit 135. Primary power circuit 115 provides power to processor circuit 110.

[0020] The first secondary power circuit 120 is coupled to the power supply 105, the processor circuit 110, and the power circuits 115, 125, and 130. Figure 1 In the example of FIG. 1 , the first secondary power circuit 120 includes a first example secondary clock generation circuit 145 and a second example power converter 150. The first secondary power circuit 120 converts and / or adjusts power from the power supply 105 based on a clock signal from the first secondary clock generation circuit 145. The first secondary power circuit 120 provides power to the processor circuit 110.

[0021] The second secondary power circuit 125 is coupled to the power supply 105, the processor circuit 110, and the power circuits 115, 120, and 130. Figure 1 In the example of FIG. 1 , the second secondary power circuit 125 includes a second example secondary clock generating circuit 155 and a third example power converter 160 . The second secondary power circuit 125 is configured similarly to the first secondary power circuit 120 .

[0022] The third secondary power circuit 130 is coupled to the power supply 105, the processor circuit 110, and the power circuits 115-125. Figure 1 In the example of FIG. 1 , the third secondary power circuit 130 includes a third example secondary clock generating circuit 165 and a fourth example power converter 170 . The third secondary power circuit 130 is configured similarly to the secondary power circuits 120 and 125 .

[0023] The primary clock generation circuit 135 has a first terminal (SYNCOUT) coupled to the first secondary power circuit 120. The primary clock generation circuit 135 has a second terminal (SYNCIN) coupled to the third secondary power circuit 130. The primary clock generation circuit 135 has a third terminal coupled to the first power converter 140. The primary clock generation circuit 135 receives an input clock signal from the third secondary power circuit 130. The primary clock generation circuit 135 generates an interlock voltage based on the input clock signal and the output clock signal of the primary clock generation circuit 135. The primary clock generation circuit 135 generates a reference clock based on the interlock voltage. The primary clock generation circuit 135 replicates the duty cycle of the reference clock to generate an output clock signal. The primary clock generation circuit 135 supplies the output clock signal to the first secondary power circuit 120. The primary clock generation circuit 135 may supply the output clock to the first power converter 140. In some examples, the primary clock generation circuit 135 uses spread spectrum modulation (SSM) to generate an internal clock signal based on the output clock signal. In such an example, the primary clock generation circuit 135 supplies an internal clock signal to the first power converter 140. Figure 2 Example implementations of primary clock generation circuit 135 are described in further detail.

[0024] The first power converter 140 has a first terminal coupled to the power supply 105. The first power converter 140 has a second terminal coupled to the primary clock generation circuit 135. The first power converter 140 has a third terminal coupled to the processor circuit 110 and the secondary power circuits 120-130. The first power converter 140 converts and / or regulates power from the power supply 105. The first power converter 140 can use the phase of the clock signal from the primary clock generation circuit 135 to power the processor circuit 110. In some examples, the first power converter 140 can be a switching power converter, a regulator circuit, etc.

[0025] The first secondary clock generation circuit 145 has a first terminal (SYNCIN) coupled to the primary clock generation circuit 135 of the primary power circuit 115. The first secondary clock generation circuit 145 has a second terminal (SYNCOUT) coupled to the second secondary power circuit 125. The first secondary clock generation circuit 145 receives an input clock signal from the primary clock generation circuit 135. The first secondary clock generation circuit 145 generates an output clock signal by replicating the duty cycle of the input clock signal. The first secondary clock generation circuit 145 generates the output clock signal to have a rising edge approximately simultaneous with the falling edge of the input clock signal from the primary clock generation circuit 135. The first secondary clock generation circuit 145 supplies the output clock signal to the second secondary power circuit 125. The first secondary clock generation circuit 145 can supply the output clock to the second power converter 150. In some examples, the first secondary clock generation circuit 145 uses SSM to generate an internal clock signal based on the output clock signal. In such examples, the first secondary clock generation circuit 145 supplies the internal clock signal to the second power converter 150. The following is in conjunction with Figure 3 An example implementation of the first secondary clock generation circuit 145 is described in further detail.

[0026] Second power converter 150 has a first terminal coupled to power supply 105. Second power converter 150 has a second terminal coupled to first secondary clock generation circuit 145. Second power converter 150 has a third terminal coupled to processor circuit 110 and power circuits 115, 125, and 130. Second power converter 150 converts and / or regulates power from power supply 105. Second power converter 150 can use the phase of the clock signal from first secondary clock generation circuit 145 to power processor circuit 110. In some examples, second power converter 150 can be a switching power converter, a regulator circuit, etc.

[0027] The second secondary clock generating circuit 155 has a first terminal coupled to the first secondary clock generating circuit 145 of the first secondary power circuit 120. The second secondary clock generating circuit 155 has a second terminal coupled to the third secondary power circuit 130. The second secondary clock generating circuit 155 is configured similarly to the first secondary clock generating circuit 145.

[0028] Third power converter 160 has a first terminal coupled to power source 105. Third power converter 160 has a second terminal coupled to second secondary clock generation circuit 155. Third power converter 160 has a third terminal coupled to processor circuit 110. Third power converter 160 is configured similarly to power converters 140 and 150.

[0029] The third secondary clock generating circuit 165 has a first terminal coupled to the second secondary clock generating circuit 155 of the second secondary power circuit 125. The third secondary clock generating circuit 165 has a second terminal coupled to the primary clock generating circuit 135 of the primary power circuit 115. The third secondary clock generating circuit 165 is configured similarly to the secondary clock generating circuits 145 and 155.

[0030] Fourth power converter 170 has a first terminal coupled to power source 105. Fourth power converter 170 has a second terminal coupled to third secondary clock generation circuit 165. Fourth power converter 170 has a third terminal coupled to processor circuit 110. Fourth power converter 170 is configured similarly to power converters 140, 150, and 160.

[0031] In an example startup operation, the primary clock generation circuit 135 generates a first output clock based on the interlock voltage. The primary clock generation circuit 135 supplies the first output clock to the first secondary clock generation circuit 145. The first secondary clock generation circuit 145 replicates and phase-shifts the first output clock to generate a second output clock. The duty cycle of the second output clock is approximately equal to the duty cycle of the first output clock from the primary clock generation circuit 135. The rising edge of the second output clock occurs approximately simultaneously with the falling edge of the first output clock from the primary clock generation circuit 135. The first secondary clock generation circuit 145 supplies the second output clock to the second secondary clock generation circuit 155.

[0032] In such an example operation, the second secondary clock generating circuit 155 replicates and phase-shifts the second output clock to generate a third output clock. The duty cycle of the third output clock is approximately equal to the duty cycles of the output clocks from the clock generating circuits 135 and 145. The rising edge of the third output clock occurs approximately simultaneously with the falling edge of the second output clock from the first secondary clock generating circuit 145. The second secondary clock generating circuit 155 supplies the third output clock to the third secondary clock generating circuit 165. The third secondary clock generating circuit 165 replicates and phase-shifts the third output clock to generate a fourth output clock. The duty cycle of the fourth output clock is approximately equal to the duty cycle of the output clocks from the clock generating circuits 135, 145, and 155. The rising edge of the fourth output clock occurs approximately simultaneously with the falling edge of the third output clock from the second secondary clock generating circuit 155. The third secondary clock generating circuit 165 supplies the fourth output clock to the primary clock generating circuit 135.

[0033] In such an example operation, the primary clock generation circuit 135 compares the falling edge of the fourth output clock with the rising edge of the first output clock. When the falling edge of the fourth output clock occurs before the rising edge of the first output clock, the primary clock generation circuit 135 modifies the interlock voltage. The primary clock generation circuit 135 generates the first output clock using the modified interlock voltage. Modifying the interlock voltage changes the duty cycle of the first output clock, which determines the duty cycle of the output clocks of the secondary clock generation circuits 145, 155, and 165. The secondary clock generation circuits 145, 155, and 165 generate the output clocks using the modified duty cycle. The primary clock generation circuit 135 continues to modify the interlock voltage until the rising edge of the fourth output clock from the third secondary clock generation circuit 165 occurs approximately simultaneously with the rising edge of the reference clock.

[0034] Advantageously, primary clock generation circuit 135 dynamically adjusts the duty cycle of the clocks generated by clock generation circuits 135, 145, 155, and 165. Advantageously, primary clock generation circuit 135 can be linked to one or more instances of secondary clock generation circuits 145, 155, and / or 165 without being modified or adjusted. Advantageously, primary clock generation circuit 135 can correct the duty cycle of the output clock to compensate for one or more of the secondary clock generation circuits 145, 155, and / or 165 being inoperative. Advantageously, one or more of power circuits 115-130 can continue to provide power to processor circuit 110 despite one or more of the power circuits being inoperative (e.g., damaged, shut down, disabled, etc.).

[0035] Figure 2 yes Figure 1 A block diagram of an example of a primary clock generating circuit 135 is shown in FIG. Figure 2 In the example of , the primary clock generation circuit 135 includes an example detection circuit 210, an example interlock circuit 220, an example reference clock generation circuit 230, an example duty cycle replica circuit 240, an example buffer circuit 250, and an example SSM circuit 260. The primary clock generation circuit 135 generates an output clock signal (SYNCOUT) based on an input clock signal (SYNCIN) and a reference clock.

[0036] Detection circuit 210 has an input coupled to an input clock signal. Detection circuit 210 has an output coupled to interlock circuit 220. Detection circuit 210 isolates interlock circuit 220 from a circuit that supplies the input clock signal. Detection circuit 210 buffers the input clock signal. For example, detection circuit 210 increases the drive strength of the input clock signal. In some examples, detection circuit 210 detects a failure of a secondary clock generation circuit (e.g., secondary clock generation circuit 145, 155, and / or 165). In such examples, detection circuit 210 determines a failure of the secondary clock generation circuit when the input clock signal is not received. Detection circuit 210 supplies the input clock signal to interlock circuit 220.

[0037] The interlock circuit 220 has a first terminal coupled to the detection circuit 210. The interlock circuit 220 has a second terminal coupled to the reference clock generation circuit 230. The interlock circuit 220 has a third terminal coupled to the buffer circuit 250 and the SSM circuit 260. The interlock circuit 220 receives an input clock signal from the detection circuit 210. The interlock circuit 220 receives an output clock signal from the buffer circuit 250. The interlock circuit 220 compares the output clock signal with the input clock signal.

[0038] The interlock circuit 220 determines an interlock voltage representing the duty cycle of the output clock signal. When the rising edge of the output clock signal does not occur at approximately the same time as the falling edge of the input clock signal, the interlock circuit 220 modifies the interlock voltage. In some examples, the interlock circuit 220 modifies the interlock voltage to increase the duty cycle of the output clock signal. In such examples, when the duty cycle of the output clock signal causes the falling edge of the input clock signal to occur at a time approximately equal to the rising edge of the output clock signal, the interlock circuit 220 no longer modifies the interlock voltage. The interlock circuit 220 sources current from the reference clock generation circuit 230 based on the interlock voltage. Figure 4 An example implementation of the interlock circuit 220 is described.

[0039] The reference clock generation circuit 230 has a first terminal coupled to the interlock circuit 220. The reference clock generation circuit 230 has a second terminal coupled to the duty cycle replica circuit 240. In some examples, the interlock circuit 220 obtains a current from the reference clock generation circuit 230 based on the interlock voltage. The reference clock generation circuit 230 generates a reference clock signal based on the reference ramp signal. The interlock circuit 220 controls the duty cycle of the reference clock signal by modifying the ramp time of the reference ramp signal. The duration of the reference ramp signal falling determines the duty cycle of the reference clock signal. The interlock circuit 220 increases the duty cycle of the reference clock signal by increasing the duration of the reference ramp signal falling. The reference clock generation circuit 230 supplies the reference clock signal to the duty cycle replica circuit 240. hereinafter combined Figure 5An example implementation of the reference clock generation circuit 230 is described.

[0040] The duty cycle replica circuit 240 has a first terminal coupled to the reference clock generation circuit 230. The duty cycle replica circuit 240 has a second terminal coupled to the buffer circuit 250. The duty cycle replica circuit 240 receives the reference clock signal from the reference clock generation circuit 230. The duty cycle replica circuit 240 generates an output clock signal by replicating the duty cycle of the reference clock signal. The duty cycle replica circuit 240 synchronizes the rising edge of the output clock signal with the falling edge of the reference clock signal. For example, when the duty cycle of the reference clock signal is 10%, the duty cycle of the output clock signal is 10%. In such an example, the rising edge of the output clock signal occurs approximately simultaneously with the falling edge of the reference clock signal. The duty cycle replica circuit 240 supplies the output clock signal to the buffer circuit 250. Advantageously, the duty cycle replica circuit 240 phase-shifts the output clock signal from the reference clock signal by synchronizing the rising edge of the output clock signal with the falling edge of the reference clock signal.

[0041] Buffer circuit 250 has an input coupled to duty cycle replica circuit 240. Buffer circuit 250 has an output coupled to interlock circuit 220 and SSM circuit 260. Buffer circuit 250 receives an output clock signal from duty cycle replica circuit 240. Buffer circuit 250 buffers the output clock signal. Buffer circuit 250 isolates duty cycle replica circuit 240 from circuits coupled to the output of buffer circuit 250. Buffer circuit 250 supplies the output clock signal to interlock circuit 220 and SSM circuit 260.

[0042] The SSM circuit 260 has a first terminal coupled to the interlock circuit 220 and the buffer circuit 250. The SSM circuit 260 has a first terminal configured to couple to the Figure 1 The SSM circuit 260 is configured to supply the output clock signal to the first power converter 140. The SSM circuit 260 applies a spread spectrum modulation technique to the output clock signal. In some examples, the SSM circuit 260 increases noise immunity by increasing the peak value at the target frequency of the output clock signal. In some examples, the SSM circuit 260 can be modified or removed from the primary clock generation circuit 135. The SSM circuit 260 is configured to supply the output clock signal to the first power converter 140.

[0043] Figure 3 yes Figure 1 A block diagram of an example of a secondary clock generation circuit 145, 155 and / or 165 is shown. Figure 3 In the example of Figure 2 The secondary clock generation circuit 145 is based on the duty cycle replica circuit 240, the example detection circuit 310, the example buffer circuit 330 and the example SSM circuit 340. Figure 1 and Figure 2 The output clock signal (SYNCOUT) is generated based on the input clock signal (SYNCIN) of one of the primary clock generation circuits 135 or the other of the secondary clock generation circuits 155 or 165.

[0044] Detection circuit 310 has an input coupled to the input clock signal. Detection circuit 310 has an output coupled to duty cycle replica circuit 240. Detection circuit 310 isolates duty cycle replica circuit 240 from the circuit that supplies the input clock signal. Detection circuit 310 buffers the input clock signal. For example, detection circuit 310 generates a replica of the input clock signal with increased drive strength. Detection circuit 310 supplies the input clock signal to duty cycle replica circuit 240.

[0045] exist Figure 3 In the example of , the duty cycle replica circuit 240 has a first terminal coupled to the detection circuit 310. The duty cycle replica circuit 240 has a second terminal coupled to the buffer circuit 330. The duty cycle replica circuit 240 receives the input clock signal from the detection circuit 310. The duty cycle replica circuit 240 generates an output clock signal by replicating the duty cycle of the input clock signal.

[0046] Buffer circuit 330 has an input coupled to duty cycle replica circuit 240. Buffer circuit 330 has an output coupled to SSM circuit 340. Buffer circuit 330 receives an output clock signal from duty cycle replica circuit 240. Buffer circuit 330 buffers the output clock signal. Buffer circuit 330 isolates duty cycle replica circuit 240 from circuits coupled to the output of buffer circuit 330. Buffer circuit 330 supplies the output clock signal to SSM circuit 340.

[0047] The SSM circuit 340 has a first terminal coupled to the buffer circuit 330. The SSM circuit 340 has a first terminal configured to couple to the Figure 1 The SSM circuit 340 applies a spread spectrum modulation technique to the output clock signal. In some examples, the SSM circuit 340 increases noise immunity by increasing the peak value at the target frequency of the output clock signal. In some examples, the SSM circuit 340 can be modified or removed from the secondary clock generation circuit 145. The SSM circuit 340 is configured to supply the output clock signal to the second power converter 150.

[0048] Figure 4 yes Figure 2 A schematic diagram of an example implementation of the interlock circuit 220 is shown. Figure 2In the example of FIG. 1 , the interlock circuit 220 includes a first example logic gate 405, a second example logic gate 410, an example inverter 415, an example logic device 420, a third example logic gate 425, a fourth example logic gate 430, a first example amplifier 435, a second example amplifier 440, an example capacitor 445, an example voltage reference 450, and a third example amplifier 455. The interlock circuit 220 receives an input clock signal (SYNCIN) and an output clock signal (SYNCOUT). The interlock circuit 220 determines an interlock voltage representing a duty cycle of the output clock signal. The interlock circuit 220 is configured to generate an interlock voltage based on the interlock voltage from the output clock signal. Figure 2 The reference clock generating circuit 230 sinks current.

[0049] The first logic gate 405 has a first input coupled to the input clock signal, the second logic gate 410, and the logic device 420. The first logic gate 405 has a second input coupled to the output clock signal, the second logic gate 410, and the inverter 415. The first logic gate 405 has an output coupled to the third logic gate 425. Figure 4 In the example of , the first logic gate 405 is an exclusive NOR gate (XNOR gate). The first logic gate 405 compares the input clock signal with the output clock signal. Alternatively, the first logic gate 405 can be replaced and / or modified with one or more alternative logic gates.

[0050] The second logic gate 410 has a first input coupled to the input clock signal, the first logic gate 405, and the logic device 420. The second logic gate 410 has a second input coupled to the output clock signal, the first logic gate 405, and the inverter 415. The second logic gate 410 has an output coupled to the fourth logic gate 430. Figure 4 In the example of , the second logic gate 410 is an AND gate. The second logic gate 410 compares the input clock signal with the output clock signal. Alternatively, the second logic gate 410 can be replaced and / or modified with one or more alternative logic gates.

[0051] Inverter 415 has a first terminal coupled to the output clock signal and logic gates 405 and 410. Inverter 415 has a second terminal coupled to logic device 420. Inverter 415 inverts the output clock signal. Inverter 415 provides an inverted output clock signal to logic device 420.

[0052] Logic device 420 has a first input coupled to the input clock signal and logic gates 405 and 410. Logic device 420 has a second input coupled to inverter 415. Logic device 420 has an output coupled to logic gates 425 and 430. Figure 4In the example of , the logic device 420 is a rising edge triggered set-reset (SR) flip-flop. The logic device 420 latches the input clock signal based on the inverted output clock signal from the inverter 415. Alternatively, the logic device 420 can be replaced and / or modified with alternative circuits.

[0053] The third logic gate 425 has a first input coupled to the first logic gate 405. The third logic gate 425 has a second input coupled to the logic device 420 and the fourth logic gate 430. The third logic gate 425 has an output coupled to the first amplifier 435. Figure 4 In the example of FIG. 4 , the third logic gate 425 is an AND gate. Alternatively, the third logic gate 425 may be replaced and / or modified with one or more alternative logic gates.

[0054] The fourth logic gate 430 has a first input coupled to the second logic gate 410. The fourth logic gate 430 has a second input coupled to the logic device 420 and the third logic gate 425. The fourth logic gate 430 has an output coupled to the second amplifier 440. Figure 4 In the example of FIG. 4 , the fourth logic gate 430 is an AND gate. Alternatively, the fourth logic gate 430 may be replaced and / or modified with one or more alternative logic gates.

[0055] The first amplifier 435 has a first input coupled to the third logic gate 425. The first amplifier 435 has a second input coupled to a common potential (e.g., ground). The first amplifier 435 has a first output coupled to the common potential. The first amplifier 435 has a second output coupled to the second amplifier 440, the capacitor 445, and the third amplifier 455. The first amplifier 435 supplies current to the second output based on the voltage of the first input. In some examples, when the voltage of the first input is greater than the voltage of the second input, the first amplifier 435 obtains current from the first output. Figure 4 In the example of FIG. 1 , the first amplifier 435 may be referred to as a transconductance (g m ) amplifier.

[0056] The second amplifier 440 has a first input coupled to the fourth logic gate 430. The second amplifier 440 has a second input coupled to a common potential. The second amplifier 440 has a first output coupled to the first amplifier 435, the capacitor 445, and the third amplifier 455. The second amplifier 440 has a second output coupled to a common potential. The second amplifier 440 obtains a current from the first output based on a voltage of the first input. In some examples, when the voltage of the first input is greater than the voltage of the second input, the second amplifier 440 obtains a current from the first output. Figure 4 In the example of FIG. 1 , the second amplifier 440 may be referred to as a transconductance (gm ) amplifier.

[0057] Capacitor 445 has a first terminal coupled to amplifiers 435, 440, and 455. Capacitor 445 has a second terminal coupled to voltage reference 450 and third amplifier 455. Capacitor 445 sets an interlock voltage based on the voltage of voltage reference 450 and currents sourced and / or sunk by amplifiers 435 and 440.

[0058] The third amplifier 455 has a first input coupled to amplifiers 435 and 440 and capacitor 445. The third amplifier 455 has a second input coupled to capacitor 445 and voltage reference 450. The third amplifier 455 has a first input coupled to amplifiers 435 and 440 and capacitor 445. Figure 2 The first output of the reference clock generation circuit 230. The third amplifier 445 has a second output coupled to the common potential. The third amplifier 455 obtains a current from the reference clock generation circuit 230 based on the voltage difference between the first input and the second input of the third amplifier 455. Figure 4 In the example of , the third amplifier 455 is controlled by the voltage difference across the capacitor 445 .

[0059] In an example operation, the first amplifier 435 begins to supply current to the capacitor 445 in response to the falling edge of the input clock signal when the output clock signal is logic low. In such operation, the interlock voltage of the capacitor 445 increases. When either the input clock signal or the output clock signal is equal to logic high, the first amplifier 435 does not supply current to the capacitor 445. Advantageously, the interlock voltage of the capacitor 445 increases in proportion to the non-overlap time between the falling edge of the input clock signal and the rising edge of the output clock signal.

[0060] In example operation, in response to the overlap duration that both the input clock signal and the output clock signal are logic high, the second amplifier 440 begins to sink current from the capacitor 445. In such operation, the interlock voltage of the capacitor 445 decreases or remains constant as the current supplied by the first amplifier 435 is sunk by the second amplifier 440. Advantageously, the second amplifier 440 prevents the interlock voltage of the capacitor 445 from increasing during the overlap duty cycle.

[0061] Figure 5 yes Figure 2 Schematic diagram of an example implementation of a reference clock generation circuit 230. Figure 5 In the example of FIG. 2 , the reference clock generation circuit 230 includes an example capacitor 505, a first example voltage reference 510, an example switch 515, a second example voltage reference 520, a first example amplifier 525, an example logic device 530, an example clock source 535, and a second example amplifier 540. The reference clock generation circuit 230 is based on Figure 2 and Figure 4 The interlock circuit 220 obtains the current and the frequency of the clock source 535 to generate a reference clock signal having a duty cycle.

[0062] Capacitor 505 has a first terminal coupled to switch 515, amplifiers 525 and 540 and adapted to be coupled to interlock circuit 220. Capacitor 505 has a second terminal coupled to voltage references 510 and 520 and switch 515. Capacitor 505 generates a reference ramp voltage based on a current supplied to and / or sunk from capacitor 505.

[0063] The first voltage reference 510 is coupled to the capacitor 505, the switch 515, and the second voltage reference 520. The first voltage reference 510 supplies a voltage to the capacitor 505 and the second voltage reference 520. Figure 5 In the example, first voltage reference 510 biases capacitor 505 .

[0064] The switch 515 has a first terminal coupled to the capacitor 505, the amplifiers 525 and 540 and adapted to be coupled to the interlock circuit 220. The switch 515 has a second terminal coupled to the capacitor 505 and the voltage references 510 and 520. The switch 515 has a control terminal coupled to the logic device 530. In response to the switch 515 being closed by the logic device 530, the first terminal of the switch 515 is coupled to the second terminal of the switch 515. In response to the switch 515 being opened by the logic device 530, the first terminal of the switch 515 is decoupled from the second terminal of the switch 515.

[0065] The second voltage reference 520 has a first terminal coupled to the capacitor 505, the first voltage reference 510, and the switch 515. The second voltage reference 520 has a second terminal coupled to the first amplifier 525. The second voltage reference 520 supplies a voltage to the first amplifier 525. Figure 5 In the example of , the second voltage reference 520 biases the input of the first amplifier 525 .

[0066] The first amplifier 525 has a first input coupled to the capacitor 505, the switch 515, the second amplifier 540 and adapted to be coupled to the interlock circuit 220. The first amplifier 525 has a second input coupled to the second voltage reference 520. The first amplifier 525 has an output coupled to the logic device 530. The first amplifier 525 supplies an output voltage to the logic device 530 based on a voltage difference between the first input and the second input of the first amplifier 525. In some examples, when the voltage of the first input is greater than the voltage of the second input, the first amplifier 525 sets the output to a logic high. In such examples, when the voltage of the first input is less than the voltage of the second input, the first amplifier 525 sets the output to a logic low. Advantageously, when the reference slope of the capacitor 505 is greater than the series combination of the voltage references 510 and 520, the first amplifier 525 generates a logic high.

[0067] The logic device 530 has a first input coupled to the first amplifier 525. The logic device 530 has a second input coupled to a clock source 535. The logic device 530 has a first output (Q) coupled to the second amplifier 540 and configured to couple to Figure 2 The duty cycle replica circuit 240. The logic device 530 has a second output (QN) coupled to the switch 515. Figure 5 In the example of , logic device 530 is a rising edge triggered set-reset (SR) flip-flop. Alternatively, logic device 530 may be replaced and / or modified with alternative circuits. Advantageously, when the reference slope of capacitor 505 is greater than reference voltages 510 and 520 and clock source 535 supplies a rising edge to logic device 530, the first output of logic device 530 is approximately equal to a logic high. Advantageously, when the reference slope of capacitor 505 is less than reference voltages 510 and 520, the first output of logic device 530 is approximately equal to a logic low.

[0068] The clock source 535 has a first terminal coupled to the logic device 530. The clock source 535 has a second terminal coupled to a common potential. The clock source 535 supplies a clock signal to the logic device 530. The period of the clock signal from the clock source 535 determines the period time of the reference clock. Advantageously, modifying the clock source 535 will modify the duty cycle of the reference clock.

[0069] The second amplifier 540 has a first input coupled to the logic device 530. The second amplifier 540 has a second input coupled to a common potential. The second amplifier 540 has a first output coupled to a common potential. The second amplifier 540 has a second output coupled to the capacitor 505, the switch 515, the first amplifier 525 and configured to couple to Figure 2The interlock circuit 220 of the embodiment of the present invention. The second amplifier 540 supplies current from a common potential based on a voltage difference between a first input and a second input of the second amplifier 540. Figure 5 In the example of , the second amplifier 540 is controlled by the logic device 530 .

[0070] In example operation, the logic device 530 closes (e.g., turns on) the switch 515 to keep the reference slope of the capacitor 505 approximately equal to zero volts. In such example operation, the rising edge from the clock source 535 sets the output of the logic device 530, thereby opening (e.g., not turning on) the switch 515. The second amplifier 540 supplies current to the capacitor 505 in response to the rising edge of the clock source 535. In response to the current from the second amplifier 540, the reference slope of the capacitor 505 begins to increase. In such example operation, the rate of increase of the reference slope is determined based on the amount of current collected by the interlock circuit 220. For example, as the current obtained by the interlock circuit 220 increases, the increase of the reference becomes slower.

[0071] The first amplifier 525 detects when the reference ramp is greater than the series combination of the reference voltages 510 and 520. In response to the first amplifier 525 detecting that the reference ramp is greater than the reference voltages 510 and 520, the logic device 530 generates a falling edge of the reference clock. In response to the falling edge of the reference clock, the logic device 530 closes the switch 515. Thus, the capacitor 505 is shorted and the reference ramp is set. Advantageously, increasing the current sunk by the interlock circuit 220 will increase the duration it takes for the reference ramp to be approximately equal to the combination of the reference voltages 510 and 520.

[0072] Figure 6 yes Figure 2 A schematic diagram of an example implementation of a duty cycle replica circuit 240 is shown. Figure 6 In the example of FIG. 1 , the duty cycle replica circuit 240 includes a first example amplifier 610, an example logic device 620, a second example amplifier 630, an example capacitor 640, an example reference voltage 650, and a third example amplifier 660. The duty cycle replica circuit 240 is configured to be coupled to Figure 2 and Figure 5 The reference clock generating circuit 230 and Figure 2 Alternatively, Figure 3 In such an example, the duty cycle replica circuit 240 is configured to be coupled to Figure 3 The detection circuit 310 and Figure 3 The buffer circuit 330 is provided.

[0073] The first amplifier 610 has a first input that is coupled to the logic device 620 and is configured to be coupled to one of the reference clock generation circuit 230 or the detection circuit 310. The first amplifier 610 has a second input coupled to a common potential. The first amplifier 610 has a first output coupled to a common potential. The first amplifier 610 has a second output coupled to the second amplifier 630, the capacitor 640, and the third amplifier 660. The first amplifier 610 supplies current to the second output based on the voltage of the first input. In some examples, when the voltage of the first input is greater than the voltage of the second input, the first amplifier 610 obtains current from the first output. Figure 6 In the example of FIG. 5 , the first amplifier 610 may be referred to as a transconductance amplifier.

[0074] The logic device 620 has a first input (S) coupled to the first amplifier 610 and configured to be coupled to one of the reference clock generation circuit 230 or the detection circuit 310. The logic device 620 has a second input (R) coupled to the third amplifier 660. The logic device 620 has an output coupled to the second amplifier 630 and configured to be coupled to one of the buffer circuits 250 or 330. Figure 6 In the example of FIG. 6 , the logic device 620 is a rising edge triggered set-reset (SR) flip-flop. Alternatively, the logic device 620 can be replaced and / or modified with alternative circuits.

[0075] The second amplifier 630 has a first input that is coupled to the logic device 620 and is configured to be coupled to one of the buffer circuits 250 or 330. The second amplifier 660 has a second input that is coupled to a common potential. The second amplifier 630 has a first output that is coupled to the first amplifier 610, the capacitor 640, and the third amplifier 660. The second amplifier 630 has a second output that is coupled to a common potential. The second amplifier 630 obtains a current from the first output based on a voltage of the first input. In some examples, when the voltage of the first input is greater than the voltage of the second input, the second amplifier 630 obtains a current from the first output. Figure 6 In the example of FIG. 5 , the second amplifier 630 may be referred to as a transconductance amplifier.

[0076] Capacitor 640 has a first terminal coupled to amplifiers 610, 630, and 660. Capacitor 640 has a second terminal coupled to reference voltage 650 and third amplifier 660. Capacitor 640 generates a replica ramp based on current obtained and / or collected by amplifiers 610 and 630. The replica ramp is a triangular waveform having a ramp-up and ramp-down duration. The ramp-up and ramp-down durations are proportional to the duty cycle of the signal at the input of the first amplifier 610 and the logic device 620. The ramp-up and ramp-down durations increase as the duty cycle of the signal coupled to the first amplifier 610 and the logic device 620 increases. In response to the first amplifier 610 receiving an input, the first amplifier 610 builds a ramp-up of the replica ramp by supplying current to capacitor 640. In response to the logic device 620 receiving an input, the second amplifier 630 builds a ramp-down of the replica ramp by collecting current from capacitor 640. Capacitor 640 supplies the replica ramp to the third amplifier 660 .

[0077] The reference voltage 650 is coupled to the capacitor 640 and the third amplifier 660. The reference voltage 650 is a DC voltage configured to bias the capacitor 640 and the third amplifier 660.

[0078] The third amplifier 660 has a first input coupled to the amplifiers 610 and 630 and the capacitor 640. The third amplifier 660 has a second input coupled to the capacitor 640 and the reference voltage 650. The third amplifier 660 has an output coupled to the logic device 620. The third amplifier 660 sets the voltage of the output based on the voltage difference between the first input and the second input. In some examples, when the voltage of the first input is greater than the voltage of the second input, the third amplifier 660 sets the output to a voltage approximately equal to a logic high. Figure 6 In the example of , the third amplifier 660 can be referred to as a comparator.

[0079] In example operation, the output of the third amplifier 660 is set based on the replica slope across the capacitor 640. In such example operation, the amplifiers 610 and 630 source and / or sink current to modify the replica slope of the capacitor 640. When the reference clock from the reference clock generation circuit is logic high, the first amplifier 610 supplies the reference current to the capacitor 640. The third amplifier 660 outputs a logic low in response to the reference current from the first amplifier 610 increasing the reference slope of the capacitor 640 to a voltage greater than and / or equal to the reference voltage 650.

[0080] In such example operation, when the reference clock from the reference clock generation circuit is logic low, the first amplifier 610 cannot supply the reference current to the capacitor 640. After the falling edge of the reference clock and the logic low from the third amplifier 660, the logic device 620 outputs a logic high. In response to the logic low from the logic device 620, the second amplifier 630 begins to source current from the capacitor 640. As the second amplifier 630 continues to sink current, the replica slope of the capacitor 640 begins to decrease. The third amplifier 660 outputs a logic high in response to the replica slope of the capacitor 640 decreasing below the reference voltage 650. In response to the logic high from the third amplifier 660 and the logic low of the reference clock, the logic device 620 begins to output a logic low.

[0081] Advantageously, the current supplied by the first amplifier 610 to the capacitor 640 is approximately equal to the current sourced by the second amplifier 630. Advantageously, the duration that the reference clock signal causes the first amplifier to source the reference current is approximately equal to the duration that the logic device 620 causes the second amplifier 630 to sink the reference current. Advantageously, the output of the duty cycle replica circuit 240 has a rising edge at a time approximately equal to a falling edge of the reference clock from the reference clock generation circuit 230. Advantageously, the duty cycle of the output of the duty cycle replica circuit 240 is approximately equal to the duty cycle of the reference clock from the reference clock generation circuit 230.

[0082] Figure 7 yes Figure 1-Figure 3 A timing diagram 700 of example operations of the clock generation circuits 135, 145, 155, and / or 165 is shown. Figure 7 In the example of the timing diagram 700, the timing diagram 700 includes an example reference clock 704, a first example clock signal 708, a second example clock signal 712, a third example clock signal 716, a fourth example clock signal 720, an example interlock voltage 724, an example reference ramp 728, a first example replica ramp 732, a second example replica ramp 736, a third example replica ramp 740, and a fourth example replica ramp 744. In the example operation of the timing diagram 700, the clock generation circuits 135, 145, 155, and 165 individually generate one of the clock signals 708-720.

[0083] Reference clock 704 represents Figure 2 and Figure 5 708 represents the time-varying output of the primary clock generating circuit. The second clock signal 712 represents the time-varying output of the first secondary clock generating circuit 145. The third clock signal 716 represents the time-varying output of the second secondary clock generating circuit 155. The fourth clock signal 720 represents the time-varying output of the third secondary clock generating circuit 165.

[0084] Interlock voltage 724 indicates Figure 2 and Figure 4 The interlock circuit 220 Figure 4 The time-varying voltage at capacitor 445 of FIG. 728 represents the voltage at capacitor 445 of FIG. Figure 5 The replica ramps 732-744 represent the voltage at the capacitor 505 that varies with time. The replica ramps 732-744 represent the voltage at the capacitor 505 that varies with time that occurs in each of the clock generation circuits 135, 145, 155, and / or 165. Figure 2 and Figure 6 For example, the first replica ramp 732 represents the voltage at the capacitor 640 in the primary clock generation circuit 135, and the second replica ramp 736 represents the voltage at the capacitor 640 in the instance of the duty cycle replica circuit 240 in the first secondary clock generation circuit 145. In such an example, the third replica ramp 740 represents the voltage at the capacitor 640 in the instance of the duty cycle replica circuit 240 in the second secondary clock generation circuit 155, and the second replica ramp 736 represents the voltage at the capacitor 640 in the instance of the duty cycle replica circuit 240 in the third secondary clock generation circuit 165.

[0085] At the first time 748, in response to the interlock voltage 724 being set to the first value, the interlock circuit 220 begins to source current from the reference clock generation circuit 230. At the first time 748, the reference ramp 728 begins to increase as the interlock circuit 220 sinks current from the capacitor 505. At the first time 748, the reference clock generation circuit 230 generates a rising edge on the reference clock 704. At the first time 748, in response to the rising edge of the reference clock 704, the first replica ramp 732 begins to increase.

[0086] After the first 748, Figure 5 The second amplifier 540 starts supplying current to the capacitor 505 and the interlock circuit 220. Once the second amplifier 540 starts supplying current to the capacitor 505 and the interlock circuit 220, the reference ramp 728 starts decreasing.

[0087] At the second time 752, in response to the reference ramp 728 being approximately equal to zero, the reference clock generation circuit 230 generates a falling edge on the reference clock 704. At the second time 752, in response to the falling edge of the reference clock 704, the first replica ramp 732 begins to decrease. At the second time 752, in response to the falling edge of the reference clock 704, the first replica ramp 732 is set Figure 6 The duty cycle replica circuit 240 generates a rising edge on the first clock signal 708 in response to the output of the logic device 620. At a second time 752, in response to the rising edge of the first clock signal 708, the second replica ramp 736 begins to increase.

[0088] At a third time 756, in response to the first replica ramp 732 being approximately equal to zero, the duty cycle replica circuit 240 of the primary clock generation circuit 135 generates a falling edge on the first clock signal 708. At the third time 756, in response to the falling edge of the first clock signal 708, the second replica ramp 736 begins to decrease. At the third time 756, in response to the falling edge of the first clock signal 708 setting the output of the logic device 620, the instance of the duty cycle replica circuit 240 of the first secondary clock generation circuit 145 generates a rising edge on the second clock signal 712. At the third time 756, in response to the rising edge of the second clock signal 712, the third replica ramp 740 begins to increase.

[0089] At a fourth time 760, in response to the second replica ramp 736 being approximately equal to zero, the instance of the duty cycle replica circuit 240 of the first secondary clock generation circuit 145 generates a falling edge on the second clock signal 712. At the fourth time 760, in response to the falling edge of the second clock signal 712, the third replica ramp 740 begins to decrease. At the fourth time 760, in response to the falling edge of the second clock signal 712 setting the output of the logic device 620, the instance of the duty cycle replica circuit 240 of the second secondary clock generation circuit 155 generates a rising edge on the third clock signal 716. At the fourth time 760, in response to the rising edge of the third clock signal 716, the fourth replica ramp 744 begins to increase.

[0090] At a fifth time 764, in response to the third replica ramp 740 being approximately equal to zero, the instance of the duty cycle replica circuit 240 of the second secondary clock generation circuit 155 generates a falling edge on the third clock signal 716. At the fifth time 764, in response to the falling edge of the third clock signal 716, the fourth replica ramp 744 begins to decrease. At the fifth time 764, in response to the falling edge of the third clock signal 716 setting the output of the logic device 620, the instance of the duty cycle replica circuit 240 of the third secondary clock generation circuit 165 generates a rising edge on the fourth clock signal 720.

[0091] At a sixth time 768, in response to the fourth replicator ramp 744 being approximately equal to zero, the instance of the duty cycle replica circuit 240 of the third secondary clock generation circuit 165 generates a falling edge on the fourth clock signal 720. At the sixth time 768, in response to the falling edge of the fourth clock signal 720, the interlock voltage 724 begins to increase.

[0092] At the seventh time 772, Figure 5 The clock source 535 is set Figure 5Logic device 530 generates a rising edge on reference clock 704. The voltage increase of interlock voltage 724 between time 768 and 772 increases the duty cycle of reference clock 704. Advantageously, duty cycle replica circuit 240 replicates the increased duty cycle to generate clock signals 708-720.

[0093] At the eighth time 776, the second increase in the interlock voltage 724 further increases the duty cycle of the reference clock 704 and the clock signals 708-720. However, the increase in the duty cycle of the reference clock 704 and the clock signals 708-720 after the eighth time 776 is less than the increase after the seventh time 772. Advantageously, the interlock voltage 724 continues to increase until the reference clock signal is approximately equal to the fourth clock signal 720. In some examples, the number of secondary clock generation circuits can be modified to generate multiple clock signals of different phases. In such examples, the secondary clock generation circuit coupled to the primary clock generation circuit generates a clock signal approximately equal to the reference clock 704.

[0094] Advantageously, clock generation circuits 135, 145, 155, and 165 dynamically adjust the duty cycle of clock signals 708-720. Advantageously, primary clock generation circuit 135 dynamically adjusts the duty cycle of reference clock 704 to compensate for a failure of one or more of secondary clock generation circuits 145, 155, and / or 165. In some examples, detection circuits (e.g., Figure 2 The detection circuit 210 and / or Figure 2 310) determines a failure of one or more of the clock generation circuits 135, 145, 155, and / or 165. In such examples, the clock generation circuits 135, 145, 155, and / or 165 may be coupled to bypass the failure of one or more of the clock generation circuits 135, 145, 155, and / or 165. Advantageously, the primary clock generation circuit 135 adjusts the duty cycle of the clock signals 708-720 based on the new configuration.

[0095] Fig. 8A and Figure 8B A flowchart is formed representing example operations 800, which may be performed by Figure 1-Figure 3 The primary clock generation circuit 135 and the secondary clock generation circuits 145, 155 and / or 165 are implemented, instantiated and / or executed to generate multiple clock signals of different phases. Operation 800 begins at block 805, where Figure 4 The amplifiers 435 and 440 are set Figure 2 and Figure 4 The interlock voltage of the interlock circuit 220 (eg, Figure 7In some examples, amplifiers 435 and 440 increase interlock voltage 724 based on a comparison of the input from detection circuit 210 with the output of primary clock generation circuit 135 (e.g., first clock signal 708). In such examples, amplifiers 435 and 440 increase interlock voltage 724 until a rising edge of first clock signal 708.

[0096] Figure 2 and Figure 5 The reference clock generation circuit 230 generates a reference ramp (eg, Figure 7 In some examples, the interlock voltage corresponds to the reference ramp 728. (Block 810). Figure 4 The magnitude of the current obtained by the third amplifier 455 of the interlock circuit 220 is proportional to the interlock voltage. The reference clock generation circuit 230 generates a reference ramp based on the current obtained by the interlock circuit 220.

[0097] The reference clock generation circuit 230 generates a reference clock (eg, Figure 7 In some examples, the reference clock generation circuit 230 generates a reference clock based on the reference ramp and Figure 5 The clock source 535 generates a reference clock. In such an example, the clock source 535 controls Figure 7 The reference clock generation circuit 230 generates a rising edge on the reference clock based on the rising edge of the clock source 535. The reference clock generation circuit 230 generates a falling edge on the reference clock based on the reference ramp.

[0098] Figure 2 and Figure 6 The duty cycle replica circuit 240 creates a clock signal (eg, Figure 7 In some examples, the duty cycle replica circuit 240 generates a replica ramp (eg, Figure 7 732-744 of the replica ramp). In such examples, the rising edge of the replica ramp corresponds to the duty cycle of the reference clock. For example, the logic device 620 uses the falling time of the first replica ramp 732 to generate the first clock signal 708. Advantageously, the duty cycle replica circuit 240 generates a clock signal whose duty cycle is approximately equal to the duty cycle of the reference clock. Advantageously, the rising edge of the clock signal from the duty cycle replica circuit 240 occurs at a time approximately equal to the falling edge of the reference clock.

[0099] Buffer circuit 250 supplies the primary clock signal to secondary clock generation circuits (eg, secondary clock generation circuits 145 , 155 , and / or 165 ). (Block 825 ) In some examples, buffer circuit 250 supplies the primary clock signal to first secondary clock generation circuit 145 and interlock circuit 220 .

[0100] An instance of duty cycle replica circuit 240 of one of secondary clock generation circuits 145, 155, and / or 165 creates another clock signal (e.g., Figure 7 8. In some examples, the duty cycle replica circuit 240 generates a replica ramp (e.g., replica ramp 732-744) based on one of the clock signals 708-720. In such examples, the rising edge of the replica ramp corresponds to the duty cycle of the supplied clock signal and the reference clock. For example, the logic device 620 generates the second clock signal 712 using the falling time of the second replica ramp 736.

[0101] Now go to Figure 8B , primary clock generation circuit 135 determines whether all secondary clock generation circuits (e.g., secondary clock generation circuits 145, 155, and 165) have created a clock signal. (Block 835). In some examples, primary clock generation circuit 135 determines that all secondary clock generation circuits 145, 155, and 165 have created a clock signal in response to receiving an input clock signal from a final secondary clock generation circuit (e.g., a third secondary clock generation circuit).

[0102] If the primary clock generation circuit 135 determines that not all of the secondary clock generation circuits have created a clock signal (e.g., block 835 returns a “no” result), control passes to block 825. If the primary clock generation circuit 135 determines that all of the secondary clock generation circuits have created a clock signal (e.g., block 835 returns a “yes” result), then Figure 3 The buffer circuit 330 supplies the clock signal from the final secondary clock generating circuit (eg, the third secondary clock generating circuit 165) to the primary clock generating circuit (eg, the primary clock generating circuit 135). (Block 840).

[0103] The interlock circuit 220 determines whether the clock signal (e.g., the fourth clock signal 720) from the final secondary clock generation circuit is approximately equal to the reference clock (e.g., the reference clock 704). (Block 845). In some examples, the interlock circuit 220 compares the falling edge of the clock signal from the third secondary clock generation circuit 165 with the rising edge of the clock signal from the primary clock generation circuit 135. In such examples, when the rising edge of the first clock signal 708 occurs at a time approximately equal to the falling edge of the fourth clock signal 720, the interlock circuit 220 determines that the fourth clock signal 720 is approximately equal to the reference clock 704.

[0104] If the interlock circuit 220 determines that the clock signal from the final secondary clock generation circuit is approximately equal to the reference clock (e.g., block 845 returns a "yes" result), control proceeds to block 810. If the interlock circuit 220 determines that the clock signal from the final secondary clock generation circuit is not approximately equal to the reference clock (e.g., block 845 returns a "no" result), the interlock circuit 220 modifies the interlock voltage to modify the duty cycle of the reference clock. (Block 850). In some examples, the amplifiers 435 and / or 440 increase the interlock voltage for a duration between the falling edge of the fourth clock signal 720 and the rising edge of the first clock signal 708. Control proceeds to return to block 810.

[0105] Although reference Fig. 8A and Figure 8B The illustrated flowchart describes an example process, but many other methods of generating a multi-phase clock may be used alternatively according to the teachings of the present disclosure. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, deleted, or combined. Similarly, additional operations may be included in the manufacturing process before, between, or after the blocks shown in the illustrated example.

[0106] In this specification, the term "and / or" (when used in a form such as A, B and / or C) refers to any combination or subset of A, B, C, such as: (a) A alone; (B) B alone; (C) C alone; (d) A and B; (e) A and C; (f) B and C; and (g) A and B and C. Similarly, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to embodiments including any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0107] In this specification, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection, or (b) in a second example, if the intermediate component C does not change the functional relationship between device A and device B, then device A is coupled to device B through the intermediate component C, so that device B is controlled by device A via the control signal generated by device A.

[0108] Numerical identifiers such as "first", "second", "third", etc. are only used to distinguish elements of substantially the same type in terms of structure and / or function. These identifiers used in the detailed description are not necessarily consistent with those used in the claims.

[0109] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform that function, and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. The configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0110] As used herein, the terms "terminal", "node", "interconnection", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection or an end point between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components.

[0111] Circuits or devices described herein that include certain components may instead be adapted to be coupled to those components to form the circuits or devices. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage sources and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources at the time of manufacture or after manufacture, for example by an end user and / or a third party, to form the described structure.

[0112] The circuit described herein can be reconfigured to include replaced components, so that the functionality provided is at least partially similar to the functionality available before the component is replaced. Unless otherwise specified, the components shown as resistors generally represent any one or more elements connected in series and / or in parallel to provide the impedance amount represented by the resistor shown. For example, the resistor or capacitor shown and described as a single component herein can be changed to multiple resistors or capacitors connected in parallel between the same nodes. For example, the resistor or capacitor shown and described as a single component herein can be changed to multiple resistors or capacitors connected in series between the same two nodes as the single resistor or capacitor. Although some elements of the example are included in the integrated circuit and other elements are outside the integrated circuit, in other example embodiments, additional or fewer features can be incorporated into the integrated circuit. In addition, some or all features illustrated as external to the integrated circuit can be included in the integrated circuit, and / or some features illustrated as internal to the integrated circuit can be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0113] The phrase "ground" used in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground and / or any other form of ground connection applicable or suitable for the teachings of this specification. Unless otherwise specified, "about", "approximately" or "substantially" before a numerical value refers to + / -10% of the numerical value, or if the numerical value is zero, then it is a reasonable numerical range around zero.

[0114] The described embodiments may be modified and other embodiments are possible within the scope of the claims.

[0115] As can be appreciated from the foregoing, example systems, apparatus, articles, and methods have been described for methods and apparatus for multiphase clock generation. Thus, the described systems, apparatus, articles, and methods relate to one or more improvements in the operation of a machine, such as a computer or other electronic and / or mechanical device.

[0116] The attached claims are incorporated by reference into the detailed description. Although certain example systems, devices, articles, and methods have been described herein, the coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles, and methods that fully fall within the scope of the claims of this patent.

Claims

1. A device comprising: A first clock generating circuit comprising: An interlock circuit having terminals; a reference clock generation circuit having a first terminal and a second terminal, the first terminal of the reference clock generation circuit being coupled to the terminal of the interlock circuit; a first duty cycle replica circuit having a first terminal and a second terminal, the first terminal of the first duty cycle replica circuit being coupled to the second terminal of the reference clock generating circuit; and a buffer circuit having a first terminal and a second terminal, the first terminal of the buffer circuit being coupled to the second terminal of the first duty cycle replica circuit; and The second clock generating circuit comprises: a detection circuit having a first terminal and a second terminal, the first terminal of the detection circuit being coupled to the second terminal of the buffer circuit; a second detection circuit having a first terminal and a second terminal, the first terminal of the second detection circuit being coupled to the second terminal of the detection circuit; and A second duty cycle replica circuit has a terminal coupled to the second terminal of the second detection circuit.

2. The device of claim 1 , wherein the buffer circuit is a first buffer circuit, the terminal of the interlock circuit is a first terminal of the interlock circuit, the terminal of the second duty cycle replica circuit is a first terminal of the second duty cycle replica circuit, and the device further comprises a second buffer circuit having a first terminal and a second terminal, the first terminal of the second buffer circuit is coupled to the second terminal of the second duty cycle replica circuit, and the second terminal of the second buffer circuit is coupled to the second terminal of the interlock circuit.

3. The device of claim 1, wherein the interlock circuit comprises: a first logic gate having a first input, a second input, and an output, the first input of the first logic gate being coupled to the second terminal of the buffer circuit; a second logic gate having a first input, a second input, and an output, the first input being coupled to the output of the first logic gate; a logic device having an input and an output, the input of the logic device being coupled to the second input of the first logic gate and the output of the logic device being coupled to the second input of the second logic gate; a first amplifier having an input and an output, the input of the first amplifier being coupled to the output of the second logic gate; as well as A second amplifier having an input and an output, the input of the second amplifier being coupled to the output of the first amplifier, the output of the second amplifier being coupled to the first terminal of the reference clock generation circuit.

4. The apparatus of claim 3 , wherein the input of the second amplifier is a first input, the second amplifier also has a second input, the interlock circuit further comprises a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to the output of the first amplifier and the first input of the second amplifier, the second terminal of the capacitor being coupled to the second input of the second amplifier.

5. The apparatus according to claim 1, wherein the reference clock generation circuit comprises: a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the terminal of the interlock circuit; a switch having a first terminal, a second terminal, and a third terminal, the first terminal of the switch being coupled to the terminal of the interlock circuit and the first terminal of the capacitor, the second terminal of the switch being coupled to the second terminal of the capacitor; a first amplifier having an input and an output, the input of the first amplifier coupled to the terminal of the interlock circuit, the first terminal of the capacitor, and the first terminal of the switch; a logic device having an input, a first output, and a second output, the input of the logic device being coupled to the output of the first amplifier, the first output of the logic device being coupled to the third terminal of the switch; as well as a second amplifier having an input and an output, the input of the second amplifier being coupled to the second output of the logic device and the first terminal of the first duty cycle replica circuit, the output of the second amplifier being coupled to the terminal of the interlock circuit, the first terminal of the capacitor, the first terminal of the switch, and the input of the first amplifier.

6. The apparatus of claim 1 , wherein the first duty cycle replica circuit comprises: a first amplifier having an input and an output, the input of the first amplifier being coupled to the second terminal of the reference clock generation circuit; a logic device having a first input, a second input, and an output, the first input of the logic device being coupled to the input of the first amplifier, the output of the logic device being coupled to the input of the buffer circuit; a second amplifier having an input and an output, the input of the second amplifier being coupled to the output of the logic device and the output of the second amplifier being coupled to the output of the first amplifier; as well as A third amplifier having an input and an output, the input of the third amplifier being coupled to the output of the first amplifier and the output of the second amplifier, the output of the third amplifier being coupled to the second input of the logic device.

7. According to the device according to claim 1, the terminal of the interlock circuit is the first terminal of the interlock circuit, the terminal of the second duty cycle replica circuit is the first terminal of the second duty cycle replica circuit, the interlock circuit also has a second terminal, the second duty cycle replica circuit also has a second terminal, and the device also includes a third clock generating circuit having a first terminal and a second terminal, the first terminal of the third clock generating circuit is coupled to the first terminal of the third clock generating circuit is coupled to the second terminal of the second duty cycle replica circuit, and the second terminal of the third clock generating circuit is coupled to the second terminal of the interlock circuit.

8. A system comprising: An interlock circuit comprising: a first logic gate having an input and an output; a second logic gate having a first input, a second input, and an output, the first input of the second logic gate being coupled to the output of the first logic gate; a logic device having an input and an output, the input of the logic device being coupled to the input of the first logic gate and the output of the logic device being coupled to the second input of the second logic gate; a first amplifier having an input and an output, the input of the first amplifier being coupled to the output of the second logic gate; and a second amplifier having an input and an output, the input of the second amplifier being coupled to the output of the first amplifier; a reference clock generation circuit having a first terminal and a second terminal, the first terminal of the reference clock generation circuit being coupled to the output of the second amplifier; and A duty cycle replica circuit has a terminal coupled to the second terminal of the reference clock generating circuit.

9. The system of claim 8, wherein the input of the second amplifier is a first input, the second amplifier also has a second input, the interlock circuit further comprises a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to the output of the first amplifier and the first input of the second amplifier, the second terminal of the capacitor being coupled to the second input of the second amplifier.

10. The system of claim 8, wherein the logic device is a first logic device, and the reference clock generation circuit comprises: a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the output of the second amplifier; a switch having a first terminal, a second terminal, and a third terminal, the first terminal of the switch being coupled to the output of the second amplifier and the first terminal of the capacitor, the second terminal of the switch being coupled to the second terminal of the capacitor; a third amplifier having an input and an output, the input of the third amplifier being coupled to the output of the second amplifier, the first terminal of the capacitor, and the first terminal of the switch; a second logic device having an input, a first output, and a second output, the input of the second logic device being coupled to the output of the third amplifier, the first output of the second logic device being coupled to the third terminal of the switch; as well as a fourth amplifier having an input and an output, the input of the fourth amplifier being coupled to the second output of the second logic device and to the terminal of the duty cycle replica circuit, the output of the fourth amplifier being coupled to the output of the second amplifier, the first terminal of the capacitor, the first terminal of the switch, and the input of the third amplifier.

11. The system of claim 8, wherein the logic device is a first logic device, and the duty cycle replica circuit comprises: a third amplifier having an input and an output, the input of the third amplifier being coupled to the second terminal of the reference clock generation circuit; a second logic device having a first input, a second input, and an output, the first input of the second logic device being coupled to the input of the third amplifier; a fourth amplifier having an input and an output, the input of the fourth amplifier being coupled to the output of the second logic device and the output of the fourth amplifier being coupled to the output of the third amplifier; as well as a fifth amplifier having an input and an output, the input of the fifth amplifier being coupled to the output of the third amplifier and the output of the fourth amplifier, the output of the fifth amplifier being coupled to the second input of the second logic device.

12. The system of claim 8, wherein the input of the first logic gate is a first input, the terminal of the duty cycle replica circuit is a first terminal, the logic gate further has a second input, the duty cycle replica circuit further has a second terminal, the system further comprises a buffer circuit having a first terminal and a second terminal, the first terminal of the buffer circuit being coupled to the second terminal of the duty cycle replica circuit, and the second terminal of the buffer circuit being coupled to the second input of the first logic gate.

13. The system of claim 12, wherein the system further comprises a secondary clock generation circuit having a first terminal and a second terminal, the first terminal of the secondary clock generation circuit being coupled to the second terminal of the buffer circuit, the second terminal of the secondary clock generation circuit being adapted to be coupled to the input of the first logic gate and the input of the logic device.

14. The system of claim 8, wherein the system further comprises a detection circuit having terminals coupled to the input of the first logic gate and the input of the logic device.

15. An apparatus comprising: An interlock circuit having terminals; A reference clock generation circuit, comprising: a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the terminal of the interlock circuit; a switch having a first terminal, a second terminal, and a third terminal, the first terminal of the switch being coupled to the terminal of the interlock circuit and the first terminal of the capacitor, the second terminal of the switch being coupled to the second terminal of the capacitor; a first amplifier having an input and an output, the input of the first amplifier coupled to the terminal of the interlock circuit, the first terminal of the capacitor, and the first terminal of the switch; a logic device having an input, a first output, and a second output, the input of the logic device being coupled to the output of the first amplifier, the first output of the logic device being coupled to the third terminal of the switch; and a second amplifier having an input and an output, the input of the second amplifier coupled to the second output of the logic device, the output of the second amplifier coupled to the terminal of the interlock circuit, the first terminal of the capacitor, the first terminal of the switch, and the input of the first amplifier; and A duty cycle replica circuit has a terminal coupled to the second output of the logic device.

16. The device of claim 15, wherein the logic device is a first logic device, and the interlock circuit comprises: a first logic gate having an input and an output; a second logic gate having a first input, a second input, and an output, the first input being coupled to the output of the first logic gate; a second logic device having an input and an output, the input of the second logic device being coupled to the input of the first logic gate and the output of the second logic device being coupled to the second input of the second logic gate; a third amplifier having an input and an output, the input of the third amplifier being coupled to the output of the second logic gate; as well as a fourth amplifier having an input and an output, the input of the fourth amplifier being coupled to the output of the third amplifier, the output of the fourth amplifier being coupled to the first terminal of the capacitor, the first terminal of the switch, and the input of the first amplifier.

17. The apparatus of claim 16, wherein the input of the fourth amplifier is a first input, the fourth amplifier also having a second input, the interlock circuit further comprising a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to the output of the third amplifier and the first input of the fourth amplifier, the second terminal of the capacitor being coupled to the second input of the fourth amplifier.

18. The device of claim 15, wherein the logic device is a first logic device, and the duty cycle replica circuit comprises: a third amplifier having an input and an output, the input of the third amplifier being coupled to the second output of the first logic device and the input of the second amplifier; a second logic device having a first input, a second input, and an output, the first input of the second logic device being coupled to the input of the third amplifier; a fourth amplifier having an input and an output, the input of the fourth amplifier being coupled to the output of the second logic device and the output of the fourth amplifier being coupled to the output of the third amplifier; as well as a fifth amplifier having an input and an output, the input of the fifth amplifier being coupled to the output of the third amplifier and the output of the fourth amplifier, the output of the fifth amplifier being coupled to the second input of the second logic device.

19. A device according to claim 18, wherein the terminal of the interlock circuit is a first terminal, the interlock circuit also has a second terminal, and the device includes a buffer circuit having a first terminal and a second terminal, the first terminal of the buffer circuit is coupled to the output of the second logic device and the input of the fourth amplifier, and the second terminal of the buffer circuit is coupled to the second terminal of the interlock circuit.

20. The apparatus of claim 15, wherein the terminal of the interlock circuit is a first terminal, the interlock circuit further having a second terminal, the apparatus comprising a detection circuit having a terminal coupled to the second terminal of the interlock circuit.

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