Method and apparatus for improving received signal strength indicator measurements at receiver

Abstract

In one embodiment, a receiver comprises: an analog front end (AFE) circuit for receiving and processing an incoming radio frequency (RF) analog signal comprising a packet; an analog-to-digital converter (ADC) coupled to the AFE circuit for receiving an analog signal based on the RF analog signal and digitizing it into a digital signal; a packet detector coupled to the ADC for detecting a packet based on the digital signal; and a computing circuit coupled to the packet detector. The computing circuitry may be configured to determine a received signal strength indicator (RSSI) value based at least in part on a portion of the preamble of the packet.

Description

Background Art

[0001] In a wireless local area network (WLAN) or other communication system, the received signal strength indicator (RSSI) measurement is done at the receiver and is used in many applications. For example, an access point (AP) can use RSSI measurements for rate adaptation. When there are multiple APs in an area that a station can reach, the station can use it to connect to the AP. RSSI is also used in applications such as direction / distance measurement or in real-time positioning systems. Existing measurement techniques incur high overhead, latency, and computational complexity, and may suffer from poor fidelity. Summary of the invention

[0002] In one aspect, the receiver includes: an analog front end (AFE) circuit for receiving and processing an incoming radio frequency (RF) analog signal including a packet; an analog-to-digital converter (ADC) coupled to the AFE circuit for receiving an analog signal based on the RF analog signal and digitizing it into a digital signal; a packet detector coupled to the ADC for detecting the packet based on the digital signal; and a computation circuit coupled to the packet detector. The computation circuit can be configured to determine a received signal strength indicator (RSSI) value based at least in part on a portion of a preamble of the packet.

[0003] In one implementation, the receiver further includes a timing circuit for determining boundaries between symbols of the packet. The calculation circuit can be coupled to the timing circuit and can determine the RSSI value based at least in part on at least one training field of the preamble of the packet. The calculation circuit can further determine the RSSI value based on a predetermined training field. In an example, the calculation circuit can further determine the RSSI value based on at least a portion of the data field of the packet.

[0004] In an implementation, the receiver further includes processing circuitry coupled to the computation circuitry, the processing circuitry to determine an RSSI metric based at least in part on the RSSI value in response to determining that the packet is from an expected source, and to discard the RSSI value in response to determining that the packet is not from an expected source. The controller may be coupled to the processing circuitry to configure at least one component of the receiver based at least in part on the RSSI metric.

[0005] In an implementation, the receiver further includes a processing circuit coupled to the calculation circuit for determining an intra-frame average RSSI value based on a plurality of symbols of the packet. The processing circuit may further determine an inter-frame average RSSI value based on the plurality of packets.

[0006] In another aspect, a method includes detecting a packet having a plurality of OFDM symbols in a receiver; calculating, in a first computational circuit of the receiver, an RSSI value for at least one of the plurality of OFDM symbols; filtering the RSSI value if the packet is not intended for the receiver, and processing the RSSI value if the packet is intended for the receiver.

[0007] In an example, processing the RSSI value includes determining an average RSSI value using the RSSI value and one or more other RSSI values. Determining the average RSSI value may include determining an intra-frame RSSI value, the intra-frame RSSI value including an average of multiple RSSI values ​​for at least some of the multiple OFDM symbols for the grouping. The method may further include weighting the updated RSSI value with a higher weight than one or more earlier RSSI values ​​when determining the intra-frame RSSI value. In another implementation, determining the average RSSI value includes determining an inter-frame RSSI value including an average of multiple RSSI values ​​for multiple groups.

[0008] In an implementation, the method further includes: providing the processed RSSI value to a controller of the receiver; and controlling, via the controller, at least one configuration setting of at least one gain control circuit of the receiver based at least in part on the processed RSSI value.

[0009] In an implementation, calculating the RSSI value includes using at least one preamble field of the packet, at least one signal field of the packet, and at least a portion of the data portion of the packet. In another implementation, calculating the RSSI value includes: iteratively, for multiple subcarriers of frequency domain samples of at least one of the multiple OFDM symbols: multiplying a sum of a first preamble field of the packet and a second preamble field of the packet with a complex conjugate value to obtain a product; squaring the product; and adding the product to a running sum, the running sum including at least a portion of the RSSI value.

[0010] In yet another aspect, a system includes an analog front end (AFE) circuit for receiving an incoming RF signal including a packet and down-converting it to a second frequency signal; a digitizer coupled to the AFE circuit for receiving the second frequency signal and digitizing it to a digital signal; a computation circuit coupled to the digitizer, the computation circuit for computing a plurality of RSSI values ​​based on one or more of a preamble field, a signal field, or a data field of the packet; a processing circuit coupled to the computation circuit, the processing circuit for determining an RSSI metric based on the plurality of RSSI values; and a controller coupled to the processing circuit, wherein the controller is to adapt a communication rate between the system and a station based at least in part on the RSSI metric.

[0011] In one implementation, the processing circuit is to determine an RSSI metric that includes an intra-frame average RSSI value based on multiple RSSI values ​​and averaged in a coherent manner. In another implementation, the processing circuit is to determine an RSSI metric that includes an inter-frame average RSSI value based on multiple RSSI values ​​for a packet and multiple additional RSSI values ​​for multiple additional packets and averaged in an incoherent manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram of a receiver according to an embodiment.

[0013] Figure 2 is a block diagram of a receiver according to another embodiment.

[0014] Figure 3 is a flow chart of a method according to an embodiment.

[0015] Figure 4 is a block diagram of a representative integrated circuit that includes RSSI circuitry as described herein.

[0016] Figure 5 is a high-level diagram of a network according to an embodiment. DETAILED DESCRIPTION

[0017] In various embodiments, techniques are provided for achieving improved, highly accurate RSSI measurements, which, in embodiments, may improve overall system performance.

[0018] WLAN packets have a transmit address (origin device address (e.g., in the form of a Media Access Control / Basic Service Set ID (MAC / BSSID))) and a receive address (destination device address (MAC / BSSID)) at the beginning of the payload so that the receiver device can determine whether the packet is destined for it and decide to continue further decoding and processing the RSSI information.

[0019] Upon packet detection, the station begins decoding the packet. Then, based on the packet type detection and the decoded data, the location of the BSSID of the transmitter within the packet is known. Based on the BSSID, it is determined whether the current packet being decoded originates from the associated AP. Note that the BSSID location in the packet / physical layer protocol data unit (PPDU) is different for aggregated or non-aggregated packets. When aggregated, the BSSID location in the decoded bit stream is determined to identify the BSSID. Also note that IEEE 802.11g packets are always non-aggregated, while IEEE 802.11ax packets are always aggregated. In the case of IEEE 802.11n packets, aggregation is determined based on one of the bits present in the signal field.

[0020] In an embodiment, a filtering process is performed to determine and further process the RSSI value for a given device pair combination to more accurately calculate / determine the RSSI. To this end, during the association process, the expected BSSID is programmed with the station or known by the station. This identifier for the associated device of the device pair combination can be stored in a register or other storage device. In the case of multiple BSSIDs (MBSSIDs), multiple BSSIDs are used to identify the AP, and therefore the receiver can store all BSSIDs that the AP may have in one or more such registers or other storage devices, and determine the BSSID match based on all of these BSSIDs.

[0021] Once it is determined that the decoded BSSID matches the expected BSSID, the calculated RSSI value or root mean square voltage (V_RMS) value can be further processed to determine a more accurate RSSI metric that can be used to more effectively control one or more receiver parameters and / or configurations. The details of this operation are further described below.

[0022] Reference now Figure 1 , which is a block diagram of a receiver according to an embodiment. Figure 1 As shown in , in some cases, the receiver 100 can be implemented as a single semiconductor die receiver such as included within an integrated circuit (IC). In such an embodiment, in addition to the external antenna 105 and the external oscillator 180 (e.g., a crystal oscillator), Figure 1 All of the circuitry shown in can be implemented on a single semiconductor die.

[0023] In the illustrated embodiment, an incoming radio frequency (RF) signal is received via an antenna 105 and provided to a signal processing path including a low noise amplifier (LNA) 110. After appropriate amplification therein, the incoming RF signal is provided to an analog front end (AFE) circuit 120. In various implementations, the AFE circuit 120 may include various filtering circuitry, including an analog filter 122, gain circuitry including a programmable gain amplifier (PGA) 123, and the like. In some embodiments, the gain of one or more of the LNA 110 and the PGA 123 may be dynamically controlled based on a gain setting that comes as an input from an automatic gain controller (AGC). In an embodiment, the AGC is part of a digital processing unit or baseband processor 140 implemented in digital logic. In another embodiment, the AGC is implemented using analog circuitry. In an embodiment, the AGC determines the gain based on a V_RMS measurement of the input signal and the current gain setting. As further shown, the AFE circuit 120 includes a mixer 125 configured to down-convert the RF signal to a lower frequency signal, for example, an intermediate frequency (IF) signal, such as a low IF signal, a zero IF signal, or other lower frequency signal.

[0024] To this end, mixer 125, which may be a complex mixer in some cases, is configured to down-convert the incoming RF signal using a mixed signal having a mixed frequency, which is shown as a mixed signal (f ) received from frequency generator 170. LO As an example, the frequency generator 170 may be a local oscillator (LO) that may be implemented as a phase locked loop (PLL). The frequency generator 170 may use an incoming oscillator signal f received from the external oscillator 180. XO to generate mixed signals.

[0025] Still referring to the signal processing path of the receiver 100, the down-converted signal output from the AFE circuit 120 is provided to the digitizer, Figure 1 1, which is shown as an analog-to-digital converter (ADC) 130, which digitizes the signal. These digitized signals, which may be at baseband, are in turn provided to a baseband processor 140. Figure 1 Although shown as a separate baseband processor in the embodiment of FIG. 1 , the baseband processor 140 may be implemented within a digital signal processor (DSP) in some cases.

[0026] After various baseband processing (including filtering, digital mixing, decimation, etc.), the resulting baseband processed signals may be provided to a demodulator 150 which demodulates the signals. In different implementations, one of a variety of demodulation schemes may be used. For the purposes of discussion herein, it is assumed that the demodulator 150 is configured to perform orthogonal frequency division multiplexing (OFDM) demodulation. The resulting demodulated signals may be output from the demodulator 150 and provided to further downstream processing circuitry, such as an audio processor (for ease of illustration, in Figure 1 not shown).

[0027] To more accurately determine RSSI information, baseband processor 140 may include an RSSI engine 145 (which may include calculation, filtering, and other processing circuitry). Although shown as included within baseband processor 140, in other implementations, RSSI engine 145 may be a separate component. As will be further described herein, RSSI engine 145 may be configured to calculate, filter, and further process RSSI values ​​for received signals to establish a highly accurate RSSI metric.

[0028] In an embodiment, the RSSI engine 145 may also pass the obtained RSSI information to the controller 160. Figure 1 100 is shown as a separate component, but in some implementations, this controller is likely to be included within the baseband processor (or as part of the DSP in some implementations). In any event, the controller 160 may include dedicated or programmable hardware circuitry configured to control one or more parameters and / or configurations of the receiver 100 based at least in part on the received RSSI information. To this end, the controller 160 may include or be coupled to a non-volatile storage device or other non-transitory storage medium to store instructions and data useful for such operations.

[0029] Based at least in part on the received RSSI information or the V_RMS value measured over a portion of the packet, the controller 160 (which may include an AGC) may determine gain settings for the front-end components including the LNA 110 and the PGA 123. Of course, additional components and / or configuration settings may be updated based at least in part on the received RSSI information or the measured V_RMS value, and the RSSI information may be used to enable connection to the most appropriate AP. In the case of the AP itself, the RSSI information may be used to control rate adaptation, such as communicating at a lower rate when there is a lower RSSI metric, and vice versa.

[0030] It is understood that although Figure 1In the embodiment of the present invention, for ease of illustration, only the receiver signal processing path is shown, but such a receiver may be part of a wireless transceiver that further includes transmission capabilities. It is understood that although in Figure 1 The embodiments are shown at this high level, but many variations and alternatives are possible.

[0031] Reference now Figure 2 , which is a block diagram of a receiver according to another embodiment. In an embodiment, the receiver 200 may be implemented on a single semiconductor die (except for the antenna 210).

[0032] As shown, the analog RF signal received from antenna 210 is processed by multiple blocks in RF-AFE circuit 220. Such processing may include amplification in an LNA, filtering, additional gain control (e.g., within an automatic gain control (AGC) circuit), etc. Thus, RF-AFE circuit 220 may perform various RF processing including amplification, filtering, and down-conversion to a lower frequency.

[0033] Thereafter, the processed analog signal is input to ADC 230. ADC 230 converts the analog signal into discrete samples, which are given as input to baseband processor 240. As shown, baseband processor 240 includes constituent components. The incoming digitized samples are provided to packet detector 245, which is configured to detect the reception of WLAN packets. Thereafter, OFDM symbol timing is determined by fine symbol timing determination circuit 250. In an embodiment, fine symbol timing (FST) is obtained based on the traditional long training field (L-LTF) field. Based on FST, the symbol boundaries between symbols (e.g., OFDM samples) are now known. Therefore, the samples corresponding to each OFDM symbol in time / frequency can be determined. In an embodiment, RSSI calculation circuit 270 is coupled to fine symbol timing determination circuit 250 to calculate RSSI measurements using samples from at least one OFDM symbol. Thereafter, the RSSI value is provided to RSSI processing circuit 280, which can further process the RSSI value as described herein.

[0034] Upon packet detection, the receiver 200 begins decoding the packet in parallel in the additional baseband processing circuit system 260, which may include a demodulator and a decoder, and calculates at least one RSSI metric or V_RMS value in the RSSI calculation circuit 270. Based on the decoded data, the location of the transmitter's MAC BSSID is known. Based on the BSSID, it is determined whether the current packet being decoded originates from the associated AP. Once it is determined that the decoded BSSID matches the expected BSSID, the RSSI of this packet is considered for further processing or otherwise discarded. Therefore, a packet filtering process is performed to remove RSSI values ​​for packets that are not intended for the receiver and / or from undesired sources. This process is repeated for each packet detected by the station.

[0035] As described, the BSSID location in the packet / PPDU is different for aggregated or non-aggregated packets. The identifiers of the associated devices of the device pair combination can be stored in a register or other storage device. In the case of MBSSID, multiple BSSIDs are used to identify the AP, and therefore the receiver can store all the BSSIDs that the AP can have in one or more such registers or other storage devices. The BSSID match is determined based on all of these BSSIDs. Therefore, in the case of MBSSID, the baseband processor 240 is programmed with all of the BSSIDs that the AP can have, and the BSSID match is determined based on all of these BSSIDs.

[0036] In one embodiment, the filtering process is done in hardware of the baseband processor 240. In another embodiment, the filtering process is done in software and the status is provided to the baseband processor 240. This process of filtering and then considering the RSSI or V_RMS value for further use is done at any device (station / AP). In an embodiment, the AP maintains RSSI measurements for each individual station associated with it.

[0037] It is understood that although Figure 2 In the embodiment of FIG. 1 , only the receiver signal processing path is shown for ease of illustration, but such a receiver may be part of a wireless transceiver that further includes transmission capabilities. It is understood that although in Figure 2 The embodiments are shown at this high level, but many variations and alternatives are possible.

[0038] Although specific techniques for determining RSSI are described below, it is understood that different combinations or variations of these techniques are possible. In addition, although embodiments are described in the context of WLANs, it is understood that the techniques disclosed herein may be applied to other wireless systems.

[0039] In an embodiment, RSSI is a function of the V_RMS value calculated using the L-LTF field, as shown below in Equation 1:

[0040] Where k is the subcarrier index, K is the total number of subcarriers, and Y LFT1 (k) is the frequency domain sample from the received L-LTF part (first cycle), Y LFT2 (k) are frequency domain samples from the received L-LTF portion (second period), and is the complex conjugate of the known LTF sequence. When averaged across symbols, the frequency offset is ensured to be very low. The resulting RSSI metric is therefore a function of the RMS value formed by a given number of subcarriers for a given number of symbols.

[0041] In another embodiment, the RSSI is calculated using the SIGNAL field, which includes the L-SIG and repeated L-SIG (RL-SIG) fields, as shown below in Equation 2:

[0042] where Y L-SIG (k) is the frequency domain sample from the received L-SIG part, Y RL-SIG (k) are frequency domain samples from the received RL-SIG part, and is the complex conjugate of the decoded L-SIG symbol (constellation symbol).

[0043] In yet another embodiment, the RSSI is calculated using the L-LTF, L-SIG, and RL-SIG fields as shown below in Equation 3:

[0044] In another embodiment, the RSSI is calculated using the L-LTF, L-SIG, and RL-SIG fields as shown below in Equation 4:

[0045] In an embodiment, the RSSI is calculated from the preamble / signal field of binary phase shift keying / quadrature phase shift keying (BPSK / QBPSK) modulation. In another embodiment, the RSSI is calculated using the data field of the WLAN packet. In another embodiment, the RSSI is calculated using the preamble / signal field and the data field of the OFDM symbol of the WLAN packet. In an embodiment where the received packet conforms to the IEEE 802.11ax specification, the RSSI can be calculated by averaging the signal and data fields, for example, every fourth tone of the HE data portion of the packet is used for averaging with the non-HE portion of the packet.

[0046] Calculating RSSI across multiple OFDM symbols of a packet and obtaining a single metric / measurement is called intra-frame calculation, and coherent averaging may be performed. Calculating RSSI across multiple WLAN packets and obtaining a single metric / measurement is called inter-frame calculation, and incoherent averaging may be performed.

[0047] In an embodiment, the receiver uses at least one of an inter-frame averaging or an intra-frame averaging process to improve RSSI accuracy. Depending on the implementation, the RSSI calculation circuit according to the embodiment (e.g., Figure 2 The circuit 270 of FIG. 270 calculates the RSSI or V_RMS value for each OFDM symbol or OFDM symbol pair. Thereafter, the RSSI processor (e.g., Figure 2 Circuit 280) performs additional processing of intra-group / inter-group averaging.

[0048] In an embodiment, intra-frame averaging of RSSI or V_RMS values ​​may be performed over a windowed duration of N microseconds (μs) and repeated every P μs. In one embodiment, the value of N is 200 μs and the value of P is 1000 μs. Inter-frame averaging may be performed over a window of every M μs. In one embodiment, the value of M is 10K μs. Averaging the RSSI across OFDM symbols in a packet and across packets ensures that the effects of noise are reduced and the accuracy of RSSI measurements of the link between the station and the AP is improved.

[0049] In an embodiment, the amount of averaging may depend on the AGC gain used for the packet. As an example, if the AGC gain is set so that the LNA output is low, this indicates that the signal is at a good level and may also be at a high signal-to-noise ratio (SNR). For such a packet, the averaging may be low. Let us assume that in the case of periodic averaging, the averaging here may be for 5 OFDM symbols or every fifth OFDM symbol.

[0050] In an embodiment, part of the RSSI calculation is done using paired samples, as shown below in Equation 5:

[0051] where H is the channel estimate, X is the data symbol, X* is the conjugate of the data symbol, and k is the subcarrier index of the OFDM symbol.

[0052] In an embodiment, the current calculation / measurement is given a higher weight than an earlier calculation / measurement, as explained in Equation 6 below. RSSI_P(g)=(1-δ)*RSSI_P(g-1)+δ*RSSI(g) (Equation 6) Where δ>0.5, and RSSI(g) is the RSSI metric / measurement obtained for OFDM symbol number "g" of the packet. RSSI_P(g) is the new RSSI metric obtained for the current OFDM symbol number g based on the RSSI of the current OFDM symbol "RSSI(g)" and all previous "g-1" OFDM symbols "RSSI_P(g-1)". In an embodiment, the RSSI calculation is a function of the LNA gain, the VGA gain during the AGC lock phase, and the V_RMS of the IQ during the lock phase. RSSI = LNA_Gain + VGA_Gain + 20*log10(V_RMS) + K (Equation 7) where K is a constant used to handle any bias conditions.

[0053] Reference now Figure 3 , which is a flow chart of a method according to an embodiment. More specifically, method 300 is a method for performing filtered RSSI calculation according to an embodiment. Therefore, method 300 can be performed by a hardware circuit system including RSSI calculation and processing circuits alone and / or in combination with firmware and / or software, which can be implemented as instructions stored in a non-transitory storage medium.

[0054] As shown, the method 300 begins by detecting a packet (block 310). In an embodiment, the packet detection may be based at least in part on the detection of at least a portion of the preamble (e.g., one or more training fields). Next, at block 320, the baseband processor may perform fine symbol timing to determine the boundaries between symbols of the packet.

[0055] At this point in time, an RSSI value may be determined for the packet. Thus, at block 330, an RSSI value may be calculated for a sample of the packet based on one or more packet fields. For example, as discussed above, depending on the implementation, one or more of the LTF, SIG, and data fields may be used to calculate an RSSI or V_RMS value. It is understood that, depending on the implementation, additional information may be used to determine an RSSI or V_RMS value, including, for example, known training fields and / or decoded information, such as decoded signal symbol information.

[0056] As further shown, in parallel with the RSSI calculation, the packet may be decoded in a decoder (block 340, which may be performed in parallel with block 330). Based at least in part on the decoding of, for example, the BSSID, the source of the packet may be identified. Thus, at diamond 350, it may be determined whether the packet was received from an expected source, such as an AP with which the receiver is communicating. If not, then at block 355, the calculated RSSI value may be discarded and control may be passed back to block 310 for detection of another packet.

[0057] Still reference Figure 3 Assuming that a packet is received from the expected source, control passes to diamond 360 to determine whether RSSI averaging is enabled. In an example, such averaging can be enabled by default, or a controllable programmable setting can be used to control this functionality. If it is determined that such averaging is not enabled, then at box 365, the RSSI value is provided to the controller.

[0058] When it is determined that averaging is enabled, control is passed to diamond 370 to determine whether intra-frame averaging is enabled. If so, at box 380, the processing circuit system can use the RSSI values ​​of multiple symbols of the group to perform this intra-frame averaging. Note that the averaging can be completed within the windowed duration and repeated within a second longer time frame. The determined intra-frame average RSSI value can be provided to the controller (box 385). It is understood that the controller can control one or more parameters and / or configurations of the receiver based at least in part on this intra-frame average RSSI value. For example, depending on the value, one or more front-end gain components and / or receiver configurations can be dynamically controlled (e.g., increase or decrease gain values ​​and / or establish a connection with a given AP). In the case of the AP itself, the controller can configure rate adaptation, etc., based at least in part on this RSSI value.

[0059] Still reference Figure 3 If, instead, it is determined at diamond 370 that inter-frame averaging is to be performed, control passes to block 390. At block 390, the processing circuitry may perform such inter-frame averaging using the RSSI values ​​for the plurality of packets (where the various processes of method 300 may be iteratively performed for the plurality of packets to obtain sufficient RSSI values ​​for averaging). Note that the averaging may be done over a windowed duration and repeated over a second, longer time frame (where these durations are longer than for the case of intra-frame averaging). The determined inter-frame average RSSI value may be provided to a controller (block 395), which may use this information to control one or more parameters or configurations of the receiver, as discussed above.

[0060] Reference now Figure 4 , shown is a block diagram of a representative integrated circuit 400 including RSSI circuitry as described herein. Figure 4 In the embodiment shown in , the integrated circuit 400 may be, for example, a dual-mode wireless transceiver that can operate according to one or more wireless protocols (e.g., WLAN and Bluetooth, etc.), or other devices that can be used in various use cases. In one or more embodiments, Figure 4 The circuitry of integrated circuit 400 shown in FIG. 4 may be implemented on a single semiconductor die.

[0061] The integrated circuit 400 may be included in a range of devices including various stations including smartphones, wearable devices, smart home devices, other consumer devices or industrial, scientific and medical (ISM) devices, among others.

[0062] In the illustrated embodiment, the integrated circuit 400 includes a memory system 410, which in an embodiment may include a volatile storage device such as RAM and a non-volatile memory as a flash memory. As further shown, the integrated circuit 400 may also optionally include a separate flash memory 490 (or other non-volatile memory). The flash memory 490 may be implemented as a non-transitory storage medium that may store instructions and data. Such a non-volatile memory may store instructions, including instructions for processing and using RSSI information as described herein.

[0063] The memory system 410 is coupled to the digital core 420 via the bus 450, and the digital core 420 may include one or more cores and / or microcontrollers that act as the main processing unit of the integrated circuit. The digital core 420 may in turn be coupled to a clock generator 430, which may provide one or more phase-locked loops or other clock generator circuit systems to generate various clocks for use by the circuit systems of the IC. As further shown, the digital core 420 includes an RSSI circuit 425, which may process RSSI values ​​as described herein, and use the processed RSSI information to control and configure the receiver circuit system. As further explained, the IC 400 further includes a power circuit system 440, which may include one or more voltage regulators. Depending on the specific implementation, additional circuit systems may optionally exist to provide various functionalities and interactions with external devices. Such circuit systems may include an interface circuit system 460 and a security circuit system 470, which may provide a LAN or other interfaces with various off-chip devices, and the security circuit system 470 may perform wireless security techniques.

[0064] In addition, if Figure 4 As shown in , transceiver circuitry 480 may be provided to enable transmission and reception of wireless signals, for example, in accordance with one or more of a local or wide area wireless communication scheme, such as Zigbee, Bluetooth, IEEE 802.11, IEEE 802.15.4, cellular communications, etc. It is understood that, although shown with this high level view, many variations and alternatives are possible.

[0065] ICs such as those described herein may be implemented in a variety of different devices, such as wireless stations, IoT devices, etc. Referring now to Figure 5 , which shows a high-level diagram of a network according to an embodiment. Figure 5 As shown in FIG. 5 , network 500 includes various devices that can utilize embodiments to improve reliability of communications between devices and access points, including wireless stations (including smart devices such as IoT devices), access points, and remote service providers.

[0066] exist Figure 5 In the embodiment of the present invention, the wireless network 505 exists in, for example, a plurality of wireless devices 510 0-n As shown, wireless device 510 is coupled to access point 530, which in turn communicates with remote service provider 560 via wide area network 550 (e.g., the Internet). As described herein, wireless device 510 can process RSSI information and use the resulting processed RSSI information. It is understood that although Figure 5 The embodiments are shown at this high level, but many variations and alternatives are possible.

[0067] While the present disclosure has been described with respect to a limited number of implementations, those skilled in the art having the benefit of this disclosure will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations.

Claims

1. A receiver, comprising: an analog front end (AFE) circuit for receiving and processing incoming radio frequency (RF) analog signals including packets; an analog-to-digital converter (ADC) coupled to the AFE circuit, configured to receive an analog signal based on the RF analog signal and digitize it into a digital signal; a packet detector coupled to the ADC for detecting the packet based on the digital signal; as well as A computation circuit is coupled to the packet detector, the computation circuit being operable to determine a received signal strength indicator (RSSI) value based at least in part on a portion of a preamble of the packet.

2. The receiver of claim 1, further comprising a timing circuit for determining boundaries between symbols of the packet.

3. The receiver according to claim 2, wherein: The calculation circuit is coupled to the timing circuit, the calculation circuit being configured to determine the RSSI value based at least in part on at least one training field of the preamble of the packet.

4. The receiver according to claim 3, wherein: The calculation circuit is further to determine the RSSI value based on a predetermined training field.

5. The receiver according to claim 2, wherein: The calculation circuit is to determine the RSSI value further based on at least a portion of a data field of the packet.

6. The receiver of claim 1 , further comprising a processing circuit coupled to the computational circuit, the processing circuit configured to, in response to determining that the packet is from an expected source, determine an RSSI metric based at least in part on the RSSI value, and in response to determining that the packet is not from the expected source, discard the RSSI value.

7. The receiver of claim 6, further comprising a controller coupled to the processing circuit, wherein the controller is to configure at least one component of the receiver based at least in part on the RSSI metric.

8. The receiver of claim 1, further comprising a processing circuit coupled to the calculation circuit for determining an intra-frame average RSSI value based on a plurality of symbols of the packet.

9. The receiver of claim 1, further comprising a processing circuit coupled to the calculation circuit, wherein the processing circuit is to determine an inter-frame average RSSI value based on a plurality of packets.

10. A method comprising: detecting, in a receiver, a packet having a plurality of orthogonal frequency division multiplexing (OFDM) symbols; calculating, in a first calculation circuit of the receiver, a received signal strength indicator (RSSI) value for at least one of the plurality of OFDM symbols; as well as If the packet is not intended for the receiver, filtering the RSSI value, and If the packet is intended for the receiver, the RSSI value is processed.

11. The method according to claim 10, wherein: Processing the RSSI value includes determining an average RSSI value using the RSSI value and one or more other RSSI values.

12. The method according to claim 11, wherein: Determining the average RSSI value includes: An intra-frame RSSI value is determined, the intra-frame RSSI value comprising an average of a plurality of RSSI values ​​for at least some of the plurality of OFDM symbols of the packet.

13. The method of claim 12, further comprising weighting updated RSSI values ​​with a higher weight than one or more earlier RSSI values ​​when determining the intra-frame RSSI value.

14. The method according to claim 11, wherein: Determining the average RSSI value includes: An inter-frame RSSI value is determined that includes an average of a plurality of RSSI values ​​for a plurality of packets.

15. The method according to claim 10, further comprising: providing the processed RSSI value to a controller of the receiver; as well as At least one configuration setting of at least one gain control circuit of the receiver is controlled via the controller based at least in part on the processed RSSI value.

16. The method according to claim 10, wherein: Calculating the RSSI value includes using at least one preamble field of the packet, at least one signal field of the packet, and at least a portion of a data portion of the packet.

17. The method according to claim 10, wherein: Calculating the RSSI value includes: Iteratively, for a plurality of subcarriers of frequency domain samples of the at least one of the plurality of OFDM symbols: multiplying a sum of a first preamble field of the packet and a second preamble field of the packet by a complex conjugate value to obtain a product; squaring the product; and The product is added to a cumulative sum, the cumulative sum including at least a portion of the RSSI value.

18. A system comprising: an analog front end (AFE) circuit for receiving an incoming radio frequency (RF) signal including packets and down-converting it to a second frequency signal; a digitizer coupled to the AFE circuit, configured to receive the second frequency signal and digitize it into a digital signal; a computation circuit coupled to the digitizer, the computation circuit being operable to compute a plurality of received signal strength indicator (RSSI) values ​​based on one or more of a preamble field, a signal field, or a data field of the packet; a processing circuit coupled to the calculation circuit, the processing circuit configured to determine an RSSI metric based on the plurality of RSSI values; as well as A controller coupled to the processing circuit, wherein the controller is to adapt a communication rate between the system and a station based at least in part on the RSSI metric.

19. The system of claim 18, wherein: The processing circuit is to determine the RSSI metric, the RSSI metric comprising an intra-frame average RSSI value based on the plurality of RSSI values ​​and averaged in a coherent manner.

20. The system of claim 18, wherein: The processing circuit is to determine the RSSI metric, the RSSI metric comprising an inter-frame average RSSI value based on the plurality of RSSI values ​​for the packet and a plurality of additional RSSI values ​​for a plurality of additional packets and averaged in a non-coherent manner.

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