Channel decoding method, belief information transfer circuit and reconfigurable chip architecture

Abstract

The application provides a channel decoding method, a belief information transmission circuit and a reconfigurable chip architecture, and relates to the field of wireless communication.The method comprises the following steps: in the case that a to-be-decoded bit sequence is received, an aggregation level is determined according to computing power information and / or information quantity related to the to-be-decoded bit sequence; the aggregation level is used to indicate the number of nodes of synchronous iteration; in this way, the speed of synchronous transmission of belief information is flexibly adjusted; the belief information alternately transmitted between each check node and each variable node is iteratively calculated according to the aggregation level; and the to-be-decoded bit sequence is decoded according to the belief information of each variable node to obtain target information; in this way, the belief information received by multiple nodes is synchronously calculated to determine the belief information that needs to be transmitted; in this way, on the one hand, the calculation process is simplified, and the decoding reconstruction speed is improved; on the other hand, the decoding performance is improved.

Description

Technical Field

[0001] This application relates to the field of wireless communication technology, and in particular to a channel decoding method, a confidence information transmission circuit, and a reconfigurable chip architecture. Background Technology

[0002] In existing channel decoding schemes, the transmission of confidence information mainly relies on algorithms such as sum-product algorithms, minimum sum algorithms, normalized minimum sum algorithms, and minimum sum algorithms with offsets. However, using these algorithms for transmitting confidence information results in cumbersome calculations and poor decoding performance. Summary of the Invention

[0003] This application provides a channel decoding method, a confidence information transmission circuit, and a reconfigurable chip architecture, which solves the problems of cumbersome calculation process and poor decoding performance in current decoding methods.

[0004] Firstly, to achieve the above objectives, embodiments of this application provide a channel decoding method, comprising:

[0005] Upon receiving a sequence of bits to be decoded, an aggregation level is determined based on computing power information and / or the amount of information related to the sequence of bits to be decoded; the aggregation level is used to indicate the number of nodes that are synchronously iterating.

[0006] Based on the aggregation level, the confidence information alternately transmitted between each verification node and each variable node is calculated iteratively;

[0007] The target information is obtained by decoding the bit sequence to be decoded based on the confidence information of each variable node.

[0008] Optionally, based on the aggregation level, the confidence information alternately transmitted between each verification node and each variable node is iteratively calculated, including:

[0009] When calculating the confidence information passed from the first node to the second node, multiple third nodes that pass confidence information with the second node are determined according to the verification matrix. Among them, the first node and the second node are of different types, and the first node and the third node are of the same type.

[0010] Based on the aggregation level, the confidence information received by multiple third nodes is synchronously iterated with the confidence information received by the first node to obtain the confidence information passed from the first node to the second node.

[0011] Optionally, based on the aggregation level, the confidence information received by multiple third nodes is synchronously iterated with the confidence information received by the first node to obtain the confidence information transmitted from the first node to the second node, including:

[0012] An iterative operation sequence is generated based on the confidence information received by the multiple third nodes and the confidence information received by the first node, wherein the confidence information received by the first node is the last piece of information in the iterative operation sequence;

[0013] Based on the aggregation level, the information in the iterative operation sequence is synchronously iterated to obtain the confidence information passed from the first node to the second node.

[0014] Optionally, an iterative operation sequence is generated based on the confidence information received from the plurality of third information sources and the confidence information received from the first node, including:

[0015] When the number of multiple third nodes is an integer multiple of the difference between the aggregation level and 1, the confidence information received by the third nodes and the confidence information received by the first nodes are sorted to obtain the iterative operation sequence;

[0016] When the number of multiple third nodes is not an integer multiple of the difference between the aggregation level and 1, a preset confidence information is constructed, and the confidence information received by multiple third nodes, the preset confidence information, and the confidence information received by the first node are sorted to obtain an iterative operation sequence; wherein, the preset confidence information is located after the confidence information received by multiple third nodes.

[0017] Optionally, based on the aggregation level, synchronous iterative operations are performed on the information in the iterative operation sequence to obtain the confidence information passed from the first node to the second node, including:

[0018] The i-th confidence information in the iterative operation sequence is sequentially operated on with the N-1 confidence information preceding the i-th confidence information to obtain a first operation result, and the i-th confidence information is updated to the first operation result; where i = k*(N-1)+1, k is a positive integer, and N is the aggregation level.

[0019] Optionally, the operation is performed between the i-th confidence information in the iterative operation sequence and the N-1 confidence information preceding the i-th confidence information, including:

[0020] Based on the Jacobian function, construct the operational relation for N confidence information to perform the operation;

[0021] The operational relationship is linearly fitted using Taylor series.

[0022] Optionally, linear fitting of the operational relation using a Taylor series includes:

[0023] The N confidence information values ​​are sorted to obtain a first value region that satisfies the preset convergence condition;

[0024] Select the expansion points for fitting within the first value range;

[0025] The operational relation is linearly fitted by performing a Taylor series expansion at the expansion point.

[0026] Secondly, to achieve the above objectives, embodiments of this application provide a confidence information transmission circuit, applicable to the confidence information calculation process in the channel decoding method as described in the first aspect, comprising:

[0027] An information calculator is used to perform calculations on N received confidence information points;

[0028] A first selector, connected to the information calculator, is used to select segments of the calculation results from the information calculator;

[0029] The rear calculator, connected to the first selector, is used to perform calculations on multiple results obtained from segmented selection, and to calculate the calculation results with the Nth confidence information to update the Nth confidence information.

[0030] Optionally, the rear calculator includes:

[0031] A processor, connected to the first selector, is used to perform calculations on the results of each segment selection;

[0032] The first adder, connected to the processor, is used to accumulate the various operation results output by the processor and the Nth confidence information.

[0033] Optionally, the processor includes:

[0034] A positive selector, connected to the first selector, is used to perform positive selection operations on the results of each segment selection;

[0035] The memory is used to store the parameter lookup table;

[0036] A multiplier, connected to the positive taker, is used to multiply the output of the positive taker with the first parameter found in the parameter lookup table.

[0037] The second adder, connected to the multiplier, is used to add the output of the multiplier to the second parameter found in the parameter lookup table.

[0038] Optionally, the confidence information transmission circuit further includes:

[0039] The second selector, connected to the first adder, is used to input the Nth confidence information into the second adder.

[0040] Thirdly, to achieve the above objectives, embodiments of this application provide a reconfigurable chip architecture suitable for the channel decoding method as described in the first aspect, including:

[0041] A control unit is configured to, upon receiving a bit sequence to be decoded, determine an aggregation level based on computing power information and / or the amount of information related to the bit sequence to be decoded; the aggregation level is used to indicate the number of nodes that are synchronously iterating.

[0042] The decoding intermediate variable unit is used to iteratively calculate the confidence information alternately transmitted between each verification node and each variable node according to the aggregation level;

[0043] The node update unit is used to decode the bit sequence to be decoded based on the confidence information of each variable node to obtain the target information.

[0044] Optionally, the decoding intermediate variable unit includes:

[0045] The decoding intermediate variable unit includes a cooperating aggregation unit and a sliding control unit;

[0046] The aggregation level unit is used to control the number of units that transmit confidence information in a single transaction according to the aggregation level, and to perform confidence information calculations based on the number of units that transmit confidence information in a single transaction.

[0047] The sliding control unit is used to set the calculation units that need to be skipped based on the information sent by the aggregation level unit.

[0048] Optionally, the node update unit includes:

[0049] The verification node update unit is used to update the verification node according to the confidence information output by the decoding intermediate variable unit;

[0050] The variable node update unit is used to update the variable nodes according to the confidence information output by the decoding intermediate variable unit, and to decode the bit sequence to be decoded according to the confidence information of each variable node to obtain the target information.

[0051] Optionally, the reconfigurable chip architecture further includes:

[0052] The memory, connected to the control unit, the decoding intermediate variable unit, and the node update unit respectively, is used to store the log-likelihood ratio of the bit sequence to be decoded, the target information, and the parity check matrix.

[0053] The beneficial effects of the above technical solution in this application are as follows:

[0054] The channel decoding method of this application, according to an embodiment, firstly, upon receiving a bit sequence to be decoded, determines an aggregation level based on computing power information and / or the amount of information related to the bit sequence to be decoded; the aggregation level is used to indicate the number of nodes for synchronous iteration; thus, the speed of synchronous transmission of confidence information is flexibly adjusted based on computational load; secondly, based on the aggregation level, the confidence information alternately transmitted between each check node and each variable node is iteratively calculated; thus, the calculation process of confidence information is simplified, and the decoding and reconstruction speed is improved; finally, the bit sequence to be decoded is decoded based on the confidence information of each variable node to obtain the target information. Thus, the confidence information received by all nodes is used to determine the confidence information transmitted between the variable nodes and check nodes, improving decoding performance. Attached Figure Description

[0055] Figure 1 Tanner diagram for LDPC decoding;

[0056] Figure 2 This is a flowchart illustrating the channel decoding method according to an embodiment of this application;

[0057] Figure 3 This is a schematic diagram of a confidence information transmission circuit according to an embodiment of this application;

[0058] Figure 4 This is a schematic diagram of a reconfigurable chip architecture according to an embodiment of this application. Detailed Implementation

[0059] To make the technical problems, technical solutions and advantages of this application clearer, a detailed description will be provided below in conjunction with the accompanying drawings and specific embodiments.

[0060] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0061] In the various embodiments of this application, it should be understood that the sequence number of each process described below does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0062] In addition, the terms "system" and "network" are often used interchangeably in this article.

[0063] In the embodiments provided in this application, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0064] Before describing the embodiments of this application, the relevant technical points will be explained first:

[0065] 1. Low-Density Parity Check Codes (LDPC)

[0066] One of the most significant characteristics of the parity-check matrix (PCM) of LDPC codes is its high sparsity. The proportion of non-zero elements in the PCM decreases as the code length increases, exhibiting typical sparsity properties. Theoretical analysis demonstrates that the sparsity of the PCM is a key reason for the excellent performance of LDPC codes, enabling efficient decoding even with long code lengths.

[0067] 2. Decoding Algorithm for LDPC Codes

[0068] LDPC code decoding algorithms can be divided into hard-decision decoding algorithms and soft-decision decoding algorithms. The former, or bit-flipping (BF) decoding algorithm, has lower complexity and is easier to implement in hardware, but its decoding performance is poor and it is only suitable for communication systems with excellent channel quality. The latter refers to the belief-propagation (BP) decoding algorithm based on a posteriori probability calculation; its performance is close to that of maximum likelihood decoding algorithms, and it has wide applications. LDPC code iterative decoding algorithms are relatively simple to implement, with complexity linear with code length, making them easy to implement in hardware.

[0069] 2.1 Hard-decision decoding algorithm

[0070] Assume the signal transmission information sequence is X = {x0, x1, ..., x...} n-1 The received information sequence after passing through the channel is Y = {y0, y1, ..., y}. n-1 The decoding process is as follows:

[0071] (1) First, determine the message to be transmitted through the channel to obtain the bit sequence;

[0072] (2) Substitute the result of step (1) into the verification equation for calculation. If the verification equation is true, stop the iteration and the decoding is successful; otherwise, find the variable node with the most false values ​​and flip all its bits.

[0073] (3) If the verification equation in step (2) is not valid, substitute the reversed decision result back into the verification equation, calculate the verification result, and repeat step (2) until all verification equations are valid or the maximum number of iterations is reached.

[0074] The problem with this algorithm is that after a certain iteration, if there are multiple nodes with the largest number of false positives, they will all be flipped simultaneously, leading to a high error rate. Some studies have proposed improvements to the BF algorithm, such as adding weights to the variable nodes, but the performance is generally poor. Therefore, this algorithm is only suitable for situations with good channel conditions, such as fiber optic communication.

[0075] 2.2 Soft-decision decoding algorithm

[0076] Soft-decision decoding algorithms for LDPC codes are a hot research topic in communication systems. LDPC code decoding is based on an iterative algorithm using probabilistic message-passing (MP), and its implementation in the logarithmic field is often referred to as the Sum-Product Algorithm (SPA).

[0077] Here, we use a mean of 0 and a variance of σ. 2 This analysis focuses on an additive white Gaussian noise (AWGN) channel, specifically the case using BPSK modulation. The parity-check matrix H has dimensions M×N, and the transmitted signal sequence is assumed to be X = {x0, x1, ..., x...}. n-1 The received information sequence after passing through the channel is Y = {y0, y1, ..., y}. n-1}, l max This represents the maximum number of iterations. Figure 1 In this context, v is the variable node, and c is the validation node. The relevant concepts are defined as follows:

[0078] M(j) represents the set of verification nodes linked to variable node j;

[0079] N(i) represents the set of variable nodes linked to the verification node i;

[0080] N(i)\j represents N(i) after removing element j;

[0081] M(j)\i represents M(j) after removing element i;

[0082] It is a modulo 2 operation;

[0083] Initial Channel Received Information This represents the probability that the transmitted variable xj takes the value a∈{1,-1};

[0084] Verification node c i To variable node v j The transmitted verification information is used This indicates that the variable node v j To the verification node c i Transmitted variable information express.

[0085] 2.2.1 The steps of soft-decision decoding of LDPC codes are as follows:

[0086] (1) Initialization: l = 0, initialize the information of each LDPC code check node and variable node, and initialize the received values ​​of the channel.

[0087] (2) Iterative message updates and delivery:

[0088] Step 1 (Verification Node Update): For verification node c i Connected variable nodes v j For each j∈N(i), transmit the verification information one by one. Variable node v j To receive information and the initial value of the channel Based on the correction

[0089] Step 2 (Variable Node Update): For variable node v j Each connected check node c i For i∈M(j), transmit variable information one by one. Verification node c i To receive information Based on the correction

[0090] (3) Judgment and Decoding Attempt:

[0091] With each variable node v j Received information and the initial value of channel reception Based on calculation And for variable node v j Make a judgment and obtain the decoded result. If Order Judgment Code otherwise The resulting decision codeword is x = [x1, x2, ..., x N If the decoding verification formula is satisfied, stop the iterative decoding, the decoding is successful, and x is output as the decoding result; otherwise, return to step (2) and continue execution. This continues until the decoding is successful or the iteration count reaches l. max The decoding operation is terminated.

[0092] In the above steps, during the first iteration, node c is verified. i For other variable nodes v j of The message is unknown, and the values ​​of the transmitted variable messages are calculated with equal probability, that is... Initialize to 0.

[0093] The update calculation operations for the above iterative decoding of the LDPC decoding algorithm vary depending on the message passing metric. Generally, common sum-product decoding algorithms use two types of metrics: probability-based and log-likelihood ratio-based. Probability-based sum-product decoding algorithms require multipliers for information transfer between nodes, which is not easy to implement in hardware. Therefore, this application focuses on introducing and using sum-product decoding algorithms based on log-likelihood ratio determination.

[0094] Under the sum-product decoding algorithm based on the log-likelihood ratio measure, Initialize to 0. The prior information of xj = a is used as the initial probability. This is represented as follows. During the decoding iteration process, information is transmitted using the Log Likelihood Ratio (LLR). In update calculations, addition is used instead of multiplication for probability measures, and normalization is not required. A common information update formula is as follows:

[0095] f j =L(x j |y j ) = log(P(x) j =0|y j ) / P(x j =1|y j ))=2y j / σ 2

[0096]

[0097] The log-likelihood ratio of the decoded symbol received information is:

[0098]

[0099] When making a decoding decision, if Q j If the value is greater than or equal to 0, the received signal determination is 1; otherwise, it is 0.

[0100] 2.2.2 Common LLR-SPA Algorithms

[0101] (1) Summation and product algorithm based on Tanh rule

[0102]

[0103] (2) Sum-product algorithm based on Gallager function

[0104]

[0105] (3) Sum-product algorithm based on Jacobian function

[0106] The aforementioned Tanh rule can also be expressed as follows:

[0107]

[0108] The above transformation is called the Jacobian transformation. For the check node c... i , there is d c 1 variable node v j Connected to this, the input variable information is as follows: Two auxiliary sets are defined as follows: and

[0109] The variable information that can be input using auxiliary sets The output information is obtained from and We can obtain:

[0110]

[0111] The update formula for the verification node then changes to:

[0112]

[0113] In simple terms, this algorithm is essentially a forward-backward recursive decoding algorithm for a single parity check code.

[0114] In general, the sum-product decoding algorithm contains nonlinear functions such as hyperbolic functions, making it quite difficult to implement in hardware.

[0115] 2.2.3 Minimum Sum Algorithm

[0116] To reduce the complexity of LDPC decoding, researchers simplified the complex check node processing flow in the sum-product algorithm, eliminating such nonlinear functions and obtaining the classic Min Sum (MS) algorithm. This algorithm only performs addition and comparison operations during check node information update calculations, which is beneficial for hardware implementation. Understanding these simplified algorithms can be inspired by the analysis of the Jacobian algorithm.

[0117] The MS algorithm simplifies the processing of check node information in the sum-product decoding algorithm as follows:

[0118]

[0119] Applying this approximation to the iterative decoding process of LDPC, the formula for updating the check node information is transformed into:

[0120]

[0121] As shown in the above formula, the MS algorithm can perform decoding operations using only the minimum value of the sign and magnitude of the information transmitted by the node. The method for finding the minimum value can generally be the binary tree method. The MS algorithm verifies node information updates by using only the sign and minimum magnitude of the transmitted information, greatly simplifying the complexity of hardware implementation. However, it ignores the magnitude of many variable information transmissions during the decoding process, thus causing a performance loss. To compensate for this performance loss, researchers have proposed corresponding mitigation measures, namely the Normalized Min Sum (NMS) and Offset Min Sum (OMS) algorithms as improvements.

[0122] 2.2.4 Normalized Minimum Sum Algorithm

[0123] The Normalized Min Sum (NMS) decoding algorithm is an improved decoding algorithm based on the MS algorithm. It involves multiplying the minimum value obtained from the transmitted information in the check node information update by a value less than 1, α. The formula for updating the check node information then becomes:

[0124]

[0125] From an optimization perspective, α should change with different decoding environments and iteration numbers to obtain the optimal decoding result. However, for ease of implementation, common NMS algorithms usually treat α as a constant, and its value can be estimated using density evolution (DE) methods.

[0126] 2.2.5 Min-sum Algorithm with Offset

[0127] The Offset Min Sum (OMS) algorithm is an improved decoding algorithm based on the MS algorithm. It involves subtracting a value β from the minimum value obtained during the check node information update. The formula for updating the check node information then becomes:

[0128]

[0129] From an optimization perspective, β should vary with different decoding environments and iteration counts to obtain the optimal decoding result. However, for ease of implementation, common OMS algorithms typically treat β as a constant. The improvement of this method over the NMS algorithm lies in the fact that information with magnitudes less than β is set to zero, and its impact on variable node updates in subsequent iterations is ignored.

[0130] As can be seen, the MS, OMS, and NMS algorithms only require the channel received value as input and do not require channel-related information.

[0131] 2.3. From the above content, we can see that:

[0132] The sum-product decoding algorithm contains nonlinear functions such as hyperbolic functions, which makes it difficult to implement in hardware.

[0133] The minimum sum algorithm checks the node information update by only transmitting the sign of the information and the minimum modulus value, which greatly simplifies the complexity of hardware implementation. However, it ignores the magnitude of many variable information transmissions during the decoding process, thus causing a performance loss.

[0134] The normalized minimum sum decoding algorithm is based on the minimum value obtained by the minimum sum algorithm in updating the information of the check node by multiplying it by a value less than 1. However, since a lot of channel information is omitted, there is still room for improvement in performance.

[0135] The min-sum decoding algorithm with offset is based on the minimum value obtained by the min-sum algorithm in the transmission information of the check node information update, minus an offset value. However, since a lot of channel information is omitted, there is still room for performance improvement.

[0136] Based on the above situation, such as Figure 2 As shown, this application provides a channel decoding method, including:

[0137] Step 201: Upon receiving the bit sequence to be decoded, determine the aggregation level based on the computing power information and / or the amount of information related to the bit sequence to be decoded; the aggregation level is used to indicate the number of nodes for synchronous iteration.

[0138] In this step, firstly, the bit sequence to be decoded is the sequence transmitted through the channel after the transmitting device encodes the information to be sent. For example, the bit sequence to be decoded is LDPC code, fountain code, polar code, etc.; secondly, the computing power information is the current computing power of the chip (decoder). For example, the computing power information includes computing power overhead, i.e. power consumption; thirdly, the amount of information related to the bit sequence to be decoded is related to the confidence value of the decoded data.

[0139] Here, it's important to note that, on the one hand, computing power is positively correlated with aggregation level; that is, the greater the computing power overhead, the higher the aggregation level. Specifically, when the current computing power overhead of the decoding chip is high, i.e., high power consumption, a large-span aggregation level is used to reduce chip power consumption, skipping more computational units to achieve the transmission of more confidence information. Conversely, when the current computing power overhead and power consumption are low, a small-span aggregation level can be used to improve decoding accuracy. On the other hand, the amount of information related to the bit sequence to be decoded is negatively correlated with aggregation level; that is, the greater the amount of information, the smaller the aggregation level. Specifically, the decoder analyzes the decoding confidence information. When the confidence information is relatively evenly distributed, i.e., the overall value fluctuation or variance / standard deviation is below a certain threshold, it means that the current amount of information is small and the values ​​of each information are similar. In this case, a large-span aggregation level is used, skipping more computational units to achieve the transmission of more confidence information. Conversely, when the confidence information is relatively dispersed, i.e., the current confidence information contains a large amount of information, a small-span aggregation level is used to achieve more accurate decoding.

[0140] In this step, the aggregation level is determined based on computing power information and / or the amount of information related to the bit sequence to be decoded. This enables flexible adjustment of the number of nodes for synchronous iteration based on the power consumption of the decoding chip and / or the amount of information based on confidence information, thereby reducing computational complexity while ensuring decoding performance.

[0141] Step 202: Based on the aggregation level, iteratively calculate the confidence information that is alternately transmitted between each verification node and each variable node;

[0142] In this step, the confidence information alternately passed between the verification node and the variable node constitutes the verification node update information and the variable node update information. For example, this step can synchronously iterate the confidence information of multiple verification nodes based on the aggregation level to reduce the number of iterations.

[0143] It should be noted here that before iteratively calculating the confidence information alternately transmitted between each verification node and each variable node, the confidence information of each verification node and each variable node is first initialized. Specifically, the initial confidence information of each variable node is the LLR of each bit of the bit sequence to be decoded, and the initial confidence information of each verification node is 0. Then, each variable node sends its initialized confidence information to the connected verification node. Each verification node updates the received confidence information through the synchronous iteration method in this step.

[0144] This step calculates confidence information based on aggregation levels, enabling the simultaneous calculation of confidence information for multiple nodes. It then iterates with other nodes until the confidence information of all relevant nodes (nodes connected to the same node) participates in the calculation. This ensures the accuracy of the calculated confidence information while simplifying the computational complexity.

[0145] Step 203: Decode the bit sequence to be decoded based on the confidence information of each variable node to obtain the target information.

[0146] In this step, the target information is the decoding result of the bit sequence to be decoded.

[0147] It should be noted that when calculating the confidence information, the confidence information of all nodes is taken into account, rather than just transmitting the confidence information symbol and the minimum modulus value as in algorithms such as the minimum sum algorithm. This can improve the decoding performance.

[0148] The channel decoding method of this application firstly determines, upon receiving the bit sequence to be decoded, an aggregation level for indicating the number of nodes for synchronous iteration based on computing power information and / or the amount of information related to the bit sequence to be decoded; thus, it enables flexible adjustment of the speed of synchronous transmission of confidence information based on computational load. Secondly, based on the aggregation level, iteratively calculates the confidence information alternately transmitted between each check node and each variable node; thus, it simplifies the confidence information calculation process. Finally, it decodes the bit sequence to be decoded based on the confidence information of each variable node to obtain the target information. This method utilizes the confidence information received by all nodes to determine the confidence information transmitted between the variable nodes and check nodes, improving decoding performance.

[0149] As an optional implementation, step 202 iteratively calculates the confidence information alternately passed between each verification node and each variable node according to the aggregation level, including:

[0150] When calculating the confidence information passed from the first node to the second node, multiple third nodes that pass confidence information to the second node are determined based on the verification matrix. The first node and the second node are of different types, while the first node and the third node are of the same type. For example, the first node and the third node are both verification nodes, while the second node is a variable node.

[0151] Here, it should be noted that in the check nodes, each row corresponds to a check equation (also called a check node), and each column corresponds to a bit of the codeword (also called a variable node). In the check matrix, an element that is 1 indicates that the check node in the row containing that element is connected to the variable node in the column containing that element. Therefore, when the second node is a variable node, the first node and multiple third nodes are the nodes in the row containing the element with the value "1" in the column corresponding to the second node. Therefore, in this step, multiple third nodes connected to the second node are selected based on the check matrix.

[0152] Based on the aggregation level, the confidence information received by multiple third nodes is synchronously iterated with the confidence information received by the first node to obtain the confidence information passed from the first node to the second node.

[0153] In this step, synchronous iteration means that when updating the first node, the first node is updated based on the iterative calculation of the third node. Specifically, during the iterative calculation process, each time the calculation can be performed on three or more nodes.

[0154] In simple terms, this step updates the first node based on the confidence information received from multiple third nodes. In this way, the node is updated based on multiple variable information, avoiding the loss of decoding performance. In addition, the node update is performed in a synchronous iterative manner, which reduces the number of iterations and reduces the complexity of hardware implementation.

[0155] As a specific implementation, based on the aggregation level, the confidence information received by multiple third nodes is synchronously iterated with the confidence information received by the first node to obtain the confidence information passed from the first node to the second node, including:

[0156] Based on the confidence information received from multiple third-party sources and the confidence information received from the first node, an iterative operation sequence is generated, wherein the confidence information received from the first node is the last information in the iterative operation sequence;

[0157] Here, taking the second node as the variable node and the first and third nodes as verification nodes as an example, let's assume the first node is C1, and the multiple third nodes are C2, C3, C4, C6, C7, C8, C9, C1, ... 12 If the second node is V1, then this step can first sort the multiple third nodes, for example, by sorting them in ascending order of their subscripts. The iterative operation sequence would then be: {C2, C3, C4, C6, C7, C8, C9, C...} 12 、V1}. Here, each symbol in the iterative operation sequence represents the confidence information received by the corresponding node.

[0158] Based on the aggregation level, the information in the iterative operation sequence is synchronously iterated to obtain the confidence information passed from the first node to the second node.

[0159] For example, if the aggregation level is 3, the synchronous iterative calculation in this step is as follows: First, calculate C2, C3, and C4 to update C4; second, calculate the updated C4, C6, and C7 together to update C7; then, calculate the updated C7 together with C8 and C9 to update C9; finally, calculate the updated C9 together with C... 12 The first node performs calculations on V1 to update V1. The updated V1 is the confidence information that the first node needs to transmit to the second node.

[0160] As a more specific implementation, an iterative computation sequence is generated based on the confidence information received by multiple third nodes and the confidence information received by the first node, including:

[0161] When the number of multiple third nodes is an integer multiple of the difference between the aggregation level and 1, the confidence information received by the third nodes and the confidence information received by the first node are sorted to obtain the iterative operation sequence.

[0162] When the number of multiple third nodes is not an integer multiple of the difference between the aggregation level and 1, multiple preset confidence information is constructed, and the confidence information received by the multiple third nodes, the preset confidence information, and the confidence information received by the first node are sorted to obtain an iterative operation sequence; wherein, the preset confidence information is located after the confidence information received by the multiple third nodes, that is, the elements in the iterative operation sequence are the confidence information of the third node, the preset confidence information, and the confidence information of the first node in sequence.

[0163] It should be noted that in this more specific implementation, by judging the relationship between the third node and the aggregation level, and determining whether fictitious pre-set confidence information is needed based on the relationship between the two, the number of elements in the final iterative operation sequence can meet the requirements of the aggregation level in each operation, thereby reusing the iterative calculation unit and reducing resource overhead. At the same time, the confidence information of all third nodes participates in the operation to ensure better decoding performance. In addition, the pre-set confidence information is fictitious node information with a value of -99.

[0164] As a specific implementation, based on the aggregation level, the information in the iterative operation sequence is synchronously iterated to obtain the confidence information passed from the first node to the second node, including:

[0165] The i-th confidence information in the iterative operation sequence is sequentially operated on with the N-1 confidence information preceding the i-th confidence information to obtain the first operation result, and the i-th confidence information is updated to the first operation result; where i = k*(N-1)+1, k is a positive integer, and N is the aggregation level.

[0166] In this specific implementation, the i-th confidence information is updated by using the N-1 confidence information preceding the i-th confidence information, and then iterative calculations are performed using the updated i-th confidence information. Finally, the last confidence information in the iterative calculation sequence (the confidence information of the first node) is updated. In this way, compared with the step-by-step iteration method, this specific implementation reduces the number of iterations, simplifies the complexity of hardware implementation, and improves the decoding speed. In addition, it ensures that all third nodes participate in the confidence information calculation, thus guaranteeing decoding performance.

[0167] As a more specific implementation, the i-th confidence information in the iterative operation sequence is operated on with the N-1 confidence information preceding the i-th confidence information, including:

[0168] Based on the Jacobian function, construct the operational relation for N confidence information to perform the operation;

[0169] Here, taking aggregation level 3 as an example, assuming the three nodes involved in the operation are U, V, and W, the operational relationship in this step can be expressed as:

[0170]

[0171] The Taylor series is used to linearly fit the operational relationship. In this step, by linearly fitting the above operational relationship, the computational complexity of the module can be increased only slightly, so as to obtain a shorter iteration time and thus improve the decoding speed.

[0172] Specifically, using Taylor series to perform linear fitting of the operational relations includes:

[0173] Sort the N confidence information to obtain the first value region that satisfies the preset convergence condition;

[0174] Here, it should be noted that, taking the above three nodes U, V, and W as an example, before sorting, the first term in the above formula can be converted into a univariate correction function, which can be calculated using existing linear approximation methods. The second term is the information content itself, and the third term can extract and construct a bivariate correction function f. c (x,y)=log(1+e x +e y ), and approximate it linearly.

[0175] After transforming the above formula, L(U), L(V), and L(W) can be sorted to ensure that f c (x, y) takes values ​​in the region y ≤ x ≤ 0 where convergence is good. At the same time, f... c (-5,-5) = 0.0134 is close to 0. For ease of calculation, the values ​​in the regions x < -5 and y < -5 are set to zero.

[0176] Select the expansion points for fitting within the first value range;

[0177] Here, f c (x,y) can be expanded using a binary Taylor series, which can be intuitively understood as approximating the surface using planes at one or more tangent points. Ignoring higher-order terms in the expansion, f... c (x, y) can be represented by a linear approximation near the expansion point (x0, y0) as follows:

[0178] f c (x,y)=log(1+e x +e y )

[0179] ≈f c (x0,y0)+f x ′(x0,y0)*(x-x0)+f y ′(x0,y0)*(y-y0)

[0180] Among them, the bivariate correction term function f c The first-order partial derivative of (x, y) with respect to variable x at the point (x0, y0) is: The first-order partial derivative of the variable y at the point (x0, y0) is: Since we sort L(U), L(V), and L(W), we can approximate f. c When considering (x, y), we only need to consider the values ​​in the region -5 ≤ y ≤ x ≤ 0. For hardware implementation and performance improvement, we consider linear approximation with single and multiple expansion points.

[0181] When several expansion points are selected for linear approximation, the bivariate correction term function f c (x,y) has the following linear approximation relationship:

[0182] f c (x,y)≈max(0,k1*x+l1*y+C1,...,k i *x+l i *y+C i )

[0183] Where k i , l i m iand C i All are real parameters.

[0184] When selecting a single expansion point, we choose (0, 0) as the expansion point. When selecting multiple expansion points, the complexity of expanding and approximating the multivariate function becomes high. For computational convenience, we use an expansion point selection scheme with a step size of 1 for iterative calculations in both the x=0 and y=x directions, with an error deviation value δ of 0.5. This yields three expansion points: (0, 0), (0, -2), and (-2, -2). The resulting list of expansion points is shown in Table 1 below.

[0185] Table 1. Relationship between expansion points and corresponding approximation terms

[0186]

[0187]

[0188] The operational relationship is linearly fitted by performing Taylor series expansion at the expansion point.

[0189] In the above embodiments, synchronous iterative computation reduces the number of iterations in the Jacobi algorithm, improving decoding speed. Simultaneously, the introduction of Taylor series linear approximation slightly increases the module's computational complexity while improving decoding accuracy. It is worth noting that the binary correction function used in this algorithm can be further extended to a multivariate correction function, and a linear approximation or other approximation can be performed on the entire function to obtain a shorter iteration time. Furthermore, this type of algorithm, by fully utilizing information from all nodes, theoretically outperforms algorithms such as MS, NMS, and OMS.

[0190] like Figure 3 As shown, this application embodiment also provides a confidence information transmission circuit, applicable to the confidence information calculation process in the channel decoding method described above. The circuit includes:

[0191] An information calculator is used to perform calculations on N received confidence information points; Figure 3 Taking the simultaneous calculation of confidence information for three nodes U, V, and W as an example, the information calculator is specifically used to accumulate the confidence information of the three nodes U, V, and W; and to subtract the confidence information of node U from the confidence information of node V and node W respectively.

[0192] The first selector, connected to the information calculator, is used to segment the calculation results of the information calculator. The information calculator will transmit the three results of the above calculation to the first selector at once. The first selector will segment the received results to obtain the results of each calculation.

[0193] The rear calculator, connected to the first selector, is used to perform calculations on multiple results obtained from segmented selection, and to calculate the result with the Nth confidence information to update the Nth confidence information.

[0194] The confidence information transmission circuit of this application embodiment first performs calculations on the received N confidence information pieces by an information calculator; then, a first selector performs segmented selection on the calculation results of the information calculator; finally, a post-calculator performs calculations on the multiple results obtained from the segmented selections, and calculates the results with the Nth confidence information to update the Nth confidence information. In this way, it achieves simultaneous calculation of the confidence information of multiple nodes before the Nth node to update the confidence information of the Nth node. Compared with the iterative method, the confidence information calculation process of this circuit can reduce the number of iterations and improve the calculation speed.

[0195] As a specific implementation, the post-calculator includes:

[0196] The processor, connected to the first selector, is used to perform calculations on the results of each segment selection; that is, the processor is used to further process the results of addition and subtraction of calculations from multiple nodes.

[0197] The first adder, connected to the processor, is used to accumulate the various operation results output by the processor and the Nth confidence information. In other words, the first adder is used to process the operation results of the Nth node with the other N-1 nodes to update the Nth node.

[0198] As a more specific implementation, the processor includes:

[0199] The positive selector, connected to the first selector, is used to perform positive selection operations on the results of each segment selection.

[0200] The memory is used to store the parameter lookup table;

[0201] The multiplier, connected to the positive taker, is used to multiply the output of the positive taker with the first parameter k found in the parameter lookup table.

[0202] The second adder, connected to the multiplier, is used to add the output of the multiplier to the second parameter c found in the parameter lookup table.

[0203] Furthermore, as an optional implementation, the confidence information transmission circuit also includes:

[0204] The second selector, connected to the first adder, is used to input the Nth confidence information into the second adder.

[0205] In other words, the operation of the confidence information transmission circuit in this embodiment is as follows (taking the calculation of confidence information of three nodes U, V, and W as an example):

[0206] First, L(U), L(V), and L(W) are added together, and simultaneously L(V) and L(W) are subtracted from L(U). The calculated values ​​will be used in the LUT to read the corresponding parameters and perform segment selection, multiplication, and addition operations. Specifically, the first selector controls |L(U)+L(V)+L(W)|, |L(V)-L(U)|, and |L(W)-L(U)| to enter the post-calculation unit (composed of memory, multiplier, and second adder) independently. In the post-calculation unit, the core operation is to perform piecewise linear multiplication and addition operations on the input data based on the input variable x. After the calculation is completed, the results of the three segments are added together to complete the calculation of the update information for a single node.

[0207] It's important to note that during the entire node information update process, this computational operation needs to be iterated repeatedly, ultimately feeding back all the information transmitted from all nodes to the specific node, completing the entire information aggregation process. When using this confidence information transmission circuit for confidence information transmission, the complexity of the computational unit remains unchanged as the number of expanded nodes increases; the only difference lies in the parameters stored in the LUT. This simplifies the hardware complexity.

[0208] like Figure 4 As shown, this application embodiment also provides a reconfigurable chip architecture suitable for the channel decoding method described above, including:

[0209] A control unit is configured to, upon receiving a bit sequence to be decoded, determine an aggregation level based on computing power information and / or the amount of information related to the bit sequence to be decoded; the aggregation level is used to indicate the number of nodes that are synchronously iterating.

[0210] Specifically, one scenario is as follows: When the decoding chip has high computing power (i.e., high power consumption), a large-span aggregation level is used to reduce power consumption, skipping more computational units to transmit more confidence information. Conversely, when the chip has low computing power and low power consumption, a small-span aggregation level can be used to improve decoding accuracy. Another scenario involves analyzing the decoding confidence information. If the confidence information is relatively evenly distributed (i.e., the overall value fluctuation or variance / standard deviation is below a certain threshold), it means the current information volume is small and the information values ​​are similar. In this case, a large-span aggregation level is used, skipping more computational units to transmit more confidence information. Conversely, if the confidence information is relatively dispersed (i.e., the current confidence information contains a large amount of information), a small-span aggregation level is used to achieve more accurate decoding. This allows for flexible adjustment of the number of computational units skipped at one time based on computing power and / or information volume.

[0211] The decoding intermediate variable unit is used to iteratively calculate the confidence information alternately transmitted between each verification node and each variable node according to the aggregation level. It should be noted that the decoding intermediate variable unit can perform the calculation method in the aforementioned channel decoding method when transmitting confidence information, which will not be elaborated here.

[0212] The node update unit is used to decode the bit sequence to be decoded based on the confidence information of each variable node to obtain the target information.

[0213] In the reconfigurable chip architecture of this application embodiment, upon receiving a bit sequence to be decoded, the control unit determines the number of nodes used to indicate synchronous iteration based on computing power information and / or the amount of information related to the bit sequence to be decoded; this enables flexible adjustment of the speed of synchronous transmission of confidence information according to the computational load; then, the decoding intermediate variable unit iteratively calculates the confidence information alternately transmitted between each verification node and each variable node according to the aggregation level; thus, compared with the step-by-step iteration method, the number of iterations is reduced, and the decoding speed can be improved; finally, the node update unit decodes the bit sequence to be decoded according to the confidence information of each variable node to obtain the target information; thus, when performing node updates, the confidence information of all relevant nodes is comprehensively considered, improving the decoding performance.

[0214] As a specific implementation, the decoding intermediate variable unit includes an aggregation unit and a sliding control unit that cooperate with each other;

[0215] The aggregation level unit is used to: control the number of units that transmit confidence information in a single transaction according to the aggregation level, and to perform calculations on multiple confidence information items according to the number of units that transmit confidence information in a single transaction. Here, the number of units that transmit confidence information in a single transaction corresponds to the aggregation level. For example, if the aggregation level is 3, then the number of units that transmit confidence information in a single transaction is 3, that is, 3 confidence information items are calculated each time.

[0216] The sliding control unit is used to: set the calculation units that need to be skipped based on the information sent by the aggregation level unit.

[0217] In this optional implementation, the aggregation level unit and the sliding control unit work together to perform calculations on multiple calculation units at once, and the calculation window is slidably set to the next calculation unit according to the aggregation level. This achieves synchronous iterative calculation and reduces the number of iterations. In specific implementations, the aggregation level unit and the sliding control unit can be adjusted by the control unit according to the aggregation level.

[0218] As a specific implementation, the node update unit includes:

[0219] The verification node update unit is used to update the verification node according to the confidence information output by the decoding intermediate variable unit; specifically, it updates the verification node according to the result of the calculation of the confidence information received by the verification node by the decoding intermediate variable unit.

[0220] The variable node update unit is used to update the variable nodes according to the confidence information output by the decoding intermediate variable unit. Specifically, it updates the variable nodes based on the result of the calculation performed by the decoding intermediate variable unit on the confidence information received by the variable nodes; and it decodes the bit sequence to be decoded according to the confidence information of each variable node to obtain the target information. Here, the process of decoding the bit sequence to be decoded according to the confidence information of each variable node can be performed in the existing manner.

[0221] Furthermore, the reconfigurable chip architecture also includes:

[0222] A memory is used to store the log-likelihood ratio (LLR) of the bit sequence to be decoded, the target information, and the parity check matrix. Specifically, such as... Figure 4 As shown, the memory may include ROM_H for storing the parity matrix, RAM_OUT for storing target information, and RAM_IN for storing LLR.

[0223] In simple terms, the entire reconfigurable chip architecture mainly includes a control unit (Decoder_Controller), a verification node update unit (CNU_UNIT), a variable node update unit (VNU_UNIT), a decoding intermediate variable unit (M_UNIT), and memory for storing decoding input information (RAM_IN), decoding output information (RAM_OUT), and a ROM_H for storing the parity check matrix. The implementation of the multivariate algorithm (synchronous iterative operation) proposed in this application is mainly completed in the decoding intermediate variable unit (M_UNIT). Figure 4 In the illustration shown, a feasible method for configuring the aggregation level is to control the number of units that transmit confidence information at one time using the aggregation level unit (Joint Unit), and then implement it using the corresponding multivariate Taylor series. For example, the number of units is two ( Figure 4 As shown in ①), the Slide Unit, in conjunction with the Joint Unit, sets up the Calculator unit that needs to skip two processes at once. When the Joint Unit controls the number of units transmitting confidence information at once to three (…),… Figure 4 As shown in ②), the Slide Unit, in conjunction with the Joint Unit, sets up a Calculator that requires skipping three processes at a time. The configuration of the Joint Unit and the Slide Unit is controlled by the Decoder_controller.

[0224] The channel decoding method, confidence information transmission circuit, and reconfigurable chip architecture of this application innovatively propose the concept of an aggregation level to refer to the number of units that continue to transmit multiple confidence information at one time. It also proposes an architecture design scheme that flexibly and adaptively adjusts the aggregation level during the decoding process to achieve a more intelligent decoding scheme. Specifically, this application replaces iterative iteration of node information one by one with synchronous iteration of multiple node information, and uses a multivariate Taylor series approximation method to fit it. The advantage of this algorithm is that it reduces the number of iterations of the Jacobi algorithm, improves the decoding speed, and the increase in module computational complexity is small due to the introduction of Taylor series linear approximation. It is worth mentioning that, as mentioned earlier, when performing Taylor series linear approximation, the binary correction term function used in this example can be further extended to a multivariate correction term function, and then linear approximation or other approximations can be performed on the whole to obtain a shorter iteration time. At the same time, since this type of algorithm makes full use of the information of all nodes, it has theoretical advantages over algorithms such as MS, NMS, and OMS, so as to achieve fast, high-precision, and easy-to-implement channel decoding. In addition, the embodiments of this application also design a corresponding hardware implementation circuit, and the circuit implements the nonlinear function through piecewise linear multiplication and addition, which has low complexity and its complexity does not change with the increase of expansion points.

[0225] In this embodiment, the module can be implemented in software so that it can be executed by various types of processors. For example, an identified executable code module may include one or more physical or logical blocks of computer instructions, which may be constructed as objects, procedures, or functions. Nevertheless, the executable code of the identified module does not need to be physically located together, but may include different instructions stored in different bits, which, when logically combined, constitute the module and achieve the module's intended purpose.

[0226] In practice, an executable code module can be a single instruction or many instructions, and can even be distributed across multiple different code segments, different programs, and across multiple memory devices. Similarly, operational data can be identified within the module and can be implemented in any suitable form and organized within any suitable type of data structure. This operational data can be collected as a single dataset or distributed across different locations (including different storage devices), and can exist, at least in part, solely as electronic signals within the system or network.

[0227] When a module can be implemented using software, considering the current level of hardware technology, modules that can be implemented in software can be implemented using hardware circuits by those skilled in the art to achieve the corresponding functions, without considering cost. These hardware circuits include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors such as logic chips and transistors, or other discrete components. Modules can also be implemented using programmable hardware devices, such as field-programmable gate arrays, programmable array logic, and programmable logic devices.

[0228] The exemplary embodiments described above are with reference to the accompanying drawings. Many different forms and embodiments are feasible without departing from the spirit and teachings of this application. Therefore, this application should not be construed as limiting the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to make this application complete and convey the scope of this application to those skilled in the art. In these drawings, component dimensions and relative dimensions may be exaggerated for clarity. The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. As used herein, unless clearly indicated otherwise, the singular forms “a,” “an,” and “the” are intended to include all such forms. It will be further understood that the terms “comprising” and / or “including”, when used in this specification, indicate the presence of the stated features, integers, steps, operations, components, and / or elements, but do not exclude the presence or addition of one or more other features, integers, steps, operations, components, and / or groups thereof. Unless otherwise indicated, when stated, a range of values ​​includes the upper and lower limits of the range and any subranges in between.

[0229] The above description is the preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principles described in this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A channel decoding method, characterized in that, include: Upon receiving a sequence of bits to be decoded, the aggregation level is determined based on computing power information and / or the amount of information related to the sequence of bits to be decoded; The aggregation level is used to indicate the number of nodes in synchronous iteration; wherein, the computing power information includes computing power overhead, the computing power overhead is positively correlated with the aggregation level, and the amount of information related to the bit sequence to be decoded is negatively correlated with the aggregation level; Based on the aggregation level, the confidence information alternately transmitted between each verification node and each variable node is iteratively calculated; this includes: when calculating the confidence information transmitted from the first node to the second node, determining multiple third nodes that transmit confidence information with the second node based on the verification matrix, wherein the first node and the second node are of different types, and the first node and the third node are of the same type; based on the aggregation level, synchronously iterating the confidence information received by the multiple third nodes with the confidence information received by the first node to obtain the confidence information transmitted from the first node to the second node; wherein the initial confidence information of the variable node is the log-likelihood ratio (LLR) of each bit of the bit sequence to be decoded, the initial confidence information of the verification node is 0, and the variable node is connected to the verification node; decoding the bit sequence to be decoded based on the confidence information of each variable node to obtain the target information.

2. The method according to claim 1, characterized in that, Based on the aggregation level, the confidence information received by multiple third nodes is synchronously iterated with the confidence information received by the first node to obtain the confidence information transmitted from the first node to the second node, including: An iterative operation sequence is generated based on the confidence information received by the multiple third nodes and the confidence information received by the first node, wherein the confidence information received by the first node is the last piece of information in the iterative operation sequence; Based on the aggregation level, the information in the iterative operation sequence is synchronously iterated to obtain the confidence information passed from the first node to the second node.

3. The method according to claim 2, characterized in that, Based on the confidence information received by the multiple third nodes and the confidence information received by the first node, an iterative operation sequence is generated, including: When the number of multiple third nodes is an integer multiple of the difference between the aggregation level and 1, the confidence information received by the third nodes and the confidence information received by the first nodes are sorted to obtain the iterative operation sequence; When the number of multiple third nodes is not an integer multiple of the difference between the aggregation level and 1, a preset confidence information is constructed, and the confidence information received by multiple third nodes, the preset confidence information, and the confidence information received by the first node are sorted to obtain an iterative operation sequence; wherein, the preset confidence information is located after the confidence information received by multiple third nodes.

4. The method according to claim 2 or 3, characterized in that, Based on the aggregation level, synchronous iterative operations are performed on the information in the iterative operation sequence to obtain the confidence information passed from the first node to the second node, including: The i-th confidence information in the iterative operation sequence is sequentially operated on with the N-1 confidence information preceding the i-th confidence information to obtain a first operation result, and the i-th confidence information is updated to the first operation result; where i=k*(N-1)+1, k is a positive integer, and N is the aggregation level.

5. The method according to claim 4, characterized in that, The operation involves performing a calculation on the i-th confidence information in the iterative sequence and the N-1 confidence information preceding the i-th confidence information, including: Based on the Jacobian function, construct the operational relation for N confidence information to perform the operation; The operational relationship is linearly fitted using Taylor series.

6. The method according to claim 5, characterized in that, Linear fitting of the operational relation using Taylor series includes: The N confidence information values ​​are sorted to obtain a first value region that satisfies the preset convergence condition; Select the expansion points for fitting within the first value range; The operational relation is linearly fitted by performing a Taylor series expansion at the expansion point.

7. A confidence information transmission circuit, applicable to the confidence information calculation process in the channel decoding method according to any one of claims 1 to 6, characterized in that, include: An information calculator is used to perform calculations on N received confidence information points; A first selector, connected to the information calculator, is used to select segments of the calculation results from the information calculator; The rear calculator, connected to the first selector, is used to perform calculations on multiple results obtained from segmented selection, and to calculate the calculation results with the Nth confidence information to update the Nth confidence information.

8. The confidence information transmission circuit according to claim 7, characterized in that, The post-calculator includes: A processor, connected to the first selector, is used to perform calculations on the results of each segment selection; The first adder, connected to the processor, is used to accumulate the various operation results output by the processor and the Nth confidence information.

9. The confidence information transmission circuit according to claim 8, characterized in that, The processor includes: A positive selector, connected to the first selector, is used to perform positive selection operations on the results of each segment selection; The memory is used to store the parameter lookup table; A multiplier, connected to the positive taker, is used to multiply the output of the positive taker with the first parameter found in the parameter lookup table. The second adder, connected to the multiplier, is used to add the output of the multiplier to the second parameter found in the parameter lookup table.

10. The confidence information transmission circuit according to claim 9, characterized in that, The confidence information transmission circuit further includes: The second selector, connected to the first adder, is used to input the Nth confidence information into the second adder.

11. A reconfigurable chip architecture, applicable to the channel decoding method as described in any one of claims 1 to 6, characterized in that, include: A control unit is configured to, upon receiving a bit sequence to be decoded, determine an aggregation level based on computing power information and / or the amount of information associated with the bit sequence to be decoded; the aggregation level is used to indicate the number of nodes that are synchronously iterating; wherein the computing power information includes computing power overhead, the computing power overhead is positively correlated with the aggregation level, and the amount of information associated with the bit sequence to be decoded is negatively correlated with the aggregation level; The decoding intermediate variable unit is used to iteratively calculate the confidence information alternately transmitted between each verification node and each variable node according to the aggregation level, including: when calculating the confidence information transmitted from the first node to the second node, determining multiple third nodes that transmit confidence information with the second node according to the verification matrix, wherein the first node and the second node are of different types, and the first node and the third node are of the same type; according to the aggregation level, synchronously iterating the confidence information received by the multiple third nodes and the confidence information received by the first node to obtain the confidence information transmitted from the first node to the second node; wherein the initial confidence information of the variable node is the log-likelihood ratio (LLR) of each bit of the bit sequence to be decoded, the initial confidence information of the verification node is 0, and the variable node is connected to the verification node; The node update unit is used to decode the bit sequence to be decoded based on the confidence information of each variable node to obtain the target information.

12. The reconfigurable chip architecture according to claim 11, characterized in that, The decoding intermediate variable unit includes a cooperating aggregation unit and a sliding control unit; The aggregation level unit is used to: control the number of units that transmit confidence information in a single transaction according to the aggregation level, and to perform confidence information calculations based on the number of units that transmit confidence information in a single transaction. The sliding control unit is used to: set the calculation units that need to be skipped based on the information sent by the aggregation level unit.

13. The reconfigurable chip architecture according to claim 11, characterized in that, The node update unit includes: The verification node update unit is used to update the verification node according to the confidence information output by the decoding intermediate variable unit; The variable node update unit is used to update the variable nodes according to the confidence information output by the decoding intermediate variable unit, and to decode the bit sequence to be decoded according to the confidence information of each variable node to obtain the target information.

14. The reconfigurable chip architecture according to claim 11, characterized in that, Also includes: The memory, connected to the control unit, the decoding intermediate variable unit, and the node update unit respectively, is used to store the log-likelihood ratio of the bit sequence to be decoded, the target information, and the parity check matrix.

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