Display device

Abstract

A display device includes: a circuit layer disposed on a base substrate; and a display element layer disposed on the circuit layer. The display element layer includes: a light emitting element; a pixel defining layer defining a light emitting region corresponding to the light emitting element; a spacer disposed on the pixel defining layer; and an auxiliary electrode disposed on the separator and including a reflective material. The auxiliary electrode is electrically connected to an electrode of the light emitting element, a side surface of the spacer is inclined toward the light emitting element, and the auxiliary electrode covers the side surface of the spacer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0085046 filed in the Korean Intellectual Property Office on June 30, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display device having improved light emitting efficiency. Background Art

[0004] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation devices, and game consoles may include a display device for displaying images. The display device may include a display panel including a plurality of pixels for displaying images, and each of the pixels may include a light-emitting element that generates light and a driving element (or pixel circuit) connected to the light-emitting element.

[0005] Display devices having organic light emitting elements among light emitting elements have advantages such as wide viewing angle, fast response speed and low power consumption, and thus are attracting attention as next generation display devices. However, there is a problem of uneven brightness as the area of ​​the display device increases. Summary of the invention

[0006] Embodiments of the present disclosure provide a display device having improved light emitting efficiency.

[0007] According to an embodiment, a display device may include: a circuit layer disposed on a base substrate; and a display element layer disposed on the circuit layer. The display element layer may include: a light-emitting element; a pixel defining layer defining a light-emitting area corresponding to the light-emitting element; a partition disposed on the pixel defining layer; and an auxiliary electrode disposed on the partition and including a reflective material. The auxiliary electrode may be electrically connected to an electrode of the light-emitting element, a side surface of the partition may be inclined toward the light-emitting element, and the auxiliary electrode may cover a side surface of the partition.

[0008] In an embodiment, the auxiliary electrode may include: an upper auxiliary electrode disposed on a top surface of the separator; and a side auxiliary electrode disposed on a side surface of the separator.

[0009] In an embodiment, the thickness of the upper auxiliary electrode and the thickness of the side auxiliary electrode may be different from each other.

[0010] In an embodiment, the thickness of the upper auxiliary electrode may be greater than the thickness of the side auxiliary electrodes.

[0011] In an embodiment, as the side auxiliary electrode is closer to the pixel defining layer, the thickness of the side auxiliary electrode may become smaller.

[0012] In an embodiment, the display element layer may further include a lower auxiliary electrode disposed between the spacer and the pixel defining layer.

[0013] In an embodiment, the auxiliary electrode and the lower auxiliary electrode may include the same material.

[0014] In embodiments, the auxiliary electrode and the lower auxiliary electrode may be electrically connected to each other.

[0015] In an embodiment, the pixel defining layer may include: a first pixel defining layer surrounding the light emitting region in a plan view; and a second pixel defining layer surrounded by the light emitting region in a plan view.

[0016] In an embodiment, the spacer may include: a first spacer disposed on the first pixel defining layer; and a second spacer disposed on the second pixel defining layer.

[0017] In an embodiment, the auxiliary electrode may be disposed on at least one of the first spacer and the second spacer.

[0018] In an embodiment, the auxiliary electrode may include: a first auxiliary electrode disposed on the first spacer; and a second auxiliary electrode disposed on the second spacer, and the first auxiliary electrode and the second auxiliary electrode may be electrically connected to each other.

[0019] In an embodiment, the auxiliary electrode may include metal.

[0020] In an embodiment, the light emitting element may include: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode electrically connected to the auxiliary electrode.

[0021] In an embodiment, the intermediate layer may be interrupted by separators.

[0022] In an embodiment, the first electrode may partially overlap the pixel defining layer in a plan view.

[0023] In an embodiment, the pixel defining layer may include a light transmissive material.

[0024] In an embodiment, an angle between a side surface of the spacer and a top surface of the pixel defining layer may be in a range of about 70° to about 80°.

[0025] In an embodiment, the circuit layer may include an auxiliary wiring applying a driving voltage to the light emitting element, and the auxiliary electrode and the auxiliary wiring may be electrically connected to each other.

[0026] According to an embodiment, a display device may include: a circuit layer disposed on a base substrate; a light emitting element disposed on the circuit layer and corresponding to a light emitting area; a partition wall disposed on the circuit layer and arranged to correspond to a non-light emitting area adjacent to the light emitting area; and an auxiliary electrode disposed on the partition wall and including a reflective material. The auxiliary electrode may be electrically connected to an electrode of the light emitting element, and the partition wall may include a first partition wall surrounding the light emitting element in a plan view and a second partition wall surrounded by the light emitting element in a plan view. The auxiliary electrode may be disposed on at least one of the first partition wall and the second partition wall.

[0027] In an embodiment, the partition wall may include: a pixel defining layer defining a light emitting area corresponding to the light emitting element; and a spacer disposed on the pixel defining layer.

[0028] In an embodiment, a side surface of the partition may be inclined toward the light emitting element, and the auxiliary electrode may cover the side surface of the partition.

[0029] In an embodiment, an angle between a side surface of the spacer and a top surface of the pixel defining layer may be in a range of about 70° to about 80°.

[0030] In an embodiment, the light emitting element may include: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode electrically connected to the auxiliary electrode.

[0031] In an embodiment, the intermediate layer may be interrupted by separators.

[0032] In an embodiment, the first electrode may partially overlap the pixel defining layer in a plan view.

[0033] In an embodiment, the pixel defining layer may include a light transmissive material.

[0034] In an embodiment, the auxiliary electrode may include: a first auxiliary electrode disposed on the first partition wall; and a second auxiliary electrode disposed on the second partition wall, and the first auxiliary electrode and the second auxiliary electrode may be electrically connected to each other.

[0035] According to an embodiment, a display device may include: a circuit layer disposed on a base substrate; a light emitting element disposed on the circuit layer and corresponding to a light emitting area; a partition wall disposed on the circuit layer, disposed to correspond to a non-light emitting area adjacent to the light emitting area and including a first portion and a second portion having a thickness greater than that of the first portion; and an auxiliary electrode disposed on the second portion of the partition wall and including a reflective material. The auxiliary electrode may be electrically connected to an electrode of the light emitting element. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other objects and features of the present disclosure will become apparent by describing in detail the embodiments of the present disclosure with reference to the accompanying drawings.

[0037] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0038] Figure 2 is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0039] Figure 3 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0040] Figure 4 is a plan view of a display panel according to an embodiment of the present disclosure.

[0041] Figure 5 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment of the present disclosure.

[0042] Figure 6 yes Figure 2 An enlarged view of region AA' is shown in FIG.

[0043] Figure 7 It is along Figure 6 Schematic cross-sectional view of the display panel taken along line II' in FIG.

[0044] Figure 8 yes Figure 7 An enlarged view of region BB' is shown in FIG.

[0045] Fig. 9A is a schematic enlarged cross-sectional view of a separator and an auxiliary electrode according to an embodiment of the present disclosure.

[0046] Fig. 9B is a schematic enlarged cross-sectional view of a separator, an auxiliary electrode, and a lower auxiliary electrode according to an embodiment of the present disclosure.

[0047] Fig.10 is a schematic cross-sectional view showing a portion of a display panel according to an embodiment of the present disclosure.

[0048] Fig.11A is an enlarged plan view of a portion of a display panel according to an embodiment of the present disclosure.

[0049] Fig. 11B It is along Fig.11A Schematic cross-sectional view of the display panel taken along line II-II' in FIG.

[0050] Fig. 12A is a schematic enlarged cross-sectional view of a separator and an auxiliary electrode according to an embodiment of the present disclosure.

[0051] Fig. 12B is a schematic enlarged cross-sectional view of a separator, an auxiliary electrode, and a lower auxiliary electrode according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] The present disclosure may be variously modified and may have various forms. Therefore, specific embodiments will be shown in the accompanying drawings and will be described in detail herein. However, this is not intended to limit the present disclosure to specific embodiments, and should be understood to include all changes, equivalents or substitutions included in the spirit and technical scope of the present disclosure.

[0053] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. In addition, when an element is referred to as being "in contact with" or "contacting" another element, etc., the element may be "electrically in contact with" or "physically in contact with" the other element, or "indirectly in contact with" or "directly in contact with" the other element.

[0054] The same reference numerals refer to the same components. In addition, in the drawings, in order to effectively describe the technical contents, the thickness, ratio and size of the components are exaggerated.

[0055] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B". In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or in a separate sense and may be understood to be equivalent to "and / or".

[0056] Although the terms "first", "second", etc. can be used to describe various types of elements in this article, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below can be referred to as the second element without departing from the teachings of the present disclosure.

[0057] The terms used in this article are for the purpose of describing specific embodiments, and are not intended to be restrictive. As used in this article, the singular "one", and "the (said)" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "include" and / or "comprise" indicate the existence of the described features, integral bodies, steps, operations, elements, parts and / or their groups, but do not exclude the existence or increase of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. It should also be noted that, as used in this article, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than degree terms, and therefore, are used to illustrate the inherent deviation of the measured values, calculated values ​​and / or the values ​​provided that those of ordinary skill in the art will recognize.

[0058] Spatially relative terms such as "below," "below," "under," "down," "above," "up," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein for descriptive purposes and thereby to describe the relationship of one element to another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will then be oriented as being "above" the other elements or features. Thus, the exemplary term "below" may include both above and below orientations. Further, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0059] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. In addition, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this article.

[0060] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0061] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure, and Figure 2 is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0062] refer to Figure 1 and Figure 2, the display device DD may be a device that is activated in response to an electrical signal and displays an image IM. The display device DD may be included in various types of electronic devices. For example, the display device DD may be included in large devices such as televisions and billboards, and small and medium-sized devices such as monitors, mobile phones, tablet computers, navigation devices, and game consoles. The embodiments of the display device DD are illustrative, and the display device DD is not limited to any one as long as it does not deviate from the concept of the present disclosure.

[0063] In a plan view, the display device DD may have a rectangular shape having long sides extending in a first direction DR1 and short sides extending in a second direction DR2 intersecting the first direction DR1. However, the present disclosure is not limited thereto, and the display device DD may have various shapes such as a circular shape and other polygonal shapes.

[0064] The display device DD may display an image IM in a third direction DR3 via a display surface IS parallel to a plane defined by the first direction DR1 and the second direction DR2. The third direction DR3 may be parallel to a normal direction of the display surface IS. The display surface IS on which the image IM is displayed may correspond to a front surface of the display device DD. The image IM may include a still image as well as a dynamic image. Figure 1 An icon image is shown as an example of the image IM.

[0065] Herein, "on a plane" or "in a plan view" may be defined as a state of viewing in the third direction DR3. Herein, "on a cross section" or "in a cross section view" may be defined as a state of viewing in the first direction DR1 or the second direction DR2. The directions indicated by the first to third directions DR1, DR2, DR3 are relative concepts and may be converted into other directions.

[0066] Figure 1 A display device DD having a flat display surface IS is shown as an embodiment. However, the shape of the display surface IS of the display device DD is not limited thereto, and the display surface IS may have a curved shape or a three-dimensional shape.

[0067] The display device DD may be flexible. "Flexible" means a bendable property, and may include everything from a fully foldable structure to a structure that is bendable at a level of a few nanometers. For example, a flexible display device DD may include a curved display device or a foldable display device. However, the present disclosure is not limited thereto, and the display device DD may be rigid.

[0068] The display surface IS of the display device DD may include a display portion D-DA and a non-display portion D-NDA. The display portion D-DA may display an image IM. A user may view the image IM via the display portion D-DA. Figure 1 , the display part D-DA is illustrated as having a rectangular shape in a plan view, but the present disclosure is not limited thereto and the display part D-DA may have various shapes.

[0069] The non-display portion D-NDA may not display the image IM. The non-display portion D-NDA may correspond to a portion having a (predetermined or selectable) color and blocking light. The non-display portion D-NDA may be adjacent to the display portion D-DA. For example, the non-display portion D-NDA may extend outward from the display portion D-DA and may surround the display portion D-DA in a plan view. However, the present disclosure is not limited thereto, and the non-display portion D-NDA may be adjacent to only one side of the display portion D-DA, or may be disposed on a side surface other than the front surface of the display device DD. However, the present disclosure is not limited thereto, and the non-display portion D-NDA may be omitted.

[0070] In an embodiment, the display device DD may sense an external input applied from the outside. The external input may have various forms such as pressure, temperature, and light provided from the outside. The external input may include an input applied close to the display device DD (e.g., hovering) and an input contacting the display device DD (e.g., contact of a user's hand or a pen).

[0071] The display device DD may include a window WM, a display module DM, and a housing HAU. The display module DM may include a display panel DP and a light control member LCM.

[0072] The window WM may be disposed on the display module DM. The window WM may protect the display module DM from external impact. The front surface of the window WM may correspond to the above-mentioned display surface IS of the display device DD. The front surface of the window WM may include a transmission area TA and a frame area BA.

[0073] The transmission area TA of the window WM may be an optically transparent area. The window WM may transmit the image IM provided by the display module DM through the transmission area TA, and the user may view the corresponding image IM. The transmission area TA may correspond to the display portion D-DA of the display device DD.

[0074] The window WM may include an optically transparent insulating material. For example, the window WM may include glass, sapphire or plastic. The window WM may have a single-layer or multi-layer structure. The window WM may further include a functional layer such as an anti-fingerprint layer, a phase control layer and a hard coating layer disposed on the optically transparent substrate.

[0075] The frame area BA of the window WM may be provided as an area where a material having a (predetermined or selectable) color is deposited, coated or printed. The frame area BA of the window WM may prevent components of the display module DM that are arranged to overlap with the frame area BA in a plan view from being viewed from the outside. The frame area BA may correspond to a non-display portion D-NDA of the display device DD.

[0076] The display module DM may be disposed between the window WM and the housing HAU. The display module DM may display an image IM in response to an electrical signal. The display module DM may include a display area DA and a non-display area NDA adjacent to the display area DA.

[0077] The display area DA may be an area activated in response to an electrical signal. The display area DA may be an area where an image IM provided by the display module DM is projected. The display area DA of the display module DM may correspond to the above-mentioned transmission area TA. In this article, "an area / portion and another area / portion correspond to each other" means that these areas / portions "overlap each other", and these areas / portions are not limited to having the same area size and / or the same shape. The image IM displayed on the display area DA can be viewed from the outside via the transmission area TA.

[0078] The non-display area NDA may be disposed adjacent to the display area DA. For example, in a plan view, the non-display area NDA may surround the display area DA. However, the present disclosure is not limited thereto, and the non-display area NDA may be defined in various shapes. The non-display area NDA may be an area where pads, a driving circuit or driving wiring for driving the display area DA, and various signal lines for providing electrical signals are disposed. The non-display area NDA of the display module DM may correspond to the aforementioned border area BA. The border area BA may prevent the components of the display module DM disposed in the non-display area NDA from being viewed from the outside.

[0079] The display panel DP according to one embodiment may be a light-emitting display panel, but the present disclosure is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. For example, the light-emitting layer of the inorganic light-emitting display panel may include micro-LEDs or nano-LEDs, etc. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots or quantum rods, etc. In the following, the display panel DP will be described as an organic light-emitting display panel.

[0080] The light control member LCM may be disposed on the display panel DP. After being provided on the display panel DP, the light control member LCM may be connected to the display panel DP via a bonding process using a sealing member. However, the present disclosure is not limited thereto, and the light control member LCM may be disposed (e.g., directly disposed) on the display panel DP. Herein, formation by a continuous process without providing a separate adhesive layer or adhesive member may be expressed as “directly disposed”. For example, the expression “the light control member LCM is directly disposed on the display panel DP” may mean that after the display panel DP is formed, the light control member LCM is formed on the substrate surface provided by the display panel DP via a continuous process.

[0081] The light control member LCM may include a light control pattern that may convert the optical characteristics of light provided by the display panel DP. The light control member LCM may convert the wavelength or color of the light, or may transmit the light through the light control member LCM. The light control member LCM may control the color purity or color reproducibility of the light emitted from the display device DD, and may prevent reflection of external light incident from the outside of the display device DD.

[0082] The housing HAU may be disposed under the display module DM to accommodate the display module DM in the housing HAU. The housing HAU may absorb impact from the outside and may prevent foreign matter / moisture from penetrating into the display module DM to protect the display module DM. The housing HAU according to one embodiment may be provided in a form in which a plurality of accommodating members are coupled to each other.

[0083] In an embodiment, the display module DM may further include an input sensing unit. The input sensing unit may obtain coordinate information of an external input applied from outside the display device DD. The input sensing unit may be disposed between the display panel DP and the light control member LCM. For example, the input sensing unit may be disposed (e.g., directly disposed) on the display panel DP via a continuous process, but the present disclosure is not limited thereto, and the input sensing unit may be manufactured separately and attached to the display panel DP via an adhesive layer.

[0084] The display device DD may further include an electronic module including various functional modules for operating the display module DM, a power module supplying power required by the display device DD, and / or a bracket coupled to the display module DM and / or the housing HAU to divide the internal space of the display device DD.

[0085] Figure 3 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0086] refer to Figure 3, the display panel DP may include a base substrate BS, a circuit layer DP-CL, a display element layer DP-OL and an encapsulation layer TFE.

[0087] The base substrate BS may include a display area DA and a non-display area NDA. The base substrate BS may provide a base surface on which the circuit layers DP-CL are disposed. The base substrate BS may be a rigid substrate or a flexible substrate, without being limited thereto.

[0088] The circuit layer DP-CL may be disposed on the base substrate BS. The circuit layer DP-CL may include a driving element, a signal line, and a signal pad. The display element layer DP-OL may include a light emitting element disposed in the display area DA. The light emitting element of the display element layer DP-OL may be electrically connected to the driving element of the circuit layer DP-CL, and may provide light via the display area DA in response to a signal of the driving element.

[0089] The encapsulation layer TFE may be disposed on the display element layer DP-OL to seal the display element layer DP-OL. The encapsulation layer TFE may include a plurality of thin films. The thin films of the encapsulation layer TFE may improve optical efficiency or may protect the light emitting element.

[0090] Figure 4 is a plan view of a display panel according to an embodiment of the present disclosure.

[0091] refer to Figure 4 , the display panel DP may include pixels PX11 to PXnm disposed in the display area DA and signal lines SL1 to SLn and DL1 to DLm electrically connected to the pixels PX11 to PXnm, where n and m may be integers greater than 0. The display panel DP may further include a driving circuit GDC and pads PD disposed in the non-display area NDA.

[0092] Each of the pixels PX11 to PXnm may include a light emitting element, a capacitor, and a plurality of transistors (e.g., a switching transistor and a driving transistor, etc.) connected to the light emitting element, which will be described below. Each of the pixels PX11 to PXnm may emit light in response to an electrical signal applied thereto. Figure 4 The pixels PX11 to PXnm arranged in a matrix form are shown as an embodiment, but the arrangement of the pixels PX11 to PXnm is not limited thereto.

[0093] The signal lines SL1 to SLn and DL1 to DLm may include scan lines SL1 to SLn and data lines DL1 to DLm. Each of the pixels PX11 to PXnm may be connected to a corresponding scan line among the scan lines SL1 to SLn and a corresponding data line among the data lines DL1 to DLm. Depending on the configuration of the pixel circuits of the pixels PX11 to PXnm, more types of signal lines may be provided in the display panel DP.

[0094] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and may sequentially output the gate signal to the scan lines SL1 to SLn. The gate driving circuit may further output another control signal to the pixel circuits of the pixels PX11 to PXnm.

[0095] The driving circuit GDC and the pixels PX11 to PXnm according to one embodiment may include a plurality of thin film transistors formed through a low temperature polysilicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process.

[0096] The pads PD may be arranged in a certain direction (e.g., a first direction DR1) in the non-display area NDA. The pads PD may be a portion connected to a circuit board. Each of the pads PD may be connected to a corresponding signal line among the signal lines SL1 to SLn and DL1 to DLm, and may be connected to a corresponding pixel via the signal line. The pads PD and the signal lines SL1 to SLn and DL1 to DLm may be integral with each other. However, the present disclosure is not limited thereto, and the pads PD and the signal lines SL1 to SLn and DL1 to DLm may be disposed in different layers and connected to each other via contact holes.

[0097] Although not shown, the power module may apply a driving voltage to the pixels PX11 to PXnm. For example, the driving voltage may be applied from the power module to the second power line VL2, and the second power line VL2 may apply the driving voltage to the auxiliary electrode SE. Their details will be described below.

[0098] Figure 5 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment of the present disclosure.

[0099] Figure 5 A pixel PXnm connected to an nth scan line SLn, an nth sensing line SSLn, an mth data line DLm, and an mth reference line RLm as an embodiment is schematically illustrated.

[0100] refer to Figure 5 , the pixel PXnm may include a pixel circuit PC and a light emitting element OLED connected to the pixel circuit PC.

[0101] The pixel circuit PC may include a plurality of transistors T1, T2, and T3 and a capacitor Cst. The transistors T1, T2, and T3 may include a first transistor (or driving transistor) T1, a second transistor (or switching transistor) T2, and a third transistor (sensing transistor) T3. Each of the first to third transistors T1, T2, and T3 may be a thin film transistor.

[0102] The first to third transistors T1, T2 and T3 may be NMOS transistors, but the present disclosure is not limited thereto, and at least one of the first to third transistors T1, T2 and T3 may be a PMOS transistor. The first to third transistors T1, T2 and T3 may include sources S1, S2 and S3, drains D1, D2 and D3, and gates G1, G2 and G3, respectively.

[0103] The light emitting element OLED may be an organic light emitting element including an anode (or a first electrode) and a cathode (or a second electrode). The anode of the light emitting element OLED may receive a first voltage (or a first driving voltage) ELVDD via a driving transistor T1, and the cathode of the light emitting element OLED may receive a second voltage (or a second driving voltage) ELVSS. For example, the driving transistor T1 may receive a first voltage ELVDD from a power supply module via a first power supply line VL1, and the anode of the light emitting element OLED may receive the first voltage ELVDD via the driving transistor T1. For example, the cathode of the light emitting element OLED may receive a second voltage ELVSS from a power supply module via a second power supply line VL2. The light emitting element OLED may emit light by receiving the first voltage ELVDD and the second voltage ELVSS.

[0104] The driving transistor T1 may include a drain electrode D1 receiving a first voltage ELVDD, a source electrode S1 connected to an anode of the light emitting element OLED, and a gate electrode G1 connected to the capacitor Cst. The driving transistor T1 may control a driving current flowing from the first power line VL1 to the light emitting element OLED in response to a voltage value stored in the capacitor Cst.

[0105] The switching transistor T2 may include a drain D2 connected to the mth data line DLm, a source S2 connected to the capacitor Cst, and a gate G2 receiving the nth write scan signal SCn. The mth data line DLm may receive a data voltage Vd and a data voltage for sensing. The switching transistor T2 may transmit the data voltage Vd input from the mth data line DLm to the driving transistor T1 in response to a switching voltage input from the nth scan line SLn.

[0106] The sensing transistor T3 may include a source S3 connected to the mth reference line RLm, a drain D3 connected to the anode of the light emitting element OLED, and a gate G3 receiving the nth sampling scan signal SSn. The mth reference line RLm may receive a reference voltage Vr.

[0107] The capacitor Cst may be connected to the gate G1 of the driving transistor T1 and the anode of the light emitting element OLED. The capacitor Cst may include a first capacitor electrode connected to the gate G1 of the driving transistor T1 and a second capacitor electrode connected to the anode of the light emitting element OLED. The capacitor Cst may store a voltage corresponding to the difference between the voltage received from the switching transistor T2 and the first voltage ELVDD.

[0108] The equivalent circuit of the pixel PXnm is not limited to Figure 5 In another embodiment of the present disclosure, the equivalent circuit of the pixel PXnm can be implemented in various forms to allow the light emitting element OLED to emit light.

[0109] Figure 6 yes Figure 2 An enlarged view of region AA' is shown in FIG.

[0110] refer to Figure 6 , and is set in the display area DA (see Figure 2 ) and non-light emitting areas NPXA adjacent to the light emitting areas PXA1, PXA2, and PXA3 may be defined on the display panel DP (see Figure 2 )middle.

[0111] The light emitting areas PXA1, PXA2, and PXA3 may correspond to areas from which light provided from the light emitting element is emitted. The light emitting areas PXA1, PXA2, and PXA3 may include a first light emitting area PXA1, a second light emitting area PXA2, and a third light emitting area PXA3. The first to third light emitting areas PXA1, PXA2, and PXA3 may be based on the direction toward the display device DD (see Figure 1 ) are distinguished from each other by the color of the light emitted externally.

[0112] The first light emitting area PXA1 may correspond to an area providing a first color light, the second light emitting area PXA2 may correspond to an area providing a second color light, and the third light emitting area PXA3 may correspond to an area providing a third color light. In one embodiment, the first to third color lights may have different colors. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, the present disclosure is not limited thereto.

[0113] The first light emitting area PXA1 may be formed by a pixel defining layer PDL (see Figure 7 ) is defined by the first opening PDL-OP1 defined in the ). The first light-emitting area PXA1 may be disposed to be spaced apart from each of the second light-emitting area PXA2 and the third light-emitting area PXA3. The first light-emitting area PXA1 may be provided in plurality. The plurality of first light-emitting areas PXA1 may be spaced apart from each other in the first direction DR1 (wherein the second light-emitting area PXA2 is interposed between the first light-emitting areas PXA1), and may be spaced apart from each other in the second direction DR2 (wherein the third light-emitting area PXA3 is interposed between the first light-emitting areas PXA1).

[0114] The second light-emitting area PXA2 may be defined by a second opening PDL-OP2 defined in the pixel defining layer PDL. The second light-emitting area PXA2 may be disposed to be spaced apart from each of the first light-emitting area PXA1 and the third light-emitting area PXA3. The second light-emitting area PXA2 may be provided in plurality. The plurality of second light-emitting areas PXA2 may be spaced apart from each other in the first direction DR1 (wherein the first light-emitting area PXA1 is interposed between the second light-emitting areas PXA2), and may be spaced apart from each other in the second direction DR2 (wherein the third light-emitting area PXA3 is interposed between the second light-emitting areas PXA2).

[0115] The third light emitting area PXA3 may be defined by a third opening PDL-OP3 defined in the pixel defining layer PDL. The third light emitting area PXA3 may be disposed to be spaced apart from each of the first light emitting area PXA1 and the second light emitting area PXA2. The third light emitting area PXA3 may be provided in plurality. The plurality of third light emitting areas PXA3 may be arranged in the first direction DR1, and may be arranged in the second direction DR2 (wherein the first light emitting area PXA1 and the second light emitting area PXA2 are interposed between the third light emitting areas PXA3).

[0116] However, the arrangement of the first to third light emitting areas PXA1, PXA2, and PXA3 is not limited to Figure 6 The embodiment shown in FIG. 2 is a diagram of an embodiment of the present invention, and the arrangement of the light emitting areas may vary depending on the design of the display device DD.

[0117] In a plan view, each of the first to third light-emitting regions PXA1, PXA2, and PXA3 may have a polygonal shape. For example, in a plan view, each of the first light-emitting region PXA1, the second light-emitting region PXA2, and the third light-emitting region PXA3 may have an octagonal shape. The areas of the first light-emitting region PXA1, the second light-emitting region PXA2, and the third light-emitting region PXA3 may be different from each other. For example, in a plan view, the area of ​​the first light-emitting region PXA1 may be greater than the area of ​​the second light-emitting region PXA2, and the area of ​​the third light-emitting region PXA3 may be greater than the area of ​​the first light-emitting region PXA1.

[0118] The shapes and areas of the first to third light emitting regions PXA1, PXA2, and PXA3 may be designed in various ways in consideration of emission efficiency of light emitted via these regions, and are not limited to Figure 6 . For example, in a plan view, each of the first to third light emitting areas PXA1, PXA2, and PXA3 may have a rectangular shape or a circular shape. For example, in a plan view, some of the first to third light emitting areas PXA1, PXA2, and PXA3 may have a rhombus shape and the remaining areas may have an octagonal shape, but the present disclosure is not limited thereto.

[0119] The non-luminescent area NPXA, which is an area not overlapping the first to third light-emitting areas PXA1, PXA2, and PXA3 in a plan view, may be disposed adjacent to the first to third light-emitting areas PXA1, PXA2, and PXA3. The non-luminescent area NPXA may define boundaries of the first to third light-emitting areas PXA1, PXA2, and PXA3, and may prevent color mixing between the first to third light-emitting areas PXA1, PXA2, and PXA3.

[0120] The auxiliary electrode SE may be disposed in the non-light emitting area NPXA. The auxiliary electrode SE may extend in the first direction DR1 or the second direction DR2. In a plan view, the auxiliary electrode SE may not overlap the first to third light emitting areas PXA1, PXA2, and PXA3. For example, the auxiliary electrode SE may be disposed in an area where the first to third light emitting areas PXA1, PXA2, and PXA3 are spaced apart from each other. In a plan view, the auxiliary electrode SE may not overlap each of the first opening PDL-OP1, the second opening PDL-OP2, and the third opening PDL-OP3. For ease of description, Figure 6 The auxiliary electrodes SE shown in FIG. 1 are schematically shown, and the arrangement, shape, area, etc. of the auxiliary electrodes SE may vary depending on the design of the display panel DP.

[0121] Figure 7 It is along Figure 6 Schematic cross-sectional view of the display panel taken along line II' in FIG.

[0122] refer to Figure 7 , the display panel DP may include a base substrate BS, a circuit layer DP-CL, a display element layer DP-OL and an encapsulation layer TFE.

[0123] The display panel DP may include an insulating layer, a semiconductor pattern, a conductive pattern, a signal line, etc. In the manufacturing stage of the display panel DP, the insulating layer, the semiconductor layer, and the conductive layer may be formed on the base substrate BS by a coating process or a deposition process, etc. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by a photolithography process. Using such a process, a semiconductor pattern, a conductive pattern, a signal line, etc. included in the circuit layer DP-CL may be formed. The semiconductor pattern of the circuit layer DP-CL may be arranged in a pattern across a plurality of pixels.

[0124] The base substrate BS may include a glass substrate, a metal substrate, a polymer substrate, or an organic / inorganic composite material substrate. The base substrate BS may have a single layer or a multilayer structure. For example, a multilayer base substrate BS may include a synthetic resin layer and at least one inorganic layer disposed between the synthetic resin layers.

[0125] The synthetic resin layer may include at least one of acrylate resin, methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, perylene resin, and polyimide resin. However, the material of the synthetic resin layer of the base substrate BS is not limited thereto.

[0126] At least one inorganic layer may be disposed on the top surface of the base substrate BS. The inorganic layer may constitute a barrier layer and / or a buffer layer. Figure 7 An inorganic layer defined as a buffer layer 10 as an embodiment is shown. The buffer layer 10 may improve the bonding strength between the base substrate BS and the semiconductor pattern of the circuit layer DP-CL. The buffer layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide, but the present disclosure is not limited thereto.

[0127] The circuit layer DP-CL may include a semiconductor pattern. The semiconductor pattern may include polysilicon. However, the present disclosure is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. The circuit layer DP-CL may include an insulating layer and a semiconductor layer that constitutes a pixel circuit PC (see Figure 5 ) transistor. Figure 7 , a first transistor T1 and first to fourth insulating layers 20, 30, 40, and 50 are shown as an embodiment. A source S1, an active region (or channel region) AT, and a drain D1 of the first transistor T1 may be formed of a semiconductor pattern.

[0128] The semiconductor pattern may have different electrical characteristics depending on whether it is doped. The semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region or a region doped with a concentration lower than that of the first region.

[0129] The conductivity of the first region may be greater than that of the second region, and the first region may be substantially used as an electrode or a signal line. The second region may substantially correspond to an active region (or channel region) of a transistor. In other words, a portion of the semiconductor pattern may be an active region of a transistor, and another portion may be a source or drain of the transistor.

[0130] The first to fourth insulating layers 20, 30, 40, and 50 may be disposed on the buffer layer 10. The first to fourth insulating layers 20, 30, 40, and 50 may include an inorganic layer or an organic layer, and may have a single layer structure or a multi-layer structure.

[0131] The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide, but the present disclosure is not limited thereto. The organic layer may include at least one of phenolic polymers, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, paraxylene polymers, vinyl alcohol polymers, and combinations thereof, but the present disclosure is not limited thereto.

[0132] The first insulating layer 20 may cover the semiconductor pattern of the circuit layer DP-CL. The gate G1 of the first transistor T1 may be disposed on the first insulating layer 20. The gate G1 may be a part of the conductive pattern. In a plan view, the gate G1 may overlap the active area AT. The gate G1 may be used as a mask in a process of doping the semiconductor pattern. The second insulating layer 30 may be disposed on the first insulating layer 20 and may cover the gate G1. The third insulating layer 40 may be disposed on the second insulating layer 30.

[0133] In embodiments, a layer including the buffer layer 10 , the first to third insulating layers 20 , 30 , and 40 , and a transistor (eg, the first transistor T1 ) formed between the first to third insulating layers 20 , 30 , and 40 may be defined as a transistor layer TFL.

[0134] The connection electrode CNE may be disposed between the first transistor T1 and the light emitting element OLED and may connect the first transistor T1 and the light emitting element OLED to each other. The connection electrode CNE may be disposed on the third insulating layer 40 and may be connected to the source electrode S1 via a first contact hole CH1 extending through the first insulating layer 20, the second insulating layer 30, and the third insulating layer 40.

[0135] The fourth insulating layer 50 may be disposed on the third insulating layer 40. The fourth insulating layer 50 may cover the connection electrode CNE. In one embodiment, the fourth insulating layer 50 may include an organic layer. The fourth insulating layer 50 including the organic layer may provide a flat top surface. However, the present disclosure is not necessarily limited thereto.

[0136] The display element layer DP-OL may be disposed on the circuit layer DP-CL. The display element layer DP-OL may include a light emitting element OLED, a pixel defining layer PDL, a spacer SR, an auxiliary electrode SE, and a dummy layer DML. The light emitting element OLED may include a first electrode (or anode) AE, an intermediate layer ML, and a second electrode (cathode) CE.

[0137] The first electrode AE ​​may be disposed on the fourth insulating layer 50 of the circuit layer DP-CL. The first electrode AE ​​may be connected to the connection electrode CNE via the second contact hole CH2 extending through the fourth insulating layer 50. The first electrode AE ​​may be connected to the first transistor T1 via the connection electrode CNE. The first electrode AE ​​may include a plurality of layers. The first electrode AE ​​may receive the first voltage ELVDD (see FIG. 1 ) via the first transistor T1. Figure 5 ).

[0138] The pixel defining layer PDL may be disposed on the fourth insulating layer 50. In the pixel defining layer PDL, a first opening PDL-OP1 exposing a portion of the first electrode AE ​​may be defined. The pixel defining layer PDL may cover a portion of the top surface of the first electrode AE. The portion of the first electrode AE ​​exposed by the first opening PDL-OP1 of the pixel defining layer PDL may correspond to the first light emitting area PXA1.

[0139] The pixel defining layer PDL may include an organic material. For example, the pixel defining layer PDL may include a polyacrylate resin or a polyimide resin, but the material of the pixel defining layer PDL is not limited thereto. In another embodiment, the pixel defining layer PDL may be made of an inorganic material. For example, the pixel defining layer PDL may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) etc., but the material of the pixel defining layer PDL is not limited thereto.

[0140] The pixel defining layer PDL may include a light absorbing material, or may have a (predetermined or selectable) color. For example, the pixel defining layer PDL may include a base resin and a black pigment and / or a black dye mixed with the base resin.

[0141] The middle layer ML may overlap the first opening PDL-OP1 in a plan view. The middle layer ML may include a plurality of organic layers and a charge generation layer, etc., disposed between the first electrode AE ​​and the second electrode CE facing each other. The organic layers may have a sequentially stacked structure. Each of the organic layers may include a functional layer containing a hole transport material or an electron transport material or a light emitting material. In one embodiment, the light emitting element OLED may be a light emitting element including a series structure of a plurality of light emitting layers.

[0142] The second electrode CE may face the first electrode AE ​​and may be disposed on the middle layer ML. The second electrode CE may be provided to be aligned with the light emitting regions PXA1, PXA2, and PXA3 (see FIG. 1 ) in a plan view. Figure 6 ) and a common layer overlapped with the non-light emitting area NPXA. A common voltage may be provided to the second electrode CE. For example, the common voltage may be the second voltage ELVSS (see Figure 5 ).

[0143] The first electrode AE ​​may be a semi-transmissive reflective electrode or a reflective electrode. The first electrode AE ​​may include silver (Ag) or a compound or mixture including silver (e.g., AgMg or AgYb). However, the present disclosure is not limited thereto, and the first electrode AE ​​according to an embodiment of the present disclosure may include Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, Yb, W, In, Zn, Sn, or a compound or mixture including them or a material having a multilayer structure such as LiF / Ca or LiF / Al.

[0144] The present disclosure is not limited thereto, and the first electrode AE ​​may have a multilayer structure including a reflective film or a semi-transmissive film made of the above material and a transparent conductive film made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), etc.

[0145] The second electrode CE may be formed by being thinly deposited to have a light-transmitting property. For example, the second electrode CE may have a thickness equal to or less than about However, the thickness of the second electrode CE is not limited thereto.

[0146] The spacer SR may be disposed on the pixel defining layer PDL. In one embodiment, the second electrode CE and the middle layer ML may be formed via common deposition across a plurality of pixels using an open mask. At this point, the middle layer ML may be divided by the spacer SR. The spacer SR may have a closed line shape with respect to the first light emitting area PXA1. Figure 7 As shown in FIG, the spacer SR may have an inverted tapered shape in a cross-sectional view. The shape of the spacer SR will refer to Figure 8 Described in detail.

[0147] In one embodiment of the present disclosure, the spacer SR may include an insulating material (e.g., an organic insulating material). According to an embodiment, the spacer SR may include an inorganic insulating material, may include a multilayer made of an organic insulating material and an inorganic insulating material, and may include a conductive material. For example, as long as the middle layer ML is electrically disconnected for each pixel, the type of material of the spacer SR is not particularly limited.

[0148] The auxiliary electrode SE may be disposed on the separator SR. Figure 7 As shown in , the auxiliary electrode SE may cover the top surface and the side surface of the separator SR. The auxiliary electrode SE may extend to the pixel defining layer PDL along the top surface and the side surface of the separator SR. For example, the auxiliary electrode SE may be disposed on the separator SR and the pixel defining layer PDL. The auxiliary electrode SE may overlap the pixel defining layer PDL in a plan view. The auxiliary electrode SE may be disposed in the non-luminous area NPXA.

[0149] According to one embodiment of the present disclosure, the auxiliary electrode SE may include a reflective material. The auxiliary electrode SE may include a reflective metal material. For example, the auxiliary electrode SE may include copper (Cu). However, the present disclosure is not limited thereto, and the auxiliary electrode SE may include Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, Yb, W, In, Zn, Sn, or a compound or mixture thereof or a material having a multilayer structure such as LiF / Ca or LiF / Al.

[0150] The dummy layer DML may be disposed on the auxiliary electrode SE. The dummy layer DML and the intermediate layer ML may be formed via the same process. Accordingly, the dummy layer DML and the intermediate layer ML may include the same material. The dummy layer DML may be formed to contact a portion of the top surface and the side surface of the auxiliary electrode SE. The intermediate layer ML may be formed to contact a portion of the auxiliary electrode SE disposed on the pixel defining layer PDL, and the second electrode CE may be disposed in a region where the intermediate layer ML and the dummy layer DML are not in contact with the auxiliary electrode SE.

[0151] The auxiliary electrode SE may be electrically connected to the second electrode CE. For example, the middle layer ML may be disconnected by the separator SR, and the second electrode CE and the auxiliary electrode SE may contact and be electrically connected to each other in the region where the middle layer ML is disconnected. The auxiliary electrode SE may include one of the materials that may be used for the second electrode CE. The second electrode CE may easily contact the auxiliary electrode SE including the same material. Accordingly, the second electrode CE may be electrically connected to the auxiliary electrode SE.

[0152] In the display device DD (see Figure 1 ) has a large area, the resistance of the second electrode CE may increase, resulting in a voltage drop (IR drop), which may prevent uniform image quality from being achieved. However, according to the present disclosure, the second electrode CE is electrically connected to the second voltage ELVSS (see Figure 5 ) can be electrically connected to the second electrode CE. Accordingly, the second voltage ELVSS can be directly provided to the second electrode CE electrically connected to the auxiliary electrode SE. Since the second electrode CE directly receives the second voltage ELVSS from the auxiliary electrode SE, the resistance of the second electrode CE can be reduced, and the second electrode CE electrically connected to the auxiliary electrode SE can prevent the voltage drop problem. As a result, the display device DD with stable image brightness (see Figure 1 ) can be provided.

[0153] The encapsulation layer TFE may be disposed on the display element layer DP-OL to seal the display element layer DP-OL. The encapsulation layer TFE may include a plurality of inorganic films and at least one organic film.

[0154] Each of the inorganic films may protect the light emitting element OLED from moisture and / or oxygen. Each of the inorganic films may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide, but the present disclosure is not limited thereto.

[0155] The at least one organic film may protect the light emitting element OLED from foreign matter such as dust particles. The at least one organic film may include an acrylic resin, but the present disclosure is not limited thereto.

[0156] Figure 8 yes Figure 7 An enlarged view of region BB' is shown in FIG. Figure 8 It is schematically shown that light Lg emitted from the middle layer ML is reflected from the auxiliary electrode SE and travels to the display device DD (see FIG. Figure 1 ) outside.

[0157] refer to Figure 8, light Lg may be emitted from the light emitting layer included in the middle layer ML. The emitted light Lg may be reflected from a portion of the auxiliary electrode SE disposed on the side surface SR-W of the partition SR and incident to the first electrode AE, and the light Lg incident to the first electrode AE ​​may be reflected from the first electrode AE ​​and easily emitted to the outside of the display device DD.

[0158] The pixel defining layer PDL and the spacer SR may serve as a partition wall SP. For example, the partition wall SP may include the pixel defining layer PDL and the spacer SR. The partition wall SP may include a first portion B1 and a second portion B2. The thickness of the second portion B2 in the third direction DR3 may be greater than the thickness of the first portion B1 in the third direction DR3. The first portion B1 may be a portion including only the pixel defining layer PDL, and the second portion B2 may be a portion including the pixel defining layer PDL and the spacer SR disposed on the pixel defining layer PDL. Light-emitting areas PXA1, PXA2, and PXA3 (see Figure 6 ) may be defined by the first portion B1 of the partition wall SP. The middle layer ML may be disconnected by the second portion B2 of the partition wall SP, and the second electrode CE and the auxiliary electrode SE may contact and be electrically connected to each other in the second portion B2.

[0159] According to one embodiment of the present disclosure, the thickness d1 of the spacer SR in the third direction DR3 and the thickness d2 of the pixel defining layer PDL in the third direction DR3 may be the same. For example, the thickness d1 of the spacer SR may be in the range of about 1 μm to about 2 μm. The thickness d2 of the pixel defining layer PDL may be in the range of about 1 μm to about 2 μm. However, the present disclosure is not limited thereto, and the thickness d2 of the pixel defining layer PDL may be greater than the thickness d1 of the spacer SR.

[0160] According to one embodiment of the present disclosure, a portion of the first electrode AE ​​may overlap with the pixel defining layer PDL in a plan view. The pixel defining layer PDL may be disposed on the first electrode AE ​​in a region overlapping with the portion of the first electrode AE. The first electrode AE ​​overlapping with the pixel defining layer PDL in a plan view may not overlap with the separator SR in a plan view. However, the present disclosure is not limited thereto, and the first electrode AE ​​may partially overlap with the separator SR in a plan view. The length d3 of the portion of the first electrode AE ​​overlapping with the pixel defining layer PDL in a plan view in the second direction DR2 may be equal to or greater than about 3 μm.

[0161] According to one embodiment of the present disclosure, the pixel defining layer PDL may include a light-transmitting material. Accordingly, light Lg reflected from a portion of the auxiliary electrode SE disposed on the side surface SR-W of the separator SR may be incident on the first electrode AE ​​overlapping the pixel defining layer PDL in a plan view. The light Lg may be reflected from the first electrode AE ​​overlapping the pixel defining layer PDL in a plan view, and the reflected light Lg may be easily emitted to the outside of the display device DD. As a result, the light Lg emitted from the light-emitting layer included in the middle layer ML may be easily emitted to the outside of the display device DD, and a display device DD with improved light-emitting efficiency may be provided.

[0162] The length (or width) of the separator SR in the second direction DR2 may gradually increase in the third direction DR3 (e.g., in the thickness direction of the separator SR). For example, the separator SR may have an inverted tapered shape in a cross-sectional view. The angle θ (hereinafter, the cone angle) formed by the side surface SR-W of the separator SR facing the intermediate layer ML relative to the top surface of the pixel defining layer PDL may be an acute angle. That is, the side surface SR-W of the separator SR facing the intermediate layer ML may be inclined toward the light-emitting element OLED. The cone angle θ may be in the range of about 70° to about 80°. However, the present disclosure is not limited thereto, and the cone angle θ may be set differently as long as the separator SR can electrically disconnect the intermediate layer ML for each pixel. The separator SR may include a plurality of layers and the uppermost layer of the separator SR may include a tip protruding from the intermediate layer of the separator SR, but the present disclosure is not limited thereto.

[0163] In the auxiliary electrode SE, a length d4 of a portion disposed on and extending on the pixel defining layer PDL when viewed in the third direction DR3 and a length of a portion disposed on the top surface SR-T of the spacer SR from a point corresponding to a distal end of the bottom surface of the spacer SR to a distal end of the portion disposed on the top surface SR-T of the spacer SR extending in a direction opposite to the second direction DR2 may be the same. For example, the length d4 of the portion of the auxiliary electrode SE extending on the pixel defining layer PDL may be equal to or less than about 0.5 μm.

[0164] In the display device DD according to one embodiment of the present disclosure, since the auxiliary electrode SE including a reflective material is disposed on the side surface SR-W of the partition SR, the light Lg emitted from the light emitting layer included in the middle layer ML to the auxiliary electrode SE may be reflected from the auxiliary electrode SE and easily emitted to the outside of the display device DD. As a result, the light emitting efficiency may be increased by about 10% compared to the amount of light Lg emitted from the light emitting layer.

[0165] Fig. 9Ais a schematic enlarged cross-sectional view of a separator and an auxiliary electrode according to an embodiment of the present disclosure.

[0166] refer to Fig. 9A , the auxiliary electrode SEa may include an upper auxiliary electrode T-SE disposed on the top surface SR-T of the separator SR and a side auxiliary electrode S-SE disposed on the side surface SR-W of the separator SR. The upper auxiliary electrode T-SE may be disposed to cover the top surface SR-T of the separator SR, and may have a uniform thickness Th1 throughout the top surface SR-T of the separator SR in a normal direction to the top surface SR-T of the separator SR. The side auxiliary electrode S-SE may be disposed to cover the side surface SR-W of the separator SR, and may have a non-uniform thickness Th2 throughout the side surface SR-W of the separator SR in a normal direction to the side surface SR-W of the separator SR.

[0167] According to one embodiment of the present disclosure, the thickness Th1 of the upper auxiliary electrode T-SE and the thickness Th2 of the side auxiliary electrode S-SE may be different from each other. For example, the thickness Th1 of the upper auxiliary electrode T-SE may be greater than the thickness Th2 of the side auxiliary electrode S-SE. During the formation of the auxiliary electrode SEa, since the spacer SR has an inverted tapered shape, the upper auxiliary electrode T-SE may be uniformly deposited in the positive direction. However, as it becomes closer to the pixel defining layer PDL, the side auxiliary electrode S-SE may not be uniformly deposited due to the top surface SR-T of the spacer SR. Therefore, the thickness Th2 of the side auxiliary electrode S-SE may be less than the thickness Th1 of the upper auxiliary electrode T-SE. As it becomes closer to the pixel defining layer PDL, the deposited material may become difficult to be deposited on the side surface SR-W of the spacer SR due to the top surface SR-T of the spacer SR, so that the thickness Th2 of the side auxiliary electrode S-SE may become smaller.

[0168] Fig. 9B is a schematic enlarged cross-sectional view of a separator, an auxiliary electrode, and a lower auxiliary electrode according to an embodiment of the present disclosure.

[0169] refer to Fig. 9B , the auxiliary electrode SEb may be disposed on the top surface SR-T and the side surface SR-W of the separator SR to cover all of the top surface SR-T and the side surface SR-W of the separator SR.

[0170] The lower auxiliary electrode B-SE may be disposed between the spacer SR and the pixel defining layer PDL. The lower auxiliary electrode B-SE may be in direct contact with the bottom surface of the spacer SR and each of the auxiliary electrodes SEb. According to one embodiment of the present disclosure, the auxiliary electrode SEb and the lower auxiliary electrode B-SE may include the same material. For example, each of the auxiliary electrode SEb and the lower auxiliary electrode B-SE may include a reflective material. However, the present disclosure is not limited thereto, and the lower auxiliary electrode B-SE may not include a reflective material. For example, the lower auxiliary electrode B-SE may include a metal material that may be electrically connected to the auxiliary electrode SEb. Accordingly, the lower auxiliary electrode B-SE and the auxiliary electrode SEb may be electrically connected to each other.

[0171] Fig.10 2 is a schematic cross-sectional view showing a portion of a display panel according to an embodiment of the present disclosure. Redundant descriptions will be omitted below.

[0172] refer to Fig.10 The display panel DPa may further include an auxiliary wiring SBL disposed on the third insulating layer 40. In one embodiment, the auxiliary wiring SBL and the connection electrode CNE may be disposed on the same layer. The auxiliary wiring SBL may be electrically connected to the connection electrode CNE to which the second voltage ELVSS (see Figure 5 ) power line to provide a second voltage ELVSS.

[0173] The auxiliary wiring SBL may be electrically connected to the auxiliary electrode SE disposed on the pixel defining layer PDL. For example, the first connection electrode CNE1 may be disposed on the fourth insulating layer 50 to electrically connect the auxiliary wiring SBL and the auxiliary electrode SE to each other. The auxiliary electrode SE may be connected to the first connection electrode CNE1 via a fourth contact hole CH4 extending through the pixel defining layer PDL, and the first connection electrode CNE1 may be connected to the auxiliary wiring SBL via a third contact hole CH3 extending through the fourth insulating layer 50. The second voltage ELVSS (see Figure 5 ) may be applied to the auxiliary electrode SE via the auxiliary wiring SBL. However, the present disclosure is not limited thereto, and the auxiliary wiring SBL and the gate G1 or the source S1 and the drain D1 may be disposed at the same layer.

[0174] Fig.11A is an enlarged plan view of a portion of a display panel according to an embodiment of the present disclosure. Fig. 11B It is along Fig.11A Schematic cross-sectional view of the display panel taken along line II-II' in FIG.

[0175] refer to Fig.11A and Fig. 11BThe light emitting areas PXA1a, PXA2a, and PXA3a and the non-light emitting area NPXA may be defined in the display panel DPb. The light emitting areas PXA1a, PXA2a, and PXA3a may include a first light emitting area PXA1a, a second light emitting area PXA2a, and a third light emitting area PXA3a.

[0176] The pixel defining layer PDLa may include a first pixel defining layer PDL1 surrounding the light emitting areas PXA1a, PXA2a, and PXA3a in a plan view, and a second pixel defining layer PDL2 surrounded by each of the light emitting areas PXA1a, PXA2a, and PXA3a in a plan view. The first light emitting area PXA1a may be defined by a first opening PDL-OP1a defined in the first pixel defining layer PDL1 and the second pixel defining layer PDL2. The second light emitting area PXA2a may be defined by a second opening PDL-OP2a defined in the first pixel defining layer PDL1 and the second pixel defining layer PDL2. The third light emitting area PXA3a may be defined by a third opening PDL-OP3a defined in the first pixel defining layer PDL1 and the second pixel defining layer PDL2. The first pixel defining layer PDL1 and the second pixel defining layer PDL2 may overlap with the non-light emitting area NPXA in a plan view.

[0177] The spacer SRa may include a first spacer SR1 disposed on the first pixel defining layer PDL1 and a second spacer SR2 disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1 and the first spacer SR1 may serve as a first partition wall, and the second pixel defining layer PDL2 and the second spacer SR2 may serve as a second partition wall. The first spacer SR1 may be Figure 7 . Each of the second spacer SR2 and the first spacer SR1 may have an inverted tapered shape in a cross-sectional view. Accordingly, the second spacer SR2 may be disposed on the second pixel defining layer PDL2 to disconnect the middle layer ML. The width of the second spacer SR2 in the second direction DR2 may be smaller than the width of the first spacer SR1 in the second direction DR2. A sufficient size of the first light emitting area PXA1a may be ensured by making the width of the second spacer SR2 in the second direction DR2 small.

[0178] The auxiliary electrode SEc may include a first auxiliary electrode SE1 disposed on the first separator SR1 and a second auxiliary electrode SE2 disposed on the second separator SR2. Figure 6. Each of the first auxiliary electrode SE1 and the second auxiliary electrode SE2 may include a reflective material. The second auxiliary electrode SE2 and the first auxiliary electrode SE1 may have shapes corresponding to the shapes of the second separator SR2 and the first separator SR1, respectively, in a cross-sectional view. The width of the second separator SR2 in the second direction DR2 and the width of the first separator SR1 in the second direction DR2 may be different from each other. For example, the width of the second separator SR2 in the second direction DR2 may be smaller than the width of the first separator SR1 in the second direction DR2. The present disclosure is not limited thereto, and the auxiliary electrode SEc may be provided only on one of the first separator SR1 and the second separator SR2.

[0179] According to one embodiment, since the first auxiliary electrode SE1 including a reflective material is disposed on the side surface of the first separator SR1 and the second auxiliary electrode SE2 including a reflective material is disposed on the side surface of the second separator SR2, light Lg (see FIG. 1 ) emitted from the light emitting layer included in the middle layer ML to the first auxiliary electrode SE1 or the second auxiliary electrode SE2 is Figure 8 ) may be reflected from the first auxiliary electrode SE1 or the second auxiliary electrode SE2 and easily emitted to the display device DD (see Figure 1 ) outside. As a result, a display device DD with improved light emitting efficiency can be provided.

[0180] The dummy layer DMLa may include a first dummy layer DML1 disposed on the first auxiliary electrode SE1 and a second dummy layer DML2 disposed on the second auxiliary electrode SE2. The first dummy layer DML1 and the second dummy layer DML2 and the intermediate layer ML may be formed by the same process. Accordingly, the first dummy layer DML1 and the second dummy layer DML2 and the intermediate layer ML may include the same material.

[0181] The second electrode CE may be electrically connected to the first auxiliary electrode SE1 and the second auxiliary electrode SE2. For example, the middle layer ML may be disconnected by the first separator SR1 and the second electrode CE and the first auxiliary electrode SE1 may contact and be electrically connected to each other in a region where the middle layer ML is disconnected, and the middle layer ML may be disconnected by the second separator SR2 and the second electrode CE and the second auxiliary electrode SE2 may contact and be electrically connected to each other in a region where the middle layer ML is disconnected.

[0182] In one embodiment, each of the first auxiliary electrode SE1 and the second auxiliary electrode SE2 may include one of the materials that may be used for the second electrode CE. Accordingly, the second electrode CE may directly contact each of the first auxiliary electrode SE1 and the second auxiliary electrode SE2 and may be electrically connected to each of the first auxiliary electrode SE1 and the second auxiliary electrode SE2.

[0183] Fig. 12A is a schematic enlarged cross-sectional view of a separator and an auxiliary electrode according to an embodiment of the present disclosure.

[0184] refer to Fig. 12A , the auxiliary electrode SEd may be disposed on both side surfaces SR-W of the separator SR. The auxiliary electrode SEd may be disposed to cover both side surfaces SR-W of the separator SR. Fig. 9A Compared with the auxiliary electrode SEa shown in Fig. 12A The auxiliary electrode SEd shown in FIG. 1 may not include the upper auxiliary electrode T-SE (see FIG. 1-1 ). Fig. 9A ). For example, in the formation Fig. 9A After the auxiliary electrode SEa shown in FIG. 1 is formed, the auxiliary electrode SEd can be formed by patterning the upper auxiliary electrode T-SE using a separate mask. As a result, it is possible to prevent the display device DD (see FIG. 1 ) from being damaged. Figure 1 ) is reflected from the upper auxiliary electrode T-SE and viewed by the user.

[0185] As the auxiliary electrode SEd becomes closer to the pixel defining layer PDL, the thickness Th3 of the auxiliary electrode SEd in the normal direction of the side surface SR-W of the spacer SR may become smaller. Because the spacer SR has an inverted tapered shape, as it becomes closer to the pixel defining layer PDL, the deposition material may become difficult to be deposited on the side surface SR-W of the spacer SR due to the top surface SR-T of the spacer SR, so that the thickness Th3 of the auxiliary electrode SEd may become smaller.

[0186] Fig. 12B is a schematic enlarged cross-sectional view of a separator, an auxiliary electrode, and a lower auxiliary electrode according to an embodiment of the present disclosure.

[0187] refer to Fig. 12B , the auxiliary electrode SEe may be disposed on the side surface SR-W of the separator SR to cover the entirety of the side surface SR-W of the separator SR.

[0188] The lower auxiliary electrode B-SE may be disposed between the spacer SR and the pixel defining layer PDL. The lower auxiliary electrode B-SE may be in direct contact with the bottom surface of the spacer SR and each of the auxiliary electrodes SEe. According to one embodiment of the present disclosure, the auxiliary electrode SEe and the lower auxiliary electrode B-SE may include the same material. For example, each of the auxiliary electrode SEe and the lower auxiliary electrode B-SE may include a reflective material. However, the present disclosure is not limited thereto, and the lower auxiliary electrode B-SE may not include a reflective material. For example, the lower auxiliary electrode B-SE may include a metal material that may be electrically connected to the auxiliary electrode SEe. Accordingly, the lower auxiliary electrode B-SE and the auxiliary electrode SEe may be electrically connected to each other.

[0189] In the display device of the present disclosure, since the auxiliary electrode including the reflective material is disposed on the side surface of the partition, the light emitted from the light emitting layer to the auxiliary electrode can be reflected from the auxiliary electrode and easily emitted to the outside of the display device. As a result, a display device with improved light emitting efficiency can be provided.

[0190] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure belongs will be able to make various modifications and changes.Therefore, the above embodiments of the present disclosure can be implemented separately or in combination with each other.

[0191] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the claims, and it should be understood that all technical spirits within the equivalent scope are included in the protection scope of the present disclosure.

Claims

1. A display device, comprising: A circuit layer is disposed on the base substrate; as well as A display element layer is arranged on the circuit layer, wherein The display element layer includes: a light emitting element; a pixel defining layer defining a light emitting area corresponding to the light emitting element; a partition disposed on the pixel defining layer; and an auxiliary electrode disposed on the partition and including a reflective material. The auxiliary electrode is electrically connected to the electrode of the light emitting element, The side surface of the partition is inclined toward the light emitting element, and The auxiliary electrode covers the side surface of the separator.

2. The display device according to claim 1, wherein: The auxiliary electrode comprises: an upper auxiliary electrode disposed on a top surface of the separator; and A side auxiliary electrode is disposed on the side surface of the separator.

3. The display device according to claim 2, wherein: A thickness of the upper auxiliary electrode and a thickness of the side auxiliary electrode are different from each other.

4. The display device according to claim 3, wherein: The thickness of the upper auxiliary electrode is greater than the thickness of the side auxiliary electrode.

5. The display device according to claim 2, wherein: As the side auxiliary electrode approaches the pixel defining layer, the thickness of the side auxiliary electrode becomes smaller.

6. The display device according to claim 1, wherein: The display element layer further includes a lower auxiliary electrode disposed between the spacer and the pixel defining layer.

7. The display device according to claim 6, wherein: The auxiliary electrode and the lower auxiliary electrode include the same material.

8. The display device according to claim 7, wherein: The auxiliary electrode and the lower auxiliary electrode are electrically connected to each other.

9. The display device according to claim 1, wherein: The pixel defining layer comprises: a first pixel defining layer surrounding the light emitting area in a plan view; and A second pixel defining layer is surrounded by the light emitting area in the plan view.

10. The display device according to claim 9, wherein: The separator comprises: A first spacer, disposed on the first pixel defining layer; and The second spacer is disposed on the second pixel defining layer.

11. The display device according to claim 10, wherein: The auxiliary electrode is disposed on at least one of the first separator and the second separator.

12. The display device according to claim 11, wherein The auxiliary electrode comprises: a first auxiliary electrode, disposed on the first separator; and a second auxiliary electrode disposed on the second separator, and The first auxiliary electrode and the second auxiliary electrode are electrically connected to each other.

13. The display device according to claim 1, wherein: The auxiliary electrode includes metal.

14. The display device according to claim 1, wherein: The light emitting element comprises: a first electrode; an intermediate layer, disposed on the first electrode; and The second electrode is electrically connected to the auxiliary electrode.

15. The display device according to claim 14, wherein: The intermediate layer is interrupted by the separator.

16. The display device according to claim 14, wherein: The first electrode partially overlaps the pixel defining layer in a plan view.

17. The display device according to claim 16, wherein: The pixel defining layer includes a light-transmitting material.

18. The display device according to any one of claims 1 to 17, wherein: An angle between the side surface of the spacer and a top surface of the pixel defining layer is in a range of 70° to 80°.

19. The display device according to any one of claims 1 to 17, wherein The circuit layer includes auxiliary wiring for applying a driving voltage to the light emitting element, and The auxiliary electrode and the auxiliary wiring are electrically connected to each other.

20. A display device, comprising: A circuit layer is disposed on the base substrate; A light emitting element, disposed on the circuit layer and corresponding to the light emitting area; A partition wall is disposed on the circuit layer and is disposed to correspond to a non-luminescent area adjacent to the luminescent area; as well as an auxiliary electrode disposed on the partition wall and comprising a reflective material, wherein The auxiliary electrode is electrically connected to the electrode of the light emitting element, The partition walls include a first partition wall surrounding the light emitting element in a plan view and a second partition wall surrounded by the light emitting element in the plan view, and The auxiliary electrode is disposed on at least one of the first barrier ribs and the second barrier ribs.

21. The display device according to claim 20, wherein: The partition wall comprises: a pixel defining layer, defining the light emitting area corresponding to the light emitting element; and A spacer is disposed on the pixel defining layer.

22. The display device according to claim 21, wherein The side surface of the partition is inclined toward the light emitting element, and The auxiliary electrode covers the side surface of the separator.

23. The display device according to claim 22, wherein: An angle between the side surface of the spacer and a top surface of the pixel defining layer is in a range of 70° to 80°.

24. The display device according to claim 21, wherein: The light emitting element comprises: a first electrode; an intermediate layer, disposed on the first electrode; and The second electrode is electrically connected to the auxiliary electrode.

25. The display device according to claim 24, wherein: The intermediate layer is interrupted by the separator.

26. The display device according to claim 24, wherein: The first electrode partially overlaps the pixel defining layer in the plan view.

27. The display device according to claim 26, wherein: The pixel defining layer includes a light-transmitting material.

28. The display device according to any one of claims 20 to 27, wherein The auxiliary electrode comprises: A first auxiliary electrode is disposed on the first partition wall; and a second auxiliary electrode disposed on the second partition wall, and The first auxiliary electrode and the second auxiliary electrode are electrically connected to each other.

29. A display device comprising: A circuit layer is disposed on the base substrate; A light emitting element, disposed on the circuit layer and corresponding to the light emitting area; a partition wall disposed on the circuit layer, disposed to correspond to a non-light emitting area adjacent to the light emitting area and including a first portion and a second portion having a thickness greater than that of the first portion; as well as an auxiliary electrode disposed on the second portion of the partition wall and comprising a reflective material, Wherein, the auxiliary electrode is electrically connected to the electrode of the light emitting element.

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