Display panel

Abstract

The invention discloses a display panel and a display device. The display panel comprises a driving back plate (BP), first electrodes (ANO), a pixel definition layer (PDL), a light-emitting layer (OL) and a second electrode (CAT), wherein the first electrodes (ANO) and the pixel definition layer (PDL) are arranged on one side surface of the driving back plate (BP); the pixel definition layer (PDL) is provided with pixel openings (PH) for exposing the first electrodes and separation grooves (SES) located between two adjacent pixel openings (PH), and the boundaries of the pixel openings (PH) are located within the boundaries of the exposed first electrodes (ANO); a first cut-off groove (CU1) is formed in the side wall of the pixel opening (PH), and a second cut-off groove (CU2) is formed in the side wall of the separation groove (SES); the first cut-off groove (CU1) is at least partially positioned on one side of the second cut-off groove (CU2) far away from the driving back plate (BP); the light-emitting layer (OL) covers the pixel definition layer (PDL) and the first electrode (ANO); the second electrode (CAT) covers the light emitting layer (OL).

Description

[0001] This disclosure is a divisional application. The application number of the original application is 202280004050.X, the application date is November 7, 2022, and the name of the invention is “Display panel and display device”.

[0002] Cross-references

[0003] This disclosure claims priority to the PCT international application entitled “Display Substrate” and having application number PCT / CN2021 / 133886 and filed on November 29, 2021. The entire contents of the PCT international application are incorporated herein by reference in their entirety. Technical Field

[0004] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0005] With the development of display technology, display panels have been widely used in various electronic devices such as mobile phones to realize image display and touch operation. Among them, OLED (Organic Light-Emitting Diode) display panel is a more common one. However, existing display panels have the problem of cross-color.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] The present disclosure provides a display panel and a display device.

[0008] According to one aspect of the present disclosure, there is provided a display panel, comprising:

[0009] Driver backplane;

[0010] A plurality of first electrodes are arranged in an array on a side surface of the driving back plate;

[0011] A pixel definition layer is arranged on the same side of the driving backplane as the first electrode, and is provided with a pixel opening exposing each of the first electrodes and a separation groove between two adjacent pixel openings, wherein the boundary of the pixel opening is located within the boundary of the first electrode exposed therein; a first truncation groove is provided on the sidewall of the pixel opening, and a second truncation groove is provided on the sidewall of the separation groove; and the first truncation groove is at least partially located on a side of the second truncation groove away from the driving backplane;

[0012] a light-emitting layer, covering the pixel definition layer and the first electrode;

[0013] The second electrode covers the light-emitting layer.

[0014] In an exemplary embodiment of the present disclosure, the pixel definition layer includes an etch stop layer, a first definition layer, and a second definition layer sequentially stacked in a direction away from the driving backplane;

[0015] The pixel opening penetrates the etch stop layer, the first definition layer and the second definition layer; the separation groove penetrates the first definition layer and the second definition layer and exposes the etch stop layer;

[0016] The first truncation groove and the second truncation groove are located in the first definition layer.

[0017] In an exemplary embodiment of the present disclosure, the etch stop layer comprises:

[0018] A buffer layer, at least partially disposed on a surface of the first electrode away from the driving backplane;

[0019] The barrier layer is stacked on the surface of the buffer layer away from the driving back plate; and the first definition layer is stacked on the surface of the barrier layer away from the driving back plate.

[0020] In an exemplary embodiment of the present disclosure, the pixel opening includes a first segment located in the etch stop layer and a second segment located in the second definition layer, and the boundary of the orthographic projection of the second segment on the driving backplane surrounds the boundary of the orthographic projection of the first segment on the driving backplane.

[0021] In an exemplary embodiment of the present disclosure, a distance between a boundary of an orthographic projection of the second segment on the driving backplane and a boundary of an orthographic projection of the first segment on the driving backplane is not greater than 0.2 μm and not less than 0.06 μm.

[0022] In an exemplary embodiment of the present disclosure, the distance between the two adjacent pixel openings located in the first segment is not greater than 1.9 μm and not less than 1.1 μm;

[0023] The distance between the two adjacent pixel openings located in the second segment is not greater than 1.6 μm and not less than 0.9 μm.

[0024] In an exemplary embodiment of the present disclosure, the length of the sidewalls of both sides of the first truncation groove away from the driving back plate is not less than 0.03 μm and not more than 0.05 μm.

[0025] In an exemplary embodiment of the present disclosure, the length of the side walls of the second truncation groove away from the driving back plate is not less than 0.07 μm and not more than 0.1 μm.

[0026] In an exemplary embodiment of the present disclosure, the pixel definition layer further includes:

[0027] The filling layer is arranged on the same side of the driving back plate as the first electrodes and separates the first electrodes; a portion of the etching stop layer is stacked on a surface of the filling layer away from the driving back plate.

[0028] In an exemplary embodiment of the present disclosure, the surface of the filling layer away from the driving back plate is located on a side of the surface of the first electrode away from the driving back plate close to the driving back plate;

[0029] The pixel definition layer includes an edge portion, a middle portion and a connection portion. The edge portion is located on a surface of the first electrode away from the driving backplane; the middle portion is located between two adjacent first electrodes; and the connection portion connects the edge portion and the middle portion.

[0030] In an exemplary embodiment of the present disclosure, the sidewall of the separation groove is a slope surface expanding in a direction away from the driving back plate.

[0031] In an exemplary embodiment of the present disclosure, the bottom surface of the first truncation groove is a slope surface whose depth decreases in a direction away from the driving back plate.

[0032] The bottom surface of the second truncation groove is a slope surface whose depth decreases in a direction away from the driving back plate.

[0033] In an exemplary embodiment of the present disclosure, a slope of the connecting portion is smaller than slopes of a bottom surface of the first truncation groove and a bottom surface of the second truncation groove.

[0034] In an exemplary embodiment of the present disclosure, the orthographic projection of the first truncation groove on the driving backplane is located within the orthographic projection of the first electrode on the driving backplane.

[0035] In an exemplary embodiment of the present disclosure, the width of at least a portion of the second truncation groove is greater than the width of the first truncation groove.

[0036] In an exemplary embodiment of the present disclosure, a depth of the second truncation groove is smaller than a depth of the first truncation groove.

[0037] In an exemplary embodiment of the present disclosure, an angle between a side wall of the second truncation groove away from the driving back plate and a surface of the driving back plate on which the first electrode is provided is greater than an angle between a side wall of the first truncation groove away from the driving back plate and a surface of the driving back plate on which the first electrode is provided.

[0038] In an exemplary embodiment of the present disclosure, a distance between the first truncation groove and the second truncation groove perpendicular to the driving back plate is greater than 0 and is smaller than a width of one of the first truncation groove and the second truncation groove.

[0039] In an exemplary embodiment of the present disclosure, half of the difference between a distance between two adjacent pixel openings and a width of the separation groove is greater than the width of the separation groove.

[0040] In an exemplary embodiment of the present disclosure, the first electrode comprises:

[0041] A first conductive layer, disposed on a side surface of the driving backplane;

[0042] A second conductive layer, stacked on a surface of the first conductive layer away from the driving backplane;

[0043] The first conductive protection layer covers the surface of the second conductive layer away from the driving back plate, and the side walls of the second conductive layer and the first conductive layer.

[0044] In an exemplary embodiment of the present disclosure, the first electrode further includes a second conductive protection layer covering the first conductive protection layer.

[0045] In an exemplary embodiment of the present disclosure, a first groove is provided on the surface of the driving backplane where the first electrode is provided, and a second groove is provided at the bottom of the first groove;

[0046] The first conductive protection layer and the second conductive protection layer cover the sidewall and the bottom surface of the first groove in an area outside the second groove.

[0047] In an exemplary embodiment of the present disclosure, a width of the separation groove is equal to a width of the second groove.

[0048] In an exemplary embodiment of the present disclosure, the width of the first groove is not less than 0.5 μm and not more than 1.2 μm; the width of the second groove is not less than 0.2 μm and not more than 0.9 μm.

[0049] In an exemplary embodiment of the present disclosure, the light-emitting layer includes a hole injection layer and a plurality of light-emitting sublayers, each of the light-emitting sublayers is arranged on a side of the hole injection layer away from the driving backplane in a direction away from the driving backplane; two adjacent light-emitting sublayers are connected in series via a charge generation layer; the light-emitting sublayer includes a hole transport layer, at least one light-emitting material layer and an electron transport layer arranged in a direction away from the driving backplane;

[0050] The hole injection layer is disconnected at the first truncation groove;

[0051] At least one of the charge generation layers is disconnected at the second cutoff groove.

[0052] In an exemplary embodiment of the present disclosure, a side wall of at least one of the pixel openings is provided with a plurality of first truncation grooves distributed along a circumferential direction; and at least two of the first truncation grooves of the same pixel opening have different widths.

[0053] In an exemplary embodiment of the present disclosure, the number of the light-emitting sublayers is three, and the number of the charge generation layers is two;

[0054] In two first truncation grooves with different widths in the same pixel opening, a width difference between the two first truncation grooves is 0.8 to 1.2 times a width difference between the first truncation groove and the second truncation groove.

[0055] In an exemplary embodiment of the present disclosure, the number of the light-emitting sublayers is two, and the number of the charge generation layer is one; the light-emitting sublayer farther from the driving backplane includes a light-emitting material layer that emits blue light;

[0056] The distance between the blue light emitting material layer and the charge generation layer in the pixel opening is greater than the distance between them in the range of the pixel definition layer.

[0057] In an exemplary embodiment of the present disclosure, the second electrode forms a flat portion in a region corresponding to the first electrode, and forms a recessed portion in a region corresponding to the separation groove, and the recessed portion smoothly transitions to the flat portion.

[0058] According to one aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above.

[0059] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0061] Figure 1 It is a partial cross-sectional view of an embodiment of the display panel disclosed in the present invention.

[0062] Figure 2It is a partial cross-sectional view of a driving backplane, a first electrode and a pixel definition layer in one embodiment of the display panel of the present disclosure.

[0063] Figure 3 It is a partial cross-sectional view of a driving backplane and a first electrode in one embodiment of a display panel disclosed herein.

[0064] Figure 4 It is a partial cross-sectional view of a driving backplane in one embodiment of the display panel disclosed herein.

[0065] Figure 5 It is a partial cross-sectional view of a driving backplane, a first electrode and a pixel definition layer in another embodiment of the display panel of the present disclosure.

[0066] Figure 6 It is a partial cross-sectional view of a first embodiment of the display panel disclosed in the present invention.

[0067] Figure 7 It is a partial cross-sectional view of a second embodiment of the display panel disclosed in the present invention.

[0068] Figure 8 It is a partial cross-sectional view of a driving backplane, a first electrode and a pixel definition layer in one embodiment of the display panel of the present disclosure.

[0069] Fig. 9 It is a partial cross-sectional view of a driving backplane, a first electrode and a pixel definition layer in another embodiment of the display panel of the present disclosure.

[0070] Fig.10 It is a partial cross-sectional view of a driving backplane, a first electrode and a pixel definition layer in yet another embodiment of the display panel of the present disclosure.

[0071] Fig.11 It is a schematic diagram showing that a light-emitting unit has two light-emitting sub-layers in one embodiment of a display panel disclosed herein.

[0072] Fig.12 It is a schematic diagram showing that a light-emitting unit has three light-emitting sub-layers in one embodiment of a display panel disclosed herein.

[0073] Fig.13 It is a partial top view of an embodiment of the display panel disclosed in the present invention. DETAILED DESCRIPTION

[0074] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0075] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0076] Any "slope" in this application is a straight line in a cross section perpendicular to the drive back plate, and the slope of the "slope" (for example, Figure 5 α, β) in the graph can be defined as the angle of the first electrode surrounded by the slope surface in the angle between the straight line or its extension and the surface where the slope surface is located. It should be noted that, considering the influence of process errors, the straight line mentioned above may not be an absolute straight line, but may be a curve extending roughly along the straight line. The curve may have multiple tangent lines, each of which has an angle with the surface where the slope surface is located. The slope of the curve may be the maximum angle among the angles, or the average value of the angles.

[0077] In the related art, a silicon-based OLED display panel includes a driving backplane and a light-emitting functional layer, wherein: the light-emitting layer is arranged on one side of the driving backplane and includes a plurality of light-emitting units, and the light-emitting unit may include a first electrode (anode), a light-emitting layer, and a second electrode (cathode) stacked in sequence in a direction away from the driving backplane. By applying an electrical signal to the first electrode and the second electrode, the light-emitting layer can be driven to emit light. The specific light-emitting principle of the light-emitting device will not be described in detail here.

[0078] In addition, the light-emitting layer of each light-emitting unit can be formed by direct evaporation through a fine mask (FMM), and the light-emitting layer of each light-emitting unit is distributed at intervals and emits light independently to achieve color display. However, due to the limitations of the fine mask manufacturing process, it is difficult to achieve high PPI (pixel density). Therefore, color display can also be achieved by monochromatic light or white light in combination with a color filter, that is, each light-emitting unit shares the same continuous light-emitting layer, the light-emitting layer can emit white light or other monochromatic light, and the color filter layer has multiple filter parts corresponding to the light-emitting units one by one. A filter part and the corresponding light-emitting unit can constitute a sub-pixel, and multiple sub-pixels constitute a pixel. The colors of light that can be transmitted by different filter parts can be different, so that the luminous colors of different sub-pixels can be different. The same pixel includes multiple sub-pixels of different colors. For example, a pixel may include three sub-pixels with luminous colors of red, green, and blue. In this way, color display can be achieved through multiple pixels.

[0079] However, if the light-emitting layer is a continuous whole-layer structure, leakage is likely to occur between a light-emitting unit and the surrounding light-emitting units, resulting in cross-color. Each light-emitting unit may include multiple light-emitting devices connected in series, and each light-emitting device of the same light-emitting unit shares a first electrode and a second electrode. There are multiple light-emitting sublayers between the first electrode and the second electrode, and at least two adjacent light-emitting sublayers can be connected in series through a charge generation layer. For example, when the light-emitting unit of the red filter part in the corresponding color filter layer emits light, due to the influence of leakage, the light-emitting unit of the green filter part in the corresponding color filter layer will also emit light, resulting in a decrease in the purity of the light emission of a single pixel and a decrease in the color gamut of the entire display panel.

[0080] The present disclosure provides a display panel. Figure 1 As shown, the display panel may include a driving backplane BP, a first electrode ANO, a pixel definition layer PDL, a light emitting layer OL, and a second electrode CAT, wherein:

[0081] The first electrode ANO is arranged on a side of the driving backplane BP, and the number of the first electrodes ANO is multiple and distributed at intervals. The pixel definition layer PDL and the first electrode ANO are arranged on the same side of the driving backplane BP. The pixel definition layer PDL is provided with a pixel opening PH exposing each first electrode ANO, and the boundary of the pixel opening PH is located within the boundary of the exposed first electrode ANO. At the same time, the pixel definition layer PDL is also provided with a separation groove SES separating each pixel opening PH, and the side wall of the pixel opening PH is provided with a first truncation groove CU1, and the side wall of the separation groove SES is provided with a second truncation groove CU2; the first truncation groove CU1 is at least partially located on the side of the second truncation groove CU2 away from the driving backplane BP. The light-emitting layer OL covers the pixel definition layer PDL and the first electrode ANO. The second electrode CAT covers the light-emitting layer OL.

[0082] In the display panel of the embodiment of the present disclosure, any first electrode ANO and its corresponding light-emitting layer OL and second electrode CAT can constitute a light-emitting unit LD, and the pixel definition layer PDL can separate each light-emitting unit LD to define the range of each light-emitting unit LD. At the same time, due to the presence of the first truncation groove CU1 and the second truncation groove CU2, at least part of the film layer of the light-emitting layer OL can be disconnected in the first truncation groove CU1 and the second truncation groove CU2, thereby reducing the risk of mutual leakage between adjacent light-emitting units LD and improving cross-color.

[0083] Since the first truncation groove CU1 is at least partially located on the side of the second truncation groove CU2 away from the driving backplane BP, the first truncation groove CU1 is at least partially higher than the second truncation groove CU2, wherein the second truncation groove CU2 can cut off the film layer in the light-emitting layer OL that is closer to the driving backplane BP, and the first truncation groove CU1 can not only cut off the film layer in the light-emitting layer OL that is closer to the driving backplane BP, but also cut off the film layer farther away, so that the risk of mutual leakage of adjacent light-emitting units LD can be further reduced by the first truncation groove CU1 and the second truncation groove CU2, thereby improving cross-color.

[0084] In addition, since the film layer in the light-emitting layer OL that is farther away from the driving backplane BP can be cut off by the second truncation groove CU2 that is closer to the driving backplane BP, there is no need to increase the thickness of the pixel definition layer PDL and the widths of the first truncation groove CU1 and the second truncation groove CU2, the puncture phenomenon caused by the second electrode CAT being greatly reduced at the side walls of the pixel opening PH and the separation groove SES due to the increase in the thickness and width can be avoided, thereby avoiding the problem of excessive voltage drop of the second electrode CAT caused by the second puncture phenomenon.

[0085] The structure of the display panel of the present disclosure to realize the display function is described in detail below:

[0086] The display panel may include a display area and a peripheral area, wherein the peripheral area is located outside the display area and may be arranged around the display area. The driving backplane BP is used to form a driving circuit for driving the light-emitting unit LD to emit light, and the driving circuit may include a pixel circuit and a peripheral circuit, wherein:

[0087] The number of pixel circuits and light-emitting units LD can be multiple, and at least a part of the pixel circuits is located in the display area. The pixel circuit can be a 2T1C, 4T1C or other pixel circuits. As long as it can drive the light-emitting unit LD to emit light, its structure is not specifically limited here. The number of pixel circuits is the same as the number of first electrodes ANO, and is connected to the first electrode ANO in a one-to-one correspondence so as to control each light-emitting unit LD to emit light. Among them, nTmC means that a pixel circuit includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C"). Of course, the same pixel circuit can also drive multiple light-emitting units LD.

[0088] The peripheral circuit is located in the peripheral area and connected to the pixel circuit. The peripheral circuit may include a light emitting control circuit, a gate driving circuit, a source driving circuit, etc. In addition, it may also include a power supply circuit connected to the second electrode CAT for inputting a power supply signal to the second electrode CAT. The peripheral circuit may input a signal to the first electrode ANO and the second electrode CAT through the pixel circuit, thereby causing the light emitting unit LD to emit light.

[0089] In some embodiments of the present disclosure, Figure 1 As shown, the driving backplane BP may include a substrate SU, and the substrate SU may be a silicon substrate. The above-mentioned driving circuit may be formed on the silicon substrate through a semiconductor process. For example, both the pixel circuit and the peripheral circuit may include a plurality of transistors, and a well region WL may be formed in the silicon substrate through a doping process. The well region WL has two doping regions DR distributed at intervals. Take a well region WL as an example: a gate GATE is provided on one side of the driving backplane BP, and the positive projection of the gate GATE on the driving backplane BP is located between the two doping regions DR. The well region WL and the gate GATE may form a transistor, and the doping regions DR of the well region WL are respectively the first pole and the second pole of the transistor, and the well region WL between the two doping regions DR is the channel region of the transistor.

[0090] The driving backplane BP may further include at least one routing layer TL and a planar layer PLN. The routing layer TL is disposed on one side of the substrate SU. The planar layer PLN covers the routing layer TL. At least one routing layer TL is connected to each doping region DR.

[0091] For example: Figure 1 As shown, there are two routing layers TL, and they are located in the flat layer PLN. For example, the routing layer TL includes a first routing layer TL1 and a second routing layer TL2. The first routing layer TL1 is arranged on one side of the substrate SU, and a part of the flat layer PLN is arranged between the first routing layer TL1 and the substrate SU. The second routing layer TL2 is arranged on the side of the first routing layer TL1 away from the substrate SU, and is separated from the first routing layer TL1 by a part of the flat layer PLN, and at least a part of the second routing layer TL2 is connected to the first routing layer TL1.

[0092] Each wiring layer TL can be formed by a sputtering process. The material of the planar layer PLN can be silicon oxide, silicon oxynitride or silicon nitride, and formed layer by layer through multiple deposition and polishing processes, that is, the planar layer PLN can be formed by stacking multiple insulating film layers.

[0093] like Figure 1As shown, each light emitting unit LD array is distributed on one side of the driving backplane BP, for example, each light emitting unit LD is arranged on the surface of the flat layer PLN away from the substrate SU. Each light emitting unit LD may include a first electrode ANO, a second electrode CAT, and a light emitting layer OL located between the first electrode ANO and the second electrode CAT. The first electrode ANO and the second electrode CAT may be connected to the wiring layer TL. A driving signal is applied to the first electrode ANO and a power supply signal is applied to the second electrode CAT through the driving backplane BP, thereby driving the light emitting layer OL to emit light.

[0094] In order to realize color display, each light emitting unit LD can emit light of the same color, and cooperate with the color filter layer located on the side of the second electrode CAT away from the driving backplane BP to realize color display. The embodiment of the present disclosure is explained by taking this color display solution as an example.

[0095] In some embodiments of the present disclosure, Figure 1 As shown, a plurality of light emitting units LD may be formed by the first electrode ANO, the pixel definition layer PDL, the light emitting layer OL and the second electrode CAT, wherein:

[0096] The first electrode ANO is disposed on a side of the driving backplane BP, for example, the first electrode ANO is disposed on a surface of the planar layer PLN away from the substrate SU. Each first electrode ANO is located in the display area and connected to a pixel circuit, and one first electrode ANO is connected to one pixel circuit.

[0097] The first electrode ANO may be a single-layer or multi-layer structure, and its material is not particularly limited. Figure 1 and Figure 3 As shown, in some embodiments of the present disclosure, the first electrode ANO may include a first conductive layer AL1, a second conductive layer AL2 and a first conductive protection layer AL3, wherein:

[0098] The first conductive layer AL1 is provided on the back plate BP, for example, the first conductive layer AL1 is provided on the surface of the flat layer PLN away from the substrate SU. The material of the first conductive layer AL1 adopts conductive materials such as metal or metal oxide, for example, titanium, titanium nitride, etc. The second conductive layer AL2 is provided on the surface of the first conductive layer AL1 away from the driving back plate BP, and the resistivity of the material thereof is lower than that of the first conductive layer AL1. The material of the second conductive layer AL2 can be a conductive material such as metal such as aluminum, silver, or metal oxide.

[0099] like Figure 1 and Figure 3As shown, the first conductive protection layer AL3 covers the surface of the second conductive layer AL2 away from the driving back plate Bp, and at the same time, also covers the side walls of the second conductive layer AL2 and the first conductive layer AL1, that is, the first conductive protection layer AL3 extends from the surface of the second conductive layer AL2 away from the driving back plate BP to the driving back plate BP, thereby covering the entirety of the first conductive layer AL1 and the second conductive layer AL2, and preventing the subsequent process from corroding or otherwise damaging the second conductive layer AL2. The first conductive protection layer AL3 can be made of metal or metal oxide, such as titanium or titanium nitride conductive material, and its material can be the same as or different from that of the first conductive layer AL1.

[0100] Further, such as Figure 1 and Figure 3 As shown, the first electrode ANO may further include a second conductive protection layer AL4, which may cover the first conductive protection layer AL3, and the second conductive protection layer AL4 may be made of transparent conductive materials such as ITO (indium tin oxide) to further prevent corrosion or other damage to the second conductive layer AL2 in subsequent processes.

[0101] like Figure 1 , Figure 3 and Figure 4 As shown, when forming the first conductive layer AL1 to the second conductive protection layer AL4 of the first electrode ANO, the first conductive layer AL1 and the second conductive layer AL2 may be sequentially formed on the driving backplane BP by a photolithography process. In this process, due to the etching of the first conductive layer AL1 and the second conductive layer AL2, a first groove FL1 may be formed on the driving backplane BP, for example, the first groove FL1 is formed on the flat layer PLN. After forming the second conductive layer AL2, the first conductive protection layer AL3 and the second conductive protection layer AL4 may be sequentially formed by a photolithography process. In this process, due to the etching of the first conductive protection layer AL3 and the second conductive protection layer AL4, the bottom of the first groove FL1 may be further etched to form a second groove FL2, so as to realize the patterning of the first conductive protection layer AL3 and the second conductive protection layer AL4, and form the first electrode ANO distributed at intervals. The second groove FL2 is smaller than the bottom surface of the first groove FL1, and the first conductive protection layer AL3 and the second conductive protection layer AL4 both extend to the area on the bottom surface of the first groove FL1 where the second groove FL2 is not set, mainly to ensure that the first conductive protection layer AL3 and the second conductive protection layer AL4 can cover the side walls of the second conductive layer AL2.

[0102] In some embodiments of the present disclosure, Figure 2 and Figure 4 As shown, the width d1 of the first groove FL1 is not less than 0.5 μm and not more than 1.2 μm. For example, the width d1 of the first groove FL1 may be 0.5 μm, 0.8 μm, 1.1 μm, 1.2 μm, etc.

[0103] like Figure 2 and Figure 4 As shown, the width d2 of the second groove FL2 is not less than 0.2 μm and not more than 0.9 μm. For example, the width d2 of the second groove FL2 may be 0.2 μm, 0.5 μm, 0.8 μm, 0.9 μm, etc.

[0104] The width d4 of the separation groove SES may be equal to the width d2 of the second groove FL2. Accordingly, the width d4 of the separation groove SES may also be not less than 0.2 μm and not more than 0.9 μm.

[0105] In some embodiments of the present disclosure, the first electrode ANO may include only a first conductive layer AL1, a second conductive layer AL2 and a first conductive protective layer AL3, and the corrosion resistance of the first conductive protective layer AL3 is higher than that of the conductive material of the second conductive layer AL2. For example, the material of the second conductive layer AL2 is aluminum, and the material of the first conductive protective layer AL3 is indium tin oxide.

[0106] In some embodiments of the present disclosure, the first electrode ANO may include a first conductive layer AL1 to a second conductive protection layer AL4, but the second conductive protection layer AL4 may be stacked on the surface of the second conductive layer AL2 away from the driving backplane BP without covering the side walls of the second conductive layer AL2 and the first conductive layer AL1, and the second conductive protection layer AL4 covers the side walls of the first conductive layer AL1 to the first conductive protection layer AL3.

[0107] like Figure 1 and Figure 2 As shown, the pixel definition layer PDL and the first electrode ANO are disposed on the same surface of the driving backplane BP, for example, the pixel definition layer PDL is located on the surface of the planar layer PLN away from the substrate SU, and the pixel definition layer PDL exposes each first electrode ANO. Specifically, the pixel definition layer PDL may be provided with a plurality of pixel openings PH exposing each first electrode ANO.

[0108] The positive projection of any pixel opening PH on the driving backplane BP can be located within the exposed first electrode ANO, that is, the pixel opening PH is not larger than the exposed first electrode ANO. For example, the boundary of the pixel opening PH is located on the inner side of the boundary of the exposed first electrode ANO, that is, the area of ​​the pixel opening PH is smaller than the area of ​​the exposed first electrode ANO, so that the pixel definition layer PDL covers the edge of the first electrode ANO.

[0109] like Fig.13 As shown, the shape of the pixel opening PH can be a polygon such as a rectangle, a pentagon, a hexagon, etc., but it is not necessarily a regular polygon. The shape of the pixel opening PH can also be other shapes such as an ellipse, which is not particularly limited here.

[0110] like Figure 1 As shown, the light-emitting layer OL covers the pixel definition layer PDL and the first electrode ANO, and the area where the light-emitting layer OL and the first electrode ANO are stacked is used to form a light-emitting unit LD, that is, each light-emitting unit LD can share the same light-emitting layer OL, and the portion of the light-emitting layer OL stacked on different first electrodes ANO belongs to different light-emitting units LD. In addition, since each light-emitting unit LD shares the light-emitting layer OL, the light-emitting colors of different light-emitting units LD are the same.

[0111] In some embodiments of the present disclosure, Figure 1 , Fig.11 and Fig.12 As shown, the light-emitting unit LD may include a plurality of light-emitting devices connected in series, each of which includes a first electrode ANO, a second electrode CAT, and a plurality of light-emitting sublayers OLP between the first electrode ANO and the second electrode CAT, and the light-emitting devices of the same light-emitting unit LD may share the same first electrode ANO and the same second electrode CAT, that is, the same light-emitting unit LD may have only one first electrode ANO and one second electrode CAT.

[0112] For example: Figure 1 , Fig.11 and Fig.12 As shown, the light-emitting layer OL may include a hole injection layer HIL1, a plurality of light-emitting sublayers OLP and an electron injection layer EIL, wherein the light-emitting sublayer OLP is disposed between the hole injection layer HIL1 and the electron injection layer EIL, and is connected in series in a direction away from the driving backplane BP, wherein two adjacent light-emitting sublayers OLP may be connected in series through a charge generation layer CGL located therebetween. When an electrical signal is applied to the first electrode ANO and the second electrode CAT, each light-emitting sublayer OLP may emit light, and different light-emitting sublayers OLP may be used to emit light of different colors.

[0113] Further, such as Fig.11 and Fig.12 As shown, any light-emitting sublayer OLP may at least include a hole transport layer HTL, a light-emitting material layer EML and an electron transport layer ETL distributed in a direction away from the driving backplane BP. The specific light-emitting principle will not be described in detail here, wherein:

[0114] The number of the hole injection layer HIL, the hole transport layer HTL, the electron transport layer ETL and the electron injection layer EIL is not particularly limited, and adjacent light-emitting sublayers OLP may share one or more of the hole injection layer HIL, the hole transport layer HTL, the electron transport layer ETL and the electron injection layer EIL. At the same time, a charge generation layer CGL may be provided between at least two adjacent light-emitting sublayers OLP, so that the two light-emitting sublayers OLP are connected in series.

[0115] In some embodiments of the present disclosure, Fig.11 As shown, the light-emitting layer OL may include two light-emitting sublayers OLP of different colors, namely, a first light-emitting sublayer emitting red and green light at the same time and a second light-emitting sublayer emitting blue light. The first light-emitting sublayer and the second light-emitting sublayer may emit light at the same time, so that the light-emitting layer OL emits white light. The first light-emitting sublayer has two light-emitting material layers EML, namely, a light-emitting material layer R-EML emitting red light and a light-emitting material layer G-EML emitting green light. Specifically, the first light-emitting sublayer may include a hole transport layer HTL1, a light-emitting material layer R-EML, a light-emitting material layer G-EML, and an electron transport layer ETL2 sequentially stacked on the hole injection layer HIL1 in a direction away from the driving backplane BP.

[0116] The surface of the first light-emitting sublayer away from the driving backplane BP may be provided with a charge generation layer CGL. The second light-emitting sublayer is provided on the surface of the charge generation layer CGL away from the driving backplane BP, so that the first light-emitting sublayer and the second light-emitting sublayer are connected in series. The second light-emitting sublayer includes a hole injection layer HIL2, a hole transport layer HTL2, a hole transport layer HTL3, a blue light-emitting material layer B-EML, a hole blocking layer HBL and an electron transport layer ETL2, which are sequentially stacked on the side of the charge generation layer CGL away from the driving backplane BP in the direction away from the driving backplane BP. The electron injection layer EIL is provided on the surface of the electron transport layer ETL2 away from the driving backplane BP. The second electrode CAT is provided on the surface of the electron injection layer EIL away from the driving backplane BP.

[0117] In other embodiments of the present disclosure, Fig.12 As shown, the number of light-emitting sublayers OLP can be three, and they are stacked between the hole injection layer HIL1 and the electron injection layer EIL in the direction away from the driving backplane BP. Each light-emitting sublayer OLP can only include a hole transport layer HTL, a light-emitting material layer EML and an electron transport layer ETL stacked in the direction away from the driving backplane BP.

[0118] The luminescent material layer EML of the three luminescent sublayers OPL may include two blue luminescent material layers B-EML and one yellow luminescent Y-EML. By selecting the color and material of the filter part of the color filter layer, color display may also be achieved. For example:

[0119] The three light-emitting sublayers OLP are respectively the first light-emitting sublayer, the second light-emitting sublayer and the third light-emitting sublayer, and the first light-emitting sublayer, the second light-emitting sublayer and the third light-emitting sublayer are sequentially distributed in a direction away from the driving backplane BP, wherein:

[0120] The first light-emitting sublayer includes a hole transport layer HTL1, a light-emitting material layer B-EML and an electron transport layer ETL1; the second light-emitting sublayer includes a hole transport layer HTL2, a light-emitting material layer Y-EML and an electron transport layer ETL2; the third light-emitting sublayer includes a hole transport layer HTL3, a light-emitting material layer B-EML and an electron transport layer ETL3.

[0121] There are two charge generation layers CGL, one charge generation layer CGL is disposed between two adjacent light-emitting sublayers OLP, that is, one charge generation layer CGL is disposed between the first light-emitting sublayer and the second light-emitting sublayer, and another charge generation layer CGL is disposed between the second light-emitting sublayer and the third light-emitting sublayer.

[0122] Of course, in other embodiments of the present disclosure, the light-emitting material layers EML of the three light-emitting sublayers OPL may emit red light, blue light and green light respectively, and the colors are not particularly limited herein.

[0123] In some embodiments of the present disclosure, for the case of three light-emitting sublayers OLP, in two first truncated grooves CU1 of different widths in the same pixel opening PH, the width difference between the two first truncated grooves CU1 is 0.8 to 1.2 times the width difference between the first truncated groove CU1 and the second truncated groove CU2. Figure 6 As shown, the width difference between the first truncated groove CU11 and the second truncated groove CU2 is a first width difference, the width difference between the first truncated groove CU12 and the second truncated groove CU2 is a second width difference, and the second width difference is 0.8 to 1.2 times the first width difference.

[0124] In addition, in some embodiments of the present disclosure, the widths of the second truncation grooves CU2 on the two side walls of the separation groove SES may also be different. The second truncation grooves CU2 of different widths may be located on the same side wall and distributed around the first electrode ANO. They may be connected or staggered, so that the second truncation grooves CU2 of different widths may be set on the same side wall; or, the second truncation grooves CU2 of different widths may also be located on the two side walls of the separation groove SES, respectively, so that the widths of the second truncation grooves CU2 on the same side wall are the same.

[0125] By setting the second truncation groove CU2 with a larger width, two charge generation layers CGL and the hole injection layer HIL1 in the three-layer light-emitting sublayer solution can be truncated, thereby improving the anti-crosstalk effect.

[0126] It should be noted that, in the same display panel, there may be multiple first truncation grooves CU1 with different widths, and there may also be multiple second truncation grooves CU2 with different widths. As long as the hole injection layer HIL1 and the charge generation layer CGL can be truncated to prevent crosstalk, the combination of the first truncation grooves CU1 and the second truncation grooves CU2 with different widths can also reduce the risk of overlap between the charge generation layer CGL and the first electrode ANO, which is beneficial to ensure the normal light emission of the light-emitting unit LD.

[0127] The above-mentioned light-emitting layer OL structure is only an example and does not constitute a limitation on its film layer. The number of light-emitting sublayers OLP can be greater, or only one light-emitting sublayer OLP can be included, as long as it can cooperate with the color filter layer to achieve color display.

[0128] like Figure 1 As shown, the second electrode CAT covers the light-emitting layer OL, and the orthographic projection of the second electrode CAT on the driving backplane BP can cover the display area and extend into the peripheral area. Each light-emitting unit LD can share the same second electrode CAT. The light-emitting layer OL can be controlled to emit light by controlling the voltage of the power signal input to the second electrode CAT and the driving signal input to the first electrode ANO.

[0129] like Figure 1 As shown, the display panel may also include a color filter layer, which may be arranged on the side of the second electrode CAT away from the driving backplane BP, and includes a plurality of filter parts, each first electrode ANO and each filter part are arranged one by one in a direction perpendicular to the driving backplane BP, that is, the positive projection of a filter part on the driving backplane BP at least partially overlaps with a first electrode ANO. Each filter part includes at least three color filter parts, for example, a filter part that can transmit red light, a filter part that can transmit green light, and a filter part that can transmit blue light. After the light emitted by each light-emitting unit LD is filtered by the filter part, monochromatic light of different colors can be obtained, thereby realizing color display, wherein a filter part and its corresponding light-emitting unit LD can constitute a sub-pixel, and the color of light emitted by any sub-pixel is the color of the light transmitted by its filter part, and multiple sub-pixels can constitute a pixel, and the light emission colors of each sub-pixel of the same pixel are different.

[0130] The color filter layer may further include a light shielding portion separating the filter portion, the light shielding portion is light-proof and shields the area between the two light-emitting units LD. The filter portion may be directly arranged with a light shielding material and spaced from the filter portion; or, in some embodiments of the present disclosure, adjacent filter portions may be stacked in the area corresponding to the area between two adjacent light-emitting units LD, and the colors of the light transmitted by the two light-emitting units are different, so that the stacked area is light-proof.

[0131] In addition, in some embodiments of the present disclosure, on the basis of the light-emitting layer OL emitting white light, in order to improve the brightness of the picture, the color filter layer may further include a transparent portion. In a direction perpendicular to the substrate, a transparent portion may be arranged opposite to a light-emitting unit LD, so that the color filter layer can also directly transmit the light emitted by the light-emitting layer OL, such as white light, and the brightness can be increased by the white light.

[0132] In order to improve light extraction efficiency, a light extraction layer may be covered on the side of the second electrode CAT away from the driving backplane BP to improve brightness. Furthermore, the light extraction layer may directly cover the surface of the second electrode CAT away from the driving backplane BP.

[0133] In order to facilitate the connection of the second electrode CAT with the driving circuit, in some embodiments of the present disclosure, the first electrode layer FE further includes an adapter ring, the orthographic projection of the adapter ring on the driving backplane BP is located in the peripheral area, the adapter ring can be connected to the peripheral circuit, and surrounds the outside of the display area. The second electrode CAT can be connected to the adapter ring, so that the second electrode CAT can be connected to the peripheral circuit through the adapter ring, so that the peripheral circuit applies a driving signal to the second electrode CAT. The pattern of the adapter ring can be the same as the pattern of the first electrode ANO in the display area, so as to improve the uniformity of the pattern of the first electrode layer FE.

[0134] In some embodiments of the present disclosure, Figure 1 As shown, the display panel of the present disclosure may further include an encapsulation layer, which may be provided on the side of the second electrode CAT away from the driving backplane BP, and between the color film layer and the second electrode CAT, for blocking corrosion from external water and oxygen. The encapsulation layer may be a single-layer or multi-layer structure. For example, the encapsulation layer may include a first encapsulation sublayer, a second encapsulation sublayer, and a third encapsulation sublayer stacked in sequence in a direction away from the driving backplane BP, wherein the materials of the first encapsulation sublayer and the second encapsulation sublayer may be inorganic insulating materials such as silicon nitride and silicon oxide, and the second encapsulation sublayer may be formed by an ALD (Atomic layer deposition) process; the material of the third encapsulation sublayer may be an organic material, which may be formed by an MLD (Molecular Layer Deposition) process. Of course, the encapsulation layer may also adopt other structures, and the structure of the encapsulation layer is not particularly limited here.

[0135] In addition, the display panel may further include a transparent cover plate, which may cover the side of the encapsulation layer away from the driving backplane BP. The transparent cover plate may be a single-layer or multi-layer structure, and its material is not particularly limited herein.

[0136] Based on the above analysis of related technologies, since each light-emitting unit LD shares the light-emitting layer OL, the carriers (e.g., holes) of one light-emitting unit LD may move to other light-emitting units LD, especially to adjacent light-emitting units LD, through the charge generation layer CGL, the hole injection layer near the driving backplane BP and other film layers, i.e., leakage occurs, affecting the purity of light emission and causing cross-color. For this reason, if Figure 1 and Figure 2 As shown, a separation groove SES can be set in the pixel definition layer PDL, a first truncation groove CU1 can be set on the side wall of the pixel opening PH, and a second truncation groove CU2 can be opened on the side wall of the separation groove SES. The light-emitting layer OL can be restricted by the first truncation groove CU1 and the second truncation groove CU2, so that at least part of the film layer of the light-emitting layer OL is difficult to be continuous in the first truncation groove CU1 and the second truncation groove CU2, and is thus disconnected, thereby preventing carriers from moving between the light-emitting units LD, thereby avoiding cross-color caused by leakage.

[0137] The sidewall of the separation groove SES is a slope surface expanding in a direction away from the driving back plate BP.

[0138] like Figure 1 and Figure 2 As shown, since there are multiple film layers that may leak electricity in the light-emitting layer OL, in order to ensure that the first truncation groove CU1 and the second truncation groove CU2 can prevent leakage, the first truncation groove CU1 and the second truncation groove CU2 can be staggered in a direction perpendicular to the driving back plate BP, so that the second truncation groove CU2 is at least partially located on the side of the first truncation groove CU1 close to the driving back plate BP. Relative to the driving back plate BP, the position of the first truncation groove CU1 is higher, even if the light-emitting layer OL has multiple film layers, it can at least cut off the hole injection layer HIL1 closest to the driving back plate BP. At the same time, the position of the second truncation groove CU2 is lower, and the depth of the depression required for the light-emitting layer OL is greater, which is conducive to cutting off the charge generation layer CGL that is farther away from the driving back plate BP than the hole injection layer HIL1. Of course, at this time, the hole injection layer HIL1 can also be cut off. Therefore, the first truncation groove CU1 and the second truncation groove CU2 can be used to cut off multiple film layers, reduce the risk of leakage, and improve cross-color.

[0139] The following is a detailed description of the solution to the color crossover problem of the display panel disclosed in the present invention:

[0140] like Figure 1 and Figure 2 As shown, in order to achieve the above purpose, the pixel definition layer PDL may include at least an etch stop layer PL1, a first definition layer PL2, and a second definition layer PL3 stacked in sequence in a direction away from the driving back plate BP, and the separation groove SES penetrates the second definition layer PL3 and the first definition layer PL2, and exposes the etch stop layer PL1, wherein:

[0141] The etch barrier layer PL1 is partially stacked on the surface of the first electrode ANO away from the driving backplane BP, and is partially located outside the first electrode ANO. When the separation groove SES is formed by an etching process, the etch barrier layer PL1 can limit the depth of the separation groove SES and improve the uniformity of the depth of the separation groove SES.

[0142] In some embodiments of the present disclosure, Figure 1 and Figure 2 As shown, the etching stop layer PL1 may include a buffer layer PL11 and a stop layer PL12, wherein:

[0143] The buffer layer PL11 is partially stacked on the surface of the first electrode ANO away from the driving back plate BP, and is partially located outside the first electrode ANO. The buffer layer PL11 can be inorganic insulating materials such as silicon oxide and silicon nitride, or other insulating materials.

[0144] The barrier layer PL12 may be disposed on the surface of the buffer layer PL11 away from the driving backplane BP, the material of the barrier layer PL12 is different from the material of the first definition layer PL2 and the second definition layer PL3, and under at least one etching process, the etching degree of the first definition layer PL2 and the second definition layer PL3 is higher than the etching degree of the barrier layer PL12. The material of the barrier layer PL12 may include aluminum oxide, and of course, other materials may also be used.

[0145] In other embodiments of the present disclosure, the etch stop layer PL1 may adopt a single-layer structure, which may be a conductive material such as metal or metal oxide, but is spaced apart from the first electrode ANO. Alternatively, the etch stop layer PL1 may also adopt three or more layers as long as it can block etching when forming the separation groove SES.

[0146] The first definition layer PL2 is disposed on the surface of the etching stop layer PL1 away from the driving back plate BP, and the second definition layer PL3 is disposed on the surface of the first definition layer PL2 away from the driving back plate BP. The first definition layer PL2 and the second definition layer PL3 are made of different materials, for example, the material of the first definition layer PL2 is silicon nitride, and the material of the second definition layer PL3 can be silicon oxide. The same etching process can be used to etch the two materials to different degrees so that the second definition layer PL3 extends out of the edge of the first definition layer PL2, thereby forming the first truncation groove CU1 and the second truncation groove CU2 in the first definition layer PL2.

[0147] like Figure 2As shown, both the first truncated groove CU1 and the second truncated groove CU2 have two side walls distributed in a direction perpendicular to the driving back plate BP, the width W1 of the first truncated groove CU1 is the distance between its two side walls, and the width W2 of the second truncated groove CU2 is the distance between its two side walls. For any one of the first truncated groove CU1 and the second truncated groove CU2, one side wall is the surface of the second definition layer PL3 close to the driving back plate BP, and the other side wall is the surface of the etching barrier layer PL1 away from the driving back plate. The width of the first truncated groove CU1 and the second truncated groove CU2 can be limited by the etching barrier layer PL1 which is more difficult to be etched than the first definition layer PL2, that is, the distance between the two side walls is limited, and the uniformity of the width of the first truncated groove CU1 and the second truncated groove CU2 is improved, and the situation that the width of different first truncated grooves CU1 has a large deviation and the width of different second truncated grooves CU2 has a large deviation is avoided. Accordingly, this is conducive to improving the uniformity of the surface of the driving back plate BP. Since the pixel definition layer PDL itself includes the etching stop layer PL1, there is no need to reserve a space between adjacent first electrodes ANO for setting the etching stop layer PL1, which is conducive to shortening the distance between adjacent first electrodes ANO, that is, shortening the spacing between light-emitting units LD. When the size of the display panel remains unchanged, it is conducive to setting more light-emitting units LD, thereby improving the resolution. According to experimental verification, the distance can be reduced to less than 1μm, while the distance in existing display panels is usually more than 1μm.

[0148] In some embodiments of the present disclosure, due to the presence of the separation groove SES, the pixel definition layer PDL has a large step difference at the separation groove SES, and the light-emitting layer OL is highly concentrated in the separation groove SES, so that the second truncation groove CU2 is subjected to greater pressure than the first truncation groove CU1, thereby increasing the risk of collapse. If collapse occurs, it is difficult to play a truncation role. To this end, the present disclosure provides a variety of means to solve this problem, for example:

[0149] In one embodiment, if Figure 8 As shown, the width of at least part of the second truncation groove CU2 is greater than the width of the first truncation groove CU1. Of course, the width of any area of ​​the second truncation groove CU2 can be made greater than the first truncation groove CU1 to leave a margin for potential collapse. Even if the second truncation groove CU2 collapses to a certain extent, it can still play a truncation role.

[0150] In one embodiment, if Figure 2 and 9As shown, the side walls of the first truncated groove CU1 and the second truncated groove CU2 away from the driving back plate BP can be regarded as cantilevers relative to their respective bottom surfaces. The longer the cantilever, the longer the force arm, and the greater the risk of collapse. In order to solve the problem of collapse, the depth d5 ​​of the second truncated groove CU2 can be made smaller than the depth d7 of the first truncated groove CU1. The depth can be the maximum distance between the end of the side wall of the truncated groove CU2 away from its bottom surface in the direction parallel to the driving back plate BP and its bottom surface, thereby shortening the cantilever of the second truncated groove CU2 and reducing the risk of collapse.

[0151] In one embodiment, if Fig.10 As shown, the angle between the side wall of the second truncation groove CU2 away from the driving back plate BP and the surface of the driving back plate BP provided with the first electrode ANO can be greater than the angle between the side wall of the first truncation groove CU1 away from the driving back plate BP and the surface of the driving back plate BP provided with the first electrode ANO. In other words, relative to the side wall of the first truncation groove CU1 away from the driving back plate BP, the side wall of the second truncation groove CU2 away from the driving back plate BP is tilted in the direction away from the driving back plate BP, so as to avoid the collapse of the second truncation groove CU2, and even if there is a collapse, there will be no contact between the two side walls, thereby ensuring the truncation effect.

[0152] It should be noted that the above-mentioned implementation methods for solving the collapse problem can be applied individually or one or more of them can be applied simultaneously. For example, they will not be described in detail here.

[0153] In some embodiments of the present disclosure, Figure 2 As shown, the length d7 of the sidewalls of the first truncated groove CU1 away from the driving back plate BP is not less than 0.03 μm and not more than 0.05 μm, for example, 0.03 μm, 0.04 μm, 0.05 μm. The length d7 can be regarded as the depth of the first truncated groove CU1.

[0154] In some embodiments of the present disclosure, Figure 2 As shown, the length d5 ​​of the sidewalls of the second truncated groove CU2 away from the driving back plate BP is not less than 0.07 μm and not more than 0.1 μm, for example, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm. The length d5 ​​can be regarded as the depth of the second truncated groove CU2.

[0155] In some embodiments of the present disclosure, the second truncated groove CU2 may be located on a side of the first truncated groove CU1 close to the driving back plate BP. The width difference between the first truncated groove CU1 and the second truncated groove CU2 is smaller than the width of one of the first truncated groove CU1 and the second truncated groove CU2.

[0156] It should be noted that the width difference between A and B in this article is: the absolute value of the difference between the width of A and the width of B. For example, the width difference between the first truncation groove CU1 and the second truncation groove CU2 is the absolute value of the difference between the two widths, so the width difference must be greater than or equal to 0.

[0157] In some embodiments of the present disclosure, Figure 5 As shown, the bottom surface of the first truncation groove CU1 is a slope whose depth decreases in the direction away from the driving back plate BP. The slope of the slope is α, which may refer to the angle between the slope and the surface on which it is located.

[0158] The bottom surface of the second truncation groove CU2 is a slope whose depth decreases in the direction away from the driving back plate BP, and the slope of the slope is β. The slope β may be smaller than the slope α, which may refer to the angle between the slope and the surface on which it is located. The slope β may be smaller than the slope α.

[0159] In some embodiments of the present disclosure, Figure 1 and Figure 2 As shown, the pixel definition layer PDL may further include a filling layer PL4, which may be arranged on the same side of the driving backplane BP as the first electrode, for example, both are arranged on the flat layer PLN. The filling layer PL4 may separate each first electrode ANO and contact the side wall of the first electrode ANO. The filling layer PL4 may be regarded as a film layer having a plurality of through holes, and each first electrode ANO may be arranged in each through hole in a one-to-one correspondence. At the same time, part of the etching stop layer PL1 is stacked on the surface of the filling layer PL4 away from the driving backplane BP, and part of it is located on the surface of the first electrode ANO away from the driving backplane BP. The filling layer PL4 may also fill the first groove FL1 and the second groove FL2. The material of the filling layer PL4 may be silicon oxide, and of course, it may also be other insulating materials such as silicon nitride.

[0160] In some embodiments of the present disclosure, Figure 1 As shown, for the first electrode ANO including the first conductive layer AL1 to the second conductive protection layer AL4, the thickness of the etch barrier layer PL1 may be greater than the thickness of any layer of the first conductive layer AL1 to the second conductive protection layer AL4, but less than the sum of the thicknesses of the first conductive layer AL1 to the second conductive protection layer AL4.

[0161] In some embodiments of the present disclosure, Figure 1 and Figure 2 As shown, the surface of the filling layer PL4 away from the driving back plate BP is located on the side of the surface of the first electrode ANO away from the driving back plate BP close to the driving back plate BP, so that the etching stop layer PL1 and the first definition layer PL2 and the second definition layer PL3 thereon can be recessed at the filling layer PL4.

[0162] like Figure 2As shown, the pixel definition layer PDL may include an edge portion PE, a middle portion PM and a connection portion PS, wherein the edge portion PE is located on the surface of the first electrode ANO away from the driving backplane BP, and the edge portion PE includes an etching stop layer PL1, a first definition layer PL2 and a second definition layer PL3. The pixel opening PH is located in the edge portion PE.

[0163] The middle portion PM is located between two adjacent first electrodes ANO, and includes a filling layer PL4 to a second definition layer PL3. The orthographic projection of the middle portion PM on the driving backplane BP does not overlap with the first electrode ANO.

[0164] The connection part PS connects the edge part PE and the middle part PM. Since the etching stop layer PL1 and the first definition layer PL2 and the second definition layer PL3 thereon are recessed in the filling layer PL4, the middle part PM needs the connection part PS to extend to the surface of the first electrode ANO away from the driving back plate BP to obtain the edge part PE. The separation groove SES can be opened in the middle part PM.

[0165] The slope of the connection portion PS is smaller than the slopes of the bottom surface of the first dividing groove CU1 and the bottom surface of the second dividing groove CU2.

[0166] Of course, in other embodiments of the present disclosure, the surface of the filling layer PL4 away from the driving backplane BP can also be located in the same plane as the surface of the first electrode ANO away from the driving backplane BP, filling the space between adjacent first electrodes ANO, and the etching blocking layer PL1 extends along the plane.

[0167] In some embodiments of the present disclosure, the sidewall of at least one pixel opening PH is provided with a plurality of first truncated grooves CU1 distributed along the circumferential direction, and adjacent first truncated grooves CU1 may be connected or staggered, which is not particularly limited herein. At least two first truncated grooves CU1 of the same pixel opening PH have different widths, and the first truncated groove CU1 with a larger width may truncate a film layer in the light-emitting layer OL that is farther from the driving backplane BP.

[0168] like Figure 6 As shown, in the first embodiment of the present disclosure, at least one pixel opening PH has a first truncation groove CU11 and a first truncation groove CU12, the width W12 of the first truncation groove CU12 is greater than the width W11 of the first truncation groove CU11, and the width W11 of the first truncation groove CU11 is greater than the width W2 of the second truncation groove CU2.

[0169] like Figure 7As shown, in the second embodiment of the present disclosure, at least one pixel opening PH has a first truncation groove CU11 and a first truncation groove CU12, the width W12 of the first truncation groove CU12 is greater than the width W11 of the first truncation groove CU11, and the width W11 of the first truncation groove CU11 is equal to the width W2 of the second truncation groove CU2. At the same time, at least one pixel opening PH has a first truncation groove CU11 and a first truncation groove CU13, and the width W13 of the first truncation groove CU13 is greater than the width W11 of the first truncation groove CU11.

[0170] In some embodiments of the present disclosure, the number of light-emitting sublayers OLP is three, and the number of charge generation layers CGL is two. In combination with the first embodiment and the second embodiment described above, the hole injection layer HIL1 can be cut off by the first truncation groove CU11, while the charge generation layer CGL can be extended continuously. The first truncation groove CU12 can cut off the hole injection layer HIL1 and two charge generation layers CGL, while the other charge generation layer CGL can be extended continuously. The second truncation groove CU2 can cut off the hole injection layer HIL1 and the charge generation layer CGL closer to the driving backplane BP.

[0171] Therefore, on the basis of preventing the crosstalk problem by cutting off the hole injection layer HIL1 and one of the two charge generation layers CGL, the position where the hole injection layer HIL1 and the two charge generation layers CGL are cut off at the same time can be reduced, and the cut-off charge generation layer CGL can be prevented from extending to the driving backplane BP and contacting the first electrode ANO, thereby reducing the risk of internal short circuit in the light-emitting unit LD.

[0172] Further, in two first truncation grooves CU1 with different widths in the same pixel opening PH, the width of one first truncation groove CU1 is 0.8 to 1.2 times the width of the other first truncation groove CU1. Figure 6 and 7 As shown, the width of the first truncation groove CU12 is 0.8 to 1.2 times the width W11 of the first truncation groove CU13 , and the width W13 of the first truncation groove CU13 is 0.8 to 1.2 times the width W11 of the first truncation groove CU11 .

[0173] In some embodiments of the present disclosure, there are two light-emitting sublayers OLP and one charge generation layer CGL. The structure is as described above in the embodiment of two light-emitting sublayers OLP, and the light-emitting sublayer OLP farther from the driving backplane BP includes a blue light-emitting material layer B-EML.

[0174] The distance between the blue light-emitting material layer B-EML and the charge generation layer CGL in the pixel opening PH is greater than the distance in the pixel definition layer PDL, so that the light-emitting layer OL in the pixel opening PH can emit light normally, while the pixel definition layer PDL does not need to emit light.

[0175] The inventors have found that after the hole injection layer HIL1 of the light emitting layer OL is cut off at the first cut-off groove CU1, if the charge generation layer CGL is not cut off, it may bend toward the first electrode ANO and may eventually directly overlap with the first electrode ANO, causing a short circuit. Figure 2 As shown, in some embodiments of the present disclosure, the pixel opening PH includes a first segment PH1 and a second segment PH2 distributed in a direction perpendicular to the driving backplane BP, the first segment PH1 is located in the etching stop layer PL1, the second segment PH2 is located in the second definition layer PL3, and the first truncation groove CU1 is located between the first segment PH1 and the second segment PH2. The boundary of the orthographic projection of the second segment PH2 on the driving backplane BP surrounds the boundary of the orthographic projection of the first segment PH1 on the driving backplane BH, that is, the range of the etching stop layer PL1 extending to the first electrode ANO is greater than the range of the second definition layer PL3 extending to the first electrode ANO, even if the charge generation layer CGL bends toward the first electrode ANO, it is overlapped with the etching stop layer PL1, and the etching stop layer PL1 is insulated from the first electrode ANO, so that the charge generation layer CGL and the first electrode ANO will not be short-circuited.

[0176] Furthermore, in some embodiments of the present disclosure, the distance d8 between the boundary of the orthographic projection of the second segment PH2 on the driving backplane BH and the boundary of the orthographic projection of the first segment PH1 on the driving backplane BP is not greater than 0.2μm and not less than 0.06μm, for example, 0.06μm, 0.08μm, 0.1μm, 0.2μm, etc.

[0177] In some embodiments of the present disclosure, Figure 2 As shown, the distance d3 between two adjacent pixel openings PH located in the first segment PH1 is not greater than 1.9 μm and not less than 1.1 μm, for example, 1.1 μm, 1.4 μm, 1.7 μm, 1.9 μm, etc.

[0178] In some embodiments of the present disclosure, Figure 2 As shown, the distance d6 between two adjacent pixel openings PH located in the second segment PH2 is not greater than 1.6 μm and not less than 0.9 μm, for example, 0.9 μm, 1.1 μm, 1.3 μm, 1.5 μm, or 1.6 μm.

[0179] In some embodiments of the present disclosure, the interval d6 between two adjacent pixel openings PH and the width d4 of the separation groove SES satisfy the following relationship:

[0180] (d6-d4) / 2>d4;

[0181] A half of the difference between the interval d6 between two adjacent pixel openings PH and the width d4 of the separation groove SES is greater than the width d4 of the separation groove SES.

[0182] like Figure 1 As shown, based on the morphology of the pixel definition layer PDL and the light emitting layer OL, the second electrode CAT may form a flat portion CATp in the region corresponding to the first electrode ANO, and a recessed portion CATg in the region corresponding to the separation groove SES, and the recessed portion CATg and the flat portion CATp may be smoothly connected by the transition portion CATi, thereby avoiding sharp edges and corners of the second electrode CAT. Due to the filling of the separation groove SES by the light emitting layer OL, the depth of the recessed portion CATg of the second electrode CAT is less than the depth of the separation groove SES.

[0183] The present disclosure also provides a display device, which may include a display panel of any of the above embodiments. The specific structure and beneficial effects of the display panel have been described in detail in the above embodiments of the display panel, and will not be described in detail here. The display device of the present disclosure can be used in electronic devices with image display functions such as watches, bracelets, mobile phones, and tablet computers, which will not be listed one by one here.

[0184] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising: Driver backplane; A plurality of first electrodes are arranged in an array on a side surface of the driving back plate; A pixel definition layer, which is disposed on the same side of the driving backplane as the first electrode and is provided with a pixel opening for exposing each of the first electrodes and a separation groove between two adjacent pixel openings, wherein the bottom of the separation groove includes a first flat area; a light-emitting layer, covering the pixel definition layer and the first electrode; The second electrode covers the light-emitting layer; the second electrode includes a recessed portion at a position corresponding to the first flat area, and the recessed portion includes a second flat area; and the width of the second flat area is smaller than that of the first flat area.

2. The display panel according to claim 1, wherein: The pixel definition layer comprises: The filling layer is disposed on the same side of the driving back plate as the first electrodes and separates the first electrodes.

3. The display panel according to claim 2, wherein: The width of the filling layer is greater than the width of the first flat area.

4. The display panel according to claim 2, wherein: The width of the filling layer is greater than the width of the second flat area.

5. The display panel according to claim 1, wherein: The second electrode further includes a flat portion and a transition portion, the flat portion corresponds to the first electrode, and the recessed portion and the flat portion are smoothly connected via the transition portion.

6. The display panel according to claim 5, wherein: The transition portion protrudes toward a side of the recessed portion and the flat portion away from the driving back plate.

7. The display panel according to claim 5, wherein: The width of the transition portion is greater than the width of the recessed portion.

8. The display panel according to claim 1, wherein: The separation groove does not overlap with the first electrode.

9. The display panel according to claim 2, wherein: The pixel definition layer further comprises an etching stop layer, a first definition layer and a second definition layer sequentially stacked in a direction away from the driving backplane; The pixel opening penetrates the etch stop layer, the first definition layer and the second definition layer; the separation groove penetrates the first definition layer and the second definition layer and exposes the etch stop layer; A portion of the etching stop layer is stacked on a surface of the filling layer away from the driving back plate.

10. The display panel according to claim 9, wherein: The etch stop layer comprises: A buffer layer, at least partially disposed on a surface of the first electrode away from the driving backplane; The barrier layer is stacked on the surface of the buffer layer away from the driving back plate; and the first definition layer is stacked on the surface of the barrier layer away from the driving back plate.

11. The display panel according to claim 9, wherein: The surface of the filling layer away from the driving back plate is located on a side of the surface of the first electrode away from the driving back plate close to the driving back plate; The pixel definition layer includes an edge portion, a middle portion and a connection portion. The edge portion is located on a surface of the first electrode away from the driving backplane; the middle portion is located between two adjacent first electrodes; and the connection portion connects the edge portion and the middle portion.

12. The display panel according to claim 11, wherein: The side wall of the separation groove is a slope surface expanding in a direction away from the driving back plate.

13. The display panel according to claim 9, wherein: The boundary of the pixel opening is located within the boundary of the exposed first electrode; the side wall of the pixel opening is provided with a first truncation groove, and the side wall of the separation groove is provided with a second truncation groove; the first truncation groove is at least partially located on the side of the second truncation groove away from the driving backplane.

14. The display panel according to claim 13, wherein: The first truncation groove and the second truncation groove are located in the first definition layer.

15. The display panel according to claim 13, wherein: The bottom surface of the first truncation groove is a slope surface whose depth decreases in a direction away from the driving back plate; The bottom surface of the second truncation groove is a slope surface whose depth decreases in a direction away from the driving back plate.

16. The display panel according to claim 13, wherein: The orthographic projection of the first truncation groove on the driving backplane is located within the orthographic projection of the first electrode on the driving backplane.

17. The display panel according to claim 13, wherein: The width of at least a portion of the second truncation groove is greater than the width of the first truncation groove.

18. The display panel according to claim 13, wherein: The depth of the second truncation groove is smaller than the depth of the first truncation groove.

19. The display panel according to claim 13, wherein: The angle between the side wall of the second truncation groove away from the driving back plate and the surface of the driving back plate where the first electrode is provided is greater than the angle between the side wall of the first truncation groove away from the driving back plate and the surface of the driving back plate where the first electrode is provided.

20. The display panel according to claim 13, wherein: The difference in width between the first truncated groove and the second truncated groove is smaller than the width of one of the first truncated groove and the second truncated groove.

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