Display panel and display device

Abstract

The invention relates to a display panel and a display device, the display panel comprises a substrate, a first fan-out wire and a partition structure, the substrate is provided with a display area and a non-display area, the non-display area is internally provided with a first fan-out area, the display area is internally provided with a second fan-out area close to the non-display area, and the display area is internally provided with a signal wire; the first fan-out wire is arranged on the substrate and located in the first fan-out area. The partition structures are arranged on the substrate and used for partitioning the adjacent light-emitting units; wherein at least part of the partition structure is arranged in the second fan-out area, and the partition structure located in the second fan-out area is electrically connected with the first fan-out wire and the signal wire. According to the display panel and the display device provided by the embodiment of the invention, the wiring mode of the display panel can be optimized on the basis of not increasing the process cost of the display panel, and a narrow frame effect is realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, the screen-to-body ratio of display panels is getting larger and larger, and narrow-border technology is attracting more and more attention.

[0003] In the related technology, FIAA (Fanout in AA, part of the fan-out wiring is arranged in the display area) technology is generally used in display panels to achieve narrow or ultra-narrow borders while ensuring the display performance of the display panel. The core of FIAA technology is to add a layer of metal wiring in the display panel by adding two mask processes to solve the problem of difficult fan-out wiring layout in the border area of ​​the display panel under narrow and ultra-narrow borders. However, the use of this technology will significantly increase the preparation cost of the display panel and cause production capacity loss. Summary of the invention

[0004] Based on this, it is necessary to provide a display panel and a display device, aiming to optimize the display panel routing method and achieve a narrow frame effect without increasing the display panel process cost.

[0005] An embodiment of the first aspect of the present application provides a display panel, including a substrate, a first fan-out routing and a partition structure, the substrate having a display area and a non-display area, a first fan-out area being provided in the non-display area, a second fan-out area being provided in the display area close to the non-display area, and a signal line being provided in the display area; the first fan-out routing is provided on the substrate and is located in the first fan-out area; the partition structure is provided on the substrate, and the partition structure is used to partition adjacent light-emitting units; wherein at least a portion of the partition structure is provided in the second fan-out area, and the partition structure located in the second fan-out area connects the first fan-out routing and the signal line.

[0006] In the embodiment of the present application, the partition structure can not only separate adjacent light-emitting functional parts, but also be used as a fan-out routing to realize the electrical connection between the signal line and the chip. There is no need to add additional metal routing in the display panel to connect the signal line and the chip, which can simplify the film layer structure of the display panel, simplify the production process of the fan-out routing of the display panel, and reduce the production cost of the display panel; and the partition structure used as the fan-out routing is set in the display area, which can optimize the routing method of the display panel, realize the FIAA technology without increasing the process cost of the display panel, reduce the width of the non-display area of ​​the display panel, and realize the narrow frame effect of the display panel.

[0007] In some embodiments, the partition structure includes a first partition structure and a second partition structure, the first partition structure is arranged in the second fan-out area, and the second partition structure is arranged in the area of ​​the display area excluding the second fan-out area; the first partition structure and the second partition structure are arranged on the same layer.

[0008] In some embodiments, the first partition structure includes a first isolator and a first blocking portion stacked in a direction away from the substrate, the first isolator connecting the first fan-out routing and the signal line; the orthographic projection of the first isolator on the substrate is located within the orthographic projection of the first blocking portion on the substrate.

[0009] In some embodiments, a cross-sectional area of ​​the first insulator gradually increases in a direction perpendicular to the substrate and pointing toward the substrate.

[0010] In some embodiments, in a direction perpendicular to the substrate and pointing toward the substrate, a cross-sectional area of ​​the first blocking portion gradually increases.

[0011] In some embodiments, the first fan-out routing includes a first routing and a second routing connected by vias in the thickness direction of the substrate, the first routing is connected to the first isolator and is arranged in the same layer; the second routing connects the first routing and a driving chip.

[0012] In some embodiments, the display panel further includes a driving circuit layer, the driving circuit layer includes a first metal layer, and the second wiring is disposed in the same layer as the first metal layer.

[0013] In some embodiments, the first fan-out routing further includes a third routing, the third routing is disposed between the first routing and the second routing, and the first routing and the third routing, and the second routing and the third routing are connected through the via.

[0014] In some embodiments, the driving circuit layer further includes a second metal layer, the second metal layer is disposed on a side of the first metal layer away from the substrate, and the third trace is disposed on the same layer as the second metal layer.

[0015] In some embodiments, the second partition structure includes a second isolator and a second blocking portion stacked in a direction away from the substrate, and an orthographic projection of the second isolator on the substrate is located within an orthographic projection of the second blocking portion on the substrate.

[0016] In some embodiments, the first trace includes a third isolator and a third blocking portion stacked in a direction away from the substrate, and an orthographic projection of the third isolator on the substrate is located within an orthographic projection of the third blocking portion on the substrate.

[0017] In some embodiments, the first isolator, the second isolator and the third isolator are arranged in the same layer, and / or the first blocking part, the second blocking part and the third blocking part are arranged in the same layer.

[0018] In some embodiments, a cross-sectional area of ​​the second insulator gradually increases in a direction perpendicular to the substrate and pointing toward the substrate.

[0019] In some embodiments, in a direction perpendicular to the substrate and pointing toward the substrate, a cross-sectional area of ​​the second blocking portion gradually increases.

[0020] In some embodiments, the first partition structure also includes a first bearing portion, which is arranged on a side of the first isolating body close to the substrate, the second partition structure also includes a second bearing portion, which is arranged on a side of the second isolating body close to the substrate, the first routing also includes a third bearing portion, which is arranged on a side of the third isolating body close to the substrate; the first bearing portion, the second bearing portion and the third bearing portion are arranged on the same layer.

[0021] In some embodiments, a pixel defining layer is further included, the partition structure is arranged on a side of the pixel defining layer away from the substrate, a plurality of pixel openings are arranged on the pixel defining layer, and the light emitting unit is arranged in the pixel openings.

[0022] An embodiment of a second aspect of the present application provides a display device, comprising any of the display panels described above.

[0023] In the display panel included in the display device in the embodiment of the present application, the partition structure can not only separate adjacent light-emitting functional parts, but also be used as a fan-out routing to realize the electrical connection between the signal line and the chip. There is no need to add additional metal routing in the display panel to connect the signal line and the chip, which can simplify the film layer structure of the display panel, simplify the production process of the fan-out routing of the display panel, and reduce the production cost of the display panel; and the partition structure used as the fan-out routing is arranged in the display area, which can optimize the routing method of the display panel, realize the FIAA technology without increasing the process cost of the display panel, reduce the width of the non-display area of ​​the display panel, and realize the narrow frame effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic structural diagram of a display panel in an embodiment of the present application;

[0025] Figure 2 is a schematic diagram of a partial structure of a display panel in an embodiment of the present application;

[0026] Figure 3is a schematic cross-sectional structure diagram of a display panel in an embodiment of the present application;

[0027] Figure 4 is a schematic cross-sectional structure diagram of a display panel in another embodiment of the present application;

[0028] Figure 5 is a schematic cross-sectional structure diagram of a display panel in yet another embodiment of the present application;

[0029] Figure 6 is a schematic cross-sectional structure diagram of a display area of ​​a display panel in an embodiment of the present application;

[0030] Figure 7 is a schematic cross-sectional structure diagram of a display area of ​​a display panel in another embodiment of the present application;

[0031] Figure 8 FIG. 4 is a schematic diagram of the structure of a display device in an embodiment of the present application.

[0032] Figure 1: display device 200, display panel 100, substrate 1, display area AA, non-display area NA, first fan-out area 101, second fan-out area 102, chip 103, drive circuit layer 2, transistor 20, signal line 21, active layer 201, gate metal layer 202, gate 2021, first metal layer 203, first source 2031, first drain 2032, second metal layer 204, passivation layer 205, planarization layer 206, first fan-out wiring 3, first wiring 31, third insulator 311, third blocking portion 312, first The second routing line 32, the third routing line 33, the first via connection structure 34, the second via connection structure 35, the third via connection structure 36, the pixel defining layer 4, the first insulating layer 5, the fifth via connection structure 51, the light-emitting unit 6, the first electrode 61, the light-emitting functional part 62, the second electrode 63, the fourth via connection structure 64, the partition structure 7, the first partition structure 71, the first isolating body 711, the first blocking part 712, the second partition structure 72, the second isolating body 721, the second blocking part 722, the second bearing part 723, the encapsulation layer 8, and the encapsulation part 81. DETAILED DESCRIPTION

[0033] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0035] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intervening elements. Further, when a layer is referred to as being "under" another layer, it can be directly under or there may be one or more intervening elements. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there may be one or more intervening elements.

[0036] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0037] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0038] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately", "approximately" or "substantially" can mean within one or more standard deviations, which are not limited here.

[0039] Furthermore, in the specification, the phrase “planar distribution schematic diagram” refers to a drawing when a target portion is viewed from above, and the phrase “cross-sectional schematic diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0040] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0041] With the development of display technology, the screen-to-body ratio of display panels is getting larger and larger, and narrow-border technology is attracting more and more attention.

[0042] In the related technology, FIAA (Fanout in AA, part of the fan-out wiring is arranged in the display area) technology is generally used in display panels to achieve narrow or ultra-narrow borders while ensuring the display performance of the display panel. The core of FIAA technology is to add a layer of metal wiring in the display panel by adding two mask processes to solve the problem of difficult fan-out wiring layout in the border area of ​​the display panel under narrow and ultra-narrow borders. However, the use of this technology will significantly increase the preparation cost of the display panel and cause production capacity loss.

[0043] In response to the above problems, the embodiments of the present application provide a display panel and a method for manufacturing the same, and a display device, aiming to optimize the display panel routing method and achieve a narrow frame effect without increasing the process cost of the display panel.

[0044] The embodiment of the first aspect of the present application provides a display panel 100, such as Figures 1 to 6 As shown, the display panel 100 includes a substrate 1, a first fan-out wiring 3 and a partition structure 7, the substrate 1 has a display area AA and a non-display area NA, a first fan-out area 101 is provided in the non-display area NA, a second fan-out area 102 arranged close to the non-display area NA is provided in the display area AA, and a signal line 21 is arranged in the display area AA; the first fan-out wiring 3 is arranged on the substrate 1 and is located in the first fan-out area 101; the partition structure 7 is arranged on the substrate 1, and the partition structure 7 is used to isolate adjacent light-emitting units 6; wherein, at least a portion of the partition structure 7 is arranged in the second fan-out area 102, and the partition structure 71 located in the second fan-out area 102 is electrically connected to the first fan-out wiring 3 and the signal line 21.

[0045] In the present application embodiment, Figures 1 to 5 As shown, the partition structure 7 can not only separate the adjacent light-emitting units 6, but also be used as a fan-out wiring to realize the electrical connection between the signal line 21 and the chip 103. There is no need to add additional metal wiring in the display panel 100 to connect the signal line 21 and the chip 103, which can simplify the film structure of the display panel 100, simplify the manufacturing process of the fan-out wiring of the display panel 100, and reduce the manufacturing cost of the display panel 100; and the partition structure 7 used as the fan-out wiring is set in the display area AA, which can optimize the wiring method of the display panel 100, realize the FIAA technology without increasing the process cost of the display panel 100, reduce the width of the non-display area NA of the display panel 100, and realize the narrow frame effect of the display panel 100.

[0046] In the present application embodiment, Figures 1 to 5As shown, the non-display area NA includes a first fan-out area 101, the first fan-out area 101 includes a plurality of first fan-out traces 3, and the first fan-out traces 3 are used to connect to the chip 103 in the non-display area NA. The display area AA includes a second fan-out area 102, and the second fan-out area 102 is provided with a first partition structure 71, and the first partition structure 71 connects the first fan-out traces 3 and the signal line 21, so that the signal line 21 in the display area AA is connected and bound to the chip 103 located in the non-display area NA.

[0047] In the present application embodiment, Figures 1 to 7 As shown, the substrate 1 can be a rigid substrate, such as a glass substrate, etc., or a flexible substrate, such as a polyimide substrate, etc. The type of the substrate 1 can be set according to actual needs, and this application does not limit this.

[0048] In the present application embodiment, Figures 3 to 7 As shown, the light-emitting unit 6 is arranged on the side of the driving circuit layer 2 away from the substrate 1 and located in the display area AA. The plurality of light-emitting units 6 can emit light of different colors according to actual needs, such as white light, red light, green light and blue light. The light-emitting functional part 62 can be made of organic material, and the light-emitting unit 6 can also include but is not limited to one of the following or a combination thereof: an electron injection layer, an electron transport layer, a hole transport layer and a hole injection layer.

[0049] In the present application embodiment, Figure 2 As shown, the plurality of signal lines 21 and the plurality of first fan-out wirings 3 are correspondingly connected, and then correspondingly connected and bound to the chip 103 of the non-display area NA through the first fan-out wirings 3. The second fan-out area 102 is located in the area of ​​the display area AA close to the non-display area NA. For example, the second fan-out area 102 can be located in two R corner areas on one side of the display area AA close to the non-display area NA, or in the middle area between the two R corner areas. It can be set according to actual needs, and this application does not limit this.

[0050] In some embodiments, Figures 3 to 5 As shown, the partition structure 7 includes a first partition structure 71 and a second partition structure 72. The first partition structure 71 is arranged in the second fan-out area 102, and the second partition structure 72 is arranged in the display area AA excluding the second fan-out area 102. The first partition structure 71 and the second partition structure 72 are arranged in the same layer.

[0051] In the present application embodiment, Figures 3 to 5As shown, the first partition structure 71 can not only partition the adjacent light-emitting units 6, but also be used as a fan-out wiring to realize the electrical connection between the signal line 21 and the chip 103. It is not necessary to add additional metal wiring in the display panel 100 to connect the signal line 21 and the chip 103, which can simplify the film layer structure of the display panel 100, simplify the manufacturing process of the fan-out wiring of the display panel 100, and reduce the manufacturing cost of the display panel 100; and the first partition structure 71 used as the fan-out wiring is set in the display area AA, which can optimize the wiring method of the display panel 100, realize the FIAA technology without increasing the process cost of the display panel 100, reduce the width of the non-display area NA of the display panel 100, and realize the narrow frame effect of the display panel 100. The first partition structure 71 and the second partition structure 72 are set in the same layer, which can simplify the manufacturing process of the partition structure 7 of the display panel 100 and reduce the manufacturing cost of the display panel 100.

[0052] In some embodiments, Figures 3 to 5 As shown, the first partition structure 71 includes a first isolator 711 and a first blocking portion 712 stacked in a direction away from the substrate 1. The first isolator 711 is electrically connected to the first fan-out trace 3 and the signal line 21; the orthographic projection of the first isolator 711 on the substrate 1 is located within the orthographic projection of the first blocking portion 712 on the substrate 1. The first blocking portion 712 is disposed above the first isolator 711. When the first isolator 711 is made of a conductive material, the first blocking portion 712 is made of an insulating material. The first blocking portion 712 is used to separate the first isolator 711 from the conductive layer located above the first isolator 711. Optionally, the material of the first blocking portion 712 includes, but is not limited to, silicon oxide and polyimide.

[0053] In some examples, such as Figure 2 As shown, along the length direction and / or width direction of the display panel 100, there is a certain distance between the routing formed by the first partition structure 71 electrically connected to each other and the signal line 21. This is only for the convenience of clearly illustrating the two routings. In fact, the two routings are located in different film layers, and their projections may overlap to a certain extent. Therefore, vias may be set on the insulating layer between the second insulator 9012 and the signal line 21 to enable the conductive material on the first partition structure 71 to be electrically connected to the signal line 21.

[0054] In the embodiment of the present application, the fan-out routing in the display panel 100 includes a routing formed by the first fan-out routing 3 and the first partition structure 71. The routing formed by the first fan-out routing 3 and the first partition structure 71 can be a fan-out routing for transmitting data signals, or a fan-out routing for transmitting scan signals, power signals, etc. The type of the driving signal transmitted on the routing formed by the first fan-out routing 3 and the first partition structure 71 can be set according to actual needs, and the present application does not limit this.

[0055] Optionally, the first fan-out routing line 3 can be formed by connecting horizontal and vertical routing segments, and the spacing between adjacent routing segments is consistent, so that the design distribution of the first fan-out routing line 3 is more regular, thereby ensuring that the interference between adjacent routing segments is consistent, and reducing the probability of differences in the driving signals transmitted by the signal line 21 connected to the first fan-out routing line 3 due to signal interference between the first fan-out routing lines 3.

[0056] Optionally, the first fan-out routing line 3 may also be an oblique line segment, and the first fan-out routing line 3 may be directly set as an oblique line segment or partially set as an oblique line segment. By routing the oblique line segment, the shortest connection between two points can be achieved, which can ensure that the first fan-out routing line 3 has a shorter line length, and reduce the attenuation of the data signal transmitted by the impedance on the first fan-out routing line 3. Furthermore, each oblique line segment may have a different degree of inclination, that is, each oblique line segment may be parallel to each other or may not be parallel to each other.

[0057] In some embodiments, the display area AA includes multiple first connecting lines formed by the first partition structure 71 and extending along the first direction and / or multiple second connecting lines extending along the second direction, the first direction and the second direction intersect, and the first connecting lines and the second connecting lines are staggered.

[0058] In an embodiment of the present application, the display panel 100 may include only a plurality of first connecting lines extending along a first direction to electrically connect the first fan-out line 3 and the signal line 21, or may include only a plurality of second connecting lines extending along a second direction to electrically connect the first fan-out line 3 and the signal line 21, or may include both the first connecting line and the second connecting line. Preferably, the first direction and the second direction are perpendicular, and the first connecting line and the second connecting line are perpendicular and staggered. The setting position and connection relationship of the first connecting line and the second connecting line can be set according to actual needs, and the present application does not limit this. Among them, the first direction can be the length direction of the display panel 100, and the second direction can be the width direction of the display panel 100.

[0059] In some embodiments, the material of the first fan-out routing 3 is the same as the material of the first isolator 711, the first fan-out routing 3 is a low-impedance material, and the first isolator 711 is a low-impedance material. For example, the first fan-out routing 3 can be formed of a low-impedance metal material, and the first isolator 711 can also be formed of a low-impedance metal material. Forming the first fan-out routing 3 and the first isolator 711 with a low-impedance metal material can reduce the impedance generated by the first fan-out routing 3 and the first isolator 711 during operation, thereby improving the reliability of the display panel 100.

[0060] In some embodiments, Figures 3 to 5As shown, the cross-sectional area of ​​the first isolating body 711 gradually increases in the direction perpendicular to the substrate 1 and pointing to the substrate 1. Optionally, the cross-sectional shape of the first isolating body 711 on the cross-sectional plane perpendicular to the plane where the substrate 1 is located can be a trapezoid, and the cross-sectional shape of the first isolating body 711 on the cross-sectional plane perpendicular to the plane where the substrate 1 is located can also be a rectangle.

[0061] In some embodiments, Figures 3 to 5 As shown, the cross-sectional area of ​​the first blocking portion 712 gradually increases in a direction perpendicular to the substrate 1 and pointing toward the substrate 1. Optionally, the cross-sectional shape of the first blocking portion 712 on a cross section perpendicular to the plane where the substrate 1 is located may be a trapezoid, and the cross-sectional shape of the first blocking portion 712 on a cross section perpendicular to the plane where the substrate 1 is located may also be a rectangle.

[0062] In some embodiments, Figure 3 As shown, the first fan-out wiring 3 includes a first wiring 31 and a second wiring 32 connected by vias in the thickness direction of the substrate 1, the first wiring 31 is electrically connected to the first isolation body 711 and is arranged in the same layer; the second wiring 32 is electrically connected to the first wiring 31 and the driver chip 103. Specifically, as Figure 3 As shown, the first routing line 31 is electrically connected to the second routing line 32 through a first via connection structure 34 , and the first via connection structure 34 is filled with a conductive material, and the material of the conductive material is the same as that of the first fan-out routing line 3 .

[0063] In the present application embodiment, Figure 3 As shown, the first wiring 31 and the first isolator 711 are arranged in the same layer, and the first wiring 31 and the first isolator 711 can be formed by the same mask. The first wiring 31 and the first isolator 711 are arranged in the same layer, which can further simplify the production process of the fan-out wiring in the display panel 100 and reduce the production cost of the display panel 100.

[0064] In the present application embodiment, Figure 3 As shown, the first fan-out routing 3 includes a first routing 31 and a second routing 32 arranged in different layers, the first routing 31 and the second routing 32 are separated by an insulating layer, a via is arranged on the insulating layer, and the first routing 31 and the second routing 32 are electrically connected through the via. The first routing 31 and the second routing 32 are arranged in different film layers, so as to avoid the first routing 31 and the second routing 32 being wired in the same layer, reduce the interference between the first routing 31 and the second routing 32, reduce the wiring difficulty of the first fan-out routing 3, and independently design the routing mode, arrangement mode, shape, line width, position, etc. of the first routing 31 and the second routing 32, so as to facilitate the impedance optimization of the first fan-out routing 3.

[0065] In some embodiments, Figures 3 to 5As shown, the display panel 100 further includes a driving circuit layer 2 , the driving circuit layer 2 includes a first metal layer 203 , and the second wiring 32 is disposed in the same layer as the first metal layer 203 .

[0066] In the present application embodiment, Figures 3 to 5 As shown, the driving circuit layer 2 is arranged on one side of the substrate 1 and is located in the display area AA. The driving circuit layer 2 includes a plurality of pixel circuits, and the pixel circuit includes a transistor 20 and a capacitor. A plurality of signal lines 21 are arranged on one side of the substrate 1, and each signal line 21 is electrically connected to a plurality of transistors 20 arranged along a first direction. The signal line 21 is used to provide a data signal or other signal to the corresponding transistor 20. The first direction can be the length direction of the display panel 100, or it can be the width direction of the display panel 100. The transistor 20 and the light-emitting unit 6 are arranged correspondingly, and the transistor 20 is used to drive the corresponding light-emitting unit 6 to emit light or not emit light.

[0067] In the present application embodiment, Figures 3 to 7 As shown, the first metal layer 203 is disposed on one side of the substrate 1, and the second trace 32 is disposed on the same layer as the first metal layer 203. ， The second wiring 32 and the first metal layer 203 can be formed by the same mask. The second wiring 32 and the first metal layer 203 are arranged in the same layer, which can further simplify the manufacturing process of the fan-out wiring in the display panel 100 and reduce the manufacturing cost of the display panel 100.

[0068] In the present application embodiment, Figures 4 to 7 As shown, the transistor 20 includes multiple metal layers, adjacent metal layers are separated by insulating layers, and the multiple metal layers include an active layer 201, a gate metal layer 202, a first metal layer 203, and a second metal layer 204 arranged in sequence along a side away from the substrate 1. The gate metal layer 202 includes a gate 2021, and the first metal layer 203 includes a first source 2031 and a first drain 2032. The first source 2031 or the first drain 2032 is connected to a via on the active layer 201. According to the position of the gate 2021, the driving circuit layer 2 can be any one of a top gate structure, a bottom gate structure, or a double gate structure. Optionally, the material of the active layer 201 can be any one of amorphous silicon, low temperature polysilicon, metal oxide, and organic material. The insulating layer can be a polyimide film layer.

[0069] In some embodiments, Figure 6 and Figure 7As shown, the display panel 100 further includes a passivation layer 205 and a planarization layer 206. The passivation layer 205 is disposed above the driving circuit layer 2, and is used to protect other layer structures located thereunder, and to slow down the corrosion rate of layer structures such as the second metal layer 204. The planarization layer 206 is disposed above the passivation layer 205, and is used to improve the flatness of the surface of the driving circuit layer 2 away from the substrate 1, so as to facilitate the subsequent film layer production.

[0070] Alternatively, if Figure 6 and Figure 7 As shown, the display panel 100 further includes a fourth via connection structure 64, the fourth via connection structure 64 penetrates the planarization layer 206 and the passivation layer 205, the fourth via connection structure 64 is filled with a conductive material, and the second electrode 63 is connected to the source or drain of the transistor 20 through the fourth via connection structure 64. Optionally, the material of the conductive material filled in the fourth via connection structure 64 can be the same as that of the second electrode 63.

[0071] In some embodiments, Figure 4 and Figure 5 As shown, the first fan-out wiring 3 also includes a third wiring 33, and the third wiring 33 is arranged between the first wiring 31 and the second wiring 32. The first wiring 31 and the third wiring 33, and the second wiring 32 and the third wiring 33 are connected through vias. Specifically, as Figure 4 As shown, the first routing line 31 and the third routing line 32 are electrically connected through the second via connection structure 34, and the second routing line 32 and the third routing line 33 are electrically connected through the third via connection structure 35. The second via connection structure 34 and the third via connection structure 35 are filled with a conductive material, and the material of the conductive material is the same as that of the first fan-out routing line 3.

[0072] In the present application embodiment, Figure 4 and Figure 5 As shown, the first fan-out routing 3 includes a first routing 31, a second routing 32, and a third routing 33 arranged in different layers, and the first routing 31, the second routing 32, and the third routing 33 are separated by an insulating layer, and a via is arranged on the insulating layer, and the first routing 31, the second routing 32, and the third routing 33 are electrically connected through the via. The first routing 31, the second routing 32, and the third routing 33 are arranged in different film layers, so as to avoid the first routing 31, the second routing 32, and the third routing 33 being wired in the same layer, and reduce the interference between the first routing 31, the second routing 32, and the third routing 33. Furthermore, the first routing 31, the second routing 32, and the third routing 33 are arranged in different layers, so as to reduce the wiring difficulty of the first fan-out routing 3, and the routing mode, arrangement mode, shape, line width, position, etc. of the first routing 31, the second routing 32, and the third routing 33 can be independently designed, so as to facilitate the impedance optimization of the first fan-out routing 3.

[0073] In some embodiments, Figures 4 to 7 As shown, the driving circuit layer 2 further includes a second metal layer 204, the second metal layer 204 is arranged on the side of the first metal layer 203 away from the substrate 1, and the third wiring 33 is arranged in the same layer as the second metal layer 203. The second metal layer 204 is electrically connected to the first metal layer 203. The third wiring 33 is arranged in the same layer as the second metal layer 204, and the third wiring 33 and the second metal layer 204 can be prepared and formed by the same mask. The third wiring 33 and the second metal layer 204 are arranged in the same layer, which can further simplify the production process of the fan-out wiring in the display panel 100 and reduce the production cost of the display panel 100.

[0074] In the embodiment of the present application, the display panel 100 may include only one metal layer, such as Figure 3 As shown, the display panel 100 only includes the first metal layer 203; the display panel 100 may also include multiple metal layers, such as Figure 4 As shown, the display panel 100 may include a first metal layer 203 and a second metal layer 204. The first metal layer 203 and the second metal layer 204 may be made of the same material, including but not limited to aluminum, molybdenum, titanium, silver, copper, aluminum and alloys thereof.

[0075] In some embodiments, Figures 3 to 7 As shown, the second partition structure 72 includes a second isolating body 721 and a second blocking portion 722 stacked in a direction away from the substrate 1 , and the orthographic projection of the second isolating body 721 on the substrate 1 is located within the orthographic projection of the second blocking portion 722 on the substrate 1 .

[0076] In the present application embodiment, Figures 3 to 7 As shown, the second blocking portion 722 is disposed above the second isolating body 721. When the second isolating body 721 is made of a conductive material, the second blocking portion 722 is made of an insulating material, and the second blocking portion 722 is used to separate the second isolating body 721 from the conductive layer above the second isolating body 721. Optionally, the material of the second blocking portion 722 includes, but is not limited to, silicon oxide and polyimide.

[0077] In some embodiments, Figures 3 to 7 As shown, the light-emitting unit 6 includes a first electrode 61, a light-emitting functional part 62, and a second electrode 63 stacked in a direction away from the substrate 1, and the second isolator 721 is electrically connected to the first electrode 61. The second isolator 721 is made of a conductive material, and at least part of the first electrode 61 can be connected through the first isolator 9011 to have an equipotential, so as to reduce the influence of other wiring on the signal transmitted in the first electrode 61. The conductive material includes, but is not limited to, silver, aluminum, titanium, molybdenum, tungsten, indium zinc oxide, indium gallium zinc oxide, and indium tin oxide.

[0078] In some embodiments, Figures 3 to 5 As shown, the first trace 31 includes a third insulator 311 and a third blocking portion 312 stacked in a direction away from the substrate 1 , and in a direction perpendicular to the substrate 1 , the orthographic projection of the third insulator 311 on the substrate 1 is located within the orthographic projection of the third blocking portion 312 on the substrate 1 .

[0079] In some embodiments, Figures 3 to 5 As shown, the first isolating body 711, the second isolating body 721 and the third isolating body 311 are arranged on the same layer, and / or the first blocking part 712, the second blocking part 722 and the third blocking part 312 are arranged on the same layer.

[0080] In the display panel 100 provided in the embodiment of the present application, Figure 3 As shown, the second isolator 721 and the first isolator 711 both belong to the partition structure 7, and the first isolator 711 and the second isolator 721 are not electrically connected. The first isolator 711, the second isolator 721 and the third isolator 311 are arranged on the same layer, and the first isolator 711, the second isolator 721 and the third isolator 311 can be prepared simultaneously through a mask plate; the first blocking portion 712, the second blocking portion 722 and the third blocking portion 312 are arranged on the same layer, and the first blocking portion 712, the second blocking portion 722 and the third blocking portion 312 can be prepared simultaneously through a mask plate, which can further simplify the production process of the partition structure 7 and the first wiring 31 in the display panel 100, and reduce the production cost of the display panel 100. Optionally, as Figure 5 As shown, the first insulator 711 and / or the second insulator 711 may also be arranged higher than the third insulator 311 .

[0081] In some embodiments, Figures 3 to 7 As shown, the cross-sectional area of ​​the second isolating body 721 gradually increases in the direction perpendicular to the substrate 1 and pointing to the substrate 1. Optionally, the cross-sectional shape of the second isolating body 721 on the cross-sectional plane perpendicular to the plane where the substrate 1 is located can be a trapezoid, and the cross-sectional shape of the second isolating body 721 on the cross-sectional plane perpendicular to the plane where the substrate 1 is located can also be a rectangle.

[0082] In some embodiments, Figures 3 to 7 As shown, the cross-sectional area of ​​the second blocking portion 722 gradually increases in a direction perpendicular to the substrate 1 and pointing toward the substrate 1. Optionally, the cross-sectional shape of the second blocking portion 722 on a cross section perpendicular to the plane where the substrate 1 is located may be a trapezoid, and the cross-sectional shape of the second blocking portion 722 on a cross section perpendicular to the plane where the substrate 1 is located may also be a rectangle.

[0083] In some embodiments, Figure 7As shown, the first partition structure 71 also includes a first bearing part, which is arranged on the side of the first isolating body 711 close to the substrate 1, the second partition structure 72 also includes a second bearing part 723, which is arranged on the side of the second isolating body 722 close to the substrate 1, and the first wiring 31 also includes a third bearing part, which is arranged on the side of the third isolating body 312 close to the substrate 1; the first bearing part, the second bearing part 723 and the third bearing part are arranged on the same layer. The first bearing part, the second bearing part 723 and the third bearing part are arranged on the same layer, which can further simplify the manufacturing process of the partition structure 7 and the first wiring 31 in the display panel 100 and reduce the manufacturing cost of the display panel 100.

[0084] In the embodiment of the present application, the first bearing portion is disposed below the first isolator 711, and along the direction perpendicular to the substrate 1, the orthographic projection of the bottom surface of the first isolator 711 on the substrate 1 is located within the orthographic projection of the top surface of the first bearing portion on the substrate 1. The first bearing portion can increase the contact area between the second partition structure 72 and its lower structure, improve the connection stability between the first isolator 711 and its lower structure, and improve the reliability of the display panel 100.

[0085] In the present application embodiment, Figures 3 to 6 As shown, the second bearing portion 723 is arranged below the second insulating body 721. Along the direction perpendicular to the substrate 1, the orthographic projection of the bottom surface of the second insulating body 721 on the substrate 1 is located within the orthographic projection of the top surface of the second bearing portion 723 on the substrate 1. The second bearing portion 723 includes a conductive material. The second bearing portion 723 can be connected to the first electrode 61 as an auxiliary cathode to optimize the impedance generated by the first electrode 61 during operation. The second bearing portion 723 can also increase the contact area between the second partition structure 72 and its underlying structure, improve the connection stability between the second partition structure 723 and its underlying structure, and improve the reliability of the display panel 100.

[0086] In some embodiments, Figures 3 to 7 As shown, the pixel defining layer 4 is also included, and the partition structure 7 is arranged on the side of the pixel defining layer 4 away from the substrate 1. A plurality of pixel openings are provided on the pixel defining layer 4, and the light-emitting unit 6 is arranged in the pixel opening. The pixel defining layer 4 includes a plurality of pixel openings, and the light-emitting unit 6 is placed in the pixel opening to separate adjacent light-emitting units 6 and limit the size of the light-emitting unit 6. Optionally, the pixel defining layer 4 includes an organic material, an organic material with an inorganic coating disposed thereon, or an inorganic material. Among them, the organic material includes but is not limited to polyimide, and the inorganic material includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, magnesium fluoride, or a combination thereof.

[0087] In some embodiments, Figures 3 to 7As shown, the display panel 100 also includes an encapsulation layer 8, which is arranged on the side of the partition structure 7 and the light-emitting unit 6 away from the substrate 1 and covers the partition structure 7 and the light-emitting unit 6, so as to encapsulate the partition structure 7 and the light-emitting unit 6 and other layer structures located thereunder, and reduce the probability of corrosion of the first isolation part 711 and the second isolation part 721 of the metal conductive material due to the entry of impurities such as water and oxygen into the partition structure 7, or the probability of failure of the light-emitting unit 6 and the layer structure below due to the entry of impurities such as water and oxygen into the light-emitting unit 6. The encapsulation layer 8 includes a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked in sequence from bottom to top, the first encapsulation layer includes a plurality of encapsulation parts 81 arranged at intervals, the encapsulation part 81 is used to encapsulate the light-emitting unit 6, the first encapsulation layer and the third encapsulation layer are inorganic film layers, and the second encapsulation layer is an organic film layer, which can further extend the water and oxygen invasion path and improve the encapsulation effect. Optionally, the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer can be formed by precipitation, inkjet printing, etching, and the like.

[0088] The embodiment of the second aspect of the present application provides a display device 200, including the display panel 100 in any embodiment of the first aspect. Therefore, the display device 200 provided by the present application has all the advantages of the display panel 100. The embodiment of the present application does not specifically limit the application scope of the display panel 100. Figure 8 As shown, it can be a display panel 100 used in a handheld device (smartphone, tablet computer, etc.), or it can be a display panel 100 used in a wearable device (smart bracelet, wireless headset, smart watch, smart glasses, etc.), a vehicle-mounted device (navigation device, auxiliary reversing system, driving recorder, car refrigerator, etc.), a virtual reality device, an augmented reality device, a terminal device, etc.

[0089] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: include: The substrate has a display area and a non-display area, wherein a first fan-out area is provided in the non-display area, a second fan-out area arranged close to the non-display area is provided in the display area, and a signal line is arranged in the display area; A first fan-out wiring is disposed on the substrate and located in the first fan-out area; A partition structure, disposed on the substrate, and used to partition adjacent light-emitting units; At least part of the partition structure is disposed in the second fan-out area, and the partition structure located in the second fan-out area connects the first fan-out wiring and the signal line.

2. The display panel according to claim 1, characterized in that: The partition structure includes a first partition structure and a second partition structure. The first partition structure is arranged in the second fan-out area, and the second partition structure is arranged in the area of ​​the display area excluding the second fan-out area. The first partition structure and the second partition structure are arranged in the same layer.

3. The display panel according to claim 2, characterized in that: The first partition structure comprises a first isolator and a first blocking portion stacked in a direction away from the substrate, the first isolator connecting the first fan-out trace and the signal line; the orthographic projection of the first isolator on the substrate is located within the orthographic projection of the first blocking portion on the substrate; Preferably, in a direction perpendicular to the substrate and pointing toward the substrate, the cross-sectional area of ​​the first isolator gradually increases; Preferably, in a direction perpendicular to the substrate and pointing toward the substrate, a cross-sectional area of ​​the first blocking portion gradually increases.

4. The display panel according to claim 3, characterized in that: The first fan-out routing includes a first routing and a second routing connected via holes in the thickness direction of the substrate, the first routing is connected to the first isolator and is arranged in the same layer; The second wiring connects the first wiring and the driving chip; Preferably, the display panel further includes a driving circuit layer, the driving circuit layer includes a first metal layer, and the second wiring is arranged in the same layer as the first metal layer.

5. The display panel according to claim 4, characterized in that: The first fan-out routing also includes a third routing, and the third routing is arranged between the first routing and the second routing, and the first routing and the third routing, and the second routing and the third routing are connected through the via.

6. The display panel according to claim 5, characterized in that: The driving circuit layer further includes a second metal layer, which is disposed on a side of the first metal layer away from the substrate, and the third wiring is disposed on the same layer as the second metal layer.

7. The display panel according to claim 4, characterized in that: The second partition structure comprises a second isolator and a second blocking portion stacked in a direction away from the substrate, wherein the orthographic projection of the second isolator on the substrate is located within the orthographic projection of the second blocking portion on the substrate; Preferably, the first wiring includes a third isolator and a third blocking portion stacked in a direction away from the substrate, and the orthographic projection of the third isolator on the substrate is located within the orthographic projection of the third blocking portion on the substrate; Preferably, the first isolator, the second isolator and the third isolator are arranged in the same layer, and / or the first blocking part, the second blocking part and the third blocking part are arranged in the same layer; Preferably, in a direction perpendicular to the substrate and pointing toward the substrate, the cross-sectional area of ​​the second isolator gradually increases; Preferably, in a direction perpendicular to the substrate and pointing toward the substrate, a cross-sectional area of ​​the second blocking portion gradually increases.

8. The display panel according to claim 7, characterized in that: The first partition structure also includes a first bearing part, which is arranged on a side of the first isolating body close to the substrate. The second partition structure also includes a second bearing part, which is arranged on a side of the second isolating body close to the substrate. The first wiring also includes a third bearing part, which is arranged on a side of the third isolating body close to the substrate. The first bearing part, the second bearing part and the third bearing part are arranged on the same layer.

9. The display panel according to claim 8, characterized in that: It also includes a pixel defining layer, the partition structure is arranged on a side of the pixel defining layer away from the substrate, a plurality of pixel openings are arranged on the pixel defining layer, and the light emitting unit is arranged in the pixel openings.

10. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 9.

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