Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a manufacturing method of the display device. A display device according to an embodiment includes: a base electrode including a first reflective layer; a lower electrode including a second reflective layer, the lower electrode being disposed on the base electrode; and a rib portion covering an edge portion of the base electrode and having a pixel opening overlapping the lower electrode. Further, the width of the base electrode is larger than the width of the lower electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-106953 filed on June 29, 2023, and cites all the contents described in the Japanese Patent Application. Technical Field

[0003] Embodiments of the present invention relate to a display device and a method for manufacturing the display device. Background Art

[0004] In recent years, display devices using various types of display elements such as organic light emitting diodes (OLEDs) have been put into practical use. For example, an OLED display element includes a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer emits light in response to the voltage between the lower electrode and the upper electrode. The light emitted by the organic layer passes through the upper electrode and is emitted from the display surface. The lower electrode is required to have a good reflectivity for reflecting the light emitted by the organic layer.

[0005] From the viewpoints of increasing the aperture ratio, increasing the resolution, improving the reflectivity, or improving the yield of display elements, there is still room for research on the structure of the lower electrode. Summary of the invention

[0006] In general, according to an embodiment, a display device includes: a base electrode including a first reflective layer, a lower electrode including a second reflective layer and arranged on the base electrode, and a rib covering an edge of the base electrode and having a pixel opening overlapping with the lower electrode. In addition, the base electrode has a width greater than that of the lower electrode.

[0007] In addition, in general, according to an embodiment, a method for manufacturing a display device includes forming a first layer including a first reflective layer, forming a second layer including a second reflective layer on the first layer, forming a lower electrode by performing a first etching on the second layer, forming a base electrode having a width greater than that of the lower electrode by performing a second etching on the first layer, and forming a rib covering an edge of the base electrode and having a pixel opening overlapping with the lower electrode.

[0008] According to the embodiments, a display device having an improved electrode structure and a method for manufacturing the display device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a diagram showing a configuration example of a display device according to the first embodiment.

[0010] Figure 2 This is a schematic plan view showing an example of the layout of sub-pixels according to the first embodiment.

[0011] Figure 3 is along Figure 2 A schematic cross-sectional view of a display device taken along line III-III in FIG.

[0012] Figure 4 It is a schematic plan view of the base electrode, the lower electrode, and the axial layer of the partition wall according to the first embodiment.

[0013] Figure 5 It is along Figure 4 Schematic cross-sectional view of the display device along line VV in FIG.

[0014] Figure 6 It is a schematic cross-sectional view of the layer structure of the base electrode and the lower electrode which can be applied to the first embodiment.

[0015] Figure 7 It is a schematic cross-sectional view of another layer structure that can be applied to the base electrode and the lower electrode.

[0016] Figure 8 This is a schematic cross-sectional view of yet another layer structure that can be applied to the base electrode and the lower electrode.

[0017] Fig. 9 This is a schematic cross-sectional view of yet another layer structure that can be applied to the base electrode and the lower electrode.

[0018] Fig.10 This is a flowchart showing an example of the method for manufacturing the display device according to the first embodiment.

[0019] Fig.11A This is a schematic cross-sectional view showing an example of a process of forming a base electrode and a lower electrode.

[0020] Fig. 11B Then Fig.11A A schematic cross-sectional view of the process.

[0021] Fig. 11C Then Fig. 11B A schematic cross-sectional view of the process.

[0022] Fig.11D Then Fig. 11C A schematic cross-sectional view of the process.

[0023] Fig.11E Then Fig.11D A schematic cross-sectional view of the process.

[0024] Fig.11F Then Fig.11E A schematic cross-sectional view of the process.

[0025] Fig.11G Then Fig.11F A schematic cross-sectional view of the process.

[0026] Fig. 12A This is a schematic cross-sectional view showing an example of a process for forming a display element.

[0027] Fig. 12B Then Fig. 12A A schematic cross-sectional view of the process.

[0028] Fig. 12C Then Fig. 12B A schematic cross-sectional view of the process.

[0029] Fig.12D Then Fig. 12C A schematic cross-sectional view of the process.

[0030] Fig.12E Then Fig.12D A schematic cross-sectional view of the process.

[0031] Fig.13 This is a graph showing the result of simulating the relationship between the reflectivity of the anode and the wavelength.

[0032] Fig.14 This is a graph showing the results of simulation of the relationship between the thickness of the silver layer and the reflectivity in a laminated body in which a silver layer is arranged on an aluminum layer.

[0033] Fig.15 This is a graph showing the results of a simulation of the relationship between the thickness of the ITO layer and the reflectivity in a laminated body in which an aluminum layer, an ITO layer, and a silver layer are arranged in this order.

[0034] Fig.16 This is a graph showing the results of a simulation of the relationship between the thickness of the titanium nitride layer and the reflectivity in a laminated body in which an aluminum layer, a titanium nitride layer, an ITO layer, and a silver layer are arranged in this order.

[0035] Fig.17 This is a graph showing the results of a simulation of the relationship between the thickness of the silver layer and the reflectivity in a laminated body in which an aluminum layer, a titanium nitride layer, an ITO layer, and a silver layer are arranged in this order.

[0036] Fig.18A It is a schematic cross-sectional view showing the second etching step of the second embodiment.

[0037] Fig.18B Then Fig.18A A schematic cross-sectional view of the process.

[0038] Fig.19 It is a schematic cross-sectional view of a display device according to a modified example. DETAILED DESCRIPTION

[0039] Several embodiments will be described with reference to the drawings.

[0040] The disclosed content is only an example, and appropriate changes that can be easily thought of by those skilled in the art while maintaining the gist of the invention are certainly included in the scope of the present invention. In addition, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically shown in the drawings compared with the actual way, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same reference numerals are marked for the constituent elements that perform the same or similar functions as the constituent elements previously described in relation to the figures that have appeared, and repeated detailed descriptions are sometimes appropriately omitted.

[0041] It should be noted that in the drawings, mutually orthogonal X-axis, Y-axis and Z-axis are recorded as needed for easy understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of the plane including the X-direction and the Y-direction. In addition, the situation of observing various elements parallel to the Z-direction is called top-down observation.

[0042] The display device involved in each embodiment is an organic electroluminescent display device having an organic light emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, vehicle-mounted equipment, tablet terminals, smartphones, mobile phone terminals, wearable terminals, etc.

[0043] [First embodiment]

[0044] Figure 1 1 is a diagram showing a configuration example of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 includes a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film.

[0045] In the present embodiment, the shape of the substrate 10 when viewed from above is a rectangle, but the shape of the substrate 10 when viewed from above is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0046] The display area DA has a plurality of pixels PX arranged in a matrix in the X direction and the Y direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, it is assumed that the pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. However, the pixel PX may also include a sub-pixel SP of another color such as white together with the sub-pixels SP1, SP2, and SP3 or instead of any of the sub-pixels SP1, SP2, and SP3.

[0047] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0048] In the display area DA, a plurality of scanning lines G for supplying scanning signals to the pixel circuits 1 of the sub-pixels SP, a plurality of signal lines S for supplying video signals to the pixel circuits 1 of the sub-pixels SP, and a plurality of power supply lines PL are arranged. Figure 1 In the example of FIG. 5 , the scanning lines G and the power lines PL extend in the X direction, and the signal lines S extend in the Y direction.

[0049] The gate electrode of the pixel switch 2 is connected to the scanning line G. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line S, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0050] It should be noted that the structure of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0051] Figure 2 is a schematic top view showing an example of the layout of sub-pixels SP1, SP2, and SP3. Figure 2 In the example of FIG. 1 , the sub-pixels SP2 and SP3 are arranged in the X direction with the sub-pixel SP1. In addition, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the Y direction.

[0052] When the sub-pixels SP1, SP2, and SP3 are arranged in this way, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the Y direction and columns in which a plurality of sub-pixels SP1 are repeatedly arranged in the Y direction are formed in the display area DA. These columns are alternately arranged in the X direction. It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 Examples of other layouts can also be applied.

[0053] The rib 5 is disposed in the display area DA. The rib 5 has pixel openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. Figure 2 In the example, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3. That is, among the sub-pixels SP1, SP2, and SP3, the sub-pixel SP1 has the highest aperture ratio, and the sub-pixel SP3 has the lowest aperture ratio.

[0054] The sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 respectively overlapping the pixel opening AP1. The sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 respectively overlapping the pixel opening AP2. The sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 respectively overlapping the pixel opening AP3.

[0055] The lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 overlapping with the pixel opening AP1 constitute the display element DE1 of the sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 overlapping with the pixel opening AP2 constitute the display element DE2 of the sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 overlapping with the pixel opening AP3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may also include a cover layer and a base electrode described later. The ribs 5 surround each of the display elements DE1, DE2, and DE3.

[0056] A conductive partition wall 6 is disposed on the rib 5. The partition wall 6 overlaps the rib 5 as a whole and has the same planar shape as the rib 5. That is, the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3, respectively. From another point of view, the rib 5 and the partition wall 6 are lattice-shaped when viewed from above, and surround the pixel openings AP1, AP2, and AP3, respectively. The partition wall 6 has a function as a wiring for supplying a common voltage to the upper electrodes UE1, UE2, and UE3.

[0057] Figure 3 is along Figure 2 A schematic cross-sectional view of a display device DSP along line III-III in FIG. A circuit layer 11 is arranged on the substrate 10. The circuit layer 11 includes Figure 1 The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes the unevenness generated in the circuit layer 11.

[0058] In this embodiment, base electrodes BE1, BE2, and BE3 are arranged on the organic insulating layer 12. The lower electrode LE1 is arranged on the base electrode BE1, the lower electrode LE2 is arranged on the base electrode BE2, and the lower electrode LE3 is arranged on the base electrode BE3. Figure 3 In the example of FIG. 1 , the edges of the base electrodes BE1 , BE2 , and BE3 protrude from the lower electrodes LE1 , LE2 , and LE3 , respectively.

[0059] The ribs 5 cover the edges of the lower electrodes LE1, LE2, LE3. The ribs 5 also cover the edges of the base electrodes BE1, BE2, BE3 protruding from the lower electrodes LE1, LE2, LE3. In addition, the ribs 5 cover the organic insulating layer 12 between the base electrodes BE1, BE2, BE3. Figure 3 Although not shown in the cross section of FIG. 1 , the lower electrodes LE1 , LE2 , LE3 and the base electrodes BE1 , BE2 , BE3 are connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12 , respectively.

[0060] The partition wall 6 includes a conductive lower portion 61 disposed on the rib 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. Thus, both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called a cantilever shape.

[0061] exist Figure 3 In the example of , the lower portion 61 has a bottom layer 63 disposed on the rib 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the shaft layer 64. Figure 3 In the example, both ends of the bottom layer 63 protrude from the side of the shaft layer 64. However, both ends of the bottom layer 63 may be aligned with the side of the shaft layer 64. It should be noted that the lower portion 61 may not have the bottom layer 63. In addition, the lower portion 61 may have a multilayer structure with more than three layers.

[0062] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and is opposite to the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and is opposite to the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and is opposite to the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower portion 61 of the partition wall 6.

[0063] The display element DE1 includes a cover layer CP1 disposed on the upper electrode UE1. The display element DE2 includes a cover layer CP2 disposed on the upper electrode UE2. The display element DE3 includes a cover layer CP3 disposed on the upper electrode UE3. The cover layers CP1, CP2, and CP3 respectively have the function of serving as optical adjustment layers to improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3.

[0064] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3.

[0065] A portion of the laminate film FL1 is located above the upper portion 62. This portion is separated from the portion of the laminate film FL1 located below the partition wall 6 (the portion constituting the display element DE1). Similarly, a portion of the laminate film FL2 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL2 located below the partition wall 6 (the portion constituting the display element DE2). In addition, a portion of the laminate film FL3 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL3 located below the partition wall 6 (the portion constituting the display element DE3).

[0066] Sealing layers SE1, SE2, and SE3 are respectively arranged in sub-pixels SP1, SP2, and SP3. Sealing layer SE1 continuously covers cap layer CP1 and partition walls 6 around sub-pixel SP1. Sealing layer SE2 continuously covers cap layer CP2 and partition walls 6 around sub-pixel SP2. Sealing layer SE3 continuously covers cap layer CP3 and partition walls 6 around sub-pixel SP3.

[0067] exist Figure 3 In the example, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE3 on the partition wall 6.

[0068] The sealing layers SE1, SE2, and SE3 are covered by the resin layer 13. The resin layer 13 is covered by the sealing layer 14. The sealing layer 14 is covered by the resin layer 15. The resin layers 13, 15, and the sealing layer 14 are continuously provided at least over the entire display area DA, and a part of them also reaches the peripheral area SA.

[0069] A cover member such as a polarizing plate, a touch panel, a protective film or a cover glass may be further disposed on the resin layer 15. Such a cover member may be bonded to the resin layer 15 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0070] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib 5 and the sealing layers 14, SE1, SE2, and SE3 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). In one example, the rib 5 is formed of silicon oxide or silicon oxynitride, and the sealing layers 14, SE1, SE2, and SE3 are formed of silicon nitride. The resin layers 13 and 15 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0071] The upper electrodes UE1, UE2, UE3 are formed of metal materials such as magnesium and silver alloy (MgAg). For example, the stack of the base electrodes BE1, BE2, BE3 and the lower electrodes LE1, LE2, LE3 corresponds to the anode, and the upper electrodes UE1, UE2, UE3 corresponds to the cathode.

[0072] The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially stacked in the Z direction. However, the organic layers OR1, OR2, and OR3 may also have other structures such as a so-called tandem structure including a plurality of light-emitting layers.

[0073] The cover layers CP1, CP2, and CP3, for example, have a stacked structure formed by overlapping multiple transparent layers. These transparent layers may include layers formed by inorganic materials and layers formed by organic materials. In addition, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the refractive indices of the sealing layers SE1, SE2, and SE3. It should be noted that at least one of the cover layers CP1, CP2, and CP3 may also be omitted.

[0074] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of metal materials. As the metal material of the bottom layer 63, for example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW) or molybdenum-niobium alloy (MoNb) can be used. As the metal material of the shaft layer 64, for example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY) or aluminum-silicon alloy (AlSi) can be used. It should be noted that the shaft layer 64 can also be formed of an insulating material.

[0075] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a transparent oxide. As the metal material forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used. As the transparent oxide forming the upper layer, for example, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) can be used. It should be noted that the upper portion 62 may also have a single-layer structure of a metal material. In addition, the upper portion 62 may include a layer formed of an insulating material.

[0076] A common voltage is supplied to the partition wall 6. The common voltage is supplied to the upper electrodes UE1, UE2, UE3 respectively in contact with the side surface of the lower portion 61. The lower electrodes LE1, LE2, LE3 and the base electrodes BE1, BE2, BE3 are supplied with pixel voltages corresponding to the image signals of the signal lines S through the pixel circuits 1 of the sub-pixels SP1, SP2, SP3 respectively.

[0077] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength region. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength region. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength region.

[0078] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may also emit light of the same color (for example, white). In this case, the display device DSP may also include a color filter that converts the light emitted by the light-emitting layer into light of a color corresponding to the sub-pixels SP1, SP2, and SP3. In addition, the display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layer to generate light of a color corresponding to the sub-pixels SP1, SP2, and SP3.

[0079] Figure 4 1 is a schematic plan view of the base electrode BE1, the lower electrode LE1, and the axial layer 64 of the partition wall 6. In this figure, the axial layer 64 is shaded, and the outer shape of the base electrode BE1 is indicated by a dotted line.

[0080] exist Figure 4 In the example of FIG. 1 , the base electrode BE1 has an edge E1 that is rectangular in plan view, and the lower electrode LE1 has an edge E2 that is rectangular in plan view. However, the shapes of the edges E1 and E2 are not limited to rectangles.

[0081] The base electrode BE1 has a width Wx1 in the X direction and a width Wy1 in the Y direction. The lower electrode LE1 has a width Wx2 in the X direction and a width Wy2 in the Y direction. In the present embodiment, the width Wx1 is larger than the width Wx2 (Wx1 > Wx2). Further, the width Wy1 is larger than the width Wy2 (Wy1 > Wy2). Thus, the vicinity of the edge portion E1 of the base electrode BE1 is exposed from the lower electrode LE1.

[0082] In Figure 4 the example of, the entire edge portion E1 of the base electrode BE1 overlaps with the axis layer 64. On the other hand, the edge portion E2 of the lower electrode LE1 does not overlap with the axis layer 64. As another example, at least a part of the edge portion E1 may not overlap with the axis layer 64. Further, at least a part of the edge portion E2 may overlap with the axis layer 64.

[0083] Figure 5 is a schematic cross-sectional view of the display device DSP along the Figure 4 V-V line in. In this figure, the substrate 10, the circuit layer 11, the resin layer 13, the sealing layer 14, and the resin layer 15 are omitted.

[0084] Two partition walls 6 in the figure are both located between the sub-pixels SP1 adjacent in the Y direction. In Figure 5 the example of, the upper portions 62 of these partition walls 6 are entirely covered by the laminated film FL1 and the sealing layer SE1. As other examples, the laminated film FL1 and the sealing layer SE1 may be laminated with a gap above the upper portions 62 of these partition walls 6.

[0085] The edge portion E1 of the base electrode BE1 and the edge portion E2 of the lower electrode LE1 are covered by the rib portion 5. The rib portion 5 made of an inorganic material is formed thinner than the organic insulating layer 12 or the like. Therefore, a step corresponding to the edge portions E1 and E2 is formed on the surface of the rib portion 5. In Figure 5 the example of, the edge portion E1 is located below the axis layer 64. Therefore, the step caused by the edge portion E1 is covered by the bottom layer 63 and the axis layer 64.

[0086] The adjacent base electrodes BE1 are separated by a distance D1. The adjacent lower electrodes LE1 are separated by a distance D2. The distance D1 is smaller than the distance D2 (D1 < D2). As an example, the distance D2 is 5 μm or more and the distance D1 is 3 μm or less.

[0087] It should be noted that, for the configurations of the base electrode BE2 and the lower electrode LE2, and the configurations of the base electrode BE3 and the lower electrode LE3, the same as those in Figure 4 and Figure 5The substrate electrode BE1 shown in the figure has the same structure as the lower electrode LE1. For example, two adjacent substrate electrodes BE1, BE2, and BE3 are separated by the distance D1. In addition, two adjacent lower electrodes LE1, LE2, and LE3 are separated by the distance D2. However, the distance between two adjacent substrate electrodes BE1, BE2, and BE3 is not necessarily the same at all locations. In addition, the distance between two adjacent lower electrodes LE1, LE2, and LE3 is not necessarily the same at all locations.

[0088] Figures 6 to 9 1 and 1 are schematic cross-sectional views of layer structures applicable to the base electrode BE1 and the lower electrode LE1. The layer structures shown in these figures are also applicable to the base electrodes BE2 and BE3 and the lower electrodes LE2 and LE3.

[0089] exist Figures 6 to 9 In any of the above, the base electrode BE1 includes a first reflective layer RF1, and the lower electrode LE1 includes a second reflective layer RF2. These reflective layers RF1 and RF2 are formed of a metal material having excellent reflectivity of visible light. A portion of the light emitted by the organic layer OR1 is reflected by the second reflective layer RF2. Moreover, at least a portion of the light that passes through the second reflective layer RF2 is reflected by the first reflective layer RF1.

[0090] In this embodiment, it is assumed that the first reflective layer RF1 is formed of aluminum (Al) or an aluminum alloy, and the second reflective layer RF2 is formed of silver (Ag). However, the reflective layers RF1 and RF2 may be formed of other metals or metal alloys.

[0091] exist Figure 6 In the example of , the base electrode BE1 is a single-layer structure of the first reflective layer RF1. On the other hand, the lower electrode LE1 includes the second reflective layer RF2 and the first transparent oxide layer CL1 covering the upper surface of the second reflective layer RF2. The lower surface of the second reflective layer RF2 is in contact with the upper surface of the first reflective layer RF1.

[0092] The first transparent oxide layer CL1 is formed of, for example, ITO or IZO, and functions as a hole injection electrode facing the hole injection layer of the organic layer OR1. The first transparent oxide layer CL1 is, for example, thinner than the second reflective layer RF2.

[0093] exist Figure 7 In the example of , the lower electrode LE1 further includes a second transparent oxide layer CL2 covering the lower surface of the second reflective layer RF2. The second transparent oxide layer CL2 is in contact with the upper surface of the first reflective layer RF1. The second transparent oxide layer CL2 is formed of, for example, ITO or IZO.

[0094] The second reflective layer RF2 made of silver may not exhibit sufficient adhesion to the first reflective layer RF1 made of aluminum or aluminum alloy. In view of this, the second transparent oxide layer CL2 is disposed between the reflective layers RF1 and RF2 to improve the adhesion of the reflective layers RF1 and RF2.

[0095] The thinner the second transparent oxide layer CL2 is, the higher the reflectivity of the anode stacked with the base electrode BE1 and the lower electrode LE1 is. Fig.15 Therefore, the second transparent oxide layer CL2 is preferably formed thinner than each of the reflective layers RF1 and RF2. As an example, the thickness of the second transparent oxide layer CL2 is 5 to 10 nm.

[0096] It should be noted that, for example, when the first reflective layer RF1 is formed of aluminum (pure aluminum) and the second transparent oxide layer CL2 is formed of ITO, a high connection resistance will be generated between the first reflective layer RF1 and the second transparent oxide layer CL2. From the viewpoint of reducing the connection resistance, it is preferred that the first reflective layer RF1 is formed of an aluminum alloy such as an aluminum-nickel alloy (AlNi).

[0097] exist Figure 8 In the example of , the base electrode BE1 further includes a first metal layer ML1 covering the upper surface of the first reflective layer RF1. The first metal layer ML1 is in contact with the second transparent oxide layer CL2. The first metal layer ML1 is formed of, for example, titanium nitride (TiN). By configuring such a first metal layer ML1, even when the first reflective layer RF1 is formed of aluminum, the above-mentioned connection resistance can be improved.

[0098] The thinner the first metal layer ML1 is, the higher the reflectivity of the anode layer formed by stacking the base electrode BE1 and the lower electrode LE1 is. Fig.16 Therefore, the first metal layer ML1 is preferably formed thinner than each of the reflective layers RF1 and RF2. As an example, the thickness of the first metal layer ML1 is 5 to 10 nm.

[0099] exist Fig. 9 In the example of FIG. 1 , the base electrode BE1 further includes a second metal layer ML2 covering the lower surface of the first reflective layer RF1. The second metal layer ML2 is formed of, for example, titanium (Ti) and has a Figure 5 The second metal layer ML2 is shown in contact with the organic insulating layer 12. By providing such a second metal layer ML2, the adhesion between the first reflective layer RF1 and the organic insulating layer 12 is improved.

[0100] It should be noted that the second metal layer ML2 has almost no effect on the optical and electrical properties of the anode formed by stacking the base electrode BE1 and the lower electrode LE1. Therefore, the second metal layer ML2 can be formed thicker than the first metal layer ML1. As an example, the thickness of the second metal layer ML2 is 10 to 100 nm.

[0101] The thickness of the reflective layers RF1, RF2, the metal layers ML1, ML2, and the transparent oxide layers CL1, CL2 can be appropriately determined in consideration of reflectivity, the total thickness of each layer, etc. In one example, the reflective layers RF1, RF2 are both 30 nm, the first metal layer ML1 is 5 nm, the second metal layer ML2 is 10 nm, the first transparent oxide layer CL1 is 25 nm, and the second transparent oxide layer CL2 is 7 nm.

[0102] Fig.10 1 is a flowchart showing an example of a method for manufacturing a display device DSP. When manufacturing the display device DSP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10 (process PR1). Next, base electrodes BE1, BE2, BE3 and lower electrodes LE1, LE2, LE3 are formed on the organic insulating layer 12 (process PR2).

[0103] FIG. 11A to FIG. 11G 1 is a schematic cross-sectional view showing an example of a process for forming the base electrodes BE1, BE2, BE3 and the lower electrodes LE1, LE2, LE3. Fig. 9 The structure shown. FIG. 11A to FIG. 11G In the figure, the substrate 10 and the circuit layer 11 are omitted.

[0104] In process PR2, first Fig.11A As shown, a first layer L1 for processing into base electrodes BE1, BE2, BE3 and a second layer L2 for processing into lower electrodes LE1, LE2, LE3 are formed on the organic insulating layer 12.

[0105] The first layer L1 includes a first reflective layer L10, a first metal layer L11 covering the upper surface of the first reflective layer L10, and a second metal layer L12 covering the lower surface of the first reflective layer L10. The materials of the first reflective layer L10, the first metal layer L11, and the second metal layer L12 are the same as the materials described above as the materials of the first reflective layer RF1, the first metal layer ML1, and the second metal layer ML2. In forming the first reflective layer L10, the first metal layer L11, and the second metal layer L12, for example, sputtering can be used.

[0106] The second layer L2 includes a second reflective layer L20, a first transparent oxide layer L21 covering the upper surface of the second reflective layer L20, and a second transparent oxide layer L22 covering the lower surface of the second reflective layer L20. The materials of the second reflective layer L20, the first transparent oxide layer L21, and the second transparent oxide layer L22 are the same as the materials described above as the materials of the second reflective layer RF2, the first transparent oxide layer CL1, and the second transparent oxide layer CL2. In forming the second reflective layer L20, the first transparent oxide layer L21, and the second transparent oxide layer L22, for example, sputtering can be used.

[0107] After forming the first layer L1 and the second layer L2, as Fig. 11B As shown in FIG. 1 , a resist R1 is disposed on the second layer L2. The resist R1 is patterned into the shape of, for example, base electrodes BE1, BE2, and BE3.

[0108] After the resist R1 is formed, a first etching is performed to remove the portion of the second layer L2 exposed from the resist R1. The first etching includes wet etching of the first transparent oxide layer L21 ( Fig. 11C ), wet etching of the second reflective layer L20 ( Fig.11D ), and wet etching of the second transparent oxide layer L22 ( Fig.11E ).

[0109] In the wet etching of the first transparent oxide layer L21, Fig. 11C As shown in FIG. 1 , the portion of the first transparent oxide layer L21 exposed from the resist R1 is removed. Thus, the first transparent oxide layer CL1 of the lower electrodes LE1, LE2, and LE3 is formed. Fig. 11C In the example of FIG. 1 , the width of the first transparent oxide layer CL1 is slightly smaller than the width of the resist R1 .

[0110] In the wet etching of the second reflective layer L20, Fig.11D As shown in FIG. 1 , the portion of the second reflective layer L20 exposed from the resist R1 is removed. Thus, the second reflective layer RF2 of the lower electrodes LE1, LE2, and LE3 is formed. Fig.11D In the example of FIG. 1 , the width of the second reflective layer RF2 is slightly smaller than the width of the first transparent oxide layer CL1 .

[0111] It should be noted that, in the wet etching of the second reflective layer L20, in order to suppress damage to the first reflective layer L10 below, it is preferable to use an etching solution that is difficult to dissolve the first reflective layer L10. For example, when the first reflective layer L10 is formed of aluminum or an aluminum alloy, a solution with a nitric acid concentration of 20% or more can be used as the etching solution. Thus, even if the second transparent oxide layer L22 and the first metal layer L11 are damaged by the previous wet etching, or pinholes are formed on the second transparent oxide layer L22 and the first metal layer L11, the dissolution of the first reflective layer L10 can be suppressed.

[0112] In the wet etching of the second transparent oxide layer L22, Fig.11E As shown, the portion of the second transparent oxide layer L22 exposed from the resist R1 is removed, thereby forming the second transparent oxide layer CL2 of the lower electrodes LE1, LE2, and LE3.

[0113] exist Fig.11E In the example of FIG. 1 , the width of the second transparent oxide layer CL2 is slightly smaller than the width of the second reflective layer RF2. In addition, the end of the first transparent oxide layer CL1 is also corroded during the wet etching. Fig.11E In the example of , the width of the first transparent oxide layer CL1 is slightly smaller than the width of the second reflective layer RF2.

[0114] In this way, through FIG. 11C to FIG. 11E In the first etching shown, the second layer L2 is patterned into the shape of the lower electrodes LE1, LE2, and LE3. After the first etching, the second etching is performed on the first layer L1.

[0115] For example, the second etching is dry etching for processing the first reflective layer L10, the first metal layer L11, and the second metal layer L12 at the same time. As another example, the second etching may include multiple dry etchings for processing the first reflective layer L10, the first metal layer L11, and the second metal layer L12 separately.

[0116] In the second etching, if Fig.11F As shown in FIG. 1 , the portion of the first layer L1 exposed from the resist R1 is removed. Thus, the first layer L1 is patterned into the shape of the base electrodes BE1, BE2, and BE3. After the second etching, as shown in FIG. Fig.11G As shown, the resist R1 is removed.

[0117] It should be noted that the second etching is preferably a dry etching with high anisotropy. Thus, the portion of the first layer L1 located below the resist R1 is not easily corroded. Therefore, the base electrodes BE1, BE2, and BE3 can be formed with high precision.

[0118] After the base electrodes BE1, BE2, BE3 and the lower electrodes LE1, LE2, LE3 are formed as described above, the ribs 5 and the partitions 6 are formed. Fig.10 In this process, an inorganic insulating layer for processing into the rib 5 is first formed, and the partition 6 is formed thereon. Then, the rib 5 is formed by providing pixel openings AP1, AP2, and AP3 on the inorganic insulating layer. As another example, the partition 6 may be formed after providing pixel openings AP1, AP2, and AP3 on the inorganic insulating layer.

[0119] After forming the ribs 5 and the partitions 6, a step for forming the display elements DE1, DE2, and DE3 is performed ( Fig.10 In the present embodiment, it is assumed that the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last. However, the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0120] FIG. 12A to FIG. 12E The schematic cross-sectional views are schematic views showing an example of the process of forming the display elements DE1, DE2, and DE3. In these drawings, the substrate 10 and the circuit layer 11 are omitted.

[0121] When forming the display element DE1, first Fig. 12A As shown in FIG. 1 , a laminated film FL1 and a sealing layer SE1 are formed (step PR4 ). Figure 3 As shown, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cover layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cover layer CP1 are formed by evaporation. In addition, the sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The laminated film FL1 is partitioned into multiple parts by the cantilevered partition wall 6. The sealing layer SE1 continuously covers the partitioned parts of the laminated film FL1 and the partition wall 6.

[0122] After step PR4, the laminate film FL1 and the sealing layer SE1 are patterned (step PR5). In this patterning, Fig. 12B As shown in FIG. 1 , a resist Rs is disposed on the sealing layer SE1 . The resist Rs covers the sub-pixel SP1 and a part of the partition wall 6 around it.

[0123] Then, by using the resist Rs as a mask for etching, Fig. 12CAs shown, the portions of the laminated film FL1 and the sealing layer SE1 exposed from the resist Rs are removed. In other words, the portions of the laminated film FL1 and the sealing layer SE1 overlapping with the lower electrode LE1 are left, and the other portions are removed. Thus, a display element DE1 is formed in the sub-pixel SP1. For example, the etching includes wet etching or dry etching sequentially performed on the sealing layer SE1, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist Rs is removed.

[0124] The display element DE2 is formed in the same steps as the display element DE1. That is, when forming the display element DE2, the laminated film FL2 and the sealing layer SE2 are formed on the entire display area DA (process PR6). Figure 3 As shown, the stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0125] The organic layer OR2, the upper electrode UE2 and the cap layer CP2 are formed by evaporation. In addition, the sealing layer SE2 is formed by CVD. The laminate film FL2 is partitioned into a plurality of parts by the cantilever partition wall 6. The sealing layer SE2 continuously covers the partitioned parts of the laminate film FL2 and the partition wall 6.

[0126] After step PR6, the laminate film FL2 and the sealing layer SE2 are patterned (step PR7). Fig.12D As shown, a display element DE2 is formed in the sub-pixel SP2.

[0127] The display element DE3 is formed in the same steps as the display elements DE1 and DE2. That is, when forming the display element DE3, the laminated film FL3 and the sealing layer SE3 are formed on the entire display area DA (step PR8). Figure 3 As shown, the stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0128] The organic layer OR3, the upper electrode UE3 and the cap layer CP3 are formed by evaporation. In addition, the sealing layer SE3 is formed by CVD. The laminate film FL3 is partitioned into a plurality of parts by the cantilever partition wall 6. The sealing layer SE3 continuously covers the partitioned parts of the laminate film FL3 and the partition wall 6.

[0129] After step PR8, the laminate film FL3 and the sealing layer SE3 are patterned (step PR9). Fig.12E As shown, the display element DE3 is formed in the sub-pixel SP3.

[0130] After forming the display elements DE1, DE2, and DE3, Figure 3 The resin layer 13, the sealing layer 14 and the resin layer 15 are shown (process PR10). After such processes, the display device DSP is completed.

[0131] Next, the effects of the display device DSP and the manufacturing method thereof according to the present embodiment will be described. It should be noted that the effects described here are only examples, and the display device DSP and the manufacturing method thereof according to the present embodiment can have various other effects.

[0132] In this embodiment, substrate electrodes BE1, BE2, BE3 are arranged below the lower electrodes LE1, LE2, LE3. Assuming that there are no substrate electrodes BE1, BE2, BE3, the light emitted by the organic layers OR1, OR2, OR3 must be mainly reflected by the second reflection layer RF2 of the lower electrodes LE1, LE2, LE3. At this time, in order to obtain sufficient reflectivity, the second reflection layer RF2 needs to be thickened to about 100nm, for example. If the second reflection layer RF2 is, for example, about 50nm, part of the light will pass through the second reflection layer RF2, and the luminous efficiency of the display elements DE1, DE2, DE3 will be reduced.

[0133] On the other hand, if the second reflective layer RF2 is thickened, a large step difference is generated on the upper surface of the rib 5 covering the end thereof. Due to the step difference, the upper electrodes UE1, UE2, UE3 are interrupted, and there is a possibility of poor conduction with the partition 6. In addition, cracks may also be generated on the rib 5 near the edge of the thick lower electrodes LE1, LE2, LE3.

[0134] In contrast, in the present embodiment, base electrodes BE1, BE2, BE3 including the first reflective layer RF1 are disposed under the lower electrodes LE1, LE2, LE3, respectively. According to this configuration, the light of the organic layers OR1, OR2, OR3 is reflected by the lower electrodes LE1, LE2, LE3 and the base electrodes BE1, BE2, BE3. Therefore, even when the lower electrodes LE1, LE2, LE3 and the base electrodes BE1, BE2, BE3 are formed thin, sufficient reflectivity can be obtained.

[0135] In addition, if Figure 4 and Figure 5As shown, the width of the substrate electrode BE1 is greater than the width of the lower electrode LE1. Therefore, the edge E1 of the substrate electrode BE1 is offset from the edge E2 of the lower electrode LE1. According to such a structure, the step difference generated on the upper surface of the rib 5 will also be dispersed above the edge E1 and above the edge E2, so it is difficult to generate a large step difference. Moreover, in the present embodiment, the edge E1 is located below the axial layer 64 of the partition wall 6. Therefore, the step difference of the rib 5 caused by the edge E1 is covered by the axial layer 64. Therefore, in the present embodiment, the interruption of the upper electrode UE1 and the generation of cracks in the rib 5 can be suppressed, thereby improving the yield. In addition, the lower electrodes LE2, LE3 and the substrate electrodes BE2, BE3 also produce the same effect.

[0136] In addition, for example, when the second reflective layer RF2 is formed of silver, it is difficult to process the lower electrodes LE1, LE2, and LE3 by dry etching. On the other hand, when the lower electrodes LE1, LE2, and LE3 are processed by wet etching, the end faces of the lower electrodes LE1, LE2, and LE3 are eroded, so that the width becomes smaller than the resist used as a mask. Therefore, it is difficult to fully reduce the interval between adjacent lower electrodes LE1, LE2, and LE3, and about 5 μm becomes the minimum interval in reality. As a result, the high-definition of the display device DSP is limited.

[0137] On the other hand, in this embodiment, the base electrodes BE1, BE2, and BE3 are processed by dry etching. In this case, the outer shapes of the base electrodes BE1, BE2, and BE3 can be formed with good precision. In one example, the interval between the base electrodes BE1, BE2, and BE3 can be made less than 3 μm. As a result, the anodes (base electrodes and lower electrodes) of the display elements DE1, DE2, and DE3 can be arranged at a narrow pitch, thereby realizing a high-definition display device DSP.

[0138] When the organic insulating layer 12 is exposed from the base electrodes BE1, BE2, BE3 and the lower electrodes LE1, LE2, LE3 at the pixel openings AP1, AP2, AP3 of the rib 5, the organic insulating layer 12 may be corroded by etching or the like when the display elements DE1, DE2, DE3 are formed. Therefore, it is preferred that the pixel openings AP1, AP2, AP3 overlap with the base electrodes BE1, BE2, BE3 or the lower electrodes LE1, LE2, LE3 as a whole.

[0139] Assuming that there are no base electrodes BE1, BE2, BE3, the lower electrodes LE1, LE2, LE3 need to reliably overlap with the pixel openings AP1, AP2, AP3. At this time, considering the positional offset between the pixel openings AP1, AP2, AP3 and the lower electrodes LE1, LE2, LE3, it is necessary to ensure a sufficient margin between the edge E2 of the lower electrodes LE1, LE2, LE3 and the pixel openings AP1, AP2, AP3. As a result, the size of the pixel openings AP1, AP2, AP3 is limited, and it is difficult to increase the aperture ratio.

[0140] In contrast, in this embodiment, as described above, the base electrodes BE1, BE2, and BE3 can be arranged at a narrow pitch. In addition, the margin can be determined based on the edge E1 of the base electrodes BE1, BE2, and BE3. Therefore, compared with the case where there are no base electrodes BE1, BE2, and BE3, the pixel openings AP1, AP2, and AP3 can be increased, thereby improving the aperture ratio.

[0141] It should be noted that the edge E2 of the lower electrodes LE1, LE2, and LE3 does not necessarily need to be as Figure 5 As shown in the figure, the ribs 5 are covered. As another example, at least a part of the edge E2 of the lower electrodes LE1, LE2, LE3 may not be covered by the ribs 5.

[0142] Here, the result of verifying the reflectivity of an anode in which a base electrode and a lower electrode are stacked will be described.

[0143] Fig.13 : is a graph showing the result of simulating the relationship between the reflectance of the anode and the wavelength. In this simulation, the reflectance was obtained for each of the cases where five types of laminates, namely samples A1 to A5, were arranged on the ribs 5 formed of silicon oxide.

[0144] Sample A1 is composed of a 100nm silver layer (Ag). Sample A2 is composed of a 50nm silver layer. Sample A3 is a laminated body in which a 50nm silver layer is arranged on a 30nm aluminum layer (Al). Sample A4 is a laminated body in which a 7nm ITO layer and a 50nm silver layer are arranged in sequence on a 30nm aluminum layer. Sample A5 is a laminated body in which a 5nm titanium nitride layer (TiN), a 7nm ITO layer and a 30nm silver layer are arranged in sequence on a 30nm aluminum layer. R, G, and B in the figure represent the wavelength regions of red, green, and blue, respectively.

[0145] Comparing samples A1 and A2, it can be seen that the thicker the silver layer, the higher the reflectivity in any wavelength region of red, green and blue. In samples A3, A4 and A5 including an aluminum layer, the silver layer is equal to or lower than that of sample A2. However, the reflectivity of samples A3, A4 and A5 in any wavelength region of red, green and blue is improved to a level that is not inferior to that of sample A1. That is, in the case where the base electrodes BE1, BE2 and BE3 include the first reflective layer RF1 of aluminum and the lower electrodes LE1, LE2 and LE3 include the second reflective layer RF2 of silver, good reflectivity can be obtained even if the second reflective layer RF2 is thin.

[0146] Fig.14 This is a graph showing the results of simulating the relationship between the thickness of the silver layer and the reflectivity in a laminated body in which a silver layer is arranged on a 30nm aluminum layer. The simulation was performed for red wavelength (R: 620nm), green wavelength (G: 530nm), and blue wavelength (B: 460nm). The graph also plots the reflectivity in the case of a 50nm aluminum layer alone and the reflectivity in the case of a 100nm silver layer alone.

[0147] The reflectivity of red wavelengths gradually increases until the thickness of the silver layer reaches about 50nm, but there is almost no change even if the thickness is further increased. In addition, the reflectivity of green wavelengths gradually increases until the thickness of the silver layer reaches about 40nm, but there is almost no change even if the thickness is further increased. The reflectivity of blue wavelengths gradually increases until the thickness of the silver layer reaches about 20nm, and gradually decreases when the thickness is further increased.

[0148] According to the simulation results, the thickness of the second reflective layer RF2 made of silver is preferably in the range of 20 to 50 nm, for example. Within such a range, a good reflectivity can be achieved at the wavelength of each color.

[0149] Fig.15 This is a graph showing the results of simulating the relationship between the thickness of the ITO layer and the reflectivity in a laminated body having a 30nm aluminum layer, an ITO layer, and a 30nm silver layer arranged in order from the bottom. The simulation was performed for red wavelength (R: 620nm), green wavelength (G: 530nm), and blue wavelength (B: 460nm).

[0150] In any wavelength of red, green, and blue, the reflectance decreases as the thickness of the ITO layer increases. Therefore, the second transparent oxide layer CL2 formed of ITO is preferably as thin as possible.

[0151] Fig.16This is a graph showing the results of simulating the relationship between the thickness of the titanium nitride layer and the reflectivity in a laminated body having a 30nm aluminum layer, a titanium nitride layer, a 7nm ITO layer, and a 30nm silver layer arranged in that order from the bottom. The simulation was performed for the red wavelength (R: 620nm), the green wavelength (G: 530nm), and the blue wavelength (B: 460nm).

[0152] In any wavelength of red, green, and blue, the reflectivity decreases as the thickness of the titanium nitride layer increases. Therefore, it is preferable that the first metal layer ML1 formed of titanium nitride is as thin as possible.

[0153] Fig.17 This is a graph showing the results of simulating the relationship between the thickness of the silver layer and the reflectivity in a laminated body having a 30nm aluminum layer, a 5nm titanium nitride layer, a 7nm ITO layer, and a silver layer arranged in order from the bottom. The simulation was performed for red wavelength (R: 620nm), green wavelength (G: 530nm), and blue wavelength (B: 460nm). The graph also plots the reflectivity in the case of only a 50nm aluminum layer and the reflectivity in the case of only a 100nm silver layer.

[0154] At any wavelength of red, green, and blue, the reflectivity increases as the thickness of the silver layer increases. However, if the thickness of the silver layer exceeds 50 nm, the change in reflectivity decreases. Fig.14 When the thickness of the silver layer is 20 to 50 nm as described above, the reflectivity at each wavelength is considered to be in the same range as that of a single silver layer of 100 nm.

[0155] Based on the above Figures 13 to 17 The simulation results shown in Figure 6 As in the example of the present invention, the first reflective layer RF1 of aluminum and the second reflective layer RF2 of silver are overlapped, as shown in FIG. Figure 7 The second transparent oxide layer CL2 of ITO is arranged between the reflective layers RF1 and RF2. Figure 8 and Fig. 9 In each of the structures in which the second transparent oxide layer CL2 of ITO and the first metal layer ML1 of titanium nitride are arranged between the reflective layers RF1 and RF2 in this manner, good reflectivity can be achieved.

[0156] [Second embodiment]

[0157] The second embodiment is described. In this embodiment, the steps of forming the base electrodes BE1, BE2, BE3 and the lower electrodes LE1, LE2, LE3 are disclosed. Fig.10 The configuration of the display device DSP and the manufacturing process other than the process PR2 are the same as those of the first embodiment.

[0158] and FIG. 11A to FIG. 11G In the present embodiment, it is assumed that the substrate electrodes BE1, BE2, BE3 and the lower electrodes LE1, LE2, LE3 also have Fig. 9 In step PR2 of this embodiment, first Fig.11A Similarly, the first layer L1 and the second layer L2 are formed on the organic insulating layer 12. Fig. 11B Similarly, the resist R1 is disposed on the second layer L2. FIG. 11C to FIG. 11E By the same first etching, the second layer L2 is patterned into the shape of the lower electrodes LE1, LE2, and LE3. In the present embodiment, the resist R1 is removed after the first etching and before the second etching.

[0159] Fig.18A and Fig.18B 2 is a schematic cross-sectional view showing the second etching process of this embodiment. After removing the resist R1 (first resist), Fig.18A As shown in FIG. 1 , a resist R2 (second resist) is disposed. The resist R2 is patterned into the shape of the base electrodes BE1 , BE2 , and BE3 .

[0160] The resist R2 entirely covers the lower electrodes LE1, LE2, and LE3 formed by the first etching. Furthermore, the resist R2 also covers the first layer L1 around the lower electrodes LE1, LE2, and LE3.

[0161] The second etching is performed using the resist R2 as a mask. Fig.18B As shown, the portion of the first layer L1 exposed from the resist R2 is removed. Thus, the first layer L1 is patterned into the shape of the base electrodes BE1, BE2, and BE3. After the second etching, the resist R2 is removed.

[0162] When both the first layer L1 and the second layer L2 are processed using the resist R1 as in the first embodiment, the resist R1 is corroded in the first etching, and the base electrodes BE1, BE2, and BE3 may not be formed into the designed shape in the second etching. In contrast, if the resist R1 is removed after the first etching and another resist R2 is formed as in the present embodiment, the base electrodes BE1, BE2, and BE3 can be formed with good accuracy.

[0163] It should be noted that, in this embodiment, since different resists are used in the first etching and the second etching, the relative positional relationship between the lower electrodes LE1, LE2, LE3 and the base electrodes BE1, BE2, BE3 may be deviated. In addition, compared with the first embodiment, the steps for forming and removing the resist R2 are added. From the viewpoint of suppressing these, the manufacturing process of the first embodiment is advantageous.

[0164] It should be noted that, by using the manufacturing process of this embodiment, the base electrodes BE1, BE2, BE3 and the lower electrodes LE1, LE2, LE3 may be intentionally offset from each other. This modification example will be described below.

[0165] Fig.19 is a diagram for explaining this modification example, and Figure 5 Similarly, a schematic cross section of a plurality of sub-pixels SP1 arranged in the Y direction is shown. Here, the right edge of the base electrode BE1 in the figure is referred to as the first edge E1a, and the left edge in the figure is referred to as the second edge E1b. In addition, the right edge of the lower electrode LE1 in the figure is referred to as the first edge E2a, and the left edge in the figure is referred to as the second edge E2b. Furthermore, the right partition wall 6 in the figure is referred to as the first partition wall 6a, and the left partition wall 6 in the figure is referred to as the second partition wall 6b.

[0166] exist Fig.19 In the example of , the upper electrode UE1 contacts the bottom layer 63 of the first partition wall 6a, but does not contact the bottom layer 63 of the second partition wall 6b. Such an upper electrode UE1 can be formed by tilting the evaporation source that emits the material of the upper electrode UE1 relative to the Z direction. According to such a configuration, the upper electrode UE1 can be well connected to at least the first partition wall 6a.

[0167] It should be noted that the upper electrode UE1 may slightly contact the lower portion 61 of the second partition wall 6b. In this case, the contact area between the upper electrode UE1 and the first partition wall 6a may be larger than the contact area between the upper electrode UE1 and the lower portion 61 of the second partition wall 6b.

[0168] exist Fig.19 In the example, the first edges E1a and E2a are aligned. These first edges E1a and E2a are located below the first partition wall 6a. As a result, near the first partition wall 6a, it is not easy to generate a step difference caused by the first edges E1a and E2a on the upper surface of the rib 5. That is, near the first partition wall 6a, the upper surface of the rib 5 is flat, which can suppress the upper electrode UE1 from being interrupted due to the above-mentioned step difference. Therefore, it is possible to ensure better conduction between the upper electrode UE1 and the first partition wall 6a.

[0169] On the other hand, Fig.19 In the example, the second edge E1b, E2b and Figure 5 The second partition wall 6b and the upper electrode UE1 do not necessarily need to be in conduction. Therefore, even if a step difference is generated on the upper surface of the rib 5 due to the second edge E2b, no particular problem will occur from the perspective of supplying power to the upper electrode UE1.

[0170] Fig.19 The structure shown can also be applied to sub-pixels SP2 and SP3. Fig.19 2 shows a structure in which the base electrode BE1 and the lower electrode LE1 are offset in the Y direction, but the base electrode BE1 and the lower electrode LE1 may be offset in the X direction.

[0171] Based on the display device and the manufacturing method thereof described above as the embodiments of the present invention, all display devices and the manufacturing methods thereof that can be implemented by those skilled in the art through appropriate design changes also belong to the scope of the present invention as long as they include the gist of the present invention.

[0172] Within the scope of the present invention, those skilled in the art can think of various variations, which also belong to the scope of the present invention. For example, for the above-mentioned embodiments, those skilled in the art appropriately perform an embodiment in which constituent elements are added, deleted or the design is changed, or perform an embodiment in which a process is added, omitted or the condition is changed, and as long as they have the gist of the present invention, they are included in the scope of the present invention.

[0173] In addition, regarding other effects brought about by the methods described in the above embodiments, effects that are clear from the description of this specification or effects that can be appropriately conceived by those skilled in the art are of course understood as effects brought about by the present invention.

Claims

1. A display device comprising: A substrate electrode comprising a first reflective layer; a lower electrode comprising a second reflective layer and disposed on the base electrode; and a rib portion covering an edge of the base electrode and having a pixel opening overlapping the lower electrode, in, The width of the base electrode is greater than that of the lower electrode.

2. The display device according to claim 1, wherein: The first reflective layer is formed of aluminum or an aluminum alloy.

3. The display device according to claim 1, wherein: The base electrode further includes at least one of a first metal layer covering an upper surface of the first reflective layer and a second metal layer covering a lower surface of the first reflective layer.

4. The display device according to claim 3, wherein: The first metal layer is formed of titanium nitride, The second metal layer is formed of titanium.

5. The display device according to claim 1, wherein: The second reflective layer is formed of silver.

6. The display device according to claim 1, wherein: The lower electrode further includes at least one of a first transparent oxide layer covering an upper surface of the second reflective layer and a second transparent oxide layer covering a lower surface of the second reflective layer.

7. The display device according to claim 6, wherein: The first transparent oxide layer and the second transparent oxide layer are formed of ITO or IZO.

8. The display device according to any one of claims 1 to 7, further comprising a partition wall surrounding the pixel opening, in, The partition wall comprises: a conductive lower portion disposed over the rib; and An upper portion has an end portion protruding from a side of the lower portion.

9. The display device according to claim 8, wherein: The edge of the base electrode overlaps with the lower portion in a plan view.

10. The display device according to claim 8, wherein: The edge of the lower electrode does not overlap with the lower portion in a plan view.

11. The display device according to claim 8, further comprising: An organic layer covering the lower electrode through the pixel opening and emitting light in response to application of a voltage; and An upper electrode covers the organic layer and contacts the lower portion.

12. A method for manufacturing a display device, comprising: forming a first layer including a first reflective layer, forming a second layer including a second reflective layer on the first layer, The second layer is subjected to a first etching to form a lower electrode, A base electrode having a larger width than that of the lower electrode is formed by performing a second etching on the first layer, A rib portion is formed to cover an edge portion of the base electrode and to have a pixel opening overlapping the lower electrode.

13. The method for manufacturing a display device according to claim 12, further comprising disposing a first resist on the second layer, in, In the first etching, the lower electrode is formed under the first resist by removing the portion of the second layer exposed from the first resist.

14. The method for manufacturing a display device according to claim 13, wherein: In the second etching, the portion of the first layer exposed from the first resist is removed, thereby forming the base electrode under the first resist.

15. The method for manufacturing a display device according to claim 13, further comprising: removing the first resist after the first etching, After removing the first resist, disposing a second resist of the first layer covering the lower electrode and the periphery of the lower electrode, In the second etching, the base electrode is formed under the second resist by removing the portion of the first layer exposed from the second resist.

16. The method for manufacturing a display device according to claim 12, wherein: The first etching includes wet etching of the second reflective layer. The second etching includes dry etching of the first reflective layer.

17. The method for manufacturing a display device according to claim 12, wherein: The first layer further includes at least one of a first metal layer covering an upper surface of the first reflective layer and a second metal layer covering a lower surface of the first reflective layer.

18. The method for manufacturing a display device according to claim 12, wherein: The second layer further includes at least one of a first transparent oxide layer covering an upper surface of the second reflective layer and a second transparent oxide layer covering a lower surface of the second reflective layer.

19. The method for manufacturing a display device according to claim 12, further comprising: A partition wall is formed, wherein the partition wall includes a conductive lower portion disposed on the rib portion and an upper portion having an end portion protruding from a side surface of the lower portion and surrounds the pixel opening.

20. The method for manufacturing a display device according to claim 19, further comprising: forming an organic layer that covers the lower electrode through the pixel opening and emits light in response to application of a voltage, An upper electrode is formed covering the organic layer and contacting the lower portion.

Images