Array substrate, display panel and display device

Abstract

The array substrate comprises a substrate body and a plurality of pixel driving circuit sets arranged on the substrate body, and the pixel driving circuit sets are arranged in an array mode in the first direction and the second direction. Wherein each pixel driving circuit group in the plurality of pixel driving circuit groups comprises two pixel driving circuits which are arranged along a first direction. The array substrate further comprises a first conducting layer and a second conducting layer, the pixel driving circuit comprises a capacitor, the capacitor comprises a first polar plate and a second polar plate, the first polar plate is located on the first conducting layer, and the second polar plate is located on the second conducting layer; and a first connecting pattern is connected between the second polar plates of the two pixel driving circuits in the pixel driving circuit group, and the first connecting pattern is positioned on the second conductive layer. Wherein the size of the first connection pattern in the second direction is smaller than the size of the second polar plate in the second direction.

Description

Array substrate, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display panels have gradually become one of the mainstreams in the display field due to their excellent performance such as low power consumption, high color saturation, wide viewing angle, thin thickness, and flexibility.

[0003] Summary of the Invention

[0004] In one aspect, an array substrate is provided, comprising: a substrate; and a plurality of pixel driving circuit groups disposed on the substrate, wherein the plurality of pixel driving circuit groups are arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting. Each of the plurality of pixel driving circuit groups includes two pixel driving circuits disposed along the first direction.

[0005] The array substrate further includes: a first conductive layer disposed on the substrate, and a second conductive layer and a power signal line disposed on a side of the first conductive layer away from the substrate. The pixel driving circuit includes: a driving transistor and a capacitor, the capacitor including: a first plate and a second plate, the first plate being connected to the gate of the driving transistor, and the second plate being connected to the power signal line; wherein the first plate is located in the first conductive layer, and the second plate is located in the second conductive layer; a first connection pattern is connected between the second plates of two pixel driving circuits in the pixel driving circuit group, and the first connection pattern is located in the second conductive layer. wherein the size of the first connection pattern in the second direction is smaller than the size of the second plate in the second direction.

[0006] In some embodiments, a ratio of a size of the first connection pattern in the second direction to a size of the second electrode plate in the second direction is in a range of 10% to 50%.

[0007] In some embodiments, a size of the first connection pattern in the second direction ranges from 2.0 μm to 5.5 μm.

[0008] In some embodiments, the array substrate further comprises: a shielding layer disposed between the substrate and the first conductive layer. The shielding layer comprises a plurality of shielding patterns; along the first direction, between at least two adjacent pixel driving circuit groups, and between the shielding patterns of two adjacent pixel driving circuits, a second connection pattern is connected, and the second connection pattern is located in the shielding layer. The array substrate further comprises: a second semiconductor layer, the second semiconductor layer being located on a side of the second conductive layer away from the substrate. The orthographic projection of the second connection pattern on the substrate overlaps with the orthographic projection of the second semiconductor layer on the substrate.

[0009] In some embodiments, a third gate dielectric layer and a third insulating layer are provided on a side of the second semiconductor layer away from the substrate. The third gate dielectric layer and the third insulating layer are provided with at least one first via hole, the at least one first via hole penetrating the third gate dielectric layer and the third insulating layer to the second semiconductor layer, and an orthographic projection of the at least one first via hole on the substrate overlaps with an orthographic projection of the second connection pattern on the substrate.

[0010] In some embodiments, the array substrate further comprises a shielding layer disposed between the substrate and the first conductive layer. The shielding layer comprises a plurality of shielding patterns. In the pixel driving circuit group, a third connection pattern is connected between the shielding patterns of two pixel driving circuits, and the third connection pattern is located in the shielding layer. The orthographic projection of the first connection pattern on the substrate overlaps with the orthographic projection of the third connection pattern on the substrate by greater than 70%.

[0011] In some embodiments, the array substrate further comprises: a fourth conductive layer disposed on a side of the second conductive layer away from the substrate, and a first initialization signal line and a second initialization signal line located on the fourth conductive layer. The orthographic projections of the first initialization signal line and the second initialization signal line on the substrate overlap with the orthographic projection of the first conductive layer on the substrate.

[0012] In some embodiments, in each of the pixel driving circuits, an overlapping area between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the first conductive layer on the substrate is greater than an overlapping area between the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the first conductive layer on the substrate.

[0013] In some embodiments, in each of the pixel driving circuits, a ratio of an overlapping area between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the first conductive layer on the substrate to an overlapping area between the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the first conductive layer on the substrate is greater than 1.5.

[0014] In some embodiments, the array substrate includes a reset signal line located in the first conductive layer, and the first initialization signal line, the second initialization signal line, and an orthographic projection of the reset signal line on the substrate overlap.

[0015] In some embodiments, the array substrate includes: the shielding layer disposed on one side of the substrate, and a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer disposed sequentially away from the shielding layer. The first semiconductor layer is made of low-temperature polysilicon, and the second semiconductor layer is made of indium gallium zinc oxide.

[0016] In some embodiments, the array substrate further comprises: a shielding layer disposed between the substrate and the first conductive layer, the shielding layer comprising a plurality of shielding patterns; a second connection pattern connected between the shielding patterns of at least two adjacent pixel driving circuit groups along the first direction, the second connection pattern being located on the shielding layer. The array substrate further comprises: a light-emitting control signal line.

[0017] The pixel driving circuit further includes: a second light-emitting control transistor, the gate of the second light-emitting control transistor being connected to the light-emitting control signal line, and the first electrode of the second light-emitting control transistor being connected to the second electrode of the driving transistor. Between two adjacent pixel driving circuit groups, the area between the first electrodes of two adjacent second light-emitting control transistors and between the second connection pattern and the light-emitting control signal line is a first light-transmitting area, and the area of ​​the first light-transmitting area is greater than 10 μm 2 .

[0018] In some embodiments, the array substrate further includes: a first initialization signal line and a light-emission control signal line. The pixel driving circuit further includes: a first reset transistor, a second light-emission control transistor, and a second reset transistor, wherein the first electrode of the first reset transistor is connected to the first initialization signal line, the second electrode of the first reset transistor is connected to the first electrode of the second light-emission control transistor, and the second electrode of the second light-emission control transistor is connected to the second electrode of the second reset transistor. The first electrode of the second light-emission control transistor is connected to the second electrode of the driving transistor, and the gate of the second light-emission control transistor is connected to the light-emission control signal line.

[0019] The area between two adjacent pixel driving circuit groups, between the second electrodes of two adjacent second light emission control transistors, and between the first initialization signal line and the light emission control signal line is a second light transmission area, and the area of ​​the second light transmission area is greater than 10 μm 2 .

[0020] On the other hand, an array substrate is provided, comprising: a substrate, and a plurality of pixel driving circuit groups disposed on the substrate, wherein the plurality of pixel driving circuit groups are arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting; wherein each pixel driving circuit group comprises: two pixel driving circuits disposed along the first direction. The array substrate further comprises: a first conductive layer disposed on the substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, and a fifth conductive layer. The pixel driving circuit comprises: a driving transistor and a capacitor, wherein the capacitor comprises: a first plate and a second plate, the first plate being connected to the gate of the driving transistor, and the second plate being connected to the fifth conductive layer.

[0021] The first electrode is located in the first conductive layer, and the second electrode is located in the second conductive layer; a first connection pattern is connected between the second electrodes of the two pixel driving circuits in the pixel driving circuit group, and the first connection pattern is located in the second conductive layer; the size of the first connection pattern in the second direction is smaller than the size of the second electrode in the second direction.

[0022] In some embodiments, the array substrate further includes: a second scanning signal line, and the pixel driving circuit further includes: a compensation transistor, the first electrode of the compensation transistor is connected to the gate of the driving transistor, the second electrode of the compensation transistor is connected to the second electrode of the driving transistor through a first pattern, and the gate of the compensation transistor is connected to the second scanning signal line.

[0023] The array substrate further includes: the shielding layer disposed on the base, and a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer disposed sequentially in a direction away from the shielding layer. The active layer of the drive transistor is located in the first semiconductor layer; the second scan signal line is at least partially located in the third conductive layer; the active layer of the compensation transistor is located in the second semiconductor layer; and the first pattern is located in the fourth conductive layer.

[0024] In some embodiments, the first pattern is connected to the second electrode of the driving transistor through a third via, the first conductive pattern is also connected to the second electrode of the compensation transistor through a first via, and the first connection pattern does not overlap with the first via and the third via.

[0025] In some embodiments, the blocking layer includes multiple blocking patterns; along the first direction, between at least two adjacent pixel driving circuit groups, a second connection pattern is connected between the blocking patterns of two adjacent pixel driving circuits, and the second connection pattern is located in the blocking layer; the second connection pattern does not overlap with the third via.

[0026] In some embodiments, the shielding pattern and the second connection pattern are used to receive a constant voltage signal.

[0027] On the other hand, a display panel is provided, comprising: an array substrate as described in any of the above embodiments, the display panel further comprising a plurality of light-emitting devices, which are arranged on a plurality of pixel driving circuits of the array substrate, and the array substrate is used to drive the plurality of light-emitting devices to emit light.

[0028] On the other hand, a display device is provided, comprising: a display panel as described in any of the above embodiments, and further comprising a driving chip for driving the display panel to display. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0030] FIG1 is a structural diagram of a mobile phone provided according to some embodiments of the present disclosure;

[0031] FIG2 is a structural diagram of a display panel provided according to some embodiments of the present disclosure;

[0032] FIG3A is an equivalent circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure;

[0033] FIG3B is a timing diagram of a pixel driving circuit according to some embodiments of the present disclosure;

[0034] FIG4 is a structural diagram of a first conductive layer, a second conductive layer, and a second semiconductor layer stacked according to some embodiments of the present disclosure;

[0035] 5 is a structural diagram of a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, and a second semiconductor layer after being stacked according to some embodiments of the present disclosure;

[0036] FIG6 is a structural diagram of the shielding layer, the first conductive layer, the second conductive layer, and the second semiconductor layer provided at CC of the array substrate provided in FIG5 after being superimposed;

[0037] FIG7A is a structural diagram of a shielding layer provided according to some embodiments of the present disclosure;

[0038] 7B is a structural diagram of a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer stacked according to some embodiments of the present disclosure;

[0039] 7C is another structural diagram of the shielding layer, the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, and the third conductive layer provided by some embodiments of the present disclosure;

[0040] 7D is another structural diagram of the shielding layer, the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, and the third conductive layer stacked according to some embodiments of the present disclosure;

[0041] 7E is another structural diagram of the shielding layer, the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, and the third conductive layer stacked according to some embodiments of the present disclosure;

[0042] FIG8 is a structural diagram of a third conductive layer provided according to some embodiments of the present disclosure;

[0043] FIG9 is a structural diagram of a fourth conductive layer provided according to some embodiments of the present disclosure;

[0044] FIG10 is a structural diagram of a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer provided by some embodiments of the present disclosure after being superimposed;

[0045] FIG11 is a structural diagram of a shielding layer, a first conductive layer, and a fourth conductive layer stacked according to some embodiments of the present disclosure;

[0046] Figure 12 is a structural diagram of the superposition of the blocking layer, the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer provided according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0050] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0051] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0052] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0053] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0054] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0055] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0056] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0057] As shown in FIG1 , some embodiments of the present disclosure provide a display device. The display device provided by the embodiments of the present disclosure can be any device that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images. More specifically, it is expected that the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0058] As shown in FIG1 , the embodiment of the present disclosure is exemplified by taking a mobile phone 1000 as the display device.

[0059] As shown in FIG2 , the mobile phone 1000 includes a display panel 100 , a frame, a circuit board, a driver chip, and other electronic components. The display panel 100 is disposed in the frame, and the driver chip is used to drive the display panel 100 for display.

[0060] For example, as shown in FIG2 , taking the display panel 100 as an OLED (Organic Light-Emitting Diode) display panel, the display panel 100 includes an array substrate 1 and a light-emitting device stack 2. The array substrate 1 includes a base 101 and a pixel circuit stack 30, which is disposed on the base 101.

[0061] For example, the material of the substrate 101 may include any one of glass, metal, or flexible material.

[0062] The pixel circuit stack 30 is formed with multiple pixel driving circuits 10. For example, the pixel circuit stack 30 includes: a blocking layer 11, a first semiconductor layer 13, a first conductive layer 15, a second conductive layer 17, a second semiconductor layer 61, a third conductive layer 62, a fourth conductive layer 19 and a fifth conductive layer 21 stacked in sequence.

[0063] Exemplarily, the material of the first semiconductor layer 13 includes low-temperature polysilicon. The material of the second semiconductor layer 61 includes indium gallium zinc oxide.

[0064] It should be noted that an insulating layer is provided between the functional film layers of the array substrate 1. The functional film layers include: a shielding layer 11, a first semiconductor layer 13, a first conductive layer 15, a second conductive layer 17, a second semiconductor layer 61, a third conductive layer 62, a fourth conductive layer 19, and a fifth conductive layer 21.

[0065] 2 , the insulating layer includes a first insulating layer 102 , a first gate dielectric layer 103 , a second gate dielectric layer 104 , a second insulating layer 105 , a third gate dielectric layer 106 , a third insulating layer 107 , a passivation layer 108 , a first planarization layer 109 and a second planarization layer 110 .

[0066] For example, the pixel circuit stack 30 includes a blocking layer 11, a first insulating layer 102, a first semiconductor layer 13, a first gate dielectric layer 103, a first conductive layer 15, a second gate dielectric layer 104, a second conductive layer 17, a second insulating layer 105, a second semiconductor layer 61, a third gate dielectric layer 106, a third conductive layer 62, a third insulating layer 107, a fourth conductive layer 19, a passivation layer 108, a first planarization layer 109, a fifth conductive layer 21 and a second planarization layer 110, which are stacked in sequence.

[0067] Exemplarily, the material of the first planarization layer 109 and the second planarization layer 110 includes polyimide, and the material of the first insulating layer 102 , the second insulating layer 105 , and the third insulating layer 107 includes any one of silicon nitride and silicon oxide.

[0068] In some embodiments, the pixel driving circuit 10 in some embodiments of the present disclosure can be a 7T1C, 8T1C or 9T1C circuit, where T represents a transistor, and the number before T represents the number of transistors, C represents a capacitor, and the number before C represents the number of capacitors. For example, 7T1C represents 7 transistors and 1 capacitor.

[0069] In some embodiments, the structure of the pixel driving circuit 10 shown in FIG3A is described. The pixel driving circuit 10 is a 7T1C pixel driving circuit. The pixel driving circuit 10 includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first emission control transistor T5, a second emission control transistor T6, and a second reset transistor T7.

[0070] For example, as shown in FIG3A , the first reset transistor T1 includes a gate, a first electrode, and a second electrode T12. The gate of the first reset transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1, and the second electrode T12 of the first reset transistor T1 is electrically connected to the third node N3. The first reset transistor T1 is configured to reset the gate of the driving transistor T3 in response to a reset signal received at the first reset signal line Reset1.

[0071] Exemplarily, as shown in FIG3A , the compensation transistor T2 includes a gate, a first electrode T21, and a second electrode T22. The gate of the compensation transistor T2 is electrically connected to the second scan signal line Gate2, the first electrode T21 of the compensation transistor T2 is electrically connected to the first node N1, and the second electrode T22 of the compensation transistor T2 is electrically connected to the third node N3. The compensation transistor T2 is configured to reset or threshold-compensate the driving transistor T3 in response to a scan signal received at the second scan signal line Gate2.

[0072] Exemplarily, as shown in FIG3A , the driving transistor T3 includes a gate T33, a first electrode, and a second electrode T32. The gate T33 of the driving transistor T3 is electrically connected to the first node N1, the first electrode of the driving transistor T3 is electrically connected to the second node N2, and the second electrode T32 of the driving transistor T3 is electrically connected to the third node N3. The driving transistor T3 is configured to generate a driving current signal.

[0073] Exemplarily, as shown in FIG3A , the data write transistor T4 includes a gate, a first electrode, and a second electrode. The gate of the data write transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the data write transistor T4 is electrically connected to the data signal line Data, and the second electrode of the data write transistor T4 is electrically connected to the second node N2. The data write transistor T4 is configured to transmit a data signal received on the data signal line Data to the driving transistor T3 in response to a scan signal received on the first scan signal line Gate1.

[0074] Exemplarily, as shown in FIG3A , the first emission control transistor T5 includes a gate, a first electrode, and a second electrode. The gate of the first emission control transistor T5 is electrically connected to the emission control signal line EM, the first electrode of the first emission control transistor T5 is electrically connected to the power signal line ELVDD, and the second electrode of the first emission control transistor T5 is electrically connected to the second node N2. The first emission control transistor T5 is configured to transmit a power signal received on the power signal line ELVDD to the driving transistor T3 in response to the emission control signal received on the emission control signal line EM.

[0075] Exemplarily, as shown in FIG3A , the second emission control transistor T6 includes a gate, a first electrode, and a second electrode. The gate of the second emission control transistor T6 is electrically connected to the emission control signal line EM, the first electrode of the second emission control transistor T6 is electrically connected to the third node N3, and the second electrode of the second emission control transistor T6 is electrically connected to the fourth node N4. The second emission control transistor T6 is configured to transmit a driving current signal to the light-emitting device L in response to a light-emitting control signal received on the light-emitting control signal line EM, thereby driving the light-emitting device L to emit light.

[0076] For example, as shown in FIG3A , the second reset transistor T7 includes a gate, a first electrode, and a second electrode. The gate of the second reset transistor T7 is electrically connected to the second reset signal line Reset2, the first electrode of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2, and the second electrode of the second reset transistor T7 is electrically connected to the fourth node N4. The second reset transistor T7 is configured to, in response to a reset signal received at the second reset signal line Reset2, transmit an initialization signal received at the second initialization signal line Vinit2 to the light-emitting device L to reset the light-emitting device L.

[0077] Exemplarily, the anode of the light emitting device L is electrically connected to the fourth node N4, and the cathode of the light emitting device L is electrically connected to the reference voltage line ELVSS.

[0078] It should be noted that the first electrode of the transistor disclosed herein is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.

[0079] In the circuit provided by the embodiments of the present disclosure, nodes do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0080] It should be noted that the plurality of pixel driving circuit groups 12 are arranged in multiple rows along the second direction Y. The first reset signal line Reset1 connected to the gate of the first reset transistor T1 in the current row can be the same reset signal line Reset as the second reset signal line Reset2 connected to the gate of the second reset transistor T7 in the previous row (as shown in FIG4 ). That is, when a reset signal line Reset is turned on, the reset signal line Reset simultaneously transmits a reset signal to the first reset transistor T1 in the current row and the second reset transistor T7 in the previous row.

[0081] Exemplarily, as shown in FIG3A , the pixel driving circuit 10 further includes a capacitor Cst, the capacitor Cst including a first plate Cst1 and a second plate Cst2, the first plate Cst1 of the capacitor Cst is electrically connected to the first node N1, and the second plate Cst2 of the capacitor Cst is electrically connected to the power signal line ELVDD.

[0082] In some embodiments, the pixel driving circuit 10 adopts an LTPO (Low Temperature Polycrystalline Oxide) circuit, that is, a pixel driving circuit 10 includes both a low-temperature polycrystalline silicon (LTPS) thin film transistor and an oxide thin film transistor. The low-temperature polycrystalline silicon thin film transistor has a strong load capacity, and the oxide thin film transistor has a small off-state current and a stronger charge retention ability than the low-temperature polycrystalline silicon thin film transistor. In this way, the pixel driving circuit 10 can achieve higher charge mobility and better stability.

[0083] For example, the compensation transistor T2 can be an oxide thin film transistor, and is an N-type transistor, that is, it is turned on at a high level. The first reset transistor T1, the drive transistor T3, the data write transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7 are all low-temperature polysilicon thin film transistors (LTPTs) P-type transistors, and are turned on at a low level. Using an oxide thin film transistor for the compensation transistor T2 can effectively prevent leakage from the first node N1.

[0084] Exemplarily, the first semiconductor layer 13, the first conductive layer 15, and the second conductive layer 17 form a first reset transistor T1, a drive transistor T3, a data write transistor T4, a first emission control transistor T5, a second emission control transistor T6, a second reset transistor T7, and a capacitor Cst in the LTPO circuit. The second semiconductor layer 61 and the third conductive layer 62 form a compensation transistor T2.

[0085] It should be noted that the above examples of the first reset transistor T1 , compensation transistor T2 , drive transistor T3 , data writing transistor T4 , first emission control transistor T5 , second emission control transistor T6 and second reset transistor T7 do not constitute a limitation on transistor types.

[0086] 3B , the timing diagram of the pixel driving circuit 10 includes three phases: an initialization phase t1 , a data writing and Vth compensation phase t2 , and an emission phase t3 .

[0087] Initialization stage t1: the first reset signal line Reset1 is at a low level, the light-emitting control signal line EM and the second scanning signal line Gate2 are at a high level, the first reset transistor T1 and the compensation transistor T2 are turned on, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off, and the voltage of the first initialization signal line Vinit1 is written into the N1 power saving transistor through the first reset transistor T1 and the compensation transistor T2 to initialize it.

[0088] In the data writing and Vth compensation phase t2, the first reset signal line Reset1 is at a high level, and the signal transmitted by the first initialization signal line Vinit1 is turned off. The first scan signal line Gate1 is at a low level, and the data signal on the data signal line Data passes through the data writing transistor T4, the driving transistor T3, and the compensation transistor T2 and is written into the N1 node, thereby compensating the Vth of the driving transistor T3.

[0089] In the emission phase t3, the second scanning signal line Gate2 is at a low level, the emission control signal line EM is at a low level, the compensation transistor T2 is turned off, and the first emission control transistor T5 and the second emission control transistor T6 are turned on to enter the emission phase.

[0090] As shown in FIG2 , a light-emitting device stack 2 is formed with a plurality of light-emitting devices L, which are disposed on a plurality of pixel driving circuits 10 of an array substrate 1. The array substrate 1 is used to drive the plurality of light-emitting devices L to emit light. The light-emitting device stack 2 includes: an anode layer 202, a pixel defining layer 201, a light-emitting functional layer 203, and a cathode layer 204, which are sequentially stacked on a side of the pixel circuit stack 30 away from the substrate 101.

[0091] In some embodiments, the mobile phone 1000 also includes components such as a camera, various sensors, and a speaker.

[0092] In order to achieve full-screen display, it is necessary to integrate the photosensitive component under the display panel 100, and the photosensitive component collects light from the front of the display panel 100. The photosensitive component is, for example, a camera, and accordingly, this technology is called under-screen camera technology; the photosensitive component is, for example, a fingerprint sensor, and accordingly, this technology is called under-screen fingerprint recognition technology. The realization of under-screen camera technology and under-screen fingerprint recognition technology has certain requirements for the light transmittance of the display screen. However, in the display screen, the arrangement of the various film layers used to form the pixel drive circuit 10 affects the light transmittance of the screen, thereby affecting the shooting effect and fingerprint recognition effect of the display screen.

[0093] To address the above issues, as shown in FIG. 2 and FIG. 4 , some embodiments of the present disclosure provide an array substrate 1 , comprising a substrate 101 and a plurality of pixel driving circuit groups 12 disposed on the substrate 101 . The plurality of pixel driving circuit groups 12 are arranged in an array along a first direction X and a second direction Y. Each of the plurality of pixel driving circuit groups 12 comprises two pixel driving circuits 10 disposed along the first direction X.

[0094] The first direction X and the second direction Y intersect, and both the first direction X and the second direction Y are parallel to the upper surface of the substrate 101. Exemplarily, the first direction X and the second direction Y are perpendicular to each other, the first direction X is the row direction in which the plurality of pixel driving circuit groups 12 are arranged, and the second direction Y is the column direction in which the plurality of pixel driving circuit groups 12 are arranged.

[0095] For example, as shown in FIG12 , two pixel driving circuits 10 are arranged as a pixel driving circuit group 12 , and the two data signal lines Data in one pixel driving circuit group 12 can be arranged adjacent to each other in the first direction X, and the two power signal lines ELVDD of the pixel driving circuit group 12 are arranged on both sides of the two data signal lines Data. That is, in one pixel driving circuit group 12 , the power signal line ELVDD, the data signal line Data, the data signal line Data, and the power signal line ELVDD are arranged in sequence along the first direction X. Based on this arrangement, in two adjacent pixel driving circuit groups 12 , the two adjacent power signal lines ELVDD can be connected to reduce the voltage drop of the power signal line ELVDD.

[0096] As shown in Figures 2 and 4 , the array substrate 1 provided in the embodiment of the present disclosure further includes: a first conductive layer 15 disposed on one side of a substrate 101 (shown in Figure 2 ), and a second conductive layer 17 disposed on a side of the first conductive layer 15 away from the substrate 101. The array substrate 1 further includes: a power signal line ELVDD (shown in Figure 12 ).

[0097] As shown in FIG4 , the pixel driving circuit 10 includes a driving transistor T3 and a capacitor Cst. The capacitor Cst includes a first plate Cst1 and a second plate Cst2. The first plate Cst1 is connected to the gate of the driving transistor T3, and the second plate Cst2 is connected to the power signal line ELVDD. As shown in FIG4 , the first plate Cst1 is located on the first conductive layer 15, and the second plate Cst2 is located on the second conductive layer 17.

[0098] Exemplarily, the first electrode plate Cst1 and the gate of the driving transistor T3 are an integrated structure.

[0099] Since the second plate Cst2 of the capacitor Cst of each pixel driving circuit 10 needs to be connected to the power signal line ELVDD, multiple second plates Cst2 of multiple capacitors Cst can be connected to reduce the voltage drop of the power signal provided by the power signal line ELVDD during transmission.

[0100] Based on this, a first connection pattern M1 is connected between the second plates Cst2 of two pixel driving circuits 10 in the pixel driving circuit group 12. The first connection pattern M1 is located on the second conductive layer 17. That is, the two adjacent second plates Cst are connected together through the first connection pattern M1.

[0101] A dimension d1 of the first connection pattern M1 in the second direction Y is smaller than a dimension d2 of the second electrode plate Cst2 in the second direction Y.

[0102] It should be noted that the dimension d1 of the first connection pattern M1 in the second direction Y refers to the maximum dimension of the first connection pattern M1 in the second direction Y, and the dimension d2 of the second electrode plate Cst2 in the second direction Y refers to the maximum dimension of the second electrode plate Cst2 in the second direction Y.

[0103] For example, the first connection pattern M1 is connected to the second electrode plate Cst2 of the two pixel driving circuits 10 in the pixel driving circuit group 12. Specifically, the first connection pattern M1 and the second electrode plate Cst2 of the two pixel driving circuits 10 in the pixel driving circuit group 12 are an integrated structure, which can simplify the structure and preparation process of the array substrate 1.

[0104] For example, as shown in FIG4 , in a pixel driver circuit group 12, a first connection pattern M1 connects the second plates Cst2 of two pixel driver circuits 10, and the two pixel driver circuits 10 can receive the same power signal. Since the first connection pattern M1 transmits the power signal within a pixel driver circuit group 12, the dimension d1 of the first connection pattern M1 in the second direction Y being smaller than the dimension d2 of the second plate Cst2 in the second direction Y does not affect the transmission of the power signal. Therefore, the dimension d1 of the first connection pattern M1 in the second direction Y can be set to be smaller than the dimension d2 of the second plate Cst2 in the second direction Y. This setting can increase the light transmittance of the region S1 between the two second plates Cst2 in a pixel driver circuit group 12.

[0105] In the embodiment of the present disclosure, by setting the dimension d1 of the first connection pattern M1 in the second direction Y to be smaller than the dimension d2 of the second electrode plate Cst2 in the second direction Y, the transmittance of the area S1 between the two second electrode plates Cst2 in a pixel driving circuit group 12 can be increased, thereby achieving the purpose of improving the light transmittance of the array substrate 1.

[0106] In some embodiments, as shown in FIG. 4 , a ratio of a dimension d1 of the first connection pattern M1 in the second direction Y to a dimension d2 of the second electrode plate Cst2 in the second direction Y is in a range of 10% to 50%.

[0107] Exemplarily, the ratio of the dimension d1 of the first connection pattern M1 in the second direction Y to the dimension d2 of the second electrode plate Cst2 in the second direction Y is 10%, 15%, 25%, 30%, 40% or 50%, etc., which is not limited here.

[0108] The ratio of the dimension d1 of the first connection pattern M1 in the second direction Y to the dimension d2 of the second electrode plate Cst2 in the second direction Y is set to be in the range of 10% to 50%. The first connection pattern M1 can not only connect the second electrodes Cst2 of two pixel driving circuits 10 in a pixel driving circuit group 12 to transmit power signals, but also improve the light transmittance of the array substrate 1.

[0109] In some examples, as shown in FIG. 4 , a dimension d1 of the first connection pattern M1 in the second direction Y ranges from 2.0 μm to 5.5 μm.

[0110] Exemplarily, as shown in FIG. 4 , a dimension d1 of the first connection pattern M1 in the second direction Y is 2.0 μm, 3.5 μm, 4.0 μm, 5.0 μm, or 5.5 μm, etc., which is not limited here.

[0111] For example, the dimension d1 of the first connection pattern M1 in the second direction Y shown in FIG4 is smaller than the dimension d2 of the second electrode Cst2 in the second direction Y, for example, d1 = 5.5 μm and d2 = 13.5 μm. In other examples, the dimension d1 of the first connection pattern M1 in the second direction Y is equal to the dimension d2 of the second electrode Cst2 in the second direction Y, for example, d1 = d2 = 13.5 μm. Compared with the two, in the layout design of a pixel driving circuit 10, in region S1, the area of ​​the second conductive layer 17 is reduced by approximately 26.9 μm. 2 In the array substrate 1 , the arrangement of the structure in the region S1 increases the light transmittance of the array substrate 1 by about 1.5%.

[0112] In some embodiments, as shown in Figures 2 and 5, and Figures 7A to 7E, the array substrate 1 includes a shielding layer 11 disposed between the base 101 and the first conductive layer 15. As shown in Figures 6 and 7A to 7E, the shielding layer 11 includes a plurality of shielding patterns 111.

[0113] The provision of the shielding layer 11 can prevent light from the side of the substrate 101 away from the shielding layer 11 from affecting the pixel driving circuit 10. As shown in Figure 6, the pixel driving circuit includes shielding patterns 111. Each shielding pattern 111 overlaps with the first plate Cst1 and the second plate Cst2 of the capacitor Cst. The first plate Cst1 and the gate of the driving transistor T3 are an integral structure, that is, the shielding pattern 111 overlaps with the gate of the driving transistor T3. The shielding pattern 111 can prevent light from the side of the substrate 101 away from the shielding pattern 111 from affecting the pixel driving circuit 10 (for example, the driving transistor T3).

[0114] Exemplarily, the shielding pattern 111 of each pixel driving circuit 10 is connected in the first direction X and the second direction Y to form a network structure, and the shielding pattern 111 is electrically connected to the reference voltage line ELVSS. As shown in FIG2 , the cathode layer 204 is used to transmit a reference voltage signal. Electrically connecting the shielding pattern 111 to the reference voltage line ELVSS, that is, connecting the shielding pattern 111 to the cathode layer 204, can reduce the resistance of the cathode layer 204, thereby reducing the voltage drop of the reference voltage line ELVSS.

[0115] Along the first direction X, a second connection pattern M2 is connected between at least two adjacent pixel driving circuit groups 12 and between the shielding patterns 111 of two adjacent pixel driving circuits 10. The second connection pattern M2 is located on the shielding layer 11. For example, the second connection pattern M2 and the shielding pattern 111 are an integrated structure, which can simplify the structure and manufacturing process of the array substrate 1.

[0116] As shown in Figures 2, 4, 5, and 6, the array substrate 1 further includes a second semiconductor layer 61, which is located on a side of the second conductive layer 17 away from the substrate 101. The orthographic projection of the second connection pattern M2 on the substrate 101 overlaps with the orthographic projection of the second semiconductor layer 61 on the substrate 101. The second semiconductor layer 61 includes an active layer pattern of the compensation transistor T2.

[0117] In some examples, as shown in Figure 6, along the first direction X, the pixel driving circuit group 12 located on the left is called the first pixel driving circuit group 121, and the pixel driving circuit group 12 located on the right is called the second pixel driving circuit group 122. The portion of the shielding layer 11 connected between the first pixel driving circuit group 121 and the second pixel driving circuit group 122 is a second connection pattern M2, which is used to transmit a fixed voltage signal, for example, the fixed voltage signal is a reference voltage signal.

[0118] The orthographic projection of the second connection pattern M2 on the substrate 101 overlaps with the orthographic projection of the second semiconductor layer 61 on the substrate 101, that is, the second connection pattern M2 is arranged between the second semiconductor layer 61 and the substrate 101, so that the light blocking area of ​​the second semiconductor layer 61 and the light blocking area of ​​the second connection pattern M2 partially overlap, thereby reducing the light blocking of the second connection pattern M2 and improving the light transmittance of the array substrate 1.

[0119] In some embodiments, as shown in FIG6 , along the first direction X, between two adjacent pixel driving circuit groups 12 , the orthographic projection of the second connection pattern M2 on the substrate 101 and the orthographic projection of the second semiconductor layer 61 on the substrate 101 overlap in an area S2 of 20 μm. 2 ~30μm 2 .

[0120] For example, as shown in Figures 2 and 6, in the pixel driving circuit 10 of the first pixel driving circuit group 121, the overlapping area of ​​the orthographic projection of the second connection pattern M2 on the substrate 101 and the orthographic projection of the second semiconductor layer 61 on the substrate 101 is represented as area S21. In the pixel driving circuit 10 of the second pixel driving circuit group 122, the overlapping area of ​​the orthographic projection of the second connection pattern M2 on the substrate 101 and the orthographic projection of the second semiconductor layer 61 on the substrate 101 is represented as area S22. The overlapping area S2 is the sum of the area S21 and the area S22, that is, S2 = S21 + S22.

[0121] For example, along the first direction X, between two adjacent pixel driving circuit groups 12, the overlap area S2 of the orthographic projection of the second connection pattern M2 on the substrate 101 and the orthographic projection of the second semiconductor layer 61 on the substrate 101 is 20 μm. 2 , 21μm 2, 23μm 2 , 25μm 2 , 27μm 2 , 29μm 2 or 30 μm 2 There is no limit here.

[0122] Exemplarily, as shown in FIG6 , by arranging the orthographic projection of the second connection pattern M2 on the substrate 101 to overlap with the orthographic projection of the second semiconductor layer 61 on the substrate 101 , the light transmittance of the array substrate 1 is increased by about 0.57%.

[0123] In some embodiments, by setting different connection modes of the shielding patterns 111 in the first direction X and the second direction Y, the light transmittance of the array substrate 1 can be improved.

[0124] As shown in FIG7A , multiple shielding patterns 111 are connected in a first direction X and a second direction Y to form a network structure. Between two adjacent pixel driving circuit groups 12, the connection pattern between adjacent shielding patterns 111 in the first direction X (referred to as a transverse connection pattern) includes one or more of the second connection patterns M21, M22, M23, and the fourth connection pattern F1. For ease of illustration, FIG7A illustrates the transverse connection patterns in a single figure. The connection pattern between adjacent shielding patterns 111 in the second direction is referred to as a longitudinal connection pattern F4. The longitudinal connection pattern F4 is strip-shaped and extends entirely along the second direction, connecting the two shielding patterns 111 at its ends.

[0125] Exemplarily, as shown in Figures 7A and 7B, the lateral connection pattern includes a first second connection pattern M21, and the orthographic projection of the first second connection pattern M21 on the substrate 101 overlaps with the orthographic projection of the second semiconductor layer 61 on the substrate 101. Specifically, the orthographic projection of the first second connection pattern M21 on the substrate 101 overlaps with the end of the active layer of the compensation transistor T2.

[0126] Exemplarily, as shown in Figures 7A and 7C, the transverse connection pattern includes a second type of second connection pattern M22. The orthographic projection of the second type of second connection pattern M22 on the substrate 101 overlaps with the orthographic projection of the second semiconductor layer 61 on the substrate 101. Specifically, the orthographic projection of the second type of second connection pattern M22 on the substrate 101 overlaps with the orthographic projection of the second scanning signal line Gate2 on the substrate 101. The second scanning signal line Gate2 includes a first sub-scanning signal line 2G2 located in the second conductive layer 17 and a second sub-scanning signal line 3G2 located in the third conductive layer 62. The first sub-scanning signal line 2G2 and the second sub-scanning signal line 3G2 are connected to form the second scanning signal line Gate2.

[0127] Exemplarily, as shown in FIG7A and FIG7D , the transverse connection pattern includes a third type of second connection pattern M23. The orthographic projection of the third type of second connection pattern M23 on the substrate 101 overlaps with the orthographic projection of the second semiconductor layer 61 on the substrate 101. Specifically, the orthographic projection of the third type of second connection pattern M23 on the substrate 101 overlaps with the other end of the active layer of the compensation transistor T2. Simultaneously, the orthographic projection of the third type of second connection pattern M23 on the substrate 101 also overlaps with the orthographic projection of the first scan signal line Gate1 on the substrate 101. The first scan signal line Gate1 is located on the first conductive layer 15.

[0128] For example, as shown in FIG7A and FIG7E , the lateral connection pattern includes a fourth connection pattern F1, the orthographic projection of the fourth connection pattern F1 on the substrate 101 overlaps with the orthographic projection of the first semiconductor layer 13 on the substrate 101 and the orthographic projection of the light-emitting control signal line EM on the substrate 101. The light-emitting control signal line EM is located in the first conductive layer 15.

[0129] 7A and 7B , the vertical connection pattern F4 overlaps with the first semiconductor layer 13 . Specifically, as shown by the arrow in FIG. 7B , a portion of the vertical connection pattern F4 overlaps with the active layer of the second reset transistor T7 in the first semiconductor layer 13 .

[0130] Through the above arrangement, the horizontal connection pattern and the vertical connection pattern in the shielding layer 11 overlap with the patterns in other film layers, so that the horizontal connection pattern and the vertical connection pattern do not need to occupy additional space, which can improve the light transmittance of the array substrate 1.

[0131] In some embodiments, as shown in FIG. 2 , a third gate dielectric layer 106 and a third insulating layer 107 are disposed on a side of the second semiconductor layer 61 away from the substrate 101 .

[0132] As shown in FIG. 7B , the third gate dielectric layer 106 and the third insulating layer 107 include at least one first via hole K1 .

[0133] Exemplarily, as shown in FIG7B , the function of the first via K1 is to connect the compensation transistor T2 to the first reset transistor T1 and the drive transistor T3. Exemplarily, as shown in FIG9 and FIG10 , the array substrate 1 has a fourth conductive layer 19, which includes a first pattern H1 and a second pattern H2. In a pixel drive circuit 10, two first vias K1 are included, designated as via K11 and via K12. As shown in FIG10 , one end of the first pattern H1 is connected to the second electrode T12 of the first reset transistor T1, and the other end of the first pattern H1 is connected to the second electrode T32 of the drive transistor T3 and the second electrode T22 of the compensation transistor T2 via via K12. One end of the second pattern H2 is connected to the first electrode T21 of the compensation transistor T2 via via K11, and the other end of the second pattern H2 is connected to the gate T33 of the drive transistor T3.

[0134] Exemplarily, at least one first via hole penetrates the third gate dielectric layer 106 (as shown in FIG. 2 ) and the third insulating layer 107 (as shown in FIG. 2 ) to the second semiconductor layer 61 , and the orthographic projection of at least one first via hole K1 on the substrate 101 overlaps with the orthographic projection of the second connection pattern M2 on the substrate 101 .

[0135] Exemplarily, as shown in FIG8 , a size d3 of the first via hole K1 is greater than 2.5 μm and less than or equal to 3 μm.

[0136] It should be noted that, in order to more clearly show the position of the first via hole K1 , the third gate dielectric layer 106 and the third insulating layer 107 are not shown in FIG. 7B and FIG. 8 . The arrangement of the third gate dielectric layer 106 and the third insulating layer 107 can be seen in FIG. 2 .

[0137] For example, as shown in FIG8 , the first via K1 is square, and the dimension d3 of the first via K1 can be the width of the first via K1 . Alternatively, the first via K1 is circular, and the dimension d3 of the first via K1 can be the diameter of the first via K1 . For example, the dimension d3 of the first via K1 can be 2.6 μm, 2.7 μm, 2.8 μm, 2.9 μm, or 3 μm, etc., without limitation.

[0138] As shown in FIG7B , because the second semiconductor layer 61 and the second connection pattern M2 overlap, the surface of the third insulating layer 107 in the area covering the second semiconductor layer 61 is relatively high, that is, the surface of this area is relatively far away from the substrate 101. When forming a via hole penetrating the third gate dielectric layer 106 and the third insulating layer 107, the first via hole K1 formed in this area can be made relatively large. For example, as shown in FIG9 , the via hole penetrating the third insulating layer 107 also includes a plurality of second via holes K2. The orthographic projections of the second via holes K2 on the substrate 101 do not overlap with the orthographic projections of the second semiconductor layer 61 on the substrate 101. The size of the second via holes K2 is generally less than or equal to 2.5 μm.

[0139] The relatively large size of the first via holes K1 (via hole number 1 K11 and via hole number 2 K12 ) can increase the contact area of ​​the two conductive patterns connected through the first via holes K1 , thereby reducing the contact resistance.

[0140] In some embodiments, as shown in FIG. 2 , FIG. 5 and FIG. 6 , the array substrate 1 includes: a shielding layer 11 disposed between the base 101 and the first conductive layer 15 .

[0141] Illustratively, the provision of the shielding layer 11 can prevent the light on the side of the substrate 101 away from the shielding layer 11 from affecting the pixel driving circuit 10 and can reduce the voltage drop of the signal line. Please refer to the above content for details and will not be repeated here.

[0142] As can be seen from the above, the shielding patterns 111 of each pixel driving circuit 10 are connected in the first direction X and the second direction Y to form a network structure. As shown in FIG12 , in the pixel driving circuit group 12 , two pixel driving circuits 10 are symmetrically arranged along the second direction Y.

[0143] For example, as shown in FIG12 , a pixel driving circuit group 12 has a centerline L1 along the second direction Y. The transistors (including a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first emission control transistor T5, a second emission control transistor T6, and a second reset transistor T7) of the two pixel driving circuits 10 on either side of the centerline L1 are arranged symmetrically relative to the centerline L1. The array substrate 1 includes a fifth conductive layer 21 , on which a power signal line ELVDD and a data signal line Data are provided. The power signal line ELVDD of two adjacent pixel driving circuit groups 12 in the first direction X can be shared by the two adjacent pixel driving circuits 10.

[0144] Based on the above symmetrical arrangement, between each two adjacent pixel driving circuit groups 12, the shielding patterns 111 of the two adjacent pixel driving circuits 10 are connected, and this pattern is referred to as a second connection pattern M2. In a pixel driving circuit group 12, the shielding patterns 111 between the two pixel driving circuits 10 are connected, and this pattern is referred to as a third connection pattern M3.

[0145] Exemplarily, as shown in FIG. 5 , in the pixel driving circuit group 12 , a third connection pattern M3 is connected between the shielding patterns 111 of two pixel driving circuits 10 , and the third connection pattern M3 is located on the shielding layer 11 .

[0146] Exemplarily, the orthographic projection of the second conductive layer 17 on the substrate 101 covers the orthographic projection of the third connection pattern M3 on the substrate 101 .

[0147] For example, the third connection pattern M3 and the shielding pattern 111 are an integrated structure, which can simplify the structure and manufacturing process of the array substrate 1 .

[0148] Exemplarily, the third connection pattern M3 is used to transmit a fixed voltage signal, for example, the fixed voltage signal is a reference voltage signal.

[0149] In some embodiments, as shown in FIG. 5 , when the second conductive layer 17 includes the first connection pattern M1 , the orthographic projection of the first connection pattern M1 on the substrate 101 overlaps with the orthographic projection of the third connection pattern M3 on the substrate 101 by more than 70%.

[0150] For example, as shown in FIG5 , in a pixel driving circuit group 12, a first connection pattern M1 connects the second plates Cst2 of two pixel driving circuits 10, and a shielding pattern 111 of a shielding layer 11 is provided on the side of the second plate Cst2 close to the substrate 101. The shielding pattern 111 can be connected to a fixed voltage signal, such as a reference voltage signal. The shielding pattern 111 can shield the influence of surrounding stray charges on the driving transistor T3. It is understandable that in a pixel driving circuit group 12, a third connection pattern M3 is used to connect the shielding pattern 111 of the two pixel driving circuits 10, so that the positive projection of the first connection pattern M1 connecting the two second plates Cst2 on the substrate 101 can be set, and the overlapping area with the positive projection of the third connection pattern M3 on the substrate 101 is greater than 70%.

[0151] Illustratively, the overlapping area of ​​the orthographic projection of the first connection pattern M1 on the substrate 101 and the orthographic projection of the third connection pattern M3 on the substrate 101 is 75%, 80%, 90% or 100%, etc., which is not limited here.

[0152] In some embodiments, as shown in FIG5 , in each pixel driving circuit group 12 , the orthographic projection of the first connection pattern M1 on the substrate 101 and the orthographic projection of the third connection pattern M3 on the substrate 101 overlap in an area S3 of 4 μm. 2 ~10μm 2 .

[0153] For example, in each pixel driving circuit group 12, the overlapping area S3 of the orthographic projection of the first connection pattern M1 on the substrate 101 and the orthographic projection of the third connection pattern M3 on the substrate 101 is 4 μm. 2 , 5μm 2 , 6μm 2 , 7μm 2 , 8μm 2 , 9μm 2 or 10 μm 2 There is no limit here.

[0154] In the above embodiment of the present disclosure, the orthographic projection of the first connection pattern M1 on the substrate 101 is set to cover the orthographic projection of the third connection pattern M3 on the substrate 101, thereby reducing the influence of the third connection pattern M3 on the light transmittance. Exemplarily, this setting increases the light transmittance of the array substrate 1 by approximately 0.19%.

[0155] In some embodiments, as shown in Figures 2, 10, and 11, the array substrate 1 includes a fourth conductive layer 19 disposed on a side of the first conductive layer 15 away from the substrate 101, and a first initialization signal line Vinit1 and a second initialization signal line Vinit2 located on the fourth conductive layer 19. The orthographic projections of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the substrate 101 overlap with the orthographic projection of the first conductive layer 15 on the substrate 101.

[0156] The first initialization signal line Vinit1 and the second initialization signal line Vinit2 are set on the fourth conductive layer 19, and the orthographic projections of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the substrate 101 are overlapped with the orthographic projection of the first conductive layer 15 on the substrate 101, which can reduce the influence of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the light transmittance.

[0157] In some examples, as shown in Figure 11, in each pixel driving circuit 10 and in each pixel driving circuit 12, the overlapping area S41 of the orthographic projection of the first initialization signal line Vinit1 on the substrate 101 and the orthographic projection of the first conductive layer 15 on the substrate 101 is greater than the overlapping area S42 of the orthographic projection of the second initialization signal line Vinit2 on the substrate 101 and the orthographic projection of the first conductive layer 15 on the substrate 101.

[0158] For example, the overlap area S4 of the orthographic projection of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the substrate 101 and the orthographic projection of the first conductive layer 15 on the substrate 101 is 15 μm. 2 ~20μm 2 .

[0159] For example, as shown in Figure 11, the overlapping area of ​​the orthographic projection of the first initialization signal line Vinit1 on the substrate 101 and the orthographic projection of the first conductive layer 15 on the substrate 101 is expressed as area S41, and the overlapping area of ​​the orthographic projection of the second initialization signal line Vinit2 on the substrate 101 and the orthographic projection of the first conductive layer 15 on the substrate 101 is expressed as area S42. It can be understood that S4=S41+S42.

[0160] For example, the orthographic projection of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the substrate 101 overlaps with the orthographic projection of the first conductive layer 15 on the substrate 101 in an area S4 of 15 μm. 2 , 16μm 2 , 17μm 2 , 18μm 2 , 19μm 2 or 20 μm 2 There is no limit here.

[0161] Exemplarily, in each of the pixel driving circuits 12, a ratio of an overlapping area S41 between an orthographic projection of the first initialization signal line Vinit1 on the substrate 101 and an orthographic projection of the first conductive layer 15 on the substrate 101, and an overlapping area S42 between an orthographic projection of the second initialization signal line Vinit2 on the substrate 101 and an orthographic projection of the first conductive layer 15 on the substrate 101, is greater than 1.5.

[0162] In some examples, as shown in FIG11 , in each pixel driving circuit 10 , the overlap area S41 of the orthographic projection of the first initialization signal line Vinit1 on the substrate 101 and the orthographic projection of the first conductive layer 15 on the substrate 101 is in the range of 12 μm. 2 ~19μm 2The overlap area S42 of the orthographic projection of the second initialization signal line Vinit2 on the substrate 101 and the orthographic projection of the first conductive layer 15 on the substrate 101 is 1 μm. 2 ~3μm 2 .

[0163] For example, in each pixel driving circuit 10, the overlap area S41 of the orthographic projection of the first initialization signal line Vinit1 on the substrate 101 and the orthographic projection of the first conductive layer 15 on the substrate 101 is 12 μm. 2 , 13μm 2 , 14μm 2 , 15μm 2 , 16μm 2 , 17μm 2 or 19 μm 2 There is no limit here.

[0164] For example, in each pixel driving circuit 10, the overlap area S42 of the orthographic projection of the second initialization signal line Vinit2 on the substrate 101 and the orthographic projection of the first conductive layer 15 on the substrate 101 is 1 μm. 2 , 2μm 2 or 3μm 2 There is no limit here.

[0165] In the embodiment of the present disclosure, the orthographic projections of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the substrate 101 are arranged to overlap with the orthographic projections of the first conductive layer 15 on the substrate 101, thereby reducing the influence of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the light transmittance. Exemplarily, this arrangement increases the light transmittance of the array substrate 1 by approximately 0.94%.

[0166] In some examples, as shown in Figures 10 and 11, the array substrate 1 includes: a reset signal line Reset, the reset signal line Reset is located in the first conductive layer 15, and the first initialization signal line Vinit1, the second initialization signal line Vinit2 and the reset signal line Reset have overlapping orthographic projections on the substrate 101.

[0167] For example, as shown in Figure 11, since the reset signal line Reset is set in the first conductive layer 15, the first initialization signal line Vinit1 and the second initialization signal line Vinit2 are located in the fourth conductive layer 19, compared with setting the first initialization signal line Vinit1 and the second initialization signal line Vinit2 in the second conductive layer 17, the reset signal line Reset and the first initialization signal line Vinit1 and the second initialization signal line Vinit2 are farther apart in the direction perpendicular to the plane where the substrate 101 is located. When the reset signal line Reset and the first initialization signal line Vinit1 and the second initialization signal line Vinit2 have overlapping projections on the substrate 101, the problem of electrostatic breakdown caused by the overlapping of the signal lines can be effectively prevented, and the light transmittance of the array substrate 1 can be improved.

[0168] In some embodiments, as shown in FIG12 , the first semiconductor layer 13 includes active layer patterns for a first reset transistor T1, a drive transistor T3, a data write transistor T4, a first emission control transistor T5, a second emission control transistor T6, and a second reset transistor T7. The active layer patterns of each of the above transistors include a transistor source and drain, and a channel region therebetween. The second semiconductor layer includes an active layer pattern for a compensation transistor T2.

[0169] The first conductive layer 15 includes the gates of the first reset transistor T1, the drive transistor T3, the data write transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7, as well as the first plate Cst1 of the capacitor Cst. The gates of each of these transistors overlap with the channel region, thereby forming each of these transistors. The first conductive layer also includes a first scan signal line Gate1, an emission control signal line EM, and a reset signal line Reset.

[0170] The second conductive layer 17 includes a first sub-scanning signal line 2G2 , and the third conductive layer 62 includes a second sub-scanning signal line 3G2 . The first sub-scanning signal line 2G2 and the second sub-scanning signal line 3G2 are connected to form a second scanning signal line Gate2 .

[0171] The fourth conductive layer 19 includes a first initialization signal line Vinit1 and a second initialization signal line Vinit2 .

[0172] The fifth conductive layer 21 includes a data signal line Data and a power signal line ELVDD.

[0173] The connection relationship between the signal lines and the transistors can be referred to the above introduction and will not be repeated here.

[0174] In some embodiments, as shown in FIG12 , the array substrate 1 further includes a shielding layer 11 disposed between the substrate 101 and the first conductive layer 15. Along the first direction X, a second connection pattern M2 is connected between at least two adjacent pixel driving circuit groups 12 and between the shielding patterns 111 of two adjacent pixel driving circuits 10. The second connection pattern M2 is located on the shielding layer 11. The array substrate 1 further includes a light-emission control signal line EM.

[0175] The pixel driving circuit 10 further includes a second light emitting control transistor T6 , a gate of which is connected to the light emitting control signal line EM, and a first electrode of which is connected to the second electrode T32 of the driving transistor T3 .

[0176] Exemplarily, the gate of the second light emitting control transistor T6 and the light emitting control signal line EM are an integrated structure.

[0177] The area between two adjacent pixel driving circuit groups 12, between the first electrodes of two adjacent second light emitting control transistors T6, and between the second connection pattern M2 and the light emitting control signal line EM is the first light transmitting area W1. The area of ​​the first light transmitting area W1 is greater than 10 μm. 2 .

[0178] For example, the area of ​​the first light-transmitting region W1 is 15 μm 2 , 20μm 2 , 25μm 2 or 30 μm 2 There is no limit here.

[0179] It should be noted that in the array substrate provided in some embodiments of the present application, conductive film layers such as the shielding layer 11, the first semiconductor layer 13, the first conductive layer 15, the second conductive layer 17, the second semiconductor layer 61, the third conductive layer 62, the fourth conductive layer 19, and the fifth conductive layer 21 are all opaque film layers. For example, the first conductive layer 15, the second conductive layer 17, the third conductive layer 62, the fourth conductive layer 19, and the fifth conductive layer 21 are typically made of an opaque metal layer. The light-transmitting area can be the area between the anode and the substrate, excluding the conductive layer pattern and the semiconductor layer pattern. If the conductive layer is made of a transparent conductive layer, such as indium tin oxide (ITO), this area can also be considered a light-transmitting area.

[0180] In some embodiments, as shown in FIG12 , the array substrate 1 further includes: a first initialization signal line Vinit1 and a light emission control signal line EM. The pixel driving circuit 10 further includes: a first reset transistor T1, a second light emission control transistor T6, and a second reset transistor T7. The first electrode of the first reset transistor T1 is connected to the first initialization signal line Vinit1, the second electrode T12 of the first reset transistor T1 is connected to the first electrode of the second light emission control transistor T6, and the second electrode of the second light emission control transistor T6 is connected to the second electrode of the second reset transistor T7. The first electrode of the second light emission control transistor T6 is connected to the second electrode T32 of the driving transistor T3, and the gate of the second light emission control transistor T6 is connected to the light emission control signal line EM.

[0181] The area between two adjacent pixel driving circuit groups 12, between the second electrodes of two adjacent second light emitting control transistors T6, and between the first initialization signal line Vinit1 and the light emitting control signal line EM is the second light transmitting area W2. The area of ​​the second light transmitting area W2 is greater than 10 μm. 2 .

[0182] For example, the area of ​​the second light-transmitting region W2 is 15 μm 2 , 20μm 2 , 25μm 2 or 30 μm 2 There is no limit here.

[0183] By setting the area of ​​the first light-transmitting region W1 to be larger than 10 μm 2 The area of ​​the second light-transmitting region W2 is greater than 10 μm 2 , which can improve the light transmittance of the array substrate 1.

[0184] In some embodiments of the present disclosure, as shown in Figures 2 and 4, the array substrate 1 includes: a substrate 101, and a plurality of pixel driving circuit groups 12 arranged on the substrate 101, wherein the plurality of pixel driving circuit groups 12 are arranged in an array along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect; wherein each pixel driving circuit group 10 includes: two pixel driving circuits 10 arranged along the first direction X.

[0185] As shown in Figures 2 and 12, the array substrate 1 also includes: a first conductive layer 15 arranged on the substrate 101, a second conductive layer 17 arranged on the side of the first conductive layer 15 away from the substrate 101, and a fifth conductive layer 21; illustratively, the fifth conductive layer 21 is provided with a power signal line ELVDD and a data signal line Data.

[0186] Taking the pixel driving circuit 10 as a 7T1C as an example, as shown in Figures 3A to 5 , the pixel driving circuit 10 includes a driving transistor T3 and a capacitor Cst. The capacitor Cst includes a first plate Cst1 and a second plate Cst2. The first plate Cst1 is connected to the gate T33 of the driving transistor T3. The first plate Cst1 is located on the first conductive layer 15, and the second plate Cst2 is located on the second conductive layer 17. As shown in Figure 12 , the second plate Cst2 is connected to the fifth conductive layer 21. Exemplarily, the second plate Cst2 of the capacitor Cst is electrically connected to the power signal line ELVDD in the fifth conductive layer 21.

[0187] Because the second plate Cst2 of the capacitor Cst in each pixel driving circuit 10 needs to be connected to the power signal line ELVDD, multiple second plates Cst2 of multiple capacitors Cst can be connected to reduce the voltage drop of the power signal provided by the power signal line ELVDD during transmission. Based on this, as shown in Figure 4, a first connection pattern M1 is connected between the second plates Cst2 of two pixel driving circuits 10 in the pixel driving circuit group 12. The first connection pattern M1 is located on the second conductive layer 17. The dimension d1 of the first connection pattern M1 in the second direction is smaller than the dimension d2 of the second plate Cst2 in the second direction Y.

[0188] It should be noted that the dimension d1 of the first connection pattern M1 in the second direction Y refers to the maximum dimension of the first connection pattern M1 in the second direction Y, and the dimension d2 of the second electrode plate Cst2 in the second direction Y refers to the maximum dimension of the second electrode plate Cst2 in the second direction Y.

[0189] For example, the first connection pattern M1 is connected to the second electrode plate Cst2 of the two pixel driving circuits 10 in the pixel driving circuit group 12. Specifically, the first connection pattern M1 and the second electrode plate Cst2 of the two pixel driving circuits 10 in the pixel driving circuit group 12 are an integrated structure, which can simplify the structure and preparation process of the array substrate 1.

[0190] For example, as shown in FIG4 , in a pixel driver circuit group 12, a first connection pattern M1 connects the second plates Cst2 of two pixel driver circuits 10, and the two pixel driver circuits 10 can receive the same power signal. Since the first connection pattern M1 transmits the power signal within a pixel driver circuit group 12, the dimension d1 of the first connection pattern M1 in the second direction Y being smaller than the dimension d2 of the second plate Cst2 in the second direction Y does not affect the transmission of the power signal. Therefore, the dimension d1 of the first connection pattern M1 in the second direction Y can be set to be smaller than the dimension d2 of the second plate Cst2 in the second direction Y. This setting can increase the light transmittance of the region S1 between the two second plates Cst2 in a pixel driver circuit group 12.

[0191] In some embodiments, as shown in FIG. 3A and FIG. 4 , the array substrate further includes a second scanning signal line Gate2 .

[0192] The pixel driving circuit further includes: a compensation transistor T2, a first electrode of the compensation transistor T2 connected to the gate of the driving transistor T3, a second electrode of the compensation transistor T2 connected to the second electrode of the driving transistor T3, and a gate of the compensation transistor T2 connected to the second scanning signal line Gate2.

[0193] As shown in Figure 2, the array substrate 1 also includes: a blocking layer 11 arranged on the substrate 101, and a first semiconductor layer 13, the first conductive layer 15, the second conductive layer 17, the second semiconductor layer 61, the third conductive layer 62 and the fourth conductive layer 19 arranged in sequence along the direction away from the blocking layer 11; the fifth conductive layer 21 is located on the side of the fourth conductive layer 19 away from the substrate 101.

[0194] As shown in FIG. 10 , the active layer of the driving transistor T3 is located in the first semiconductor layer 13 .

[0195] The second scan signal line is at least partially located in the third conductive layer 62. The second scan signal line, Gate2, includes a first sub-scan signal line 2G2 located in the second conductive layer 17 and a second sub-scan signal line 3G2 located in the third conductive layer 62. The first sub-scan signal line 2G2 and the second sub-scan signal line 3G2 are connected to form the second scan signal line Gate2. The active layer of the compensation transistor T2 is located in the second semiconductor layer 61. The portion of the second sub-scan signal line 3G2 that passes through the active layer of the compensation transistor T2 serves as the gate of the compensation transistor T2.

[0196] As shown in FIG. 9 and FIG. 10 , the second electrode of the compensation transistor T2 is connected to the second electrode of the driving transistor T3 through a first pattern H1 , and the first pattern H1 is located in the fourth conductive layer 19 .

[0197] In some examples, referring again to Figures 9 and 10, the first pattern H1 is connected to the second electrode T32 of the driving transistor T3 via a third via K3. The first pattern H1 is also connected to the second electrode T32 of the compensation transistor T2 via the first via K1. In a pixel driving circuit 10, two first vias K1 are included, designated as via K11 and via K12. As shown in Figure 10, one end of the first pattern H1 is connected to the second electrode T12 of the first reset transistor T1 via a via, and the other end of the first pattern H1 is connected to the second electrode T22 of the compensation transistor T2 via via K12. The third via K3 extends from the fourth conductive layer 19 through the third insulating layer 107, the third gate dielectric layer 106, the second insulating layer 105, the second gate dielectric layer 104, and the first gate dielectric layer 103, reaching the first semiconductor layer 13, thereby connecting the first pattern H1 to the second electrode T32 of the driving transistor T3 via the third via K3. The second via hole K12 in the first via hole K1Z passes through the third insulating layer 107 and the third gate dielectric layer 106 in sequence from the fourth conductive layer 19 to the second semiconductor layer 61 , so that the first pattern H1 is also connected to the second electrode of the compensation transistor T2 through the first via hole K1 .

[0198] In some embodiments, the first connection pattern M1 does not overlap with the first via hole K1 or the third via hole K3 .

[0199] In some embodiments, as shown in FIG. 7A and FIG. 7B , the blocking layer 11 includes a plurality of blocking patterns 111 .

[0200] Along the first direction X, between at least two adjacent pixel driving circuit groups 12, and between the shielding patterns of two adjacent pixel driving circuits, a second connection pattern M2 is connected. The second connection pattern M2 is located on the shielding layer 11. A detailed description of the second connection pattern M2 can be found in the previous description and is not repeated here. The second connection pattern M2 does not overlap with the third via K3.

[0201] By arranging the first connection pattern M1, the second connection pattern M2 and the third via K3 not to overlap, the parasitic capacitance coupling between the second electrode of the driving transistor and the constant voltage line can be reduced during the operation of the pixel driving circuit in the data writing and Vth compensation phase t2, thereby avoiding affecting the compensation effect and further preventing the luminous effect of the light-emitting device from being affected.

[0202] In some embodiments, the shielding pattern 111 and the second connection pattern M2 are used to receive a constant voltage signal. For example, the shielding layer 11 can be connected to a constant voltage signal, such as a power supply signal VDD, a reference voltage signal VSS, an initialization signal Vinit, etc. These constant voltage signals can be connected to the shielding layer 11 in the display area in the peripheral area of ​​the array substrate.

[0203] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: A substrate, and a plurality of pixel driving circuit groups arranged on the substrate, wherein the plurality of pixel driving circuit groups are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect; wherein each pixel driving circuit group comprises: two pixel driving circuits arranged along the first direction; It also includes: a first conductive layer disposed on the substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, and a power signal line; The pixel driving circuit comprises: a driving transistor and a capacitor, wherein the capacitor comprises: a first plate and a second plate, wherein the first plate is connected to the gate of the driving transistor, and the second plate is connected to the power signal line; The first electrode plate is located in the first conductive layer, and the second electrode plate is located in the second conductive layer; a first connection pattern is connected between the second electrodes of two pixel driving circuits in the pixel driving circuit group, and the first connection pattern is located in the second conductive layer; Wherein, a size of the first connection pattern in the second direction is smaller than a size of the second electrode plate in the second direction.

2. The array substrate according to claim 1, wherein: The ratio of the size of the first connection pattern in the second direction to the size of the second electrode plate in the second direction is in a range of 10% to 50%.

3. The array substrate according to claim 1 or 2, wherein: A size of the first connection pattern in the second direction ranges from 2.0 μm to 5.5 μm.

4. The array substrate according to any one of claims 1 to 3, further comprising: A shielding layer disposed between the substrate and the first conductive layer; the shielding layer comprises a plurality of shielding patterns; Along the first direction, between at least two adjacent pixel driving circuit groups, a second connection pattern is connected between the shielding patterns of two adjacent pixel driving circuits, and the second connection pattern is located in the shielding layer; It also includes: a second semiconductor layer, the second semiconductor layer is located on a side of the second conductive layer away from the substrate; An orthographic projection of the second connection pattern on the substrate overlaps with an orthographic projection of the second semiconductor layer on the substrate.

5. The array substrate according to claim 4, wherein: A third gate dielectric layer and a third insulating layer are disposed on a side of the second semiconductor layer away from the substrate; The third gate dielectric layer and the third insulating layer are provided with: at least one first via hole, the at least one first via hole penetrates at least one of the third gate dielectric layer and the third insulating layer to the second semiconductor layer, and the orthographic projection of the at least one first via hole on the substrate overlaps with the orthographic projection of the second connection pattern on the substrate.

6. The array substrate according to any one of claims 1 to 5, further comprising: A shielding layer disposed between the substrate and the first conductive layer; The shielding layer includes a plurality of shielding patterns; In the pixel driving circuit group, a third connection pattern is connected between the shielding patterns of two pixel driving circuits, and the third connection pattern is located in the shielding layer; The orthographic projection of the first connection pattern on the substrate is different from the orthographic projection of the third connection pattern on the substrate. The overlapping area of ​​the shadows is greater than 70%.

7. The array substrate according to any one of claims 1 to 6, further comprising a fourth conductive layer disposed on a side of the second conductive layer away from the substrate, and a first initialization signal line and a second initialization signal line located on the fourth conductive layer; The orthographic projections of the first initialization signal line and the second initialization signal line on the substrate overlap with the orthographic projection of the first conductive layer on the substrate.

8. The array substrate according to claim 7, wherein: In each of the pixel driving circuits, an overlapping area between an orthographic projection of the first initialization signal line on the substrate and an orthographic projection of the first conductive layer on the substrate is greater than an overlapping area between an orthographic projection of the second initialization signal line on the substrate and an orthographic projection of the first conductive layer on the substrate.

9. The array substrate according to claim 7 or 8, wherein: In each of the pixel driving circuits, a ratio of an overlapping area between an orthographic projection of the first initialization signal line on the substrate and an orthographic projection of the first conductive layer on the substrate to an overlapping area between an orthographic projection of the second initialization signal line on the substrate and an orthographic projection of the first conductive layer on the substrate is greater than 1.

5.

10. The array substrate according to any one of claims 7 to 9, further comprising: A reset signal line is located in the first conductive layer, and the first initialization signal line, the second initialization signal line and the reset signal line have an overlapped orthographic projection on the substrate.

11. The array substrate according to any one of claims 1 to 10, further comprising: The shielding layer is disposed on the substrate, and a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer and a fourth conductive layer are sequentially disposed in a direction away from the shielding layer; The material of the first semiconductor layer includes low temperature polysilicon; The material of the second semiconductor layer includes indium gallium zinc oxide.

12. The array substrate according to any one of claims 1 to 11, further comprising: A shielding layer disposed between the substrate and the first conductive layer, the shielding layer comprising a plurality of shielding patterns; Along the first direction, between at least two adjacent pixel driving circuit groups, a second connection pattern is connected between the shielding patterns of two adjacent pixel driving circuits, and the second connection pattern is located in the shielding layer; Also includes: a light-emitting control signal line; The pixel driving circuit further includes: a second light emitting control transistor, a gate of the second light emitting control transistor is connected to the light emitting control signal line, and a first electrode of the second light emitting control transistor is connected to a second electrode of the driving transistor; The area between two adjacent pixel driving circuit groups, between the first electrodes of two adjacent second light emission control transistors, and between the second connection pattern and the light emission control signal line is a first light transmission area, and the area of ​​the first light transmission area is greater than 5 μm 2 .

13. The array substrate according to any one of claims 1 to 12, further comprising: A first initialization signal line, a light emission control signal line, and a second scan signal line; The pixel driving circuit further includes: a first reset transistor, a second light emission control transistor, a second reset transistor, and a compensation transistor, wherein a first electrode of the first reset transistor is connected to the first initialization signal line, a second electrode of the first reset transistor is connected to a first electrode of the compensation transistor, and a second electrode of the second light emission control transistor is connected to a second electrode of the second reset transistor; a first electrode of the second light emission control transistor is connected to a second electrode of the driving transistor, a gate of the second light emission control transistor is connected to a light emission control signal line, and a gate of the compensation transistor is connected to a second scanning signal line; The area between two adjacent pixel driving circuit groups, between the second electrodes of two adjacent second light emission control transistors, and between the first initialization signal line and the light emission control signal line is a second light transmission area, and the area of ​​the second light transmission area is greater than 10 μm 2 .

14. An array substrate, comprising: A substrate, and a plurality of pixel driving circuit groups arranged on the substrate, wherein the plurality of pixel driving circuit groups are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect; wherein each pixel driving circuit group comprises: two pixel driving circuits arranged along the first direction; It also includes: a first conductive layer disposed on the substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, and a fifth conductive layer; The pixel driving circuit comprises: a driving transistor and a capacitor, wherein the capacitor comprises: a first electrode plate and a second electrode plate, wherein the first electrode plate is connected to the gate of the driving transistor, and the second electrode plate is connected to the fifth conductive layer; The first electrode plate is located in the first conductive layer, and the second electrode plate is located in the second conductive layer; a first connection pattern is connected between the second electrodes of two pixel driving circuits in the pixel driving circuit group, and the first connection pattern is located in the second conductive layer; Wherein, a size of the first connection pattern in the second direction is smaller than a size of the second electrode plate in the second direction.

15. The array substrate according to claim 14, further comprising: The second scanning signal line, The pixel driving circuit further includes: a compensation transistor, a first electrode of the compensation transistor is connected to a gate of the driving transistor, a second electrode of the compensation transistor is connected to a second electrode of the driving transistor through a first pattern, and a gate of the compensation transistor is connected to the second scanning signal line; It also includes: the shielding layer is disposed on the substrate, and a first semiconductor layer, the first conductive layer, the second conductive layer, a second semiconductor layer, a third conductive layer and a fourth conductive layer are sequentially disposed in a direction away from the shielding layer; The active layer of the driving transistor is located in the first semiconductor layer; The second scanning signal line is at least partially located in the third conductive layer; The active layer of the compensation transistor is located in the second semiconductor layer; The first pattern is located in the fourth conductive layer.

16. The array substrate according to claim 15, wherein: The first pattern is connected to the second electrode of the driving transistor through a third via hole, the first conductive pattern is also connected to the second electrode of the compensation transistor through a first via hole, and the first connection pattern does not overlap with the first via hole and the third via hole.

17. The array substrate according to claim 16, wherein: The shielding layer includes a plurality of shielding patterns; Along the first direction, between at least two adjacent pixel driving circuit groups, a second connection pattern is connected between the shielding patterns of two adjacent pixel driving circuits, and the second connection pattern is located in the shielding layer; the second connection pattern does not overlap with the third via hole.

18. The array substrate according to claim 17, wherein: The shielding pattern and the second connection pattern are used to receive a constant voltage signal.

19. A display panel, comprising: The array substrate according to any one of claims 1 to 13 and 14 to 18; A plurality of light emitting devices are arranged on a plurality of pixel driving circuits of the array substrate; the array substrate is used for driving the plurality of light emitting devices to emit light.

20. A display device, comprising: The display panel as claimed in claim 19; A driving chip is used to drive the display panel to display.

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