Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a plurality of repetitive units (100), each repetitive unit (100) comprises a plurality of sub-pixels, each sub-pixel at least comprises a pixel driving circuit, a scanning signal line (30) and an auxiliary signal line (30A), each pixel driving circuit comprises a first polar plate (61) and at least one transistor, and the at least one transistor is connected with the first polar plate (61) through a connecting electrode; in the direction perpendicular to the display substrate, the display substrate comprises a first conductive layer and a second conductive layer, an auxiliary signal line (30A) and a first polar plate (61) are arranged in the first conductive layer, and a scanning signal line (30) and a connecting electrode are arranged in the second conductive layer. The orthographic projection of the scanning signal line (30) on the substrate plane is located within the range of the orthographic projection of the auxiliary signal line (30A) on the substrate plane, and the scanning signal line (30) is in lap joint with the auxiliary signal line (30A).

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to PCT application No. PCT / CN2023 / 091560, filed on April 28, 2023, with application number PCT / CN2023 / 091560 and invention name “Display substrate, preparation method thereof, and display device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, display devices using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] On the one hand, the present disclosure provides a display substrate, comprising multiple repeating units, at least one repeating unit comprising multiple sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, a scanning signal line and an auxiliary signal line, the scanning signal line being configured to provide a scanning signal to the pixel driving circuit; the pixel driving circuit comprising a storage capacitor and at least one transistor, the storage capacitor comprising at least a first electrode plate, the at least one transistor being connected to the first electrode plate via a connecting electrode; in a direction perpendicular to the display substrate, the display substrate comprises a first conductive layer arranged on a substrate and a second conductive layer arranged on a side of the first conductive layer away from the substrate, the auxiliary signal line and the first electrode plate being arranged in the first conductive layer, the scanning signal line and the connecting electrode being arranged in the second conductive layer, the orthographic projection of the scanning signal line on the substrate plane being within the range of the orthographic projection of the auxiliary signal line on the substrate plane, and the scanning signal line overlaps the auxiliary signal line.

[0007] In an exemplary embodiment, the storage capacitor also includes a second plate, the orthographic projection of the second plate on the substrate plane at least partially overlaps with the orthographic projection of the first plate on the substrate plane; the at least one transistor includes a second transistor, the second transistor includes at least a second gate electrode, the second gate electrode is connected to the second plate through a plate via, and the orthographic projection of the second gate electrode on the substrate plane includes the orthographic projection of the plate via on the substrate plane.

[0008] In an exemplary embodiment, the second transistor further includes a second active layer, a first region of the second active layer is connected to a first power line through a power via, a second region of the second active layer is connected to the first electrode plate through a connecting electrode, the first power line is configured to provide a power signal to the pixel driving circuit, and an orthographic projection of the first power line on the substrate plane includes an orthographic projection of the power via on the substrate plane.

[0009] In an exemplary embodiment, the second active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are an interconnected integral structure, and / or the second active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are an interconnected integral structure.

[0010] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the power via, and / or two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power via.

[0011] In an exemplary embodiment, the connecting electrode includes a first connecting electrode and a third connecting electrode, the first connecting electrode is connected to the first electrode plate, and the third connecting electrode is overlapped with the first connecting electrode; the pixel driving circuit also includes a fifth connecting electrode, and the fifth connecting electrode is simultaneously connected to the second region of the second active layer and the third connecting electrode through a first overlapping via hole; the first size of the first overlapping via hole is larger than the second size of the first overlapping via hole, the first size is the size of the first overlapping via hole in the pixel row direction, and the second size is the size of the first overlapping via hole in the pixel column direction.

[0012] In an exemplary embodiment, the power via and the first overlapping via are not located on a straight line extending along the pixel row direction.

[0013] In an exemplary embodiment, in the pixel column direction, the power via hole shared by two adjacent sub-pixels in two adjacent repeating units is located between two adjacent first overlapping via holes in two adjacent repeating units.

[0014] In an exemplary embodiment, the at least one transistor includes a third transistor, the third transistor includes at least a third active layer, a first region of the third active layer is connected to a compensation signal line through a compensation via, a second region of the third active layer is connected to the first electrode plate through a connecting electrode, the compensation signal line is configured to provide a compensation signal to the pixel driving circuit, and the orthographic projection of the compensation signal line on the substrate plane includes the orthographic projection of the compensation via on the substrate plane.

[0015] In an exemplary embodiment, in at least one repeating unit, the third active layers of two adjacent sub-pixels in the pixel row direction are interconnected as an integrated structure, and / or the third active layers of two adjacent sub-pixels in the pixel column direction are interconnected as an integrated structure.

[0016] In an exemplary embodiment, in at least one repeating unit, two adjacent sub-pixels in the pixel row direction share the compensation via hole, and / or two adjacent sub-pixels in the pixel column direction share the compensation via hole.

[0017] In an exemplary embodiment, the connecting electrode includes a second connecting electrode and a fourth connecting electrode, the second connecting electrode is connected to the first electrode plate, and the fourth connecting electrode is overlapped with the second connecting electrode; the pixel driving circuit also includes a sixth connecting electrode, and the sixth connecting electrode is simultaneously connected to the second area of ​​the third active layer and the fourth connecting electrode through a second overlapping via; the third dimension of the second overlapping via is smaller than the fourth dimension of the second overlapping via, the third dimension is the dimension of the second overlapping via in the pixel row direction, and the fourth dimension is the dimension of the second overlapping via in the pixel column direction.

[0018] In an exemplary embodiment, the pixel driving circuit further includes a first transistor, the first transistor including at least a first active layer, a first region of the first active layer being connected to a data signal line through a data via, the data signal line being configured to provide a data signal to the pixel driving circuit, and an orthographic projection of the data signal line on the substrate plane including an orthographic projection of the data via on the substrate plane.

[0019] In an exemplary embodiment, the pixel driving circuit includes at least a first transistor and a third transistor, the first transistor includes at least a first gate electrode, the third transistor includes at least a third gate electrode, and the first gate electrode and the third gate electrode are respectively connected to the scanning signal line through gate connection electrodes.

[0020] In an exemplary embodiment, in at least one repeating unit, the gate connection electrode, the first gate electrode, and the third gate electrode of two adjacent sub-pixels in the pixel column direction are provided in the same layer and are an integrated structure connected to each other.

[0021] In an exemplary embodiment, an orthographic projection of the gate connection electrode on the substrate plane at least partially overlaps with an orthographic projection of the scan signal line on the substrate plane, and the gate connection electrode is connected to the scan signal line through a gate connection via.

[0022] In an exemplary embodiment, in at least one repeating unit, two adjacent sub-pixels in the pixel column direction share the gate connection electrode.

[0023] In an exemplary embodiment, in at least one repeating unit, two adjacent sub-pixels in the pixel column direction share the gate connection via hole.

[0024] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0025] In yet another aspect, the present disclosure further provides a method for preparing a display substrate, the display substrate comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, the at least one sub-pixel comprising a pixel driving circuit, a scan signal line, and an auxiliary signal line, the scan signal line being configured to provide a scan signal to the pixel driving circuit; the pixel driving circuit comprising a storage capacitor and at least one transistor, the storage capacitor comprising at least a first plate, the at least one transistor being connected to the first plate via a connecting electrode; the preparation method comprising:

[0026] A first conductive layer and a second conductive layer are formed on a substrate and are arranged on a side of the first conductive layer away from the substrate. The auxiliary signal line and the first electrode are arranged in the first conductive layer, and the scanning signal line and the connecting electrode are arranged in the second conductive layer. The orthographic projection of the scanning signal line on the substrate plane is within the range of the orthographic projection of the auxiliary signal line on the substrate plane, and the scanning signal line is overlapped with the auxiliary signal line.

[0027] In an exemplary embodiment, forming a first conductive layer on a substrate and a second conductive layer disposed on a side of the first conductive layer away from the substrate includes:

[0028] sequentially depositing a first conductive film and a second conductive film;

[0029] A patterning process using a half-tone mask is adopted, the scanning signal line and the auxiliary signal line are formed through a first etching process, and the first electrode plate and the connecting electrode are formed through a second etching process.

[0030] In an exemplary embodiment, the storage capacitor further includes a second electrode plate, wherein an orthographic projection of the second electrode plate on the substrate plane at least partially overlaps with an orthographic projection of the first electrode plate on the substrate plane; and the preparation method further includes:

[0031] depositing a semiconductor thin film on a side of the second conductive layer away from the substrate;

[0032] The second electrode plate is formed by adopting a patterning process of a half-tone mask and sequentially performing an etching process and a conductor treatment process.

[0033] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0035] FIG1 is a schematic structural diagram of a display device;

[0036] FIG2 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0037] FIG3 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an exemplary embodiment of the present disclosure;

[0038] FIG4 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0039] 5A to 5D are schematic diagrams showing a substrate after forming first and second conductive layer patterns according to the present disclosure;

[0040] 6A to 6C are schematic diagrams showing a substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0041] 7A and 7B are schematic diagrams showing a substrate after forming a second insulating layer pattern according to the present disclosure;

[0042] 8A to 8C are schematic diagrams showing a substrate after a third conductive layer pattern is formed according to the present disclosure;

[0043] FIG9 is a schematic diagram showing a substrate after forming a third insulating layer and a planar layer pattern according to the present disclosure;

[0044] 10A and 10B are schematic diagrams showing a substrate after a fourth conductive layer pattern is formed thereon according to the present disclosure;

[0045] FIG. 11 is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to the present disclosure.

[0046] Explanation of the accompanying drawings: 10—substrate; 11—first connecting electrode; 12—second connecting electrode; 13—third connecting electrode; 14—fourth connecting electrode; 15—fifth connecting electrode; 16—sixth connecting electrode; 21—first active layer; 22—second active layer; 23—third active layer; 30—scanning signal line; 30A—auxiliary signal line; 31—first gate electrode; 32—second gate electrode; 33—third gate electrode; 34—gate connecting electrode; 51—first power line; 52—data signal line; 53—compensation signal line; 60—storage capacitor; 61—first plate; 62—second plate; 63—first electrode; 64—anode connecting electrode; 71—first insulating layer; 72—second insulating layer; 100—repeating unit. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0048] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0049] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0050] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0051] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0052] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0053] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0054] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0055] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0056] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0057] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0058] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0059] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is respectively connected to the data driver and the scan driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scan signal line. i and j may be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line and the data signal line. The display unit may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit. Sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next level circuit under the control of a clock signal, where m can be a natural number. In an exemplary embodiment, the pixel array can be provided on a display substrate.

[0060] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, a scan signal line, and an auxiliary signal line, wherein the scan signal line is configured to provide a scan signal to the pixel driving circuit; the pixel driving circuit comprising a storage capacitor and at least one transistor, the storage capacitor comprising at least a first electrode plate, the at least one transistor being connected to the first electrode plate via a connecting electrode; in a direction perpendicular to the display substrate, the display substrate comprises a first conductive layer disposed on a base and a second conductive layer disposed on a side of the first conductive layer away from the base, the auxiliary signal line and the first electrode plate being disposed in the first conductive layer, the scan signal line and the connecting electrode being disposed in the second conductive layer, the orthographic projection of the scan signal line on the base plane being within the range of the orthographic projection of the auxiliary signal line on the base plane, and the scan signal line and the auxiliary signal line being overlapped.

[0061] In an exemplary embodiment, the storage capacitor also includes a second plate, the orthographic projection of the second plate on the substrate plane at least partially overlaps with the orthographic projection of the first plate on the substrate plane; the at least one transistor includes a second transistor, the second transistor includes at least a second gate electrode, the second gate electrode is connected to the second plate through a plate via, and the orthographic projection of the second gate electrode on the substrate plane includes the orthographic projection of the plate via on the substrate plane.

[0062] In an exemplary embodiment, the second transistor further includes a second active layer, a first region of the second active layer is connected to a first power line through a power via, the first power line is configured to provide a power signal to the pixel driving circuit, and an orthographic projection of the first power line on the substrate plane includes an orthographic projection of the power via on the substrate plane.

[0063] In an exemplary embodiment, the at least one transistor includes a first transistor and a third transistor, the first transistor includes at least a first gate electrode, the third transistor includes at least a third gate electrode, and the first gate electrode and the third gate electrode are respectively connected to the scan signal line through gate connection electrodes.

[0064] In an exemplary embodiment, the first transistor further includes a first active layer, a first region of the first active layer is connected to a data signal line through a data via, and the data signal line is configured to provide a data signal to the pixel driving circuit; and an orthographic projection of the data signal line on the substrate plane includes an orthographic projection of the data via on the substrate plane.

[0065] In an exemplary embodiment, the third transistor also includes a third active layer, the first region of the third active layer is connected to a compensation signal line through a compensation via, and the compensation signal line is configured to provide a compensation signal to the pixel driving circuit; the orthographic projection of the compensation signal line on the substrate plane includes the orthographic projection of the compensation via on the substrate plane.

[0066] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0067] Figure 2 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 2, in an exemplary embodiment, the display substrate may include multiple repeating units 100 in a direction parallel to the display substrate. At least one repeating unit 100 may include multiple sub-pixels forming at least two pixel rows and at least two pixel columns. In an exemplary embodiment, a repeating unit is the basic unit that makes up the display substrate. The display substrate is formed by repeating and continuously arranging the repeating units along at least one direction. In other words, the display substrate is composed of multiple repeating units.

[0068] In an exemplary embodiment, a repeating unit 100 may include four sub-pixels, and the four sub-pixels may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, a third sub-pixel P3 that emits a third color light, and a fourth sub-pixel P4 that emits a fourth color light. The four sub-pixels may be arranged in a square manner, which can effectively increase the aperture ratio and the area of ​​the light-transmitting region.

[0069] In an exemplary embodiment, in at least one repeating unit 100, the second subpixel P2 may be arranged on one side of the first subpixel P1 in the first direction X, the third subpixel P3 may be arranged on one side of the first subpixel P1 in the second direction Y, and the fourth subpixel P4 may be arranged on one side of the third subpixel P3 in the first direction X. The plurality of subpixels arranged sequentially along the first direction X may be referred to as a pixel row, and the plurality of subpixels arranged sequentially along the second direction Y may be referred to as a pixel column. The plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array, and the first direction X intersects the second direction Y.

[0070] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, the third subpixel P3 may be a white subpixel (W) that emits white light, and the fourth subpixel P4 may be a green subpixel (G) that emits green light. In some possible embodiments, the arrangement of the RBWGs may be adjusted according to actual needs and is not specifically limited in this disclosure.

[0071] In one exemplary embodiment, the display substrate may include at least a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, in a direction perpendicular to the display substrate. In at least one repeating unit, the driving circuit layer may include multiple circuit units, each of which may include at least a pixel driving circuit. The pixel driving circuits are connected to scan signal lines and data signal lines, respectively. The pixel driving circuits are configured to receive data voltages transmitted by the data signal lines under the control of the scan signal lines and output a corresponding current to the light-emitting device. The light-emitting structure layer may include multiple light-emitting units, each of which may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit for the sub-pixel in which it is located. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0072] In another exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a base, a color filter structure layer disposed on a side of the driving circuit layer remote from the base, and a light-emitting structure layer disposed on a side of the color filter structure layer remote from the base. In at least one repeating unit, the color filter structure layer may include multiple color filter units, each of which may include at least a color filter layer configured to cause corresponding sub-pixels to emit light of a desired color.

[0073] In exemplary embodiments, the circuit unit referred to in this disclosure refers to an area divided by pixel driver circuits. The color filter unit referred to in this disclosure refers to an area divided by color filter layers. The light-emitting unit referred to in this disclosure refers to an area divided by light-emitting devices. The orthographic projections of the circuit unit, the color filter layer, and the light-emitting unit on the substrate may correspond or may not correspond.

[0074] In the exemplary embodiment of the present disclosure, the positions of the circuit unit's orthographic projection on the substrate, the color filter layer's orthographic projection on the substrate, and the light-emitting unit's orthographic projection on the substrate are basically corresponding. The circuit unit, the color filter unit, and the light-emitting unit constitute sub-pixels. In the following content, sub-pixels are uniformly used to refer to the circuit unit, the color filter unit, and the light-emitting unit.

[0075] Figure 3 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an exemplary embodiment of the present disclosure. As shown in Figure 3, at least one repeating unit may include four pixel driving circuits, which may be arranged in a square and may have a 3T1C structure.

[0076] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and a storage capacitor C, and the pixel driving circuit is respectively connected to the scanning signal line 30, the first power line 51, the data signal line 52, and the compensation signal line 53.

[0077] In an exemplary embodiment, each pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the storage capacitor C, respectively.

[0078] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , a second end of the storage capacitor C is connected to the second node N2 , and the storage capacitor C is used to store the potential of the gate electrode of the second transistor T2 .

[0079] In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor.

[0080] In the exemplary embodiment, a gate electrode of the first transistor T1 is connected to the scan signal line 30, a first electrode of the first transistor T1 is connected to the data signal line 52, and a second electrode of the first transistor T1 is connected to the first node N1. When a turn-on signal is applied to the scan signal line 30, the first transistor T1 inputs a data signal of the data signal line 52 to the gate electrode of the second transistor T2.

[0081] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first node N1, a first electrode of the second transistor T2 is connected to the first power line 51, and a second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received at its gate electrode.

[0082] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the scan signal line 30, a first electrode of the third transistor T3 is connected to the compensation signal line 53, and a second electrode of the third transistor T3 is connected to the second node N2. When a turn-on signal is applied to the scan signal line 30, the third transistor T3 extracts the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth.

[0083] In an exemplary embodiment, in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 30 .

[0084] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one pixel row, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 30 .

[0085] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one repeating unit, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 30 .

[0086] In an exemplary embodiment, the light-emitting device EL may be an OLED, including a stacked first electrode, an organic light-emitting layer, and a second electrode, or a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. The first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL emits light of a corresponding brightness in response to the current flowing through the second electrode of the second transistor T2. In an exemplary embodiment, the first electrode may be an anode, and the second electrode may be a cathode; alternatively, the first electrode may be a cathode, and the second electrode may be an anode.

[0087] In an exemplary embodiment, the signal of the first power line 51 is a continuously provided high level signal, and the signal of the second power line VSS is a continuously provided low level signal.

[0088] In an exemplary embodiment, the first to third transistors T1 to T3 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to third transistors T1 to T3 may include P-type transistors and N-type transistors.

[0089] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can leverage the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0090] FIG4 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a structure of four repeating units (16 subpixels) in a bottom-emission display substrate. In this exemplary embodiment, the four repeating units may include a first repeating unit Q1, a second repeating unit Q2, a third repeating unit Q3, and a fourth repeating unit Q4. The second repeating unit Q1 may be disposed on one side of the first repeating unit Q1 in the first direction X, the third repeating unit Q3 may be disposed on one side of the first repeating unit Q1 in the second direction Y, and the fourth repeating unit Q4 may be disposed on one side of the third repeating unit Q3 in the first direction X. At least one repeating unit may include four subpixels forming two pixel rows and two pixel columns. The four subpixels may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4. The second subpixel P2 may be disposed on one side of the first subpixel P1 in the first direction X, the third subpixel P3 may be disposed on one side of the first subpixel P1 in the second direction Y, and the fourth subpixel P4 may be disposed on one side of the third subpixel P3 in the first direction X. The first direction X and the second direction Y intersect, and a plurality of sub-pixels arranged sequentially along the first direction X can be referred to as a pixel row, and a plurality of sub-pixels arranged sequentially along the second direction Y can be referred to as a pixel column. The plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array.

[0091] In an exemplary embodiment, at least one sub-pixel may include a pixel driving circuit, a scanning signal line 30 and an auxiliary signal line 30A, the shape of the scanning signal line 30 and the auxiliary signal line 30A may be a line shape in which the main portion extends along the first direction X (pixel row direction), the scanning signal line 30 and the auxiliary signal line 30A may both be arranged in the middle of the repeating unit in the second direction Y (pixel column direction), and the scanning signal line 30 is configured to provide a scanning signal to the pixel driving circuit.

[0092] In an exemplary embodiment, at least one pixel driving circuit may include a storage capacitor 60 and at least one transistor, the storage capacitor may include a first electrode plate, and the at least one transistor may be connected to the first electrode plate via a connecting electrode. In a direction perpendicular to the display substrate, the display substrate may include at least a first conductive layer disposed on a substrate and a second conductive layer disposed on a side of the first conductive layer away from the substrate. The auxiliary signal line 30A and the first electrode plate may be disposed in the first conductive layer, the scanning signal line 30 and the connecting electrode may be disposed in the second conductive layer, the orthographic projection of the scanning signal line 30 on the substrate plane may be within the range of the orthographic projection of the auxiliary signal line 30A on the substrate plane, and the scanning signal line 30 and the auxiliary signal line 30A may overlap to form a signal line with a double-layer structure. In an exemplary embodiment, the overlapping of the scanning signal line 30 and the auxiliary signal line 30A means that the surface of the auxiliary signal line 30A away from the substrate is aligned with the surface of the scanning signal line 30 close to the substrate.

[0093] In an exemplary embodiment, the at least one transistor may include a second transistor T2, the second electrode of the second transistor T2 may be connected to the first electrode plate via a connecting electrode, the connecting electrode may include a first connecting electrode and a third connecting electrode, the first connecting electrode is connected to the first electrode plate, and the third connecting electrode is overlapped with the first connecting electrode.

[0094] In an exemplary embodiment, the storage capacitor may further include a second plate, the orthographic projection of the second plate on the substrate plane at least partially overlapping the orthographic projection of the first plate on the substrate plane. The second transistor T2 may include at least a second gate electrode 32, which may be connected to the second plate via a plate via K1, and the orthographic projection of the second gate electrode 32 on the substrate plane includes the orthographic projection of the plate via K1 on the substrate plane.

[0095] In an exemplary embodiment, the second transistor T2 may further include a second active layer 22, the first region of the second active layer 22 is connected to the first power line 51 through the power via K2, the first power line 51 is configured to provide a power signal to the pixel driving circuit, and the orthographic projection of the first power line 51 on the substrate plane includes the orthographic projection of the power via K2 on the substrate plane.

[0096] In an exemplary embodiment, the first regions of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are connected to each other, and / or the first regions of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are connected to each other.

[0097] In an exemplary embodiment, the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are interconnected as an integrated structure, and / or the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are interconnected as an integrated structure.

[0098] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X share the power via K2 , and / or two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the power via K2 .

[0099] In an exemplary embodiment, the at least one transistor may include a third transistor T3, a second electrode of the third transistor T3 may be connected to the first electrode plate via a connecting electrode, the connecting electrode may include a second connecting electrode and a fourth connecting electrode, the second connecting electrode is connected to the first electrode plate, and the fourth connecting electrode is overlapped with the second connecting electrode.

[0100] In an exemplary embodiment, the third transistor T3 may include at least a third active layer 23, the first region of the third active layer 23 is connected to the compensation signal line 53 through the compensation via K3, the compensation signal line 53 is configured to provide a compensation signal to the pixel driving circuit, and the orthographic projection of the compensation signal line 53 on the substrate plane includes the orthographic projection of the compensation via K3 on the substrate plane.

[0101] In an exemplary embodiment, in at least one repeating unit, the first regions of the third active layer 23 of two adjacent sub-pixels in the first direction X are connected to each other, and / or the first regions of the third active layer 23 of two adjacent sub-pixels in the second direction Y are connected to each other.

[0102] In an exemplary embodiment, in at least one repeating unit, the third active layers 23 of two adjacent sub-pixels in the first direction X are connected as one body, and / or the third active layers 23 of two adjacent sub-pixels in the second direction Y are connected as one body.

[0103] In an exemplary embodiment, in at least one repeating unit, two adjacent sub-pixels in the first direction X share the compensation via K3 , and / or two adjacent sub-pixels in the second direction Y share the compensation via K3 .

[0104] In an exemplary embodiment, the pixel driving circuit may further include a first transistor T1, which may include at least a first active layer 21. The first region of the first active layer 21 is connected to the data signal line 52 through the data via K4. The data signal line 52 is configured to provide a data signal to the pixel driving circuit. The orthographic projection of the data signal line 52 on the substrate plane includes the orthographic projection of the data via K4 on the substrate plane.

[0105] In an exemplary embodiment, the first transistor T1 may further include a first gate electrode 31 , and the third transistor T3 may further include a third gate electrode 33 . The first gate electrode 31 and the third gate electrode 33 are respectively connected to the scan signal line 30 through a gate connection electrode 34 .

[0106] In an exemplary embodiment, in the same sub-pixel, the first gate electrode 31 , the third gate electrode 33 and the gate connection electrode 34 may be provided in the same layer and form an integrated structure connected to each other.

[0107] In an exemplary embodiment, in at least one repeating unit, the first gate electrode 31 , the third gate electrode 33 and the gate connection electrode 34 of two adjacent sub-pixels in the second direction Y may be disposed in the same layer and form an interconnected integral structure.

[0108] In an exemplary embodiment, an orthographic projection of the gate connection electrode 34 on the substrate plane at least partially overlaps with an orthographic projection of the scan signal line 30 on the substrate plane, and the gate connection electrode 34 is connected to the scan signal line 30 through the gate connection via K5 .

[0109] In an exemplary embodiment, in at least one repeating unit, two sub-pixels adjacent to each other in the second direction Y share the gate connection electrode 34 .

[0110] In an exemplary embodiment, in at least one repeating unit, two adjacent sub-pixels in the second direction Y share a gate connection via K5 .

[0111] In an exemplary embodiment, at least one repeating unit may include one scan signal line 30, two first power lines 51, four data signal lines 52, and one compensation signal line 53. Each of these signal lines is connected to a pixel driving circuit in a corresponding sub-pixel. In an exemplary embodiment, the first power line 51, the data signal line 52, and the compensation signal line 53 may be in the form of lines with their main portions extending along the second direction Y (pixel column direction). The compensation signal line 53 may be located in the middle of the repeating unit in the first direction X. The two first power lines 51 may be located on either side of the repeating unit in the first direction X. The four data signal lines 52 and the compensation signal line 53 may be located between the two first power lines 51. Two of the four data signal lines 52 may be located on a side of one first power line 51 close to the compensation signal line 53. The other two of the four data signal lines 52 may be located on a side of another first power line 51 close to the compensation signal line 53. A storage capacitor 60 in the pixel driving circuit may be located between the data signal lines 52 and the compensation signal line 53. In this way, a scanning signal line 30 extending along the first direction X defines two pixel rows, and a compensation signal line 53 extending along the second direction Y can define two pixel columns, forming a repeating unit of a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a fourth sub-pixel P4.

[0112] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in a first direction X refer to: in a first repeating unit Q1 and a second repeating unit Q2 adjacent in the first direction X, the second sub-pixel of the first repeating unit Q1 and the first sub-pixel of the second repeating unit Q2 are adjacent sub-pixels in the first direction X, and the fourth sub-pixel of the first repeating unit Q1 and the third sub-pixel of the second repeating unit Q2 are adjacent sub-pixels in the first direction X. Two adjacent sub-pixels in two adjacent repeating units in a second direction Y refer to: in a first repeating unit Q1 and a third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel of the first repeating unit Q1 and the first sub-pixel of the third repeating unit Q3 are adjacent sub-pixels in the second direction Y, and the fourth sub-pixel of the first repeating unit Q1 and the second sub-pixel of the third repeating unit Q3 are adjacent sub-pixels in the second direction Y.

[0113] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a first conductive layer, a second conductive layer, a semiconductor layer and a third conductive layer sequentially arranged on a base, the auxiliary signal line 30A and the first electrode plate of the storage capacitor 60 may be arranged in the first conductive layer, the scanning signal line 30 may be arranged in the second conductive layer, the first active layer 21, the second active layer 22, the third active layer 23 and the second electrode plate of the storage capacitor 60 may be arranged in the semiconductor layer, and the first gate electrode 31, the second gate electrode 32, the third gate electrode 33, the gate connection electrode 34, the first power line 51, the data signal line 52 and the compensation signal line 53 may be arranged in the third conductive layer.

[0114] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes depositing a film layer, coating a photoresist on the film layer, mask exposure, development, etching, stripping the photoresist, and other processes for metal materials, inorganic materials or transparent conductive materials. For organic materials, it includes coating an organic material, mask exposure and development, and other processes. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be achieved by any one or more of spraying, spin coating and inkjet printing. Etching can be achieved by any one or more of dry etching and wet etching. This disclosure does not limit this. "Thin film" refers to a thin film made by depositing, coating or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0115] In an exemplary embodiment, taking four repeating units (a first repeating unit Q1 , a second repeating unit Q2 , a third repeating unit Q3 , and a fourth repeating unit Q4 ) as an example, this embodiment shows that the preparation process of the substrate may include the following operations.

[0116] (1) Forming patterns of the first conductive layer and the second conductive layer. In an exemplary embodiment, forming the patterns of the first conductive layer and the second conductive layer may include: sequentially depositing a first conductive film and a second conductive film on a substrate, patterning the first conductive film and the second conductive film through a patterning process, and forming patterns of the first conductive layer and the second conductive layer on the substrate, as shown in Figures 5A, 5B, 5C, and 5D, where Figure 5B is a schematic diagram of the first conductive layer in Figure 5A, Figure 5C is a schematic diagram of the second conductive layer in Figure 5A, and Figure 5D is a cross-sectional view taken along the AA direction in Figure 5A. In an exemplary embodiment, the first conductive layer may be referred to as a first transparent (1ITO) layer, and the second conductive layer may be referred to as a light shielding (SHL) layer.

[0117] As shown in Figures 5A, 5B and 5C, the first conductive layer of each sub-pixel in each repeating unit may include at least a first connecting electrode 11, a second connecting electrode 12, an auxiliary signal line 30A and a first plate 61 of the storage capacitor, and the second conductive layer of each sub-pixel in each repeating unit may include at least a third connecting electrode 13, a fourth connecting electrode 14 and a scanning signal line 30.

[0118] In an exemplary embodiment, the shape of the first electrode plate 61 can be rectangular, and the corners of the rectangle can be chamfered. The first electrode plate 61 can serve as a transparent electrode plate of a transparent storage capacitor. The first electrode plate 61 is configured to form a transparent storage capacitor with the subsequently formed second electrode plate.

[0119] In an exemplary embodiment, the first and third connection electrodes 11 and 13 may be located on one side of the first electrode plate 61 in the second direction Y, and the second and fourth connection electrodes 12 and 14 may be located on the other side of the first electrode plate 61 in the second direction Y.

[0120] In an exemplary embodiment, in one repeating unit, the first connection electrode 11 and the third connection electrode 13 in the first subpixel P1 and the second subpixel P2 may be disposed on one side of the first electrode plate 61 in the direction opposite to the second direction Y, and the second connection electrode 12 and the fourth connection electrode 14 may be disposed on one side of the first electrode plate 61 in the second direction Y. In the third subpixel P3 and the fourth subpixel P4, the first connection electrode 11 and the third connection electrode 13 may be disposed on one side of the first electrode plate 61 in the second direction Y, and the second connection electrode 12 and the fourth connection electrode 14 may be disposed on one side of the first electrode plate 61 in the direction opposite to the second direction Y.

[0121] In an exemplary embodiment, the first connecting electrode 11 and the third connecting electrode 13 may be block-shaped (e.g., rectangular), with the orthographic projection of the third connecting electrode 13 on the substrate completely overlapping the orthographic projection of the first connecting electrode 11 on the substrate. A first end of the first connecting electrode 11 is connected to the first electrode plate 61, and a second end of the first connecting electrode 11 extends away from the first electrode plate 61. The third connecting electrode 13 directly overlaps the first connecting electrode 11. The third connecting electrode 13 is configured to connect to a subsequently formed fifth connecting electrode and to shield the second transistor from light, thereby reducing the intensity of light incident on the second transistor and lowering leakage current in the second transistor, thereby alleviating the impact of light on the characteristics of the second transistor.

[0122] In an exemplary embodiment, the second connection electrode 12 and the fourth connection electrode 14 may be block-shaped (e.g., rectangular), and the orthographic projection of the fourth connection electrode 14 on the substrate completely overlaps the orthographic projection of the second connection electrode 12 on the substrate. A first end of the second connection electrode 12 is connected to the first electrode plate 61, and a second end of the second connection electrode 12 extends away from the first electrode plate 61. The fourth connection electrode 14 directly overlaps the second connection electrode 12 and is configured to be connected to a subsequently formed sixth connection electrode.

[0123] In an exemplary embodiment, the first connection electrode 11 , the second connection electrode 12 , and the first electrode plate 61 of each sub-pixel may be an integrated structure connected to each other.

[0124] In an exemplary embodiment, the shape of the scanning signal line 30 and the auxiliary signal line 30A can be a line shape in which the main portion extends along the first direction X, and can be arranged in the middle of the repeating unit in the second direction Y, that is, between the first sub-pixel P1 and the second sub-pixel P2 and the third sub-pixel P3 and the fourth sub-pixel P4. The scanning signal line 30 is configured to simultaneously control the conduction or disconnection of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0125] In an exemplary embodiment, patterning the first conductive film and the second conductive film through a patterning process may include: after sequentially depositing the first conductive film and the second conductive film, coating a layer of photoresist on the second conductive film, exposing the photoresist using a half-tone mask, and developing the photoresist to form a fully exposed area, a partially exposed area, and an unexposed area. The photoresist in the fully exposed area is removed, exposing the surface of the second conductive film in the fully exposed area, and the photoresist in the partially exposed area is partially removed. The photoresist in the partially exposed area has a first thickness, and the photoresist in the unexposed area remains unchanged. The photoresist in the unexposed area has a second thickness, and the first thickness is less than the second thickness. The unexposed area is the area where the third connecting electrode 13, the fourth connecting electrode 14, and the scan signal line 30 are located, and the partially exposed area is the area where the first electrode 61 is located. Subsequently, a first etching process is performed to etch away the first and second conductive films in the fully exposed areas, forming patterns of the scanning signal lines 30 and the auxiliary signal lines 30A. The orthographic projection of the scanning signal lines 30 on the substrate plane is within the range of the orthographic projection of the auxiliary signal lines 30A on the substrate plane. The scanning signal lines 30 and the auxiliary signal lines 30A overlap, i.e., the surface of the scanning signal lines 30 close to the substrate aligns with the surface of the auxiliary signal lines 30A away from the substrate. Subsequently, an ashing process is performed to remove the photoresist in the partially exposed areas, exposing the surface of the second conductive film in the partially exposed areas, while the unexposed areas remain covered with photoresist. Subsequently, a second etching process is performed to etch away the partially exposed areas of the second conductive film, exposing the first conductive film and forming patterns of the first connecting electrode 11, the second connecting electrode 12, the third connecting electrode 13, the fourth connecting electrode 14, and the first electrode plate 61. The orthographic projection of the third connecting electrode 13 on the substrate completely overlaps with the orthographic projection of the first connecting electrode 11 on the substrate, and the third connecting electrode 13 directly overlaps with the first connecting electrode 11. The orthographic projection of the fourth connecting electrode 14 on the substrate completely overlaps with the orthographic projection of the second connecting electrode 12 on the substrate, and the fourth connecting electrode 14 directly overlaps with the second connecting electrode 12. Finally, the remaining photoresist is stripped.

[0126] As shown in Figure 5D, through this patterning process, a first conductive layer and a second conductive layer arranged on the side of the first conductive layer away from the substrate 10 are formed on the substrate 10. The first conductive layer may include at least a first connecting electrode 11, a second connecting electrode 12, an auxiliary signal line 30A and a first electrode plate 61, and the second conductive layer may include at least a third connecting electrode 13, a fourth connecting electrode 14 and a scanning signal line 30. The orthographic projection of the third connecting electrode 13 on the substrate completely overlaps with the orthographic projection of the first connecting electrode 11 on the substrate, and the third connecting electrode 13 is directly overlapped with the first connecting electrode 11. The orthographic projection of the fourth connecting electrode 14 on the substrate completely overlaps with the orthographic projection of the second connecting electrode 12 on the substrate, and the fourth connecting electrode 14 is directly overlapped with the second connecting electrode 12.

[0127] In an exemplary embodiment, the scan signal lines 30 and the auxiliary signal lines 30A form a double-layer signal line structure, which can effectively reduce the resistance of the scan signal lines, lower the voltage drop of the scan signals, and improve display performance.

[0128] In an exemplary embodiment, the material of the first conductive layer can be a transparent conductive material, such as indium tin oxide ITO or indium zinc oxide IZO, and the material of the second conductive layer can be a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0129] In an exemplary embodiment, in at least one repeating unit, the positions of the respective patterns in the first conductive layer and the second conductive layer in the first subpixel P1 and the positions of the respective patterns in the first conductive layer and the second conductive layer in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the positions of the respective patterns in the first conductive layer and the second conductive layer in the second subpixel P2 and the positions of the respective patterns in the first conductive layer and the second conductive layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the horizontal reference line, the positions of the respective patterns in the first conductive layer and the second conductive layer in the first subpixel P1 and the positions of the respective patterns in the first conductive layer and the second conductive layer in the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the positions of the respective patterns in the first conductive layer and the second conductive layer in the third subpixel P3 and the positions of the respective patterns in the first conductive layer and the second conductive layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line. The horizontal reference line may be a straight line extending along the first direction X and bisecting the repeating unit in the second direction Y, and the vertical reference line may be a straight line extending along the second direction Y and bisecting the repeating unit in the first direction X.

[0130] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer and the second conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIG6A, FIG6B, and FIG6C, where FIG6B is a schematic diagram of the semiconductor layer in FIG6A, and FIG6C is a cross-sectional view taken along line AA in FIG6A.

[0131] In an exemplary embodiment, the semiconductor layer of each sub-pixel in each repeating unit may include at least a first active layer 21, a second active layer 22, a third active layer 23, and a second electrode 62 of a storage capacitor. The first active layer 21 may serve as an active layer of the first transistor T1, the second active layer 22 may serve as an active layer of the second transistor T2, and the third active layer 23 may serve as an active layer of the third transistor T3. The second electrode 62 may serve as another transparent electrode of a transparent storage capacitor. The second electrode 62 is configured to form a transparent storage capacitor with the first electrode 61.

[0132] In an exemplary embodiment, the first active layer 21 and the third active layer 23 can be arranged on the side of the first electrode 61 of the sub-pixel close to the scanning signal line 30, and the second active layer 22 can be arranged on the side of the first electrode 61 of the sub-pixel away from the scanning signal line 30.

[0133] In example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.

[0134] In an exemplary embodiment, the first region of the first active layer 21 of each subpixel is disposed on a side away from the first electrode plate 61 , and the second region of the first active layer 21 is disposed on a side close to the first electrode plate 61 and connected to the second electrode plate 62 .

[0135] In an exemplary embodiment, the first region of the second active layer 22 of each sub-pixel is arranged on a side away from the first electrode 61, and the orthographic projection of the first region of the second active layer 22 on the substrate does not overlap with the orthographic projection of the third connection electrode 13 of the sub-pixel on the substrate. The second region of the second active layer 22 is arranged on a side close to the first electrode 61, and the orthographic projection of the second region and the channel region of the second active layer 22 on the substrate at least partially overlaps with the orthographic projection of the third connection electrode 13 on the substrate, so that the third connection electrode 13 as a shielding layer can shield the channel region of the second transistor T2, thereby preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2.

[0136] In an exemplary embodiment, the first regions of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the first direction X may be interconnected, so that the second transistors of the two adjacent sub-pixels in the two adjacent repeating units in the first direction X share the first region of the second active layer. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the first region of the second active layer 22 of the second sub-pixel P2 in the first repeating unit Q1 and the first region of the second active layer 22 of the first sub-pixel P1 in the second repeating unit Q2 are interconnected. The first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1 and the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2 are interconnected. For another example, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the first region of the second active layer 22 of the second sub-pixel P2 in the third repeating unit Q3 and the first region of the second active layer 22 of the first sub-pixel P1 in the fourth repeating unit Q4 are interconnected. The first region of the second active layer 22 of the fourth subpixel P4 in the third repetition unit Q3 and the first region of the second active layer 22 of the third subpixel P3 in the fourth repetition unit Q4 are connected to each other.

[0137] In an exemplary embodiment, the first regions of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integral structure connected to each other.

[0138] In an exemplary embodiment, the first regions of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y may be connected to each other, so that the second transistors of the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y share the first region of the second active layer. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent to each other in the second direction Y, the first region of the second active layer 22 of the third sub-pixel P3 in the first repeating unit Q1 and the first region of the second active layer 22 of the first sub-pixel P1 in the third repeating unit Q3 may be connected to each other, and the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1 and the first region of the second active layer 22 of the second sub-pixel P2 in the third repeating unit Q3 may be connected to each other. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent to each other in the second direction Y, the first area of ​​the second active layer 22 of the third subpixel P3 in the second repeating unit Q2 and the first area of ​​the second active layer 22 of the first subpixel P1 in the fourth repeating unit Q4 can be connected to each other, and the first area of ​​the second active layer 22 of the fourth subpixel P4 in the second repeating unit Q2 and the first area of ​​the second active layer 22 of the second subpixel P2 in the fourth repeating unit Q4 can be connected to each other.

[0139] In an exemplary embodiment, the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y may be an integral structure connected to each other.

[0140] In an exemplary embodiment, the first regions of the second active layer 22 of adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y may be connected to each other. For example, the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1, the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2, the first region of the second active layer 22 of the second sub-pixel P2 in the third repeating unit Q3, and the first region of the second active layer 22 of the first sub-pixel P1 in the fourth repeating unit Q4 may be connected to each other.

[0141] In an exemplary embodiment, the second active layers 22 of adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y may be interconnected and integrated. By arranging for the second transistors of four adjacent sub-pixels in adjacent repeating units to share the first region of the second active layer, the present disclosure not only effectively reduces the number of vias, reduces the area occupied by the pixel drive circuit, increases the pixel aperture ratio, and improves display resolution, but also reduces the number of vias, simplifies the manufacturing process, reduces production costs, and improves product yield.

[0142] In an exemplary embodiment, the first region of the third active layer 23 of each sub-pixel is arranged on a side away from the first electrode 61, the second region of the third active layer 23 is arranged on a side close to the first electrode 61, and the orthographic projection of the second region of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the fourth connecting electrode 14 of the sub-pixel on the substrate.

[0143] In an exemplary embodiment, in at least one repeating unit, the first area of ​​the third active layer 23 in the first subpixel P1 and the first area of ​​the third active layer 23 in the second subpixel P2 can be connected to each other, and the first area of ​​the third active layer 23 in the third subpixel P3 and the first area of ​​the third active layer 23 in the fourth subpixel P4 can be connected to each other, that is, the first areas of the third active layer 23 of two adjacent subpixels in one pixel row are connected to each other, and thus the third transistors of two adjacent subpixels in one pixel row share the first area of ​​the third active layer.

[0144] In an exemplary embodiment, the third active layer 23 in the first subpixel P1 and the third active layer 23 in the second subpixel P2 can be an interconnected integral structure, and the third active layer 23 in the third subpixel P3 and the third active layer 23 in the fourth subpixel P4 can be an interconnected integral structure, that is, the third active layers 23 of two adjacent subpixels in a pixel row are an interconnected integral structure.

[0145] In an exemplary embodiment, in at least one repeating unit, the first area of ​​the third active layer 23 in the first subpixel P1 and the first area of ​​the third active layer 23 in the third subpixel P3 can be connected to each other, and the first area of ​​the third active layer 23 in the second subpixel P2 and the first area of ​​the third active layer 23 in the fourth subpixel P4 can be connected to each other, that is, the first areas of the third active layer 23 of two adjacent subpixels in a pixel column are connected to each other, and thus the third transistors of two adjacent subpixels in a pixel column share the first area of ​​the third active layer.

[0146] In an exemplary embodiment, the third active layer 23 in the first sub-pixel P1 and the third active layer 23 in the third sub-pixel P3 can be an interconnected integral structure, and the third active layer 23 in the second sub-pixel P2 and the third active layer 23 in the fourth sub-pixel P4 can be an interconnected integral structure, that is, the third active layers 23 of two adjacent sub-pixels in a pixel column are an interconnected integral structure.

[0147] In an exemplary embodiment, the first regions of the third active layers 23 of adjacent sub-pixels in at least one repeating unit may be connected to each other. For example, the first regions of the third active layers 23 of the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4 may be connected to each other.

[0148] In an exemplary embodiment, the third active layers 23 of adjacent sub-pixels in at least one repeating unit may be interconnected and integrated. By arranging for the third transistors of adjacent sub-pixels to share the first region of the third active layer, the present disclosure not only effectively reduces the number of vias, reduces the area occupied by the pixel driver circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0149] In an exemplary embodiment, the shape of the second electrode plate 62 can be rectangular, the corners of the rectangle can be chamfered, and it can be arranged between the second active layer 22 and the third active layer 23 of the sub-pixel. The orthographic projection of the second electrode plate 62 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 61 on the substrate. The second electrode plate 62 can serve as another transparent electrode plate of the transparent storage capacitor, and the first electrode plate 61 and the second electrode plate 62 form a transparent storage capacitor.

[0150] In an exemplary embodiment, the second electrode plate 62 and the first active layer 21 of each sub-pixel may be an integral structure connected to each other.

[0151] In an exemplary embodiment, in each sub-pixel, the overlapping area of ​​the orthographic projection of the first plate 61 and the orthographic projection of the second plate 62 on the substrate may be substantially the same, so that the capacity of the storage capacitor in each sub-pixel is substantially the same.

[0152] In an exemplary embodiment, patterning a semiconductor thin film through a patterning process may include: after depositing the semiconductor thin film, coating a layer of photoresist on the semiconductor thin film, exposing the photoresist using a halftone mask, and developing the photoresist to form fully exposed areas, partially exposed areas, and unexposed areas. The photoresist in the fully exposed areas is removed, exposing the surface of the semiconductor thin film. The photoresist in the partially exposed areas is partially removed, and the photoresist in the partially exposed areas has a first thickness. The photoresist in the unexposed areas remains unchanged, and the photoresist in the unexposed areas has a second thickness, wherein the first thickness is less than the second thickness. The unexposed areas constitute the channel regions of each active layer, and the partially exposed areas constitute the areas requiring conductorization. Subsequently, the semiconductor thin film in the fully exposed areas is etched away through an etching process to form patterns of the first active layer 21, the second active layer 22, the third active layer 23, and the second electrode 62. Subsequently, an ashing process is used to remove the photoresist from the partially exposed areas, exposing the semiconductor layer. Unexposed areas remain covered with photoresist. Specifically, the channel region of each active layer is covered with photoresist, while areas outside the channel region are exposed. Subsequently, the semiconductor layer in the partially exposed areas is subjected to a conductorization process to form a conductorized second electrode plate 62 and conductorized first and second regions of each active layer. Finally, the remaining photoresist is stripped.

[0153] As shown in Figure 6C, through this patterning process, a first insulating layer 71 covering the first conductive layer and the second conductive layer is formed, as well as a semiconductor layer arranged on the side of the first insulating layer 71 away from the substrate 10. The semiconductor layer may include at least a second active layer 22, a third active layer 23, and a second electrode 62. The orthographic projection of the second electrode 62 on the substrate at least partially overlaps with the orthographic projection of the first electrode 61 on the substrate, and the first electrode 61 and the second electrode 62 form a transparent storage capacitor.

[0154] In exemplary embodiments, the semiconductor layer may be formed of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0155] In an exemplary embodiment, in at least one repeating unit, the position of each pattern in the semiconductor layer in the first subpixel P1 and the position of each pattern in the semiconductor layer in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the semiconductor layer in the second subpixel P2 and the position of each pattern in the semiconductor layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the semiconductor layer in the first subpixel P1 and the position of each pattern in the semiconductor layer in the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the position of each pattern in the semiconductor layer in the third subpixel P3 and the position of each pattern in the semiconductor layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line.

[0156] (3) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film through a patterning process to form a second insulating layer pattern covering the semiconductor layer, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG7A and FIG7B , FIG7B being a cross-sectional view taken along line AA in FIG7A .

[0157] In an exemplary embodiment, the plurality of via holes of each sub-pixel in each repeating unit includes at least a first via hole V1 , a second via hole V2 , a third via hole V3 , a fourth via hole V4 , a fifth via hole V5 , a sixth via hole V6 , and a seventh via hole V7 .

[0158] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer 21 on the substrate. The second insulating layer within the first via hole V1 is etched away, exposing the surface of the first region of the first active layer 21. The first via hole V1 is configured to allow a subsequently formed data signal line to pass through the via hole and simultaneously connect to the first region of the first active layer 21. In an exemplary embodiment, the first via hole V1 can serve as a data via of the present disclosure.

[0159] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is within the range of the orthographic projection of the first region of the second active layer 22 on the substrate. The second insulating layer within the second via V2 is etched away, exposing the surface of the first region of the second active layer 22. The second via V2 is configured to connect a subsequently formed first power line to the first region of the second active layer 22 through the via. In an exemplary embodiment, the second via V2 can serve as the power via of the present disclosure.

[0160] In an exemplary embodiment, because the first regions of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are interconnected, the two adjacent sub-pixels in the two adjacent repeating units in the first direction X can share the same second via hole V2. For example, the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 can share the same second via hole V2. For another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 can share the same second via hole V2.

[0161] In an exemplary embodiment, because the first regions of the second active layer 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are interconnected, the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y can share the same second via hole V2. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 can share the same second via hole V2. For another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 can share the same second via hole V2.

[0162] In an exemplary embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same second via hole V2 , that is, adjacent four sub-pixels in adjacent repeating units share the same second via hole V2 . For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth subpixel P4 of the first repeating unit Q1 and the third subpixel P3 of the second repeating unit Q2 are two adjacent subpixels; for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the second subpixel P2 of the third repeating unit Q3 and the first subpixel P1 of the fourth repeating unit Q4 are two adjacent subpixels; for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the fourth subpixel P4 of the first repeating unit Q1 and the second subpixel P2 of the third repeating unit Q3 are two adjacent subpixels; for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third subpixel P3 of the second repeating unit Q2 and the first subpixel P1 of the fourth repeating unit Q4 are two adjacent subpixels; the fourth subpixel P4 of the first repeating unit Q1, the third subpixel P3 of the second repeating unit Q2, the second subpixel P2 of the third repeating unit Q3 and the first subpixel P1 of the fourth repeating unit Q4 share the same second via hole V2. The present disclosure arranges that four adjacent sub-pixels in adjacent repeating units share the same second via hole V2, which not only effectively reduces the number of via holes, reduces the occupied area of ​​the pixel driving circuit, increases the pixel aperture ratio, and improves the display resolution, but also reduces the number of via holes, simplifies the preparation process, reduces production costs, and improves product yield.

[0163] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the second region of the second active layer 22 and the third connecting electrode 13 on the substrate. The third via hole V3 is a via hole with a transition structure, including a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away, exposing the surface of the second region of the second active layer 22. The first and second insulating layers in the deep half-hole are etched away, exposing the surface of the third connecting electrode 13. This allows the via hole in the transition structure, consisting of the two half-holes, to simultaneously expose the second region of the second active layer 22 and the third connecting electrode 13. The third via hole V3 is configured to allow a subsequently formed fifth connecting electrode to be simultaneously connected to the second region of the second active layer 22 and the third connecting electrode 13 through this via hole. The third via hole V3 can serve as the first overlapping via hole of the present disclosure.

[0164] In an exemplary embodiment, a first size L1 of the third via hole V3 may be greater than a second size L2 of the third via hole V3 , wherein the first size L1 is a size of the third via hole V3 in the first direction X and the second size L2 is a size of the third via hole V3 in the second direction Y.

[0165] In an exemplary embodiment, the second via hole V2 and the third via hole V3 are not on a straight line extending along the first direction X.

[0166] In an exemplary embodiment, in the second direction Y, the second via hole V2 shared by two adjacent sub-pixels in two adjacent repeating units may be located between two adjacent third via holes V3 in two adjacent repeating units.

[0167] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the first region of the third active layer 23 on the substrate. The second insulating layer within the fourth via V4 is etched away, exposing the surface of the first region of the third active layer 23. The fourth via V4 is configured to connect a subsequently formed compensation signal line to the first region of the third active layer 23 through the via. In an exemplary embodiment, the fourth via V4 can serve as the compensation via of the present disclosure.

[0168] In an exemplary embodiment, since the first regions of the third active layer 23 of two adjacent sub-pixels in the first direction X in one repeating unit are connected to each other, the two adjacent sub-pixels in the first direction X may share the same fourth via hole V4.

[0169] In an exemplary embodiment, since the first regions of the third active layer 23 of two adjacent sub-pixels in the second direction Y in one repeating unit are connected to each other, the two adjacent sub-pixels in the second direction Y may share the same fourth via hole V4.

[0170] In this exemplary embodiment, since the first regions of the third active layers of the four sub-pixels in a repeating unit are interconnected, the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4 in the repeating unit can share the same fourth via hole V4. By arranging for adjacent sub-pixels to share the same fourth via hole V4, the present disclosure not only effectively reduces the number of via holes, reducing the area occupied by the pixel drive circuit, increasing the pixel aperture ratio, and improving display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0171] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 14 on the substrate. The fifth via V5 is a via hole with a transition structure, including a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away, exposing the surface of the second region of the third active layer 23. The first and second insulating layers in the deep half-hole are etched away, exposing the surface of the fourth connecting electrode 14. This allows the via hole in the transition structure, consisting of the two half-holes, to simultaneously expose the second region of the third active layer 23 and the fourth connecting electrode 14. The fifth via V5 is configured to allow a subsequently formed sixth connecting electrode to be simultaneously connected to the second region of the third active layer 23 and the fourth connecting electrode 14 through this via hole. The fifth via V5 can serve as the second overlapping via hole of the present disclosure.

[0172] In an exemplary embodiment, a third size L3 of the fifth via hole V5 may be smaller than a fourth size L4 of the fifth via hole V5 , where the third size L3 is the size of the fifth via hole V5 in the first direction X and the fourth size L4 is the size of the fifth via hole V5 in the second direction Y.

[0173] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is within the range of the orthographic projection of the second electrode plate 62 on the substrate. The second insulating layer within the sixth via V6 is etched away, exposing the surface of the second electrode plate 62. The sixth via V6 is configured to connect a subsequently formed second gate electrode to the second electrode plate 62 through the via. In an exemplary embodiment, the sixth via V6 can serve as the electrode plate via of the present disclosure.

[0174] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the scan signal line 30 on the substrate. The first insulating layer and the second insulating layer within the seventh via hole V7 are etched away, exposing the surface of the scan signal line 30. The seventh via hole V7 is configured to connect a subsequently formed gate connection electrode to the scan signal line 30 through the via hole. In an exemplary embodiment, the seventh via hole V7 serves as the gate connection via hole of this embodiment.

[0175] In an exemplary embodiment, in at least one repeating unit, the first subpixel P1 and the third subpixel P3 may share a seventh via hole V7, and the second subpixel P2 and the fourth subpixel P4 may share a seventh via hole V7. That is, two adjacent subpixels in the second direction Y share a seventh via hole V7. By providing a shared seventh via hole V7 for two adjacent subpixels, the present disclosure not only effectively reduces the number of via holes, reduces the area occupied by the pixel driver circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield.

[0176] As shown in Figure 7B, this patterning process forms a second insulating layer 72 covering the semiconductor layer. At least a fifth via hole V5, a sixth via hole V6, and a seventh via hole V7 are provided on the second insulating layer 72. The fifth via hole V5 includes a shallow half hole and a deep half hole. The second insulating layer 72 in the shallow half hole is etched away, exposing the surface of the third active layer 23. The first insulating layer 71 and the second insulating layer 72 in the deep half hole are etched away, exposing the surface of the fourth connecting electrode 14. This allows the fifth via hole V5, which consists of two half holes in the transition structure, to simultaneously expose the third active layer 23 and the fourth connecting electrode 14. The second insulating layer 72 in the sixth via hole V6 is etched away, exposing the surface of the second electrode plate 62. The first insulating layer 71 and the second insulating layer 72 in the seventh via hole V7 are etched away, exposing the surface of the scan signal line 30.

[0177] (4) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film through a patterning process, and forming a third conductive layer pattern on the second insulating layer, as shown in FIG8A , FIG8B , and FIG8C , where FIG8B is a schematic diagram of the third conductive layer in FIG8A , and FIG8C is a cross-sectional view taken along the AA line in FIG8A . In an exemplary embodiment, the third conductive layer may be referred to as a gate metal (GT) layer.

[0178] In an exemplary embodiment, the third conductive layer of each subpixel in each repeating unit may include at least the fifth connection electrode 15 , the sixth connection electrode 16 , the first gate electrode 31 , the second gate electrode 32 , the third gate electrode 33 and the gate connection electrode 34 .

[0179] In an exemplary embodiment, the fifth connection electrode 15 can be in a block shape (such as a rectangle) and can be arranged on a side of the second electrode plate 62 away from the scan signal line 30. The fifth connection electrode 15 is connected to the second region of the second active layer 22 and the third connection electrode 13 at the same time through the third via hole V3.

[0180] In an exemplary embodiment, the orthographic projection of the fifth connection electrode 15 on the substrate may include the orthographic projection of the third via hole V3 on the substrate.

[0181] In the exemplary embodiment, the fifth connection electrode 15 is connected to both the second region of the second active layer 22 and the third connection electrode 13, the third connection electrode 13 is connected to the first connection electrode 11, and the first connection electrode 11 is connected to the first electrode plate 61. Therefore, the fifth connection electrode 15 allows the second electrode and the first electrode plate 61 of the second transistor to have the same potential. In the exemplary embodiment, the fifth connection electrode 15 is configured to be connected to an anode connection electrode to be formed later.

[0182] In an exemplary embodiment, the sixth connection electrode 16 can be in a block shape (such as a rectangle) and can be arranged on the side of the second electrode plate 62 close to the scan signal line 30. The sixth connection electrode 16 is simultaneously connected to the second region of the third active layer 23 and the fourth connection electrode 14 through the fifth via hole V5.

[0183] In an exemplary embodiment, the orthographic projection of the sixth connection electrode 16 on the substrate may include the orthographic projection of the fifth via hole V5 on the substrate.

[0184] In an exemplary embodiment, since the sixth connection electrode 16 is connected to the second region of the third active layer 23 and the fourth connection electrode 14 at the same time, the fourth connection electrode 14 is connected to the second connection electrode 12, and the second connection electrode 12 is connected to the first electrode plate 61, the sixth connection electrode 16 enables the second electrode and the first electrode plate 61 of the third transistor to have the same potential.

[0185] In an exemplary embodiment, the fifth connecting electrode 15 and the sixth connecting electrode 16 realize the connection between the second electrode of the second transistor, the second electrode of the third transistor and the first electrode plate 61 (the second end of the storage capacitor), forming a second node in the pixel driving circuit, so that the first electrode plate 61 has the potential of the second node in the pixel driving circuit.

[0186] In an exemplary embodiment, the gate connection electrode 34 may be in the shape of a strip extending along the first direction X and may be disposed in the middle of the repeating unit in the second direction Y, i.e., between the first subpixel P1 and the second subpixel P2 and the third subpixel P3 and the fourth subpixel P4. The orthographic projection of the gate connection electrode 34 on the substrate at least partially overlaps with the orthographic projection of the scan signal line 30 on the substrate. The gate connection electrode 34 is connected to the scan signal line 30 through the seventh via hole V7. In an exemplary embodiment, the orthographic projection of the gate connection electrode 34 on the substrate may include the orthographic projection of the seventh via hole V7 (gate connection via hole) on the substrate.

[0187] In an exemplary embodiment, in at least one repeating unit, the first subpixel P1 and the third subpixel P3 may share a gate connection electrode 34, and the second subpixel P2 and the fourth subpixel P4 may share a gate connection electrode 34. That is, two adjacent subpixels in the second direction Y may share a gate connection electrode 34. By providing a shared gate connection electrode 34 for two adjacent subpixels, the present disclosure not only effectively reduces the number of connection electrodes, reduces the area occupied by the pixel driving circuit, increases the pixel aperture ratio, and improves display resolution, but also simplifies the manufacturing process, reduces production costs, and improves product yield by reducing the number of connection electrodes.

[0188] In an exemplary embodiment, the first gate electrode 31 may be in the shape of a strip extending along the second direction Y. It may be disposed on a side of the gate connection electrode 34 close to the first active layer 21. A first end of the first gate electrode 31 is connected to the gate connection electrode 34, and a second end of the first gate electrode 31 extends toward the first active layer 21. The orthographic projection of the first gate electrode 31 on the substrate at least partially overlaps with the orthographic projection of the first active layer 21 on the substrate. In an exemplary embodiment, the first gate electrode 31 may serve as the gate electrode of the first transistor T1 and may control whether the first transistor T1 is turned on or off.

[0189] In an exemplary embodiment, the first gate electrode 31 and the gate connecting electrode 34 may be interconnected as an integral structure. Since two adjacent sub-pixels share a common gate connecting electrode 34, the gate connecting electrode 34 and the first gate electrodes 31 of the two adjacent sub-pixels are interconnected as an integral structure. For example, the gate connecting electrode 34, the first gate electrode 31 of the first sub-pixel P1, and the first gate electrode 31 of the third sub-pixel P3 are interconnected as an integral structure. For another example, the gate connecting electrode 34, the first gate electrode 31 of the second sub-pixel P2, and the first gate electrode 31 of the fourth sub-pixel P4 are interconnected as an integral structure.

[0190] In an exemplary embodiment, the second gate electrode 32 may be in the shape of a strip extending along the second direction Y. A first end of the second gate electrode 32 is connected to the second electrode plate 62 via a sixth via V6, and a second end of the second gate electrode 32 extends toward the second active layer 22. The orthographic projection of the second gate electrode 32 on the substrate at least partially overlaps with the orthographic projection of the second active layer 22 on the substrate. In an exemplary embodiment, the second gate electrode 32 may serve as the gate electrode of the second transistor T2 and may control whether the second transistor T2 is turned on or off.

[0191] In an exemplary embodiment, the orthographic projection of the second gate electrode 32 on the substrate may include the orthographic projection of the sixth via hole V6 (plate via hole) on the substrate.

[0192] In an exemplary embodiment, since the second gate electrode 32 is connected to the second electrode plate 62, and the second electrode plate 62 is connected to the second region of the first active layer 21, the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate 62 (the first end of the storage capacitor) have the same potential, forming a first node in the pixel driving circuit, and the second electrode plate 62 has the potential of the first node in the pixel driving circuit.

[0193] In an exemplary embodiment, since the first plate 61 has the potential of the second node in the pixel driving circuit and the second plate 62 has the potential of the first node in the pixel driving circuit, the first plate 61 having the potential of the second node and the second plate 62 having the potential of the first node form a storage capacitor.

[0194] In an exemplary embodiment, since the first electrode 61 is made of a transparent conductive material and the second electrode 62 is made of a transparent metal oxide, the storage capacitor is a transparent capacitor.

[0195] In an exemplary embodiment, the third gate electrode 33 may be in the shape of a strip extending along the second direction Y. It may be disposed on a side of the gate connection electrode 34 close to the third active layer 23. A first end of the third gate electrode 33 is connected to the gate connection electrode 34, and a second end of the third gate electrode 33 extends toward the third active layer 23. The orthographic projection of the third gate electrode 33 on the substrate at least partially overlaps with the orthographic projection of the third active layer 23 on the substrate. In an exemplary embodiment, the third gate electrode 33 may serve as the gate electrode of the third transistor T3 and may control whether the third transistor T3 is turned on or off.

[0196] In an exemplary embodiment, the third gate electrode 33 and the gate connecting electrode 34 may be interconnected as an integral structure. Since two adjacent sub-pixels share a common gate connecting electrode 34, the gate connecting electrode 34 and the third gate electrodes 33 of the two adjacent sub-pixels are interconnected as an integral structure. For example, the gate connecting electrode 34, the third gate electrode 33 of the first sub-pixel P1, and the third gate electrode 33 of the third sub-pixel P3 are interconnected as an integral structure. For another example, the gate connecting electrode 34, the third gate electrode 33 of the second sub-pixel P2, and the third gate electrode 33 of the fourth sub-pixel P4 are interconnected as an integral structure.

[0197] In an exemplary embodiment, the gate connection electrode 34 is connected to the first gate electrode 31 and the third gate electrode 33 of two adjacent sub-pixels as an integrated structure. For example, the gate connection electrode 34, the first gate electrode 31 and the third gate electrode 33 of the first sub-pixel P1, and the first gate electrode 31 and the third gate electrode 33 of the third sub-pixel P3 are connected to each other as an integrated structure. For another example, the gate connection electrode 34, the first gate electrode 31 and the third gate electrode 33 of the second sub-pixel P2, and the first gate electrode 31 and the third gate electrode 33 of the fourth sub-pixel P4 are connected to each other as an integrated structure.

[0198] In an exemplary embodiment, since the gate connection electrode 34 is connected to the scan signal line 30, in one sub-pixel, one scan signal line 30 is simultaneously connected to the first gate electrode 31 and the third gate electrode 33, so that the scan signal line 30 can control the conduction or disconnection of the first transistor T1 and the third transistor T3 in one sub-pixel.

[0199] In an exemplary embodiment, in one pixel row, one scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors 33 in a plurality of sub-pixels through the gate connection electrode 34, so that the scan signal line 30 can control the conduction or disconnection of all first transistors T1 and all third transistors T3 in one pixel row.

[0200] In an exemplary embodiment, in one repeating unit, one scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors 33 in a plurality of sub-pixels through the gate connection electrode 34, so that the scan signal line 30 can simultaneously control the conduction or disconnection of all first transistors T1 and all third transistors T3 in the repeating unit.

[0201] In an exemplary embodiment, the second conductive layer of each repeating unit in the display substrate may further include two first power lines 51 , four data signal lines 52 , and one compensation signal line 53 .

[0202] In an exemplary embodiment, the shapes of the first power line 51, the data signal line 52 and the compensation signal line 53 can be straight lines or broken lines with the main portion extending along the second direction Y. The compensation signal line 53 can be located in the middle of the repeating unit in the first direction X. The first first power line 51 can be located on the side opposite to the first direction X of the repeating unit. The second first power line 51 can be located on the side of the repeating unit in the first direction X. Two of the four data signal lines 52 can be located between the first first power line 51 and the compensation signal line 53. The other two of the four data signal lines 52 can be located between the second first power line 51 and the compensation signal line 53.

[0203] In an exemplary embodiment, the first power supply line 51 and the compensation signal line 53 may define a first pixel column, and the two data signal lines 52 are disposed in the first pixel column. The second first power supply line 51 and the compensation signal line 53 may define a second pixel column, and the two data signal lines 52 are disposed in the second pixel column.

[0204] In an exemplary embodiment, the four data signal lines 52 may include a first data signal line and a second data signal line arranged in a first pixel column, and a third data signal line and a fourth data signal line arranged in a second pixel column. The first data signal line may be arranged on one side of the first first power line 51 in the first direction X, the second data signal line may be arranged on one side of the first data signal line in the first direction X, and the first electrode plate 61 and the second electrode plate 62 may be located between the second data signal line and the compensation signal line 53. The fourth data signal line may be arranged on one side of the second first power line 51 in the opposite direction of the first direction X, the third data signal line may be arranged on one side of the fourth data signal line in the opposite direction of the first direction X, and the first electrode plate 61 and the second electrode plate 62 may be located between the compensation signal line 53 and the third data signal line.

[0205] In an exemplary embodiment, two adjacent repeating units in the first direction X can share the same first power line 51. For example, the first repeating unit Q1 and the second repeating unit Q2 can share the same first power line 51. The third repeating unit Q3 and the fourth repeating unit Q4 can also share the same first power line 51. By configuring adjacent repeating units to share the same first power line, the present disclosure can effectively reduce the number of signal lines and vias, thereby reducing the area occupied by the pixel driver circuit, increasing the pixel aperture ratio, and improving display resolution.

[0206] In an exemplary embodiment, the first power line 51 may be connected to the first region of the second active layer 22 through the second via hole V2 , thereby enabling the first power line 51 to write the first power signal into the first electrode of the second transistor T2 .

[0207] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate may include the orthographic projection of the second via V2 (power via) on the substrate.

[0208] In an exemplary embodiment, within each repeating unit, the first power line 51 of the first pixel column can simultaneously provide a first power signal to the pixel driving circuits in the first subpixel P1 and the third subpixel P3. The first power line 51 of the second pixel column can simultaneously provide a first power signal to the pixel driving circuits in the second subpixel P2 and the fourth subpixel P4. Thus, the first power lines 51 within a repeating unit form a one-to-two structure. By designing the first power lines as a one-to-two structure, the display substrate of the present disclosure reduces the number of signal lines and the occupied space. It has a simple structure, a rational layout, and fully utilizes the layout space, improving space utilization, increasing the pixel aperture ratio, and enhancing display resolution.

[0209] In an exemplary embodiment, the two first power lines 51 in a repeating unit are symmetrically arranged relative to the compensation signal line 53, and the second transistor T2 of the first pixel column and the second transistor T2 of the second pixel column are symmetrically arranged relative to the compensation signal line 53. This symmetrical structure of the present disclosure can ensure that the voltage drop written by the first power line to the second transistor T2 is substantially the same, thereby ensuring display uniformity.

[0210] In an exemplary embodiment, the data signal line 52 may be connected to the first region of the first active layer through the first via hole V1 , thereby enabling the data signal line 52 to write the data signal into the first electrode of the first transistor T1 .

[0211] In an exemplary embodiment, the orthographic projection of the data signal line 52 on the substrate may include the orthographic projection of the first via hole V1 (data via hole) on the substrate.

[0212] In an exemplary embodiment, the four data signal lines 52 may include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line. In each repeating unit, the first data signal line may be connected to the first region of the first active layer of the first subpixel P1 through the first via hole V1, the second data signal line may be connected to the first region of the first active layer in the third subpixel P3 through the first via hole V1, the third data signal line may be connected to the first region of the first active layer in the fourth subpixel P4 through the first via hole V1, and the fourth data signal line may be connected to the first region of the first active layer in the second subpixel P2 through the first via hole V1.

[0213] In an exemplary embodiment, the compensation signal line 53 may pass through the fourth via hole V4 and the first region of the third active layer 23 , thereby enabling the compensation signal line 53 to write the compensation signal into the first electrode of the third transistor T3 .

[0214] In an exemplary embodiment, the orthographic projection of the compensation signal line 53 on the substrate may include the orthographic projection of the fourth via hole V4 (compensation via hole) on the substrate.

[0215] In this exemplary embodiment, because the first regions of the third active layers of the four sub-pixels in a repeating unit are interconnected, the four sub-pixels share the same fourth via V4, and thus the four sub-pixels share the same compensation signal line 53. That is, the four pixel drive circuits in a repeating unit share one compensation signal line 53, and the compensation signal lines 53 in a repeating unit form a one-to-four structure. By designing the compensation signal lines as a one-to-four structure, the display substrate of the present disclosure reduces the number of signal lines and the space occupied. It has a simple structure, a rational layout, and fully utilizes the layout space, improving space utilization, increasing the pixel aperture ratio, and enhancing display resolution.

[0216] In an exemplary embodiment, the compensation signal line 53 is arranged between the first pixel column and the second pixel column, and the third transistor T3 of the first pixel column and the third transistor T3 of the second pixel column are symmetrically arranged with respect to the compensation signal line 53. This symmetrical structure of the present disclosure can ensure that the RC delay of the compensation signal written into the third transistor T3 is substantially the same, thereby ensuring display uniformity.

[0217] In an exemplary embodiment, the first power line 51 , the data signal line 52 and the compensation signal line 53 may be zigzag lines of unequal widths. Using zigzag lines of varying widths not only facilitates the layout of the pixel structure but also reduces parasitic capacitance.

[0218] In an exemplary embodiment, in at least one repeating unit, the positions of the two first power lines 51 can be substantially mirror-symmetrical with respect to a vertical reference line, and the positions of the two data signal lines 52 located on the opposite side of the first direction X of the compensation signal line 53 and the positions of the two data signal lines 52 located on the side of the first direction X of the compensation signal line 53 can be substantially mirror-symmetrical with respect to the vertical reference line.

[0219] In an exemplary embodiment, in at least one repeating unit, the position of each pattern in the third conductive layer in the first subpixel P1 and the position of each pattern in the third conductive layer in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the third conductive layer in the second subpixel P2 and the position of each pattern in the third conductive layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a horizontal reference line, the position of each pattern in the third conductive layer in the first subpixel P1 and the position of each pattern in the third conductive layer in the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the position of each pattern in the third conductive layer in the third subpixel P3 and the position of each pattern in the third conductive layer in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line.

[0220] As shown in FIG8C , through this patterning process, a third conductive layer is formed on the second insulating layer 72. The third conductive layer includes at least the sixth connecting electrode 16, the second gate electrode 32, and the gate connecting electrode 34. The sixth connecting electrode 16 is connected to both the third active layer 23 and the fourth connecting electrode 14 through the fifth via V5. The second gate electrode 32 is connected to the second electrode plate 62 through the sixth via V6. The gate connecting electrode 34 is connected to the scan signal line 30 through the seventh via V7.

[0221] In an exemplary embodiment, the third conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0222] (5) Forming a third insulating layer and a planar layer pattern. In an exemplary embodiment, forming the third insulating layer and the planar layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, then coating a planar film, patterning the planar film and the third insulating film through a patterning process to form a third insulating layer covering the third conductive layer and a planar layer pattern disposed on the third insulating layer, wherein a plurality of vias are disposed on the planar layer, as shown in FIG. 9 .

[0223] In an exemplary embodiment, the via holes of each sub-pixel in each repeating unit include at least an eleventh via hole V11 .

[0224] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 15 on the substrate, the third insulating layer and the flat layer in the eleventh via hole V11 are etched away to expose the surface of the fifth connecting electrode 15, and the eleventh via hole V11 is configured to connect a subsequently formed anode connecting electrode to the fifth connecting electrode 15 through the via hole.

[0225] In an exemplary embodiment, this process uses a single patterning process to simultaneously form vias on the third insulating layer and the planar layer, that is, the third insulating layer and the planar layer share a halftone or gray tone mask (MASK) process, effectively reducing the number of patterning processes.

[0226] (6) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film through a patterning process, and forming a fourth conductive layer pattern on the color filter layer, as shown in Figures 10A and 10B, where Figure 10B is a schematic diagram of the fourth conductive layer in Figure 10A. In an exemplary embodiment, the fourth conductive layer may be referred to as a second transparent (2ITO) layer.

[0227] In an exemplary embodiment, the fourth conductive layer of each sub-pixel in each repeating unit may include at least the first electrode 63 and the anode connection electrode 64 .

[0228] In an exemplary embodiment, the first electrode 63 may be rectangular in shape, and the corners of the rectangle may be provided with chamfers, grooves or protrusions, and the orthographic projection of the first electrode 63 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 62 on the substrate.

[0229] In an exemplary embodiment, the shape of the anode connecting electrode 64 can be a block shape (such as a rectangle), and can be located on the side of the first electrode 63 away from the scanning signal line 30. The first end of the anode connecting electrode 64 is connected to the first electrode 63, and the second end of the anode connecting electrode 64 extends in a direction away from the scanning signal line 30 and is connected to the fifth connecting electrode 15 through the eleventh via hole V11.

[0230] In an exemplary embodiment, in at least one sub-pixel, the anode connection electrode 64 and the first electrode 63 may be an integral structure connected to each other.

[0231] In an exemplary embodiment, in at least one repeating unit, the four first electrodes 63 may be arranged in a square, with the upper left first electrode connected to the pixel driving circuit in the first subpixel P1, the upper right first electrode connected to the pixel driving circuit in the second subpixel P2, the lower left first electrode connected to the pixel driving circuit in the third subpixel P3, and the lower right first electrode connected to the pixel driving circuit in the fourth subpixel P4. In some possible implementations, the first electrodes may serve as anodes of the light-emitting device. The arrangement of the first electrodes may be adjusted according to actual needs and is not specifically limited in this disclosure.

[0232] In an exemplary embodiment, the first conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0233] In an exemplary embodiment, the first electrode 63 can also serve as an auxiliary capacitor of the storage capacitor. Since the first electrode 63 is connected to the anode connection electrode 64, and the anode connection electrode 64 is connected to the first plate 61 through the fifth connection electrode 15, the third connection electrode 13 and the first connection electrode 11, the first electrode 63 has the potential of the second node in the pixel driving circuit, so that the first electrode 63 having the second node potential and the second plate 62 having the first node potential form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel. The present disclosure uses the first electrode to form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel. On the one hand, it can effectively increase the capacitance value of the storage capacitor, and on the other hand, it can reduce the plate area while ensuring the capacitance value of the storage capacitor, effectively reducing the occupied area.

[0234] (7) Forming a pixel definition layer. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate having the aforementioned pattern formed thereon, and patterning the pixel definition film through a patterning process to form a pixel definition layer covering the fourth conductive layer, as shown in FIG. 11 .

[0235] In an exemplary embodiment, a pixel opening PK is opened on the pixel definition layer of each sub-pixel in each repeating unit, the pixel definition film within the pixel opening PK is removed to expose a portion of the surface of the first electrode 63, and the orthographic projection of the pixel opening PK on the substrate is within the range of the orthographic projection of the first electrode 63 on the substrate.

[0236] In an exemplary embodiment, the shape of the pixel opening PK in a plane parallel to the substrate may be similar to that of the first electrode 63 , and the cross-sectional shape of the pixel opening PK in a plane perpendicular to the substrate may be a rectangle or a trapezoid.

[0237] In exemplary embodiments, the shape of the pixel opening may include any one or more of a triangle, a rectangle, a trapezoid, a parallelogram, a pentagon, a hexagon, a circle, and an ellipse.

[0238] In an exemplary embodiment, the shapes of the pixel openings of the four sub-pixels in the repeating unit may be the same or different, and the areas of the pixel openings of the four sub-pixels may be the same or different.

[0239] In an exemplary embodiment, the shapes and areas of the pixel openings of the four sub-pixels in the repeating unit can be different to adapt to the transmittance of different sub-pixel filters, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, thereby maximizing the lifespan of the four sub-pixel light-emitting devices and ensuring the product life.

[0240] In an exemplary embodiment, at least one partitioning groove M may be provided on the pixel definition layer of each repeating unit. The partitioning groove M may be in the shape of a strip with a main portion extending along the second direction Y, and may be provided between adjacent pixel openings PK in the first direction X. For example, the partitioning groove M may be provided between the pixel opening PK of the first subpixel P1 and the pixel opening PK of the second subpixel P2. In another example, the partitioning groove M may be provided between the pixel opening PK of the third subpixel P3 and the pixel opening PK of the fourth subpixel P4. In an exemplary embodiment, the partitioning groove M is configured to interrupt the subsequently formed organic light-emitting layer, block the lateral propagation path of hole-type carriers, eliminate lateral leakage, and reduce lateral crosstalk between subpixels.

[0241] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acryl, polyethylene terephthalate, or the like.

[0242] (8) Forming an organic light-emitting layer and cathode pattern. In an exemplary embodiment, forming the organic light-emitting layer and cathode pattern may include: first forming an organic light-emitting layer pattern, wherein the organic light-emitting layer is connected to the first electrode 63 through the pixel opening PK. Then, forming a second electrode, wherein the second electrode is connected to the organic light-emitting layer. In an exemplary embodiment, the second electrode may serve as a cathode of the light-emitting device.

[0243] In an exemplary embodiment, the organic light-emitting layer may include an emission layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed using a fine metal mask (FMM) or open mask evaporation, or using an inkjet process.

[0244] (8) Forming a packaging structure layer pattern. In an exemplary embodiment, forming a packaging structure layer pattern may include: first using an open mask to deposit a first inorganic thin film to form a first packaging layer. Subsequently, using an inkjet printing process to inkjet print an organic material on the first packaging layer, and after curing into a film, forming a second packaging layer. Subsequently, using an open mask to deposit a second inorganic thin film to form a third packaging layer, the first packaging layer, the second packaging layer and the third packaging layer constitute a packaging structure layer. The first packaging layer and the third packaging layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The second packaging layer can be made of a resin material to form a laminated structure of inorganic material / organic material / inorganic material. The organic material layer is arranged between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0245] At this point, the preparation of the display substrate of the exemplary embodiment of the present disclosure is completed. The display substrate may include a driving circuit layer arranged on a substrate, a light-emitting structure layer arranged on the side of the driving circuit layer away from the substrate, and an encapsulation structure layer arranged on the side of the light-emitting structure layer away from the substrate. In a direction perpendicular to the display substrate, the driving circuit layer may include a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer, a third insulating layer and a flat layer arranged in sequence on the substrate, the light-emitting structure layer may include a first electrode, a pixel definition layer, an organic light-emitting layer and a second electrode, and the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.

[0246] In an exemplary embodiment, for a display substrate including a color filter structure layer, after forming the third conductive layer, a third insulating layer can be formed first, and then a red color filter layer, a green color filter layer and a blue color filter layer are formed in sequence, and then a flat layer is formed, which will not be repeated here.

[0247] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0248] In an exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The planarization layer may be made of an organic material such as a resin.

[0249] The structure and preparation process shown in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit them.

[0250] An embodiment of the present disclosure provides a display substrate with a bottom emission structure. By setting the scanning signal line in the light-shielding layer, and synchronously forming the scanning signal line, the first electrode plate and multiple connecting electrodes through the same patterning process, the structure of the pixel driving circuit is optimized, the occupied area of ​​the pixel driving circuit can be effectively reduced, the pixel aperture ratio is increased, and the display resolution is improved.

[0251] The display substrate of the disclosed embodiment is formed simultaneously through the first conductive layer and the second conductive layer in a single patterning process, and the scanning signal line and the auxiliary signal line form a double-layer signal line structure, which can effectively reduce the resistance of the scanning signal line, reduce the voltage drop of the scanning signal, and improve the display performance.

[0252] The disclosed embodiment forms a semiconductor layer on a substrate through a patterning process using a half-tone mask, and simultaneously completes the conductorization process while forming the semiconductor layer. This not only simplifies the process and improves the conductorization effect, but also improves the via-hole overlap method. Compared with the existing structure that performs the conductorization process after forming the via, the disclosed embodiment not only effectively reduces the via size, effectively reduces the occupied area of ​​the via connection structure, effectively reduces the occupied area of ​​the pixel driving circuit, increases the pixel aperture ratio, and improves the display resolution, but also reduces the number of process steps, effectively improves production efficiency, effectively reduces production costs, and maximizes product yield.

[0253] The disclosed embodiment displays the substrate through adjacent repeating units, wherein the second active layers of adjacent sub-pixels are interconnected as an integrated structure, the third active layers of adjacent sub-pixels are interconnected as an integrated structure, and the first gate electrodes, third gate electrodes, and gate connection electrodes of two adjacent sub-pixels are interconnected as an integrated structure. This not only effectively reduces the number of vias, reduces the area occupied by the pixel driving circuit, increases the pixel aperture ratio, and improves the display resolution, but also reduces the number of vias, which simplifies the preparation process, reduces production costs, and improves product yield.

[0254] The disclosed embodiment of the display substrate arranges the scanning signal line in the light-shielding layer, located on the side of the semiconductor layer close to the substrate, and arranges the first power line, data signal line, compensation signal line, and gate electrodes of multiple transistors in the gate metal layer, located on the side of the semiconductor layer away from the substrate. This not only reduces one conductive layer, but also reduces the patterning process of the transfer via and the patterning process of the transfer conductive layer. As a result, the preparation process of the drive structure layer only requires five patterning (MASK) processes. Compared with the existing preparation process that requires nine patterning processes, the disclosed display substrate reduces the number of patterning processes, effectively improves production efficiency, effectively reduces production costs, and maximizes product yield.

[0255] The display substrate of the disclosed embodiment utilizes a 3T1C pixel drive circuit with one scan signal line, where the scan signal line is connected to the first and third transistors in the pixel drive circuit. By reducing the number of scan signal lines, the structure of the pixel drive circuit can be simplified, reducing the area occupied by the pixel drive circuit, thereby facilitating high-resolution display. Furthermore, since a repeating unit only requires one scan signal line to drive, the number of corresponding gate drive circuits (GOA) and clock signal lines (CLK) can be reduced exponentially, effectively reducing the area occupied by the gate drive circuits and clock signal lines, thereby facilitating narrow bezels and enhancing product advantages.

[0256] The disclosed embodiment shows that the substrate is formed into a transparent storage capacitor by a transparent conductive layer and a transparent semiconductor layer, so that light can be emitted through the transparent storage capacitor. Therefore, the storage capacitor can be set in the pixel opening, which can not only effectively increase the capacitance of the storage capacitor, but also effectively increase the pixel aperture ratio.

[0257] The transistors of the display substrate of the disclosed embodiment adopt a top-gate structure, which has a higher on-current (Ion), a higher aperture ratio and better electrical stability, which is conducive to achieving a good driving effect and improving the reliability of the display substrate.

[0258] The display substrate of the embodiment of the present disclosure arranges sub-pixels in a square manner and adopts a first power line structure with a non-mesh structure, which can effectively increase the pixel aperture ratio, improve the display effect, and is more suitable for display type display.

[0259] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0260] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0261] The exemplary embodiments of the present disclosure also provide a method for preparing a display substrate to prepare the aforementioned display substrate. In an exemplary embodiment, the display substrate includes a plurality of repeating units, at least one repeating unit includes a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel includes a pixel driving circuit, a scan signal line, and an auxiliary signal line, the scan signal line being configured to provide a scan signal to the pixel driving circuit; the pixel driving circuit includes a storage capacitor and at least one transistor, the storage capacitor includes at least a first plate, and the at least one transistor is connected to the first plate via a connecting electrode; the preparation method includes:

[0262] A first conductive layer and a second conductive layer are formed on a substrate and are arranged on a side of the first conductive layer away from the substrate. The auxiliary signal line and the first electrode are arranged in the first conductive layer, and the scanning signal line and the connecting electrode are arranged in the second conductive layer. The orthographic projection of the scanning signal line on the substrate plane is within the range of the orthographic projection of the auxiliary signal line on the substrate plane, and the scanning signal line is overlapped with the auxiliary signal line.

[0263] In an exemplary embodiment, forming a first conductive layer on a substrate and a second conductive layer disposed on a side of the first conductive layer away from the substrate includes:

[0264] sequentially depositing a first conductive film and a second conductive film;

[0265] A patterning process using a half-tone mask is adopted, the scanning signal line and the auxiliary signal line are formed through a first etching process, and the first electrode plate and the connecting electrode are formed through a second etching process.

[0266] In an exemplary embodiment, the storage capacitor further includes a second electrode plate, wherein an orthographic projection of the second electrode plate on the substrate plane at least partially overlaps with an orthographic projection of the first electrode plate on the substrate plane; and the preparation method further includes:

[0267] depositing a semiconductor thin film on a side of the second conductive layer away from the substrate;

[0268] The second electrode plate is formed by adopting a patterning process of a half-tone mask and sequentially performing an etching process and a conductor treatment process.

[0269] The present disclosure also provides a display device comprising the display substrate of the aforementioned embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0270] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, a scanning signal line and an auxiliary signal line, the scanning signal line being configured to provide a scanning signal to the pixel driving circuit; the pixel driving circuit comprising a storage capacitor and at least one transistor, the storage capacitor comprising at least a first electrode plate, the at least one transistor being connected to the first electrode plate via a connecting electrode; in a direction perpendicular to the display substrate, the display substrate comprising a first conductive layer arranged on a substrate and a second conductive layer arranged on a side of the first conductive layer away from the substrate, the auxiliary signal line and the first electrode plate being arranged in the first conductive layer, the scanning signal line and the connecting electrode being arranged in the second conductive layer, the orthographic projection of the scanning signal line on the substrate plane being within the range of the orthographic projection of the auxiliary signal line on the substrate plane, and the scanning signal line being overlapped with the auxiliary signal line.

2. The display substrate according to claim 1, wherein: The storage capacitor also includes a second electrode plate, and the orthographic projection of the second electrode plate on the substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the substrate plane; the at least one transistor includes a second transistor, and the second transistor includes at least a second gate electrode, and the second gate electrode is connected to the second electrode plate through a plate via, and the orthographic projection of the second gate electrode on the substrate plane includes the orthographic projection of the plate via on the substrate plane.

3. The display substrate according to claim 2, wherein: The second transistor also includes a second active layer, a first area of ​​the second active layer is connected to a first power line through a power via, a second area of ​​the second active layer is connected to the first electrode through a connecting electrode, the first power line is configured to provide a power signal to the pixel driving circuit, and an orthographic projection of the first power line on the substrate plane includes an orthographic projection of the power via on the substrate plane.

4. The display substrate according to claim 3, wherein: The second active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are interconnected as an integrated structure, and / or the second active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are interconnected as an integrated structure.

5. The display substrate according to claim 3, wherein: Two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the power via hole, and / or two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power via hole.

6. The display substrate according to claim 3, wherein: The connecting electrode includes a first connecting electrode and a third connecting electrode, the first connecting electrode is connected to the first electrode plate, and the third connecting electrode is overlapped with the first connecting electrode; the pixel driving circuit also includes a fifth connecting electrode, and the fifth connecting electrode is simultaneously connected to the second area of ​​the second active layer and the third connecting electrode through a first overlapping via hole; the first size of the first overlapping via hole is larger than the second size of the first overlapping via hole, the first size is the size of the first overlapping via hole in the pixel row direction, and the second size is the size of the first overlapping via hole in the pixel column direction.

7. The display substrate according to claim 6, wherein: The power via and the first overlapping via are not on a straight line extending along the direction of the pixel row.

8. The display substrate according to claim 6, wherein: In the pixel column direction, the power via hole shared by two adjacent sub-pixels in two adjacent repeating units is located between two adjacent first overlapping via holes in two adjacent repeating units.

9. The display substrate according to claim 1, wherein: The at least one transistor includes a third transistor, the third transistor includes at least a third active layer, a first area of ​​the third active layer is connected to a compensation signal line through a compensation via, a second area of ​​the third active layer is connected to the first electrode plate through a connecting electrode, the compensation signal line is configured to provide a compensation signal to the pixel driving circuit, and an orthographic projection of the compensation signal line on the substrate plane includes an orthographic projection of the compensation via on the substrate plane.

10. The display substrate according to claim 9, wherein: In at least one repeating unit, the third active layers of two adjacent sub-pixels in the pixel row direction are interconnected as an integrated structure, and / or the third active layers of two adjacent sub-pixels in the pixel column direction are interconnected as an integrated structure.

11. The display substrate according to claim 9, wherein: In at least one repeating unit, two adjacent sub-pixels in the pixel row direction share the compensation via hole, and / or two adjacent sub-pixels in the pixel column direction share the compensation via hole.

12. The display substrate according to claim 9, wherein: The connecting electrode includes a second connecting electrode and a fourth connecting electrode, the second connecting electrode is connected to the first electrode plate, and the fourth connecting electrode is overlapped with the second connecting electrode; the pixel driving circuit also includes a sixth connecting electrode, and the sixth connecting electrode is simultaneously connected to the second area of ​​the third active layer and the fourth connecting electrode through a second overlapping via hole; the third size of the second overlapping via hole is smaller than the fourth size of the second overlapping via hole, the third size is the size of the second overlapping via hole in the pixel row direction, and the fourth size is the size of the second overlapping via hole in the pixel column direction.

13. The display substrate according to claim 9, wherein: The pixel driving circuit also includes a first transistor, the first transistor includes at least a first active layer, a first area of ​​the first active layer is connected to a data signal line through a data via, the data signal line is configured to provide a data signal to the pixel driving circuit, and the orthographic projection of the data signal line on the substrate plane includes the orthographic projection of the data via on the substrate plane.

14. The display substrate according to any one of claims 1 to 13, wherein: The pixel driving circuit includes at least a first transistor and a third transistor, the first transistor includes at least a first gate electrode, the third transistor includes at least a third gate electrode, and the first gate electrode and the third gate electrode are respectively connected to the scanning signal line through gate connecting electrodes.

15. The display substrate according to claim 14, wherein: In at least one repeating unit, the gate connection electrode, the first gate electrode and the third gate electrode of two sub-pixels adjacent to each other in the pixel column direction are arranged in the same layer and are an integrated structure connected to each other.

16. The display substrate according to claim 14, wherein: The orthographic projection of the gate connection electrode on the substrate plane at least partially overlaps with the orthographic projection of the scan signal line on the substrate plane, and the gate connection electrode is connected to the scan signal line through a gate connection via.

17. The display substrate according to claim 16, wherein: In at least one repeating unit, two sub-pixels adjacent to each other in the pixel column direction share the gate connection electrode.

18. The display substrate according to claim 16, wherein: In at least one repeating unit, two adjacent sub-pixels in the pixel column direction share the gate connection via hole.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

20. A method for preparing a display substrate, the display substrate comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, a scanning signal line and an auxiliary signal line, the scanning signal line being configured to provide a scanning signal to the pixel driving circuit; the pixel driving circuit comprising a storage capacitor and at least one transistor, the storage capacitor comprising at least a first electrode plate, the at least one transistor being connected to the first electrode plate via a connecting electrode; the preparation method comprising: A first conductive layer and a second conductive layer arranged on a side of the first conductive layer away from the substrate are formed on a substrate, the auxiliary signal line and the first electrode are arranged in the first conductive layer, the scanning signal line and the connecting electrode are arranged in the second conductive layer, the orthographic projection of the scanning signal line on the substrate plane is located within the range of the orthographic projection of the auxiliary signal line on the substrate plane, and the scanning signal line is overlapped with the auxiliary signal line.

21. The display substrate according to claim 20, wherein: A first conductive layer and a second conductive layer disposed on a side of the first conductive layer away from the substrate are formed on a substrate, comprising: Depositing a first conductive film and a second conductive film in sequence; The scanning signal line and the auxiliary signal line are formed by a first etching process using a half-tone mask patterning process, and the first electrode plate and the connecting electrode are formed by a second etching process.

22. The display substrate according to claim 20, wherein: The storage capacitor further includes a second electrode plate, the orthographic projection of the second electrode plate on the substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the substrate plane; The preparation method further comprises: Depositing a semiconductor thin film on a side of the second conductive layer away from the substrate; The second electrode plate is formed by adopting a patterning process of a half-tone mask plate and sequentially performing an etching process and a conductor treatment process.

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