A method, device and storage medium for processing display screen images containing circuit areas

Abstract

The present application discloses a method, device and storage medium for processing display screen images containing circuit areas, which are used to improve the screen defect detection accuracy of display screen images containing circuit areas. The display screen to be tested is photographed to generate a display screen image; a circuit area appearance image, a display area appearance image and a boundary area appearance image are generated; a limited sample screen circuit area appearance image is generated; the circuit area appearance image and the limited sample screen circuit area appearance image are downsampled to generate the first and second compressed images; a grayscale morphological structure kernel operator is generated; bottom hat operations, morphological dilation and arithmetic operations, threshold analysis processing and upsampling expansion processing are performed on the first and second compressed images to generate a target circuit area appearance image; the display area appearance image is processed by an adaptive emphasis filtering algorithm to generate a target display area appearance image; defect detection is performed on the target circuit area appearance image, the target display area appearance image and the boundary area appearance image, and the defect analysis result is output.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of display screen detection, and in particular, to a method, device, and storage medium for processing a display screen image containing a circuit area. Background Art

[0002] With the rapid development of industrial and Internet technologies, the industry's requirements for industrial product quality are becoming more and more refined and standardized. As far as the display panel industry is concerned, the quality of products directly affects its product competitiveness. Among them, the accuracy of product shape and size specifications is the most basic process indicator of product quality. As one of the display components of the device, the display screen is used in various high-end devices, such as mobile phones, TVs, tablets, etc. As people's requirements for screen display continue to increase, the display screen has gradually become a technologically sophisticated product.

[0003] Display screen defect detection is a necessary process for adjustment. Display screen defects can be divided into display defects and screen body defects. Display defects refer to the discordant areas that appear when the display screen displays the picture. In the prior art, display defects usually require inputting a specific picture on the display screen to be tested, and then collecting the picture through the camera, and then performing image detection to analyze it. Screen body defects refer to the areas on the surface or inside of the display screen itself that have damage (such as chipped corners, foreign matter, etc.). This type of defect does not require inputting an image, and can be analyzed by collecting the picture with the camera and then performing image detection.

[0004] However, as the application fields of display screens become more and more extensive, more and more functions are added, and sophisticated circuit structures and other functional structures are added inside or on the surface of the display screen. This type of structure will not have much impact on the detection of display defects. However, since screen defects do not require image display, this type of display screen with structures is prone to false detection and missed detection of screen defects in the corresponding structural area. At present, the circuit structure and boundary structure are the most influential. The circuit structure is usually a very thin circuit board. Due to the complex internal structure of the circuit structure, it mainly presents blocks with different levels, and the overall area is large, concentrated, and arranged inside the display screen. The second is the boundary structure, which is also located inside the display screen and mainly presents thin strips with a single level.

[0005] This application is mainly aimed at the appearance display screen containing the circuit area. When detecting screen defects in the traditional way, it is necessary to illuminate with an external light source to enhance the display of defects. The enhancement effect is obvious for the display area without circuits. However, due to the appearance of the circuit structure, when the external light source environment changes slightly, it will cause a large difference between each captured display screen image in the circuit area, resulting in inaccurate detection of screen defects in this area. Summary of the invention

[0006] The present application discloses a method, a device and a storage medium for processing a display screen image containing a circuit area, which are used to improve the screen defect detection accuracy of the display screen image containing the circuit area.

[0007] The first aspect of the present application discloses a method for processing a display screen image containing a circuit area, comprising:

[0008] Turn on the light source, use the industrial line scan camera to shoot the display screen to generate a display screen image, and the display screen to be tested contains a circuit structure;

[0009] Dividing the display screen image into regional texture structures to generate a circuit area appearance image, a display area appearance image and a boundary area appearance image;

[0010] A standard sample screen is selected and photographed to generate an appearance image of the circuit area of ​​the sample screen. The standard sample screen and the display screen to be tested are of the same type and are defect-free.

[0011] Downsampling the circuit area appearance image and the limited sample screen circuit area appearance image to generate a first compressed image and a second compressed image;

[0012] Generate a grayscale morphological structure kernel operator according to the screen detection defect corresponding to the circuit area appearance image;

[0013] Performing a bottom-hat algorithm on the first compressed image and the second compressed image respectively according to the grayscale morphological structure kernel operator;

[0014] Performing morphological expansion and arithmetic operation on the first compressed image and the second compressed image to obtain a result image;

[0015] Perform threshold analysis and upsampling on the result image to generate an appearance image of the target circuit area;

[0016] Processing the display area appearance image with an adaptive emphasis filtering algorithm to generate a target display area appearance image;

[0017] Defect detection is performed on the target circuit area appearance image, the target display area appearance image and the boundary area appearance image, and defect analysis results are output.

[0018] Optionally, after turning on the light source and photographing the display screen to be tested with an industrial line scan camera to generate a display screen image, before dividing the display screen image into regional texture structures to generate a circuit area appearance image, a display area appearance image, and a boundary area appearance image, the processing method further includes:

[0019] Determine transition points of display screen images;

[0020] The least squares algorithm is used to fit the transition points into line segments;

[0021] Find the intersection points of the fitted line segments and generate the original transformation point pairs;

[0022] The original transformed point pairs and the display screen length and width parameters are combined through the point pair transformation matrix to perform pixel correction processing on the display screen image.

[0023] Optionally, after selecting a standard limited sample screen and photographing the standard limited sample screen to generate a limited sample screen circuit area appearance image, and before downsampling the circuit area appearance image and the limited sample screen circuit area appearance image to obtain the first compressed image and the second compressed image, the processing method further includes:

[0024] Determine the interference area and auxiliary repair area of ​​the appearance image of the limited sample screen circuit area;

[0025] Determine the positions of the pixels to be repaired in the interference area and the positions of the auxiliary pixels in the auxiliary repair area;

[0026] Grayscale compensation and repair processing is performed on the grayscale of the pixel to be repaired in the interference area according to the position of the pixel to be repaired, the position of the auxiliary pixel and the grayscale of the auxiliary pixel in the auxiliary repair area.

[0027] Optionally, the display screen image is divided into regional texture structures to generate a circuit area appearance image, a display area appearance image, and a boundary area appearance image, including:

[0028] Draw contour points at the intersections between the areas to be measured on the display screen image;

[0029] Generate a polygonal region set according to the coordinate positions of the contour points and the preset multi-region shapes;

[0030] Determine a circuit region and a display region in the polygonal region set, and generate a binary circuit image and a binary display image for the circuit region and the display region respectively;

[0031] Performing logical AND operations on the display screen image, the binary circuit image and the binary display image respectively to generate a circuit area appearance image and a display area appearance image;

[0032] Performing a logical OR operation on the binary circuit image and the binary display image, and then performing a logical inversion operation to obtain a binary boundary image;

[0033] Perform a logical AND operation on the display screen image and the binary boundary image to generate a boundary area appearance image.

[0034] Optionally, contour points are drawn at the boundaries between the areas to be measured on the display screen image, including:

[0035] Acquire a module enhanced image of a sample display screen, the sample display screen and the display screen to be tested are of the same type, the module enhanced image is an image of the sample display screen with the boundary structure region and the circuit structure region enhanced, and the display enhancement degrees of the boundary structure region and the circuit structure region are different;

[0036] Acquire a first grayscale mean value and a first standard deviation of the display screen image and a second grayscale mean value and a second standard deviation of the module enhanced image;

[0037] Calculating brightness adjustment coefficients of the display screen image and the module enhanced image according to the first grayscale mean and the second grayscale mean;

[0038] Calculating the contrast enhancement coefficient of the display screen image and the module enhanced image according to the first standard deviation and the second standard deviation;

[0039] Performing an arithmetic difference operation on the display screen image and the module enhanced image to generate an intermediate image;

[0040] generating contrast weighted data of the boundary structure area and the circuit structure area according to the brightness adjustment coefficient, the contrast enhancement coefficient and the intermediate image;

[0041] The grayscale values ​​of the pixels in the intermediate image are enhanced according to the contrast weighted data to generate a structural region enhanced image;

[0042] Draw equally spaced radial and transverse line segments in the structure region enhanced image;

[0043] Perform grayscale analysis on the pixels on the radial line segments and the transverse line segments to determine the coordinate data of the transition points;

[0044] The coordinate data of the transition points are used to draw the contour points between the areas to be measured on the display screen image.

[0045] Optionally, defect detection is performed on the target circuit area appearance image, the target display area appearance image, and the boundary area appearance image, and defect analysis results are output, including:

[0046] Performing morphological processing, feature screening analysis, and coordinate transformation on the appearance image of the target display area to generate a first defect analysis result of the appearance image of the target display area;

[0047] Performing feature quantity screening and coordinate transformation on the appearance image of the target circuit area to generate a second defect analysis result of the appearance image of the target circuit area;

[0048] Processing the appearance image of the boundary area by a convolution filtering algorithm, performing defect feature screening and coordinate transformation on the appearance image of the boundary area, and generating a third defect analysis result of the appearance image of the boundary area;

[0049] The first defect analysis result, the second defect analysis result, and the third defect analysis result are determined as defect analysis results.

[0050] The second aspect of the present application discloses a device for processing a display screen image including a circuit area, comprising:

[0051] The first generating unit is used to turn on the light source, shoot the display screen to be tested by an industrial line scan camera, and generate a display screen image, wherein the display screen to be tested contains a circuit structure;

[0052] A second generating unit is used to divide the display screen image into regional texture structures to generate a circuit area appearance image, a display area appearance image and a boundary area appearance image;

[0053] The third generating unit is used to select a standard sample screen and shoot the standard sample screen to generate an appearance image of the circuit area of ​​the sample screen. The standard sample screen and the display screen to be tested are of the same type, and the standard sample screen is a defect-free display screen.

[0054] A fourth generating unit is used to downsample the circuit area appearance image and the limited sample screen circuit area appearance image to generate a first compressed image and a second compressed image;

[0055] A fifth generating unit, configured to generate a grayscale morphological structure kernel operator according to a screen body detection defect corresponding to the circuit area appearance image;

[0056] A computing unit, configured to perform a bottom-hat algorithm on the first compressed image and the second compressed image respectively according to a grayscale morphological structure kernel operator;

[0057] A sixth generating unit, configured to perform morphological expansion and arithmetic operation on the first compressed image and the second compressed image to obtain a result image;

[0058] A seventh generating unit, used for performing threshold analysis and up-sampling and enlargement processing on the result image to generate an appearance image of the target circuit area;

[0059] An emphasis filtering unit, used for performing adaptive emphasis filtering algorithm processing on the appearance image of the display area to generate an appearance image of the target display area;

[0060] The output unit is used to perform defect detection on the target circuit area appearance image, the target display area appearance image and the boundary area appearance image, and output defect analysis results.

[0061] Optionally, after the first generating unit and before the second generating unit, the processing device further includes:

[0062] A first determining unit, used to determine a transition point of the display screen image;

[0063] A fitting unit, used for fitting the transition points into line segments using a least squares algorithm;

[0064] An eighth generating unit, used for obtaining intersection points of the fitted line segments and generating original transformation point pairs;

[0065] The correction unit is used to perform pixel correction processing on the display screen image by combining the original transformed point pairs and the length and width parameters of the display screen through the point pair transformation matrix.

[0066] Optionally, after the third generating unit and before the fourth generating unit, the processing device further includes:

[0067] A second determination unit is used to determine the interference area and the auxiliary repair area of ​​the appearance image of the circuit area of ​​the limited sample screen;

[0068] A third determining unit is used to determine the positions of the pixels to be repaired in the interference area and the positions of the auxiliary pixels in the auxiliary repair area;

[0069] The repair unit is used to perform grayscale compensation repair processing on the grayscale of the pixel to be repaired in the interference area according to the position of the pixel to be repaired, the position of the auxiliary pixel and the grayscale of the auxiliary pixel in the auxiliary repair area.

[0070] Optionally, the second generation unit includes:

[0071] A drawing module, used for drawing contour points at the intersections between the areas to be tested on the display screen image;

[0072] A first generating module, used for generating a polygonal region set according to the coordinate positions of the contour points and the preset multi-region shape;

[0073] A second generating module is used to determine the circuit area and the display area in the polygonal area set, and to generate a binary circuit image and a binary display image for the circuit area and the display area respectively;

[0074] A third generating module is used to perform a logical AND operation on the display screen image, the binary circuit image and the binary display image, respectively, to generate a circuit area appearance image and a display area appearance image;

[0075] A logic operation module, used for performing a logic OR operation on the binary circuit image and the binary display image, and then performing a logic inversion operation to obtain a binary boundary image;

[0076] The fourth generating module is used to perform a logical AND operation on the display screen image and the binary boundary image to generate a boundary area appearance image.

[0077] Optional, drawing module, including:

[0078] Acquire a module enhanced image of a sample display screen, the sample display screen and the display screen to be tested are of the same type, the module enhanced image is an image of the sample display screen with the boundary structure region and the circuit structure region enhanced, and the display enhancement degrees of the boundary structure region and the circuit structure region are different;

[0079] Acquire a first grayscale mean value and a first standard deviation of the display screen image and a second grayscale mean value and a second standard deviation of the module enhanced image;

[0080] Calculating brightness adjustment coefficients of the display screen image and the module enhanced image according to the first grayscale mean and the second grayscale mean;

[0081] Calculating the contrast enhancement coefficient of the display screen image and the module enhanced image according to the first standard deviation and the second standard deviation;

[0082] Performing an arithmetic difference operation on the display screen image and the module enhanced image to generate an intermediate image;

[0083] generating contrast weighted data of the boundary structure area and the circuit structure area according to the brightness adjustment coefficient, the contrast enhancement coefficient and the intermediate image;

[0084] The grayscale values ​​of the pixels in the intermediate image are enhanced according to the contrast weighted data to generate a structural region enhanced image;

[0085] Draw equally spaced radial and transverse line segments in the structure region enhanced image;

[0086] Perform grayscale analysis on the pixels on the radial line segments and the transverse line segments to determine the coordinate data of the transition points;

[0087] The coordinate data of the transition points are used to draw the contour points between the areas to be measured on the display screen image.

[0088] Optional, output unit, including:

[0089] Performing morphological processing, feature screening analysis, and coordinate transformation on the appearance image of the target display area to generate a first defect analysis result of the appearance image of the target display area;

[0090] Performing feature quantity screening and coordinate transformation on the appearance image of the target circuit area to generate a second defect analysis result of the appearance image of the target circuit area;

[0091] Processing the appearance image of the boundary area by a convolution filtering algorithm, performing defect feature screening and coordinate transformation on the appearance image of the boundary area, and generating a third defect analysis result of the appearance image of the boundary area;

[0092] The first defect analysis result, the second defect analysis result, and the third defect analysis result are determined as defect analysis results.

[0093] A third aspect of the present application provides a device for processing a display screen image including a circuit area, comprising:

[0094] Processor, memory, input-output unit, and bus;

[0095] The processor is connected to the memory, the input and output unit, and the bus;

[0096] The memory stores a program, and the processor calls the program to execute the first aspect and any optional processing method of the first aspect.

[0097] A fourth aspect of the present application provides a computer-readable storage medium, on which a program is stored. When the program is executed on a computer, the program executes the first aspect and any optional processing method of the first aspect.

[0098] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0099] In the present application, the light source is first turned on, and then the display screen to be tested is photographed by an industrial line scan camera to generate a display screen image, and the display screen to be tested contains a circuit structure. First, the display screen image is divided into regional texture structures to generate a circuit area appearance image, a display area appearance image, and a boundary area appearance image. There is no circuit structure and boundary structure in the display screen area to be tested corresponding to the display area appearance image, and the screen body can be directly detected in a normal detection method. The boundary area appearance image is a boundary area with a boundary structure, and the structural level is single, and the detection difficulty is relatively small. However, the detection difficulty of the circuit area appearance image of the circuit mechanism is increased. Although the circuit structure is thin, the overall structure is complex. When the external light source environment changes slightly, it will cause a large difference in the circuit area between each captured display screen image. After the circuit area appearance image is determined, a standard limited sample screen is selected, and the standard limited sample screen is photographed to generate a limited sample screen circuit area appearance image. The standard limited sample screen and the display screen to be tested are the same type of display screens, and the standard limited sample screen is a defect-free display screen. The circuit area appearance image and the limited sample screen circuit area appearance image are downsampled to generate a first compressed image and a second compressed image. Generate a grayscale morphological structure kernel operator according to the screen detection defect corresponding to the circuit area appearance image. Perform a bottom hat algorithm on the first compressed image and the second compressed image respectively according to the grayscale morphological structure kernel operator. Perform morphological dilation and arithmetic operations on the first compressed image and the second compressed image to obtain a result image. Perform threshold analysis and upsampling expansion on the result image to generate a target circuit area appearance image. Perform adaptive emphasis filtering algorithm processing on the display area appearance image to generate a target display area appearance image. Perform defect detection on the target circuit area appearance image, the target display area appearance image and the boundary area appearance image, and output the defect analysis results.

[0100] By first downsampling the circuit area appearance image and the circuit area appearance image of the defect-free limited sample screen, the image features of the two are extracted, the screen defects that need to be detected in the circuit area appearance image are determined, and the grayscale morphological structure kernel operator is generated according to the type and defect area of ​​the screen defect. The grayscale morphological structure kernel operator is used to perform bottom hat algorithm and morphological expansion on the first compressed image and the second compressed image after downsampling, and finally arithmetic operations are performed on the first compressed image and the second compressed image. The circuit area appearance image is processed by bottom hat operation to reduce the difference caused by illumination changes to the circuit area appearance image, and improve the screen defect detection accuracy of the display screen image containing the circuit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0101] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0102] Figure 1 A schematic diagram of an embodiment of a method for processing a display screen image including a circuit area of ​​the present application;

[0103] Figure 2 A schematic diagram of an embodiment of the first stage of the method for processing a display screen image including a circuit area of ​​the present application;

[0104] Figure 3 A schematic diagram of an embodiment of the second stage of the method for processing a display screen image including a circuit area of ​​the present application;

[0105] Figure 4 A schematic diagram of an embodiment of the third stage of the method for processing a display screen image including a circuit area of ​​the present application;

[0106] Figure 5 A schematic diagram of an embodiment of the fourth stage of the method for processing a display screen image including a circuit area of ​​the present application;

[0107] Figure 6 A schematic diagram of an embodiment of a device for processing a display screen image including a circuit area of ​​the present application;

[0108] Figure 7 A schematic diagram of another embodiment of a device for processing a display screen image including a circuit area of ​​the present application;

[0109] Figure 8 A schematic diagram of a display screen image including a circuit area of ​​the present application;

[0110] Fig. 9Another schematic diagram of a display screen image including a circuit area of ​​the present application;

[0111] Fig.10 A schematic diagram of the display area image of this application;

[0112] Fig.11 A schematic diagram of a boundary area image of the present application;

[0113] Fig.12 A schematic diagram of the circuit area image of this application. DETAILED DESCRIPTION

[0114] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0115] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0116] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0117] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0118] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0119] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0120] In the prior art, as the application fields of display screens become more and more extensive, more and more functions are added, and precise circuit structures and other functional structures are added inside or on the surface of the display screen. This type of structure will not have much impact on the detection of display defects. However, since screen defects do not require image display, this type of display screen with structures is prone to false detection and missed detection of screen defects in the corresponding structural area. At present, the circuit structure and boundary structure are the most influential. The circuit structure is usually a very thin circuit board. Due to the complex internal structure of the circuit structure, it mainly presents blocks with different levels, and the overall area is large, concentrated, and arranged inside the display screen. The second is the boundary structure, which is also located inside the display screen and mainly presents thin strips with a single level.

[0121] This application is mainly aimed at the appearance display screen containing the circuit area. When detecting screen defects in the traditional way, it is necessary to illuminate with an external light source to enhance the display of defects. The enhancement effect is obvious for the display area without circuits. However, due to the appearance of the circuit structure, when the external light source environment changes slightly, it will cause a large difference between each captured display screen image in the circuit area, resulting in inaccurate detection of screen defects in this area.

[0122] Based on this, the present application discloses a method, device and storage medium for processing a display screen image containing a circuit area, which are used to improve the screen defect detection accuracy of the display screen image containing a circuit area.

[0123] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0124] The method of the present application can be applied to a server, a device, a terminal or other devices with logic processing capabilities, and the present application does not limit this. For the convenience of description, the following description is made by taking the execution subject as an example of a terminal.

[0125] See also Figure 1 The present application provides an embodiment of a method for processing a display screen image containing a circuit area, comprising:

[0126] 101. Turn on the light source, and use an industrial line scan camera to shoot the display screen to generate a display screen image. The display screen to be tested contains a circuit structure;

[0127] In this embodiment, the display screen to be tested is first fixed, the light source is turned on, and the display screen to be tested is photographed by an industrial line scan camera to generate a display screen image. The display screen to be tested contains a circuit structure. In this embodiment, the circuit structure is block-shaped as a whole, and there are irregular circuit modules.

[0128] 102. Divide the display screen image into regional texture structures to generate a circuit area appearance image, a display area appearance image, and a boundary area appearance image;

[0129] The terminal first divides the display screen image into regional texture structures to generate a circuit area appearance image, a display area appearance image and a boundary area appearance image, the purpose of which is to detect the circuit area appearance image separately. In this embodiment, it can be delineated manually.

[0130] The textures of the image display area (corresponding to the display area appearance image), the circuit area (corresponding to the circuit area appearance image), and the boundary area (corresponding to the boundary area appearance image) are very different, so the detection can be carried out by first partitioning and then detecting. Please refer to Figure 8 and Fig. 9 , Figure 8 is a display screen image containing circuit structure and border structure, Fig. 9 An image of a display screen with the grayscale values ​​of the regional pixels adjusted so that each area can be distinguished relatively clearly. Figure 10 to Figure 12 , Figure 10 to Figure 12 They are display area image, boundary area image and circuit area image respectively.

[0131] The circuit structure is located in the trapezoidal area at the bottom of the figure. It can be seen that there are many shapes of this part, including sawtooth circuit structure, strip circuit structure and other shapes. The area formed by these structures is the circuit area appearance image. The boundary structure is the surrounding strip structure. The boundary structure can be formed by one or more strip structures. The area formed by the boundary structure is the boundary area appearance image. The part of the area enclosed by the two areas is the display area appearance image.

[0132] 103. Select a standard sample screen and shoot the standard sample screen to generate an appearance image of the circuit area of ​​the sample screen. The standard sample screen and the display screen to be tested are of the same type, and the standard sample screen is a defect-free display screen.

[0133] Before conducting the appearance inspection of the circuit area, the terminal selects a standard limited sample screen of the same type as the display screen to be tested. A standard limited sample screen can be selected from all products, or one can be prepared in advance. The standard limited sample screen can be defined as a high-quality product, which is required to be free of defects such as broken edges and corners. The standard limited sample screen is photographed and the appearance image (circuit area) of the circuit area of ​​the limited sample screen is observed.

[0134] 104. Downsample the circuit area appearance image and the sample-limited screen circuit area appearance image to generate a first compressed image and a second compressed image;

[0135] The appearance defects in the circuit area are generally macroscopic defects. In order to reduce the tt detection time, the circuit area appearance image of the limited sample screen and the circuit area of ​​the circuit area appearance image are first pre-processed and smoothed, and then down-sampled to obtain a compressed image.

[0136] 105. Generate a grayscale morphological structure kernel operator according to the screen detection defect corresponding to the circuit area appearance image;

[0137] 106. Perform a bottom-hat algorithm on the first compressed image and the second compressed image respectively according to the grayscale morphological structure kernel operator;

[0138] 107. Perform morphological expansion and arithmetic operation on the first compressed image and the second compressed image to obtain a result image;

[0139] 108. Perform threshold analysis and upsampling processing on the result image to generate an appearance image of the target circuit area;

[0140] The terminal generates a grayscale morphological structure kernel operator based on the screen detection defect corresponding to the circuit area appearance image. Specifically, it automatically determines the design based on the size of the defect area and defect type of the screen detection defect. However, it should be noted that the structure kernel size needs to be set to an odd number. Then the terminal performs a bottom-hat algorithm for the first compressed image and the second compressed image based on the grayscale morphological structure kernel operator. After the bottom-hat algorithm, the image inhomogeneity caused by external environmental interference will be greatly reduced. The formula is as follows:

[0141]

[0142] in, is the original image, is the grayscale morphological structure kernel operator, is the output image of the grayscale closing operation of the original image, This is the result image of the bottom hat algorithm.

[0143] Next, the terminal performs the first compression of the image after the bottom hat algorithm. and the second compressed image After morphological expansion, and , and then and Perform arithmetic operations to obtain images , the formula is as follows:

[0144]

[0145] Next, the terminal then Perform threshold analysis as follows:

[0146]

[0147] For the specified grayscale interval The area image within is set to .

[0148] Since the previous steps downsampled the image, the above steps are all processed on the compressed image, and the defect coordinates of the direct output results have changed, so the image needs to be Upsampling is performed to expand the size before scaling to obtain the appearance image of the target circuit area .

[0149] The traditional method for processing circuit areas is to directly use template matching and then perform differentiation.

[0150] The above algorithm uses the grayscale increase of each image, and specifically processes the circuit area appearance image by bottom-hat operation, so as to reduce the difference in the circuit area appearance image caused by changes in external environment such as lighting, and improve the screen defect detection accuracy of the display screen image containing the circuit area. The impact of external lighting environment changes on this algorithm is very small, because in actual production, the grayscale differences of images obtained by line scan cameras are large. The size of the morphological structure kernel operator in this algorithm can be set according to the type of defect detected. For example, only in the detection area, the size of the structure kernel operator can be set larger when detecting relatively large dirt and cracks, and the size of the structure kernel operator can be set smaller when detecting defects such as fine dust and foreign matter. In addition to the detection area, it can also target defect parameters unique to various circuit areas, such as circuit deformation within the circuit area.

[0151] 109. Process the display area appearance image using an adaptive emphasis filtering algorithm to generate a target display area appearance image;

[0152] In this embodiment, the terminal first performs smoothing filtering preprocessing on the appearance image of the display area, constructs a structural spatial contrast enhancement kernel operator, generates a kernel factor according to the structural spatial contrast enhancement kernel operator and the defect type of the appearance image of the display area, and performs an emphasized convolution filtering algorithm on the appearance image of the display area through the kernel factor.

[0153] The specific algorithm flow of the display area appearance image is as follows:

[0154] The texture of the appearance image of the display area is not that complicated. In this embodiment, the appearance image of the display area is firstly smoothed and filtered to remove some subtle noise points, and then a spatial contrast enhancement kernel operator is constructed. The spatial contrast enhancement kernel operator can generate different kernel factors (including polarity, size, weight, etc.) according to the set defect type. The appearance image of the display area is processed by the emphasized convolution filtering algorithm through the kernel factor. The kernel factor is as follows:

[0155]

[0156] Among them, N is the enhanced contrast distance, that is, the size parameter of the defect to be detected. By setting different enhanced contrast distances, exclusive nuclear factors can be formed for different detection defects. The appearance image of the display area is processed by the emphasized filtering algorithm through the nuclear factor, which can effectively enhance the characteristics of different detection defects. The setting of the enhanced contrast distance N can be set by human experience, or by obtaining the sizes of multiple detection defects for automatic comparison and generation.

[0157] After the nuclear factor is generated, the terminal performs an adaptive emphasis filtering algorithm on the appearance image of the display area, and after the target appearance image of the display area is generated, the appearance image of the display area can be processed by the emphasis filtering algorithm through the nuclear factor. The formula of the emphasis filtering algorithm is as follows:

[0158]

[0159] in: To emphasize the grayscale of the image output after the operation, represents the kernel matrix, is the image grayscale of the input image.

[0160] 110. Perform defect detection on the target circuit area appearance image, the target display area appearance image, and the boundary area appearance image, and output defect analysis results.

[0161] After the terminal processing is completed, defect detection can be performed on the target circuit area appearance image, the target display area appearance image and the boundary area appearance image, and the defect analysis results of the three areas can be output.

[0162] In the present application, the light source is first turned on, and then the display screen to be tested is photographed by an industrial line scan camera to generate a display screen image, and the display screen to be tested contains a circuit structure. First, the display screen image is divided into regional texture structures to generate a circuit area appearance image, a display area appearance image, and a boundary area appearance image. There is no circuit structure and boundary structure in the display screen area to be tested corresponding to the display area appearance image, and the screen body can be directly detected in a normal detection method. The boundary area appearance image is a boundary area with a boundary structure, and the structural level is single, and the detection difficulty is relatively small. However, the detection difficulty of the circuit area appearance image of the circuit mechanism is increased. Although the circuit structure is thin, the overall structure is complex. When the external light source environment changes slightly, it will cause a large difference in the circuit area between each captured display screen image. After the circuit area appearance image is determined, a standard limited sample screen is selected, and the standard limited sample screen is photographed to generate a limited sample screen circuit area appearance image. The standard limited sample screen and the display screen to be tested are the same type of display screens, and the standard limited sample screen is a defect-free display screen. The circuit area appearance image and the limited sample screen circuit area appearance image are downsampled to generate a first compressed image and a second compressed image. Generate a grayscale morphological structure kernel operator according to the screen detection defect corresponding to the circuit area appearance image. Perform a bottom hat algorithm on the first compressed image and the second compressed image respectively according to the grayscale morphological structure kernel operator. Perform morphological dilation and arithmetic operations on the first compressed image and the second compressed image to obtain a result image. Perform threshold analysis and upsampling expansion on the result image to generate a target circuit area appearance image. Perform adaptive emphasis filtering algorithm processing on the display area appearance image to generate a target display area appearance image. Perform defect detection on the target circuit area appearance image, the target display area appearance image and the boundary area appearance image, and output the defect analysis results.

[0163] By first downsampling the circuit area appearance image and the circuit area appearance image of the defect-free limited sample screen, the image features of the two are extracted, the screen defects that need to be detected in the circuit area appearance image are determined, and the grayscale morphological structure kernel operator is generated according to the type and defect area of ​​the screen defect. The grayscale morphological structure kernel operator is used to perform bottom hat algorithm and morphological expansion on the first compressed image and the second compressed image after downsampling, and finally arithmetic operations are performed on the first compressed image and the second compressed image. The circuit area appearance image is processed by bottom hat operation to reduce the difference caused by illumination changes to the circuit area appearance image, and improve the screen defect detection accuracy of the display screen image containing the circuit area.

[0164] See also Figure 2 , Figure 3 , Figure 4 and Figure 5 The present application provides another embodiment of a method for processing a display screen image containing a circuit area, comprising:

[0165] 201. Turn on the light source, shoot the display screen to be tested by an industrial line scan camera, and generate a display screen image. The display screen to be tested includes a circuit structure;

[0166] Step 201 in this embodiment is similar to step 101 in the above embodiment and will not be described again here.

[0167] 202. Determine a transition point of a display screen image;

[0168] 203. Using the least squares algorithm to fit the transition points into line segments;

[0169] 204. Find the intersection point of the fitted line segment to generate the original transformation point pair;

[0170] 205. Perform pixel correction processing on the display screen image by combining the original transformed point pairs and the length and width parameters of the display screen through the point pair transformation matrix;

[0171] In this embodiment, because the display screen to be tested is produced in large quantities due to different incoming materials, resulting in image tilt, the display screen image is first subjected to a gradient difference algorithm to find the display screen image and the corresponding transition points, and the transition points are fitted into line segments. The intersection points of the fitted line segments are obtained, and the product image is corrected by the point pair transformation matrix in combination with the actual length and width of the product. The fitting formula is as follows:

[0172]

[0173] Among them: are the coordinates of the fitted line, is the actual transition point coordinate, R is the calculation error, n is the number of transition points, and the least squares method can ensure that R is minimized. The formula of the point pair transformation matrix is ​​as follows:

[0174]

[0175] in: and are the rotation and translation matrices, and are the original transformed point pairs of the image before and after correction respectively.

[0176] 206. Acquire a module enhanced image of the sample display screen, the sample display screen and the display screen to be tested are of the same type, the module enhanced image is an image of the sample display screen with the boundary structure region and the circuit structure region enhanced, and the display enhancement degrees of the boundary structure region and the circuit structure region are different;

[0177] In this embodiment, a captured image of a display screen of the same type is first obtained, the boundary structure area and the circuit structure area are located on the captured image, and different degrees of display enhancement, that is, grayscale value adjustment, are performed on the boundary structure area and the circuit structure area to generate a module enhanced image. In this embodiment, it is usually chosen not to adjust the boundary structure area, and only the grayscale value of the pixel points in the circuit structure area is enhanced, that is, the display enhancement coefficient of the boundary structure area is set to 1, and the display enhancement coefficient of the circuit structure area is greater than 1. It is also possible to choose to slightly adjust the boundary structure area and enhance the grayscale value of the pixel points in the circuit structure area at the same time, that is, the display enhancement coefficient of the boundary structure area is set to be slightly greater than 1, and the display enhancement coefficient of the circuit structure area is greater than 1.1.

[0178] 207. Obtain a first grayscale mean value and a first standard deviation of the display screen image and a second grayscale mean value and a second standard deviation of the module enhanced image;

[0179] Next, the terminal obtains the first grayscale mean value of the display screen image , first standard deviation The second grayscale mean of the image enhanced by the module and the second standard deviation .

[0180] 208. Calculate the brightness adjustment coefficient of the display screen image and the module enhanced image according to the first grayscale mean and the second grayscale mean;

[0181] The terminal is based on the first grayscale mean and the second grayscale mean Calculate the brightness adjustment coefficient of the display image and the module enhanced image , the formula is as follows:

[0182]

[0183] in, It is the display enhancement contrast value between the boundary structure area and the circuit structure area in the module enhancement image. When the display enhancement coefficient of the boundary structure area is set to 1, this value is the display enhancement coefficient of the circuit structure area.

[0184] 209. Calculate the contrast enhancement coefficient of the display screen image and the module enhanced image according to the first standard deviation and the second standard deviation;

[0185] The terminal is based on the first standard deviation and the second standard deviation Calculate the contrast enhancement coefficient of the display image and the module enhanced image , the formula is as follows:

[0186]

[0187] 210. Perform a difference arithmetic operation on the display screen image and the module enhanced image to generate an intermediate image;

[0188] 211. Generate contrast weighted data of the boundary structure area and the circuit structure area according to the brightness adjustment coefficient, the contrast enhancement coefficient and the intermediate image;

[0189] Next, the terminal performs a difference arithmetic operation on the display screen image and the module enhanced image to generate an intermediate image. The terminal then generates contrast weighted data for the boundary structure area and the circuit structure area based on the brightness adjustment coefficient, the contrast enhancement coefficient and the intermediate image. , the formula is as follows:

[0190]

[0191] in, It is the difference between the grayscale mean values ​​of the boundary structure area and the circuit structure area in the intermediate image. Specifically, the grayscale mean value of the boundary structure area in the intermediate image is calculated first, and then the grayscale mean value of the circuit structure area in the intermediate image is calculated. Then, the larger grayscale mean value is subtracted from the smaller one. Usually, the grayscale mean value of the circuit structure area is larger than that of the boundary structure area.

[0192] 212. Enhance the grayscale values ​​of the pixels of the intermediate image according to the contrast weighted data to generate a structure region enhanced image;

[0193] The terminal enhances the grayscale value of the pixel points of the intermediate image according to the contrast weighted data to generate a structural area enhanced image. The formula is as follows:

[0194]

[0195] in, It is the pixel grayscale of the structure area enhancement image in the boundary structure area and circuit structure area. It is the grayscale of the pixels in the boundary structure area and the circuit structure area of ​​the intermediate image, that is, only the boundary structure area and the circuit structure area are enhanced, because other areas outside these two areas are usually set to grayscale 255 in order to eliminate interference from other areas. The 255 grayscale in these areas is already the maximum grayscale and cannot be enhanced again.

[0196] 213. Draw radial line segments and transverse line segments with equal intervals in the structure region enhanced image;

[0197] 214. Perform grayscale analysis on the pixel points on the radial line segment and the transverse line segment to determine the coordinate data of the transition point;

[0198] 215. Draw contour points between the areas to be tested on the display screen image using the coordinate data of the transition points;

[0199] Next, the terminal draws radial and transverse line segments with equal intervals in the structure area enhanced image. Each line segment passes through different pixel points, that is, N columns of pixel points and M rows of pixel points are evenly selected. Through the grayscale values ​​of these pixel points, the pixel points with grayscale value differences greater than the preset threshold are determined as transition points. The coordinates of these points locate the display screen image to generate contour points.

[0200] 216. Generate a polygonal region set according to the coordinate positions of the contour points and the preset multi-region shape;

[0201] 217. Determine a circuit region and a display region in the polygonal region set, and generate a binary circuit image and a binary display image for the circuit region and the display region, respectively;

[0202] 218. Performing a logical AND operation on the display screen image, the binary circuit image, and the binary display image, respectively, to generate a circuit area appearance image and a display area appearance image;

[0203] 219. Perform a logical OR operation on the binary circuit image and the binary display image, and then perform a logical inversion operation to obtain a binary boundary image;

[0204] 220. Perform a logical AND operation on the display screen image and the binary boundary image to generate a boundary area appearance image;

[0205] In this embodiment, most of the current algorithm processing is to directly detect the entire image, and the effect is not ideal. Therefore, this embodiment adopts a partition detection idea to divide the display screen image into multiple parts. The texture difference of a single image part is relatively small. Different algorithm processes are used for segmentation of each segmented image part, and defect detection is performed at the same time. It has been verified that the overall algorithm process can reduce the detection complexity, and the defect detection capability is also effectively improved.

[0206] After the terminal obtains the contour points, it forms a specified polygonal area through a polygon contour extraction algorithm to generate a binary image, and then performs a logical AND operation on the original image and the binary image to obtain the appearance image of the display area.

[0207] After drawing multiple contour points on the image through the algorithm, the terminal generates a binary image after forming the known contour points into a specified polygonal area through the polygon contour extraction algorithm, and then performs a logical AND operation on the binary image and the original image to obtain the circuit area appearance image.

[0208] The terminal first performs a logical OR operation on the binary images corresponding to the display area appearance image and the circuit area appearance image, then performs a logical inversion operation on the result image to obtain a binary image, and finally performs a logical AND operation on the original image and the binary image to obtain the boundary area appearance image.

[0209] 221. Select a standard sample screen and shoot the standard sample screen to generate an appearance image of the circuit area of ​​the sample screen. The standard sample screen and the display screen to be tested are of the same type, and the standard sample screen is a defect-free display screen.

[0210] Step 221 in this embodiment is similar to step 103 in the above embodiment and will not be described again here.

[0211] 222. Determine the interference area and auxiliary repair area of ​​the appearance image of the limited sample screen circuit area;

[0212] 223. Determine the position of the pixel point to be repaired in the interference area and the position of the auxiliary pixel point in the auxiliary repair area;

[0213] 224. Perform grayscale compensation and repair processing on the grayscale of the pixel to be repaired in the interference area according to the position of the pixel to be repaired, the position of the auxiliary pixel, and the grayscale of the auxiliary pixel in the auxiliary repair area;

[0214] In this embodiment, the standard limited sample screen needs to be a high-quality product, which is required to be free of screen defects such as broken edges and corners. The circuit area of ​​the standard limited sample screen is photographed and imaged to generate an appearance image of the circuit area of ​​the limited sample screen. Because it is difficult to find a high-quality product image in the actual intelligent manufacturing production line, a pixel grayscale compensation and repair algorithm is used in this embodiment. The algorithm performs grayscale image compensation and repair on the dust and stains on the limited sample image to obtain a good limited sample image for subsequent algorithm processing. The formula is as follows:

[0215]

[0216] in: is the grayscale of the pixel to be repaired in the appearance image of the limited sample screen circuit area (interference area), is the grayscale of the known pixels around the point to be repaired (auxiliary repair area), is the distance between the pixels in the two regions. Different pixels have different distances from point P, and the corresponding weights are also different. is the grayscale difference between the pixels in the two regions.

[0217] 225. Downsample the circuit area appearance image and the sample-limited screen circuit area appearance image to generate a first compressed image and a second compressed image;

[0218] 226. Generate a grayscale morphological structure kernel operator according to the screen detection defect corresponding to the circuit area appearance image;

[0219] 227. Perform a bottom-hat algorithm on the first compressed image and the second compressed image respectively according to the grayscale morphological structure kernel operator;

[0220] 228. Perform morphological dilation and arithmetic operation on the first compressed image and the second compressed image to obtain a result image;

[0221] 229. Perform threshold analysis and upsampling processing on the result image to generate an appearance image of the target circuit area;

[0222] 230. Process the display area appearance image using an adaptive emphasis filtering algorithm to generate a target display area appearance image;

[0223] Steps 225 to 230 in this embodiment are similar to steps 104 to 109 in the above-mentioned embodiment, and are not described again here.

[0224] 231. Perform morphological processing, feature screening analysis, and coordinate transformation on the appearance image of the target display area to generate a first defect analysis result of the appearance image of the target display area;

[0225] 232. Perform feature quantity screening and coordinate transformation on the target circuit area appearance image to generate a second defect analysis result of the target circuit area appearance image;

[0226] 233. Processing the appearance image of the boundary area by emphasizing the convolution filtering algorithm, performing defect feature screening and coordinate transformation on the appearance image of the boundary area, and generating a third defect analysis result of the appearance image of the boundary area;

[0227] 234. Determine the first defect analysis result, the second defect analysis result, and the third defect analysis result as defect analysis results.

[0228] In this embodiment, images of the three regions are subjected to separate defect detection.

[0229] When the terminal processes the display area appearance image using the adaptive emphasis filtering algorithm to generate the target display area appearance image, the kernel factor can be used to process the display area appearance image using the emphasis filtering algorithm. The emphasis filtering algorithm formula is as follows:

[0230]

[0231] in: To emphasize the grayscale of the image output after the filtering operation, represents the kernel matrix, is the image grayscale of the input image.

[0232] This patent emphasizes that filtering operations can effectively remove background images, and at the same time can clearly highlight suspected defects in the display area. The suspected defects are then morphologically processed, feature-screened and analyzed, and then the defects and positions are output through coordinate transformation, which is suitable for this type of display area appearance image.

[0233] Circuit area appearance detection algorithm flow: target circuit area appearance image It can directly filter features by area, grayscale, contrast, etc. and output defects and coordinates.

[0234] Boundary area appearance detection algorithm process: The texture of the boundary area appearance image is also relatively simple. The detection process method of this area is similar to that of the display appearance area. Because the image size of this area is not large, the setting of the nuclear factor is also relatively small. It mainly detects some small chipping angles, small foreign body defects, etc., and outputs defects and positions through convolution filtering algorithm processing, feature screening, and coordinate transformation.

[0235] Because the overall process of this algorithm is in one coordinate system, the final defect detection result is obtained by directly superimposing the regional images of the results of the above three areas.

[0236] In the present application, the light source is first turned on, and then the display screen to be tested is photographed by an industrial line scan camera to generate a display screen image, and the display screen to be tested contains a circuit structure. The transition point of the display screen image is determined. The least squares algorithm is used to fit the transition point into a line segment. The intersection of the fitted line segments is obtained to generate the original transformation point pair. The display screen image is pixel-corrected by combining the original transformation point pair and the length and width parameters of the display screen through the point pair transformation matrix. The module-enhanced image of the sample display screen is obtained, and the sample display screen and the display screen to be tested are the same type of display screens. The module-enhanced image is an image of the sample display screen with the boundary structure area and the circuit structure area enhanced by display. The display enhancement degree of the boundary structure area and the circuit structure area is different. The first grayscale mean, the first standard deviation of the display screen image and the second grayscale mean and the second standard deviation of the module-enhanced image are obtained. The brightness adjustment coefficient of the display screen image and the module-enhanced image is calculated according to the first grayscale mean and the second grayscale mean. The contrast enhancement coefficient of the display screen image and the module-enhanced image is calculated according to the first standard deviation and the second standard deviation. The display screen image and the module-enhanced image are subjected to difference arithmetic operation to generate an intermediate image. Contrast weighted data of the boundary structure area and the circuit structure area are generated according to the brightness adjustment coefficient, the contrast enhancement coefficient and the intermediate image. The grayscale value of the pixel point of the intermediate image is enhanced according to the contrast weighted data to generate a structure area enhanced image. Radial line segments and transverse line segments with equal intervals are drawn in the structure area enhanced image. Grayscale analysis is performed on the pixel points on the radial line segments and the transverse line segments to determine the coordinate data of the transition points. The contour points between the areas to be tested are drawn on the display screen image using the coordinate data of the transition points. A polygonal area set is generated according to the coordinate positions of the contour points and the preset multi-area shape. The circuit area and the display area in the polygonal area set are determined, and a binary circuit image and a binary display image are generated for the circuit area and the display area, respectively. The display screen image is logically ANDed with the binary circuit image and the binary display image, respectively, to generate a circuit area appearance image and a display area appearance image. The binary circuit image and the binary display image are logically ORed, and then logically negated to obtain a binary boundary image. The display screen image is logically ANDed with the binary boundary image to generate a boundary area appearance image. By processing the image through brightness adjustment parameters and contrast adjustment parameters, the overall grayscale between different regions can be better increased. This method can effectively improve the accuracy of region division.

[0237] After the circuit area appearance image is determined, a standard sample screen is selected and photographed to generate a circuit area appearance image of the sample screen. The standard sample screen and the display screen to be tested are of the same type and are defect-free.

[0238] Determine the interference area and auxiliary repair area of ​​the appearance image of the limited sample screen circuit area. Determine the position of the pixel to be repaired in the interference area and the position of the auxiliary pixel in the auxiliary repair area. Perform grayscale compensation and repair processing on the grayscale of the pixel to be repaired in the interference area according to the position of the pixel to be repaired, the position of the auxiliary pixel and the grayscale of the auxiliary pixel in the auxiliary repair area.

[0239] The circuit area appearance image and the limited sample screen circuit area appearance image are downsampled to generate a first compressed image and a second compressed image. A grayscale morphological structure kernel operator is generated according to the screen detection defect corresponding to the circuit area appearance image. A bottom hat algorithm is performed on the first compressed image and the second compressed image respectively according to the grayscale morphological structure kernel operator. The first compressed image and the second compressed image are subjected to morphological expansion and arithmetic operations to obtain a result image. The result image is subjected to threshold analysis processing and upsampling expansion processing to generate a target circuit area appearance image. The display area appearance image is subjected to smoothing filter preprocessing. A construction space contrast enhancement kernel operator is constructed. A kernel factor is generated according to the construction space contrast enhancement kernel operator and the defect type of the display area appearance image. The display area appearance image is subjected to an emphasis filter algorithm processing through the kernel factor. The display area appearance image is subjected to morphological processing, feature screening analysis, and coordinate transformation to generate a first defect analysis result of the display area appearance image. The target circuit area appearance image is subjected to feature quantity screening and coordinate transformation to generate a second defect analysis result of the target circuit area appearance image. The boundary area appearance image is processed by a convolution filtering algorithm, and defect feature screening and coordinate transformation are performed on the boundary area appearance image to generate a third defect analysis result of the boundary area appearance image. The first defect analysis result, the second defect analysis result and the third defect analysis result are determined as defect analysis results.

[0240] By first downsampling the circuit area appearance image and the circuit area appearance image of the defect-free limited sample screen, the image features of the two are extracted, the screen defects that need to be detected in the circuit area appearance image are determined, and the grayscale morphological structure kernel operator is generated according to the type and defect area of ​​the screen defect. The grayscale morphological structure kernel operator is used to perform bottom hat algorithm and morphological expansion on the first compressed image and the second compressed image after downsampling, and finally arithmetic operations are performed on the first compressed image and the second compressed image. The circuit area appearance image is processed by bottom hat operation to reduce the difference caused by illumination changes to the circuit area appearance image, and improve the screen defect detection accuracy of the display screen image containing the circuit area.

[0241] See also Figure 6 The present application provides an embodiment of a device for processing a display screen image including a circuit area, comprising:

[0242] The first generating unit 601 is used to turn on the light source, shoot the display screen to be tested by an industrial line scan camera, and generate a display screen image, wherein the display screen to be tested contains a circuit structure;

[0243] A first determining unit 602, configured to determine a transition point of a display screen image;

[0244] A fitting unit 603, used to fit the transition points into line segments using a least squares algorithm;

[0245] An eighth generating unit 604 is used to obtain intersection points for the fitted line segments and generate original transformation point pairs;

[0246] A correction unit 605 is used to perform pixel correction processing on the display screen image by combining the original transformed point pairs and the display screen length and width parameters through a point pair transformation matrix;

[0247] The second generating unit 606 is used to divide the display screen image into regional texture structures to generate a circuit area appearance image, a display area appearance image and a boundary area appearance image;

[0248] Optionally, the second generating unit 606 includes:

[0249] A drawing module 6061 is used to draw contour points at the intersections between the areas to be measured on the display screen image;

[0250] Optionally, the drawing module 6061 includes:

[0251] Acquire a module enhanced image of a sample display screen, the sample display screen and the display screen to be tested are of the same type, the module enhanced image is an image of the sample display screen with the boundary structure region and the circuit structure region enhanced, and the display enhancement degrees of the boundary structure region and the circuit structure region are different;

[0252] Acquire a first grayscale mean value and a first standard deviation of the display screen image and a second grayscale mean value and a second standard deviation of the module enhanced image;

[0253] Calculating brightness adjustment coefficients of the display screen image and the module enhanced image according to the first grayscale mean and the second grayscale mean;

[0254] Calculating the contrast enhancement coefficient of the display screen image and the module enhanced image according to the first standard deviation and the second standard deviation;

[0255] Performing difference arithmetic operation on the display screen image and the module enhanced image to generate an intermediate image;

[0256] generating contrast weighted data of the boundary structure area and the circuit structure area according to the brightness adjustment coefficient, the contrast enhancement coefficient and the intermediate image;

[0257] The grayscale values ​​of the pixels in the intermediate image are enhanced according to the contrast weighted data to generate a structural region enhanced image;

[0258] Draw equally spaced radial and transverse line segments in the structure region enhanced image;

[0259] Perform grayscale analysis on the pixels on the radial line segments and the transverse line segments to determine the coordinate data of the transition points;

[0260] The coordinate data of the transition points are used to draw the contour points between the areas to be measured on the display screen image.

[0261] A first generating module 6062, used to generate a polygonal region set according to the coordinate positions of the contour points and the preset multi-region shape;

[0262] The second generating module 6063 is used to determine the circuit area and the display area in the polygonal area set, and generate a binary circuit image and a binary display image for the circuit area and the display area respectively;

[0263] The third generating module 6064 is used to perform a logical AND operation on the display screen image, the binary circuit image and the binary display image, respectively, to generate a circuit area appearance image and a display area appearance image;

[0264] The logic operation module 6065 is used to perform a logic OR operation on the binary circuit image and the binary display image, and then perform a logic inversion operation to obtain a binary boundary image;

[0265] The fourth generating module 6066 is used to perform a logical AND operation on the display screen image and the binary boundary image to generate a boundary area appearance image.

[0266] The third generating unit 607 is used to select a standard sample screen and shoot the standard sample screen to generate an appearance image of the circuit area of ​​the sample screen. The standard sample screen and the display screen to be tested are of the same type, and the standard sample screen is a defect-free display screen.

[0267] The second determining unit 608 is used to determine the interference area and the auxiliary repair area of ​​the appearance image of the circuit area of ​​the limited sample screen;

[0268] A third determining unit 609 is used to determine the positions of the pixels to be repaired in the interference area and the positions of the auxiliary pixels in the auxiliary repair area;

[0269] The repair unit 610 is used to perform grayscale compensation repair processing on the grayscale of the pixel to be repaired in the interference area according to the position of the pixel to be repaired, the position of the auxiliary pixel and the grayscale of the auxiliary pixel in the auxiliary repair area;

[0270] The fourth generating unit 611 is used to downsample the circuit area appearance image and the limited sample screen circuit area appearance image to generate a first compressed image and a second compressed image;

[0271] A fifth generating unit 612, configured to generate a grayscale morphological structure kernel operator according to the screen body detection defect corresponding to the circuit area appearance image;

[0272] An operation unit 613 is used to perform a bottom-hat algorithm on the first compressed image and the second compressed image respectively according to the grayscale morphological structure kernel operator;

[0273] A sixth generating unit 614 is configured to perform morphological dilation and arithmetic operation on the first compressed image and the second compressed image to obtain a result image;

[0274] The seventh generating unit 615 is used to perform threshold analysis and up-sampling and enlargement processing on the result image to generate an appearance image of the target circuit area;

[0275] The emphasis filtering unit 616 is used to process the display area appearance image with an adaptive emphasis filtering algorithm to generate a target display area appearance image;

[0276] The output unit 617 is used to perform defect detection on the target circuit area appearance image, the display area appearance image and the boundary area appearance image, and output defect analysis results.

[0277] Optionally, the output unit 617 includes:

[0278] Performing morphological processing, feature screening analysis, and coordinate transformation on the appearance image of the display area to generate a first defect analysis result of the appearance image of the display area;

[0279] Performing feature quantity screening and coordinate transformation on the appearance image of the target circuit area to generate a second defect analysis result of the appearance image of the target circuit area;

[0280] Processing the appearance image of the boundary area by a convolution filtering algorithm, performing defect feature screening and coordinate transformation on the appearance image of the boundary area, and generating a third defect analysis result of the appearance image of the boundary area;

[0281] The first defect analysis result, the second defect analysis result, and the third defect analysis result are determined as defect analysis results.

[0282] See also Figure 7 The present application provides a device for processing a display screen image including a circuit area, comprising:

[0283] Processor 701 , memory 702 , input / output unit 703 , and bus 704 .

[0284] The processor 701 is connected to the memory 702 , the input and output unit 703 , and the bus 704 .

[0285] The memory 702 stores a program, and the processor 701 calls the program to execute the following steps: Figure 1 , Figure 2 and Figure 3 , Figure 4 and Figure 5 The processing method in .

[0286] The present application provides a computer-readable storage medium, on which a program is stored, and when the program is executed on a computer, the program performs the following steps: Figure 1 , Figure 2 and Figure 3 , Figure 4 and Figure 5 The processing method in .

[0287] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0288] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0289] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0290] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0291] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, read-only memory), random access memory (RAM, random access memory), disk or optical disk and other media that can store program code.

Claims

1. A method for processing a display screen image containing a circuit area, characterized in that: include: Turning on the light source, photographing the display screen to be tested by an industrial line scan camera to generate a display screen image, wherein the display screen to be tested contains a circuit structure; Performing regional texture structure division on the display screen image to generate a circuit area appearance image, a display area appearance image and a boundary area appearance image; A standard sample screen is selected and photographed to generate an appearance image of a circuit area of ​​the sample screen, wherein the standard sample screen and the display screen to be tested are of the same type and the standard sample screen is a defect-free display screen; Downsampling the circuit area appearance image and the sample-limited screen circuit area appearance image to generate a first compressed image and a second compressed image; Generate a grayscale morphological structure kernel operator according to the screen detection defect corresponding to the circuit area appearance image; Performing a bottom-hat algorithm on the first compressed image and the second compressed image respectively according to the grayscale morphological structure kernel operator; Performing morphological expansion and arithmetic operation on the first compressed image and the second compressed image after the bottom-hat algorithm is performed to obtain a result image; Performing threshold analysis and upsampling processing on the result image to generate an appearance image of the target circuit area; Constructing an adaptive nuclear factor to perform an emphasis filtering algorithm on the display area appearance image to generate a target display area appearance image; Defect detection is performed on the target circuit area appearance image, the target display area appearance image and the boundary area appearance image, and a defect analysis result is output.

2. The processing method according to claim 1, characterized in that: After turning on the light source and photographing the display screen to be tested with an industrial line scan camera to generate a display screen image, before dividing the display screen image into regional texture structures to generate a circuit area appearance image, a display area appearance image, and a boundary area appearance image, the processing method further includes: Determining a transition point of the display screen image; Using a least squares algorithm to fit the transition points into line segments; Find the intersection points of the fitted line segments and generate the original transformation point pairs; The pixel correction processing of the display screen image is performed by combining the original transformed point pairs and the length and width parameters of the display screen through the point pair transformation matrix.

3. The processing method according to claim 1, characterized in that: After selecting a standard limited sample screen and photographing the standard limited sample screen to generate a limited sample screen circuit area appearance image, and before downsampling the circuit area appearance image and the limited sample screen circuit area appearance image to obtain a first compressed image and a second compressed image, the processing method further includes: Determine the interference area and auxiliary repair area of ​​the appearance image of the circuit area of ​​the sample-limited screen; Determine the position of the pixel point to be repaired in the interference area and the position of the auxiliary pixel point in the auxiliary repair area; Grayscale compensation and repair processing is performed on the grayscale of the pixel to be repaired in the interference area according to the position of the pixel to be repaired, the position of the auxiliary pixel and the grayscale of the auxiliary pixel in the auxiliary repair area.

4. The processing method according to claim 1, characterized in that: The display screen image is divided into regional texture structures to generate a circuit area appearance image, a display area appearance image and a boundary area appearance image, including: Drawing contour points at the intersections between the areas to be measured on the display screen image; Generate a polygonal region set according to the coordinate positions of the contour points and a preset multi-region shape; Determine a circuit area and a display area in the polygonal area set, and generate a binary circuit image and a binary display image for the circuit area and the display area respectively; Performing a logical AND operation on the display screen image, the binary circuit image and the binary display image, respectively, to generate a circuit area appearance image and a display area appearance image; Performing a logical OR operation on the binary circuit image and the binary display image, and then performing a logical inversion operation to obtain a binary boundary image; A logical AND operation is performed on the display screen image and the binary boundary image to generate a boundary area appearance image.

5. The processing method according to claim 4, characterized in that: Drawing contour points at the intersections between the areas to be measured on the display screen image includes: Acquire a module enhanced image of a sample display screen, wherein the sample display screen and the display screen to be tested are of the same type, and the module enhanced image is an image of the sample display screen with a boundary structure region and a circuit structure region enhanced, and the display enhancement degrees of the boundary structure region and the circuit structure region are different; Acquire a first grayscale mean value and a first standard deviation of the display screen image and a second grayscale mean value and a second standard deviation of the module enhanced image; Calculating brightness adjustment coefficients of the display screen image and the module enhanced image according to the first grayscale mean and the second grayscale mean; Calculating a contrast enhancement coefficient of the display screen image and the module enhanced image according to the first standard deviation and the second standard deviation; Performing a difference arithmetic operation on the display screen image and the module enhanced image to generate an intermediate image; generating contrast weighted data of the boundary structure area and the circuit structure area according to the brightness adjustment coefficient, the contrast enhancement coefficient and the intermediate image; Enhance the grayscale values ​​of the pixels of the intermediate image according to the contrast weighted data to generate a structure region enhanced image; Drawing radial line segments and transverse line segments with equal intervals in the structure region enhanced image; Performing grayscale analysis on the pixel points on the radial line segment and the transverse line segment to determine the coordinate data of the transition point; The coordinate data of the transition points are used to draw contour points between the areas to be tested on the display screen image.

6. The processing method according to any one of claims 1 to 5, characterized in that: Performing defect detection on the target circuit area appearance image, the target display area appearance image, and the boundary area appearance image, and outputting defect analysis results, including: Performing morphological processing, feature screening analysis, and coordinate transformation on the appearance image of the target display area to generate a first defect analysis result of the appearance image of the target display area; Performing feature quantity screening and coordinate transformation on the target circuit area appearance image to generate a second defect analysis result of the target circuit area appearance image; Processing the boundary area appearance image by a convolution filtering algorithm, performing defect feature screening and coordinate transformation on the boundary area appearance image, and generating a third defect analysis result of the boundary area appearance image; The first defect analysis result, the second defect analysis result and the third defect analysis result are determined as the defect analysis results.

7. A device for processing images of a display screen including a circuit area, characterized in that: include: The first generating unit is used to turn on the light source, and to shoot the display screen to be tested by an industrial line scan camera to generate a display screen image, wherein the display screen to be tested contains a circuit structure; A second generating unit is used to divide the display screen image into regional texture structures to generate a circuit area appearance image, a display area appearance image and a boundary area appearance image; A third generating unit is used to select a standard limited sample screen and photograph the standard limited sample screen to generate an appearance image of a circuit area of ​​the limited sample screen, wherein the standard limited sample screen and the display screen to be tested are of the same type, and the standard limited sample screen is a defect-free display screen; A fourth generating unit is used to downsample the circuit area appearance image and the sample-limited screen circuit area appearance image to generate a first compressed image and a second compressed image; A fifth generating unit, configured to generate a grayscale morphological structure kernel operator according to the screen body detection defect corresponding to the circuit area appearance image; an operation unit, configured to perform a bottom-hat algorithm on the first compressed image and the second compressed image respectively according to the grayscale morphological structure kernel operator; A sixth generating unit, configured to perform morphological dilation and arithmetic operation on the first compressed image and the second compressed image after the bottom-hat algorithm is performed to obtain a result image; A seventh generating unit, configured to perform threshold analysis and up-sampling and enlargement processing on the result image to generate an appearance image of the target circuit area; An emphasis filtering unit, used for performing an adaptive emphasis filtering algorithm on the display area appearance image to generate a target display area appearance image; The output unit is used to perform defect detection on the target circuit area appearance image, the target display area appearance image and the boundary area appearance image, and output defect analysis results.

8. The processing device according to claim 7, characterized in that After the first generating unit and before the second generating unit, the processing device further includes: A first determining unit, configured to determine a transition point of the display screen image; A fitting unit, used for fitting the transition points into line segments using a least squares algorithm; An eighth generating unit, used for obtaining intersection points of the fitted line segments and generating original transformation point pairs; The correction unit is used to perform pixel correction processing on the display screen image by combining the original transformed point pairs and the length and width parameters of the display screen through a point pair transformation matrix.

9. A device for processing images of a display screen including a circuit area, characterized in that: include: Processor, memory, input-output unit, and bus; The processor is connected to the memory, the input and output unit, and the bus; The memory stores a program, and the processor calls the program to execute the processing method according to any one of claims 1 to 6.

10. A computer-readable storage medium having a program stored thereon, wherein the program, when executed on a computer, performs the processing method according to any one of claims 1 to 6.

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