Semiconductor structure preparation method and semiconductor structure

Abstract

The disclosed embodiment provides a method for preparing a semiconductor and a semiconductor structure, wherein the method comprises: forming a groove structure on a first surface of a substrate; forming a first barrier layer and a first passivation layer in sequence, wherein the first barrier layer covers the sidewall and bottom of the groove structure, and the first passivation layer covers the portion of the first barrier layer located at the bottom of the groove structure; defining the surface of the first barrier layer in contact with the bottom of the groove as a preset surface. Forming a buried power rail in the groove structure; forming a through-hole structure on a second surface of the substrate, wherein the through-hole structure exposes a preset surface of the first barrier layer; wherein the first surface and the second surface are two surfaces of the substrate arranged opposite to each other. Forming a second passivation layer, wherein the second passivation layer is located at the bottom of the through-hole structure and covers at least a portion of the preset surface; filling a second conductive material in the through-hole structure to form a conductive structure; and performing a heat treatment process to form a target interface between the conductive structure and the buried power rail.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the continuous advancement of science and technology in recent years, the performance and preparation process of semiconductor structures have been greatly developed. In order to meet the normal use of semiconductor structures, a power supply structure is usually set in the semiconductor structure. It is understandable that the structural settings contained therein will have a certain impact on the performance of the semiconductor structure.

[0003] However, in conventional technologies, there are still many problems in the preparation method of semiconductor structures that need to be improved. Summary of the invention

[0004] The present disclosure provides a method for preparing a semiconductor structure, the method comprising:

[0005] Providing a substrate; forming a groove structure on a first surface of the substrate;

[0006] forming a first barrier layer and a first passivation layer in sequence, wherein the first barrier layer covers the sidewall and the bottom of the groove structure, and the first passivation layer covers the portion of the first barrier layer located at the bottom of the groove structure; wherein a surface of the first barrier layer in contact with the bottom of the groove is defined as a preset surface;

[0007] filling a first conductive material in the groove structure to form a buried power rail;

[0008] Forming a through-hole structure on the second surface of the substrate, wherein the through-hole structure exposes a predetermined surface of the first barrier layer; wherein the first surface and the second surface are two surfaces of the substrate arranged opposite to each other;

[0009] forming a second passivation layer, wherein the second passivation layer is located at the bottom of the through-hole structure and covers at least a portion of the predetermined surface;

[0010] Filling a second conductive material in the through-hole structure to form a conductive structure;

[0011] A thermal treatment process is performed to form a target interface between the conductive structure and the buried power rail.

[0012] In some embodiments, providing the substrate comprises:

[0013] providing a substrate;

[0014] forming an etch stop layer on the substrate;

[0015] A semiconductor layer is formed on the etch stop layer.

[0016] In some embodiments, forming the groove structure on the first surface of the substrate includes:

[0017] forming a first dielectric layer on the substrate, wherein the first dielectric layer covers a surface of the substrate;

[0018] Performing an etching process on the first dielectric layer and the substrate to form the groove structure on the substrate;

[0019] After filling the first conductive material in the groove structure to form the buried power rail, the preparation method further includes:

[0020] A device structure and a metal layer on the device structure are formed.

[0021] In some embodiments, before forming the through-hole structure on the second surface of the substrate, the preparation method further includes:

[0022] Performing a thinning process on the second surface of the substrate to expose the etch stop layer;

[0023] removing the etch stop layer to expose the surface of the semiconductor layer;

[0024] A second dielectric layer is formed on the semiconductor layer.

[0025] In some embodiments, forming the through-hole structure on the second surface of the substrate, wherein the through-hole structure exposes the predetermined surface of the first barrier layer, comprises:

[0026] An etching process is performed on the second dielectric layer and the semiconductor layer to form the through-hole structure on the second surface of the substrate, wherein the through-hole structure exposes the predetermined surface of the first barrier layer.

[0027] In some embodiments, before forming the second passivation layer, the preparation method further includes:

[0028] forming an insulating layer, wherein the insulating layer covers the sidewall and the bottom of the through-hole structure;

[0029] removing a portion of the insulating layer located at the bottom of the through-hole structure;

[0030] A second barrier layer is formed, wherein the second barrier layer covers the sidewalls of the through-hole structure and covers at least a portion of the predetermined surface of the first barrier layer.

[0031] In some embodiments, the first conductive material and the second conductive material include conductive metals.

[0032] In some embodiments, the first passivation layer and the second passivation layer include at least one of palladium, gold, nickel, or a high entropy alloy.

[0033] The present disclosure also provides a semiconductor structure, the semiconductor structure comprising:

[0034] substrate;

[0035] a buried power rail on the first surface of the substrate;

[0036] a first passivation layer, the first passivation layer being located at a bottom of the buried power rail;

[0037] A first barrier layer, the first barrier layer surrounds the sidewalls of the buried power rail and surrounds the sidewalls and the bottom of the first passivation layer; wherein the first barrier layer comprises a predetermined surface, and a surface of the first barrier layer in contact with the bottom of the first passivation layer is arranged opposite to the predetermined surface along a direction perpendicular to the first surface;

[0038] a second passivation layer, the second passivation layer being located on the second surface of the substrate and covering at least a portion of the predetermined surface of the first barrier layer;

[0039] A conductive structure is located on the second surface and on the second passivation layer; wherein a target interface is formed between the conductive structure and the buried power rail.

[0040] In some embodiments, the semiconductor structure further comprises:

[0041] A second barrier layer, wherein the second barrier layer covers the sidewalls of the conductive structure and the sidewalls of the second passivation layer and at least a portion of the preset surface.

[0042] In some embodiments, the buried power rail and the conductive structure are made of the same material.

[0043] The present disclosure provides a method for preparing a semiconductor structure and a semiconductor structure, wherein the preparation method comprises: providing a substrate; forming a groove structure on a first surface of the substrate; forming a first barrier layer and a first passivation layer in sequence, wherein the first barrier layer covers the sidewall and the bottom of the groove structure, and the first passivation layer covers the portion of the first barrier layer located at the bottom of the groove structure; wherein the surface of the first barrier layer in contact with the bottom of the groove is defined as a preset surface; filling a first conductive material in the groove structure to form a buried power rail; forming a through-hole structure on the second surface of the substrate, wherein the through-hole structure exposes a preset surface of the first barrier layer; wherein the first surface and the second surface are two surfaces of the substrate arranged opposite to each other; forming a second passivation layer, wherein the second passivation layer is located at the bottom of the through-hole structure and covers at least a portion of the preset surface; filling a second conductive material in the through-hole structure to form a conductive structure; and performing a heat treatment process to form a target interface between the conductive structure and the buried power rail. It can be understood that in the preparation process of the buried power rail, in order to prevent the conductive metal from diffusing into the surrounding materials, a barrier layer is usually deposited at the interface between the conductive material and the surrounding materials. The barrier layer will be formed at the side wall and the bottom of the conductive material at the same time. If a conductive structure electrically connected to it is further formed on the basis of this structure, the barrier layer material will inevitably exist at the interface where the conductive structure contacts the buried power rail. Since the material of the barrier layer is different from the material contained in the buried power rail and the conductive structure, there will be a large thermal resistance and resistance at the interface where the buried power rail and the conductive structure contact, which is easy to increase the problem of power loss and heat dissipation. In the embodiment of the present disclosure, a passivation layer is formed on both sides of the first barrier layer at the interface where the buried power rail contacts the conductive structure. The formation of the passivation layer is conducive to the diffusion of the metal material contained in the buried power rail and the conductive structure to the interface where the two contact to form a target interface with low thermal resistance and resistance. In this way, the thermal resistance and resistance at the above interface can be effectively reduced, thereby significantly reducing power loss and heat generation.

[0044] Details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the specification and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1A flowchart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0047] Figure 2 One of the process flow charts of the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0048] Figure 3 A second process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0049] Figure 4 A third process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0050] Figure 5 A fourth process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0051] Figure 6 A fifth process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0052] Figure 7 A sixth process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0053] Figure 8 A seventh process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0054] Fig. 9 The eighth process flow chart of the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0055] Fig.10 A ninth process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0056] Fig.11 A tenth process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0057] Fig.12 The eleventh process flow chart of the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0058] Fig.13 The twelfth process flow chart of the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0059] Fig.14 The thirteenth process flow chart of the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0060] Fig.15 The fourteenth process flow chart of the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0061] Fig.16 for Fig.11 An enlarged schematic diagram of the Q region in FIG.

[0062] Fig.17 A local enlarged view of a semiconductor structure provided by an embodiment of the present disclosure;

[0063] Fig.18 A schematic diagram of the structure of the target interface provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0065] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0066] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0067] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0068] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0069] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0070] With the continuous advancement of science and technology in recent years, the performance and preparation process of semiconductor structures have been greatly developed. In order to meet the use requirements of semiconductor structures, a power supply structure network is usually provided on the substrate of the semiconductor structure.

[0071] However, when the power supply structure and the device structure are both arranged on the front side of the substrate, there is usually a problem of signal crosstalk and difficulty in shortening the process node.

[0072] Based on this, the following technical solutions of the embodiments of the present disclosure are proposed:

[0073] The present disclosure provides a method for preparing a semiconductor structure. Figure 1 As shown, the preparation method includes the following steps:

[0074] Step S101: providing a substrate; forming a groove structure on a first surface of the substrate;

[0075] Step S102: forming a first barrier layer and a first passivation layer in sequence, wherein the first barrier layer covers the sidewall and the bottom of the groove structure, and the first passivation layer covers the portion of the first barrier layer located at the bottom of the groove structure; wherein a surface of the first barrier layer in contact with the bottom of the groove is defined as a preset surface;

[0076] Step S103: filling the groove structure with a first conductive material to form a buried power rail;

[0077] Step S104: forming a through-hole structure on the second surface of the substrate, wherein the through-hole structure exposes a preset surface of the first barrier layer; wherein the first surface and the second surface are two surfaces of the substrate arranged opposite to each other;

[0078] Step S105: forming a second passivation layer, wherein the second passivation layer is located at the bottom of the through-hole structure and covers at least a portion of the preset surface;

[0079] Step S106: filling a second conductive material in the through-hole structure to form a conductive structure;

[0080] Step S107: performing a thermal treatment process to form a target interface between the conductive structure and the buried power rail.

[0081] It can be understood that in the preparation process of the buried power rail, in order to prevent the conductive metal from diffusing into the surrounding materials, a barrier layer is usually deposited at the interface between the conductive material and the surrounding materials. The barrier layer will be formed at the side wall and the bottom of the conductive material at the same time. If a conductive structure electrically connected to it is further formed on the basis of this structure, the barrier layer material will inevitably exist at the interface where the conductive structure contacts the buried power rail. Since the material of the barrier layer is different from the material contained in the buried power rail and the conductive structure, there will be a large thermal resistance and resistance at the interface where the buried power rail and the conductive structure contact, which is easy to increase the problem of power loss and heat dissipation. In the embodiment of the present disclosure, a passivation layer is formed on both sides of the first barrier layer at the interface where the buried power rail contacts the conductive structure. The formation of the passivation layer is conducive to the diffusion of the metal material contained in the buried power rail and the conductive structure to the interface where the two contact to form a target interface with low thermal resistance and resistance. In this way, the thermal resistance and resistance at the above interface can be effectively reduced, thereby significantly reducing power loss and heat generation.

[0082] It should be understood that although Figure 1 The steps in the process are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 1At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0083] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the convenience of explanation, the schematic diagram will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present disclosure.

[0084] Figures 2 to 15 A process flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure; Fig.16 for Fig.11 An enlarged schematic diagram of the Q region in FIG. Fig.17 A local enlarged view of a semiconductor structure provided by an embodiment of the present disclosure; Fig.18 A schematic diagram of the structure of the target interface provided by the embodiment of the present disclosure.

[0085] The method for preparing the semiconductor structure provided by the embodiment of the present disclosure is further described in detail below with reference to the accompanying drawings.

[0086] First, execute step S101, such as Figure 2 , Figure 3 and Figure 4 As shown, a substrate 10 is provided; a groove structure T is formed on a first surface S1 of the substrate 10 , and the groove structure T extends along a first direction, and the first direction is parallel to the first surface S1 of the substrate 10 .

[0087] In some embodiments, Figure 2 and Figure 3 As shown, providing a substrate 10 includes:

[0088] Providing a substrate 101;

[0089] forming an etch stop layer 102 on the substrate 101;

[0090] A semiconductor layer 103 is formed on the etch stop layer 102 .

[0091] Here, the substrate 101 may be a semiconductor material; specifically, it may include a single-element semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), or a III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon material. In some embodiments, the substrate 101 may include a wafer.

[0092] In some embodiments, the material of the etch stop layer 102 may include any suitable material that can achieve an etch stop function during the thinning operation of the substrate 10 , including but not limited to a silicon germanium layer.

[0093] In some embodiments, the semiconductor layer 103 may include, but is not limited to, at least one of silicon, germanium, etc., or a combination thereof.

[0094] In some embodiments, the first surface S1 of the substrate 10 may be the front side of the substrate 10, but is not limited thereto. In some other embodiments, the first surface S1 of the substrate 10 may also be the back side of the substrate. This is not specifically limited and can be flexibly selected according to actual conditions.

[0095] In some embodiments, forming a groove structure T on the first surface S1 of the substrate 10 includes:

[0096] A first dielectric layer L1 is formed on the substrate 10, and the first dielectric layer L1 covers the surface of the substrate 10;

[0097] An etching process is performed on the first dielectric layer L1 and the substrate 10 to form a groove structure T on the substrate 10 .

[0098] Here, the material of the first dielectric layer L1 may include but is not limited to insulating materials such as oxide, nitride or oxynitride. In some specific embodiments, the material of the first dielectric layer L1 may include but is not limited to silicon oxide (SiO x )wait.

[0099] Next, execute step S102, such as Figure 5 and Figure 6 As shown, a first barrier layer 111 and a first passivation layer 121 are formed in sequence, the first barrier layer 111 covers the sidewall and the bottom of the groove structure T, and the first passivation layer 121 covers the portion of the first barrier layer 111 located at the bottom of the groove structure T; wherein the surface where the first barrier layer 111 contacts the groove bottom T is defined as a preset surface S3.

[0100] In the embodiment of the present disclosure, the formation of the first barrier layer 111 can effectively prevent the formation of the buried power rail 13 in the subsequent step S103 (for details, please refer to the attached Figure 7 ) diffuses into the surrounding material layer, so as to help maintain the normal performance of the conductive function of the buried power rail 13.

[0101] Here, the first barrier layer 111 may include any suitable anti-diffusion barrier layer, for example, including but not limited to a TaN / Ti / TiN composite layer, a Ti / TiN composite layer or a Ta / TaN composite layer, a Ti / TiN / Al composite layer, etc.

[0102] In some embodiments, the first passivation layer 121 is a metal passivation layer including at least one of palladium (Pd), gold (Au), and nickel, or at least one of a binary alloy, a ternary alloy, a quaternary alloy, or a high entropy alloy.

[0103] Here, the high entropy alloy may include an alloy composed of any five of the elements Al, Cr, Ti, Gd, Zr, Fe, Mn, Ni, Co, Ag, Cu, Nb, Ta, Mo, Sc, Sn, Ga, and Bi.

[0104] In some embodiments, when the first passivation layer 121 includes a binary alloy, a ternary alloy, or a quaternary alloy, the alloy material may include a binary alloy, a ternary alloy, or a quaternary alloy of any suitable element composition.

[0105] It is understandable that when these binary alloys, ternary alloys, and quaternary alloys correspond to any two, three, or four of the elements used to form a high entropy alloy, the obtained first passivation layer 121 can have better performance. Specifically, it can be flexibly selected according to actual conditions, and no specific limitation is made here.

[0106] It can be understood that the formation of the first passivation layer 121 helps the conductive metal material filled in the buried power rail 13 in the subsequent step S103 to diffuse toward the bottom of the trench T, so that in the final semiconductor structure, the buried power rail 13 and the conductive structure 14 formed in step S106 (for details, please refer to the attached Fig.15 ) forms a target interface B with smaller thermal resistance and electrical resistance on the interface in contact with each other (please refer to the attached Fig.18 ) provide good prerequisites.

[0107] In addition, the formation of the first passivation layer 121 is beneficial to reducing the temperature of heat treatment during the formation of the target interface B, so that the desired conductive metal diffusion result can be obtained under lower temperature annealing conditions, which is beneficial to saving production costs and improving production efficiency.

[0108] Next, execute step S103, as Figure 7 As shown, a first conductive material is filled in the groove structure T to form a buried power rail 13 .

[0109] In some embodiments, the first conductive material used to form the buried power rail 13 may be a conductive metal material, specifically, may include but is not limited to metal materials, such as one or more of Cu, Co, W, Ni and Ru. By selecting these materials, the resistivity of the buried power rail 13 is low, which is beneficial to improve RC delay, improve chip processing speed and power supply efficiency.

[0110] In some specific embodiments, the material of the buried power rail 13 may be conductive metal tungsten (W).

[0111] In some embodiments, Figure 8 As shown, after the first conductive material is filled in the groove structure T to form the buried power rail 13, the preparation method further includes:

[0112] A device structure 15 and a metal layer 16 located on the device structure 15 are formed.

[0113] In some embodiments, the device structure 15 may include, but is not limited to, a transistor and the like.

[0114] In some embodiments, during or after forming the device structure 15, a process of forming a third dielectric layer L3 between the device structures 15 may be further performed to achieve electrical insulation between adjacent device structures 15. The material of the third dielectric layer L3 may be the same as or different from the material of the first dielectric layer L1, and may be flexibly selected according to actual conditions, and is not specifically limited herein.

[0115] In some embodiments, the material of the metal layer 16 may include: a conductive metal, such as tungsten.

[0116] Then, step S104 is performed, as shown in FIG. Fig.11 and Fig.16 As shown, a through hole structure H is formed on the second surface S2 of the substrate 10 , and the through hole structure H exposes a predetermined surface S3 of the first barrier layer 111 ; wherein the first surface S1 and the second surface S2 are two surfaces of the substrate 10 arranged opposite to each other.

[0117] In some embodiments, the second surface S2 of the substrate 10 may be the back side of the substrate 10, but is not limited thereto. In some other embodiments, the second surface S2 of the substrate 10 may also be the front side of the substrate 10. This is not specifically limited and can be flexibly selected according to actual conditions.

[0118] It should be noted that in the embodiment of the present disclosure, the first surface S1 and the second surface S2 are two surfaces arranged opposite to each other. For example, when the first surface S1 is the front side, the second surface S2 may be the back side. Conversely, when the first surface S1 is the back side, the second surface S2 may be the front side.

[0119] In some specific embodiments, the first surface S1 of the substrate 10 may be the front side of the substrate 10 , and the second surface S2 of the substrate 10 may be the back side of the substrate 10 .

[0120] In some embodiments, Fig. 9 and Fig.10 As shown, before forming the through hole structure H on the second surface S2 of the substrate 10, the preparation method further includes:

[0121] Performing a thinning process on the second surface S2 of the substrate 10 to expose the etch stop layer 102;

[0122] removing the etching stop layer 102 to expose the surface of the semiconductor layer 102;

[0123] A second dielectric layer L2 is formed on the semiconductor layer 103 .

[0124] In some embodiments, Fig. 9 As shown, before the substrate 10 is thinned from the second surface S2 to expose the etching stop layer 102, the preparation method further includes:

[0125] The substrate 10 is bonded to a carrier 20 on one side where the device structure 12 is provided;

[0126] The semiconductor structure is flipped 180° so that the second surface S2 of the substrate 10 faces upward.

[0127] In some embodiments, a dielectric layer (not shown) may be formed between the side of the substrate 10 provided with the device structure 12 and the carrier 20. Examples of the dielectric layer (not shown) include, but are not limited to, silicon carbonnitride (SiCN), silicon oxide, silicon nitride, etc. The formation of the dielectric layer (not shown) facilitates the bonding between the substrate 10 and the carrier 20.

[0128] Here, before the semiconductor structure is flipped, an operation process is performed to bond the side of the substrate 10 on which the device structure 12 is provided to the carrier 20. This is to ensure that during the subsequent process steps, the carrier 20 can play an effective supporting role and protect the structure located on the first surface S1 of the substrate 10 from being scratched or damaged.

[0129] In some embodiments, the carrier 20 may be a waste wafer, or may be a glass substrate, a semiconductor substrate, a ceramic substrate or other suitable material.

[0130] Continue to refer Fig.11 and Fig.16 In some embodiments, a through hole structure H is formed on the second surface S2 of the substrate 10, wherein the through hole structure H exposes a predetermined surface S3 of the first barrier layer 111, including:

[0131] An etching process is performed on the second dielectric layer L2 and the semiconductor layer 103 to form a through-hole structure H on the second surface S2 of the substrate 10 . The through-hole structure H exposes a predetermined surface S3 of the first barrier layer 111 .

[0132] In some embodiments, the material of the second dielectric layer L2 may be the same as the material of the first dielectric layer L1 and the third dielectric layer L3, but is not limited thereto. The material may also be different from the material of the first dielectric layer L1 and the third dielectric layer L3. The material may be flexibly selected and is not specifically limited here.

[0133] Next, execute step S105, such as Fig.14 and Fig.17 As shown, a second passivation layer 122 is formed, and the second passivation layer 122 is located at the bottom of the through-hole structure H and covers at least a portion of the preset surface S3.

[0134] In some embodiments, the second passivation layer 122 is a metal passivation layer including at least one of palladium (Pd), gold (Au), and nickel, or at least one of a binary alloy, a ternary alloy, a quaternary alloy, or a high entropy alloy.

[0135] Here, the high entropy alloy may include an alloy composed of any five of the elements Al, Cr, Ti, Gd, Zr, Fe, Mn, Ni, Co, Ag, Cu, Nb, Ta, Mo, Sc, Sn, Ga, and Bi.

[0136] In some embodiments, when the second passivation layer 122 comprises a binary alloy, a ternary alloy, or a quaternary alloy, the alloy material may comprise a binary alloy, a ternary alloy, or a quaternary alloy of any suitable element composition.

[0137] It is understandable that when these binary alloys, ternary alloys, and quaternary alloys correspond to any two, three, or four of the elements used to form a high entropy alloy, the obtained first passivation layer 121 and the second passivation layer 122 can have better performance. Specifically, it can be flexibly selected according to actual conditions, and no specific limitation is made here.

[0138] The formation of the second passivation layer 122 is beneficial to reducing the temperature of heat treatment during the formation of the target interface B, so that the desired conductive metal diffusion result can be obtained under a relatively low temperature annealing condition, which is beneficial to saving production costs and improving production efficiency.

[0139] In some embodiments, the first passivation layer 121 and the second passivation layer 122 may be formed by a physical vapor deposition process, but is not limited thereto and may also be formed by any other suitable process.

[0140] In some embodiments, Fig.12 , Fig.13 and Fig.17 As shown, before forming the second passivation layer 122, the preparation method further includes:

[0141] An insulating layer 17 is formed, and the insulating layer 17 covers the sidewall and bottom of the through hole structure H (for details, please refer to the attached Fig.12 );

[0142] Remove the portion of the insulating layer 17 located at the bottom of the through-hole structure H (see the attached Fig.13 );

[0143] A second barrier layer 112 is formed, and the second barrier layer 112 covers the sidewall of the through hole structure H and covers at least a portion of the preset surface S3 of the first barrier layer 111 (for details, please refer to the attached Fig.13 And attached Fig.17 ).

[0144] Here, at least a portion of the predetermined surface S3 covered by the second barrier layer 112 may be understood as a portion of the predetermined surface S3 that is exposed after the portion of the insulating layer 17 located at the bottom of the through-hole structure H is removed.

[0145] In some embodiments, the material of the insulating layer 17 may be the same as or different from the material of the second dielectric layer L2, which is not specifically limited herein and can be flexibly selected according to actual conditions. In some specific embodiments, the material of the insulating layer 17 may be an oxide, such as silicon oxide (SiOx).

[0146] In actual operation, the insulating layer 17 at the bottom of the through-hole structure H can be removed by slow sputtering etching.

[0147] However, in other aspects, since the first barrier layer 111 and the second barrier layer 112 are located on the side walls of the buried power rail 13 and the subsequently formed conductive structure 14, they are structures that exist to prevent the conductive material from diffusing into the surrounding materials. At the same time, in the direction perpendicular to the plane of the substrate 10, the structural parts of the first barrier layer 111 and the second barrier layer 112 located between the first passivation layer 111 and the second passivation layer 112 are difficult to remove by appropriate processes and methods, so that at the interface between the buried power rail 13 and the subsequently formed conductive structure, even if the materials of the two are the same, due to the existence of the first barrier layer 111 and the second barrier layer 112 composed of different materials, it is easy to have a situation where both thermal resistance and electrical resistance are large at the above-mentioned interface, resulting in large power loss and poor heat dissipation.

[0148] Based on this, in the embodiment of the present disclosure, a sandwich structure of the first passivation layer 121, the first barrier layer 111 plus the second barrier layer 112, and the second passivation layer 122 is designed to be formed in a direction perpendicular to the plane of the substrate 10, which is conducive to the diffusion part A1 (for details, please refer to the attached Fig.18 ) can smoothly reach the position where the barrier layer is located, so that a certain amount of diffusion part A1 material can be gathered at this position, so that the obtained target interface B can have a smaller thermal resistance and a smaller electrical resistance. In this way, the loss of electrical signals can be reduced, and the power supply capacity of the back power supply structure can be enhanced. At the same time, the interface has a low thermal resistance, which will effectively reduce the generation of heat and improve the heat dissipation capacity.

[0149] In addition, in the embodiments of the present disclosure, the formation of the first passivation layer 121, the first barrier layer 111 plus the second barrier layer 112, and the second passivation layer 122 are compatible with the current fab process flow, have a simple structure, and have strong matching versatility, and do not increase the complexity of the process.

[0150] In some embodiments, the material of the second barrier layer 112 may be the same as or different from the material of the first barrier layer 111. In some specific embodiments, the material of the second barrier layer 112 may also include any suitable anti-diffusion barrier layer, such as but not limited to TaN / Ti / TiN composite layer, Ti / TiN composite layer or Ta / TaN composite layer, Ti / TiN / Al composite layer, etc.

[0151] Here, the formation of the second barrier layer 112 can effectively prevent the formation of the conductive structure 14 in the subsequent step S106 (for details, please refer to the attached Fig.15 ) diffuses into the surrounding material layer to facilitate maintaining the conductive structure 14 (for details, please refer to the attached Fig.15)’s conductive function can be performed normally.

[0152] Continue to refer Fig.17 In some embodiments, the thickness L01 of the barrier layer obtained by adding the thickness of the first barrier layer 111 at the bottom of the trench structure T to the thickness of the second barrier layer 112 at the bottom of the through-hole structure may be less than the thickness L02 of the first passivation layer 121. Meanwhile, the thickness L01 of the first barrier layer 111 at the bottom of the trench structure T plus the thickness L01 of the second barrier layer 112 at the bottom of the trench may be less than the thickness L03 of the second passivation layer 122.

[0153] In this way, in the embodiment of the present disclosure, the thickness L01 of the barrier layer (the sum of the thickness of the first barrier layer 111 at the bottom of the trench structure T and the thickness of the second barrier layer 112 at the bottom of the through-hole structure) is set to be less than the thickness of the passivation layer (the first passivation layer 121 or the second passivation layer 122), which is conducive to the diffusion part A1 in the conductive metal material contained in the buried power rail 13 and the conductive structure 14 to reach the position where the barrier layer is located more smoothly after the step S107 is completed, so that more diffusion part A1 materials can be gathered at this position, so that the obtained target interface B can have a smaller thermal resistance and a smaller resistance. Therefore, the loss of electrical signals can be further reduced, and the power supply capacity of the back power supply structure can be enhanced. At the same time, this interface has a low thermal resistance, which will effectively reduce the generation of heat and improve the heat dissipation capacity.

[0154] In some embodiments, the ratio of L01 to L02 ranges from 0.05 to 0.8, for example, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, etc. The ratio of L01 to L03 ranges from 0.05 to 0.8, for example, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, etc.

[0155] Then, step S106 is performed, as shown in FIG. Fig.15 As shown, a second conductive material is filled in the through-hole structure H to form a conductive structure 14 .

[0156] Here, the conductive structure 14 may be a through silicon via (TSV) structure.

[0157] In some embodiments, the second conductive material used to form the conductive structure 14 may be a conductive metal material, specifically, may include but is not limited to metal materials, such as one or more of Cu, Co, W, Ni and Ru.

[0158] In some specific embodiments, the material of the conductive structure 14 may be conductive metal tungsten (W).

[0159] In the embodiment of the present disclosure, the material used for the buried power rail 13 may be the same as or different from the material used for the conductive structure 14 .

[0160] It can be understood that when the material used for the buried power rail 13 is the same as that used for the conductive structure 14, it can further help to lower the thermal resistance and electrical resistance at the target interface B, further helping to reduce power loss and heat generation of the semiconductor structure.

[0161] In the embodiment of the present disclosure, the buried power rail 13 and the conductive structure 18 can be used together as a back power supply structure to supply power to the power-using structures (including but not limited to) in the semiconductor structure. Figure 8 The transistor structure shown in the figure, etc.) is conducive to the realization of back side power supply technology.

[0162] In conventional structures, transistors and power supply structures are usually placed on the same surface of the substrate. Due to the close distance between these structures, crosstalk and other problems often occur. In addition, this layout method will also lead to wiring congestion in the back-end process, increase power loss, and restrict the further shortening of process nodes.

[0163] In the disclosed embodiment, the layout method of placing the transistor and the power supply structure on different surfaces of the substrate directly transfers the transistor structure and the power supply structure originally located on the same surface of the substrate to the back of the transistor for rearrangement, which is conducive to increasing the density of transistors per unit area while avoiding signal interference between transistors and the power supply network, reducing wiring congestion at the back end of the line, providing power supply performance advantages, and enhancing chip reliability. At the same time, it helps to further shorten the process node.

[0164] Finally, step S107 is executed. Fig.18 As shown, a thermal treatment process is performed to form a target interface B between the conductive layer 14 and the buried power rail 13 .

[0165] In this way, in the embodiment of the present disclosure, a sandwich structure consisting of the first passivation layer 121, the first barrier layer 111 plus the second barrier layer 112, and the second passivation layer 122 can be formed on the cross section between the buried power rail 13 and the conductive structure 14, which is conducive to the diffusion part A1 in the conductive metal material contained in the buried power rail 13 and the conductive structure 14 to smoothly reach the position where the barrier layer is located after the heat treatment process, so that a certain amount of diffusion part A1 material can be gathered at this position, so that the obtained target interface B can have a smaller thermal resistance and a smaller resistance. Thereby, the loss of electrical signals is reduced and the power supply capacity of the back power supply structure is enhanced. At the same time, this interface has a low thermal resistance, which will effectively reduce the generation of heat and improve the heat dissipation capacity.

[0166] In some embodiments, the temperature range of the heat treatment process can be between room temperature and 400°C (including endpoint values), for example, 25°C, 50°C, 80°C, 100°C, 120°C, 150°C, 180°C, 200°C, 220°C, 250°C, 280°C, 300°C, 320°C, 350°C, 380°C, 400°C, etc.

[0167] It should be noted that in the attached Fig.18 In the figure, the position, number, area size, etc. of the diffusion part A1 and the gap A0 part left after the diffusion part A1 leaves the buried power rail 13 or the conductive structure 14 are only for exemplary description and are not the only limitation for the application scenarios of the present disclosure.

[0168] In actual operation, these contents can be changed with the setting of the heat treatment method or other setting methods of parameters that may cause influence, and can be flexibly set according to actual needs, and are not specifically limited here. Generally, after the diffusion part A1 reaches the target interface B, the number and distribution of the gaps A0 generated in the buried power rail 13 and the conductive structure 14 will not affect the original performance of the two.

[0169] The present disclosure also provides a semiconductor structure, such as Fig.15 , Fig.17 and Fig.18 As shown, the semiconductor structure includes:

[0170] Substrate 10;

[0171] a buried power rail 13 located on the first surface S1 of the substrate 10;

[0172] A first passivation layer 121, the first passivation layer 121 is located at the bottom of the buried power rail 13;

[0173] A first barrier layer 111, the first barrier layer 111 surrounds the sidewalls of the buried power rail 13, and surrounds the sidewalls and the bottom of the first passivation layer 121; wherein the first barrier layer 111 includes a predetermined surface S3, and along a direction perpendicular to the first surface S1, a surface of the first barrier layer 111 in contact with the bottom of the first passivation layer 121 is arranged opposite to the predetermined surface S3;

[0174] A second passivation layer 122, the second passivation layer 122 is located on the second surface S2 of the substrate 10 and covers at least a portion of the predetermined surface S3 of the first barrier layer 111;

[0175] The conductive structure 14 is located on the second surface S2 and on the second passivation layer 122 ; wherein a target interface B is formed between the conductive structure 14 and the buried power rail 13 .

[0176] In the embodiment of the present disclosure, the first surface S1 and the second surface S2 are two surfaces arranged opposite to each other. For example, when the first surface S1 is the front side, the second surface S2 may be the back side. Conversely, when the first surface S1 is the back side, the second surface S2 may be the front side.

[0177] In some specific embodiments, the first surface S1 of the substrate 10 may be the front side of the substrate 10 , and the second surface S2 of the substrate 10 may be the back side of the substrate 10 .

[0178] In some embodiments, the material used to form the conductive structure 14 and the material used to form the buried power rail 13 may include, but are not limited to, conductive metal materials, such as one or more of Cu, Co, W, Ni, and Ru.

[0179] In some specific embodiments, the materials of the conductive structure 14 and the buried power rail 13 may both be conductive metal tungsten (W).

[0180] In the embodiment of the present disclosure, the material used for the buried power rail 13 may be the same as or different from the material used for the conductive structure 14 .

[0181] In some embodiments, the first passivation layer 121 and the second passivation layer 122 may be metal passivation layers including at least one of palladium (Pd), gold (Au), and nickel, or may be at least one of a binary alloy, a ternary alloy, a quaternary alloy, or a high entropy alloy.

[0182] Here, the high entropy alloy may include an alloy composed of any five of the elements Al, Cr, Ti, Gd, Zr, Fe, Mn, Ni, Co, Ag, Cu, Nb, Ta, Mo, Sc, Sn, Ga, and Bi.

[0183] In some embodiments, when the first passivation layer 121 and the second passivation layer 122 include a binary alloy, a ternary alloy, or a quaternary alloy, the alloy material may include a binary alloy, a ternary alloy, or a quaternary alloy of any suitable element composition.

[0184] It is understandable that when these binary alloys, ternary alloys, and quaternary alloys correspond to any two, three, or four of the elements used to form a high entropy alloy, the obtained first passivation layer 121 and the second passivation layer 122 can have better performance. Specifically, it can be flexibly selected according to actual conditions, and no specific limitation is made here.

[0185] The formation of the first passivation layer 121 and the second passivation layer 122 is beneficial to reducing the temperature of heat treatment during the formation of the target interface B, so that the desired conductive metal diffusion result can be obtained under lower temperature annealing conditions, which is beneficial to saving production costs and improving production efficiency.

[0186] In some embodiments, the semiconductor structure further comprises:

[0187] The second barrier layer 112 covers the sidewalls of the conductive structure 14 and the sidewalls of the second passivation layer 122 and at least a portion of the preset surface S3 .

[0188] In some embodiments, the material of the second barrier layer 112 may be the same as or different from the material of the first barrier layer 111. In some specific embodiments, the materials of both may include any suitable anti-diffusion barrier layer, such as but not limited to TaN / Ti / TiN composite layer, Ti / TiN composite layer or Ta / TaN composite layer, Ti / TiN / Al composite layer, etc.

[0189] In some embodiments, the buried power rail 13 and the conductive structure 14 are made of the same material.

[0190] It can be understood that when the material used for the buried power rail 13 is the same as that used for the conductive structure 14, it can further help to lower the thermal resistance and electrical resistance at the target interface B, further helping to reduce power loss and heat generation of the semiconductor structure.

[0191] In some embodiments, the semiconductor structure further includes a device structure 15 located on the first surface S1 and above the buried power rail 13 , and a metal layer 16 located on the device structure 15 .

[0192] In some embodiments, the device structure 15 may include, but is not limited to, a transistor and the like.

[0193] In the embodiment of the present disclosure, the buried power rail 13 and the conductive structure 14 can be used as part of the back power supply structure, which is helpful to be used together with other subsequently formed structures, such as the conductive structure 18, for the power-using structures in the semiconductor structure (including but not limited to Figure 8 The transistor structure shown in the figure, etc.) is conducive to the realization of back side power supply technology.

[0194] In conventional structures, transistors and power supply structures are usually placed on the same surface of the substrate. Due to the close distance between these structures, crosstalk and other problems often occur. In addition, this layout method will also lead to wiring congestion in the back-end process, increase power loss, and restrict the further shortening of process nodes.

[0195] In the disclosed embodiment, the layout method of placing the transistor and the power supply structure on different surfaces of the substrate directly transfers the transistor structure and the power supply structure originally located on the same surface of the substrate to the back of the transistor for rearrangement, which is conducive to increasing the density of transistors per unit area while avoiding signal interference between transistors and the power supply network, reducing wiring congestion at the back end of the line, providing power supply performance advantages, and enhancing chip reliability. At the same time, it helps to further shorten the process node.

[0196] In addition, in the embodiments of the present disclosure, the formation of the first passivation layer 121, the first barrier layer 111 plus the second barrier layer 112, and the second passivation layer 122 are compatible with the current fab process flow, have a simple structure, and have strong matching versatility, and do not increase the complexity of the process.

[0197] Continue to refer Fig.17 In some embodiments, the thickness L01 of the barrier layer obtained by adding the thickness of the first barrier layer 111 at the bottom of the trench structure T to the thickness of the second barrier layer 112 at the bottom of the through-hole structure may be less than the thickness L02 of the first passivation layer 121. Meanwhile, the thickness L01 of the first barrier layer 111 at the bottom of the trench structure T plus the thickness L01 of the second barrier layer 112 at the bottom of the trench may be less than the thickness L03 of the second passivation layer 122.

[0198] In some embodiments, the ratio of L1 to L2 ranges from 0.05 to 0.8, for example, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, etc. The ratio of L01 to L03 ranges from 0.05 to 0.8, for example, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, etc.

[0199] It can be understood that in the embodiment of the present disclosure, a sandwich structure consisting of a first passivation layer 121, a first barrier layer 111, a second barrier layer 112, and a second passivation layer 122 is formed on the cross section between the buried power rail 13 and the conductive structure 14, which is conducive to the diffusion part A1 in the conductive metal material contained in the buried power rail 13 and the conductive structure 14 to smoothly reach the position where the barrier layer is located after the heat treatment process, so that a certain amount of diffusion part A1 material can be gathered at this position, so that the obtained target interface B can have a smaller thermal resistance and a smaller resistance. Thereby, the loss of electrical signals is reduced and the power supply capacity of the back power supply structure is enhanced. At the same time, this interface has a low thermal resistance, which will effectively reduce the generation of heat and improve the heat dissipation capacity.

[0200] It should be noted that the semiconductor structure and the method for manufacturing the same provided by the embodiments of the present disclosure can be applied to any semiconductor device including the structure, and no further limitation is given here. The embodiments of the method for manufacturing the semiconductor device provided by the present disclosure and the embodiments of the semiconductor device belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict.

[0201] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: Providing a substrate; forming a groove structure on a first surface of the substrate; forming a first barrier layer and a first passivation layer in sequence, wherein the first barrier layer covers the sidewall and the bottom of the groove structure, and the first passivation layer covers the portion of the first barrier layer located at the bottom of the groove structure; wherein a surface of the first barrier layer in contact with the bottom of the groove is defined as a preset surface; filling a first conductive material in the groove structure to form a buried power rail; Forming a through-hole structure on the second surface of the substrate, wherein the through-hole structure exposes a predetermined surface of the first barrier layer; wherein the first surface and the second surface are two surfaces of the substrate arranged opposite to each other; forming a second passivation layer, wherein the second passivation layer is located at the bottom of the through-hole structure and covers at least a portion of the predetermined surface; Filling a second conductive material in the through-hole structure to form a conductive structure; A thermal treatment process is performed to form a target interface between the conductive structure and the buried power rail.

2. The preparation method according to claim 1, characterized in that: Providing the substrate comprises: providing a substrate; forming an etch stop layer on the substrate; A semiconductor layer is formed on the etch stop layer.

3. The preparation method according to claim 2, characterized in that: The groove structure is formed on the first surface of the substrate, comprising: forming a first dielectric layer on the substrate, wherein the first dielectric layer covers a surface of the substrate; Performing an etching process on the first dielectric layer and the substrate to form the groove structure on the substrate; After filling the first conductive material in the groove structure to form the buried power rail, the preparation method further includes: A device structure and a metal layer on the device structure are formed.

4. The preparation method according to claim 2, characterized in that: Before forming the through-hole structure on the second surface of the substrate, the preparation method further includes: Performing a thinning process on the second surface of the substrate to expose the etch stop layer; removing the etch stop layer to expose the surface of the semiconductor layer; A second dielectric layer is formed on the semiconductor layer.

5. The preparation method according to claim 4, characterized in that: The through-hole structure is formed on the second surface of the substrate, wherein the through-hole structure exposes the predetermined surface of the first barrier layer, comprising: An etching process is performed on the second dielectric layer and the semiconductor layer to form the through-hole structure on the second surface of the substrate, wherein the through-hole structure exposes the predetermined surface of the first barrier layer.

6. The preparation method according to any one of claims 1 to 5, characterized in that: Before forming the second passivation layer, the preparation method further includes: forming an insulating layer, wherein the insulating layer covers the sidewall and the bottom of the through-hole structure; removing a portion of the insulating layer located at the bottom of the through-hole structure; A second barrier layer is formed, wherein the second barrier layer covers the sidewalls of the through-hole structure and covers at least a portion of the predetermined surface of the first barrier layer.

7. The preparation method according to claim 1, characterized in that: The first conductive material and the second conductive material include conductive metal.

8. The preparation method according to claim 1, characterized in that: The first passivation layer and the second passivation layer include at least one of palladium, gold, nickel or a high entropy alloy.

9. A semiconductor structure, characterized in that: The semiconductor structure comprises: substrate; a buried power rail on the first surface of the substrate; a first passivation layer, the first passivation layer being located at a bottom of the buried power rail; A first barrier layer, the first barrier layer surrounds the sidewalls of the buried power rail and surrounds the sidewalls and the bottom of the first passivation layer; wherein the first barrier layer comprises a predetermined surface, and a surface of the first barrier layer in contact with the bottom of the first passivation layer is arranged opposite to the predetermined surface along a direction perpendicular to the first surface; a second passivation layer, the second passivation layer being located on the second surface of the substrate and covering at least a portion of the predetermined surface of the first barrier layer; A conductive structure is located on the second surface and on the second passivation layer; wherein a target interface is formed between the conductive structure and the buried power rail.

10. The semiconductor structure according to claim 9, characterized in that: The semiconductor structure further comprises: A second barrier layer, wherein the second barrier layer covers the sidewalls of the conductive structure and the sidewalls of the second passivation layer and at least a portion of the preset surface.

11. The semiconductor structure according to claim 9, characterized in that: The buried power rail and the conductive structure are made of the same material.

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