Remote debugging system and method for domestic FPGA based on XVC protocol

Abstract

The invention relates to a remote debugging system and method for a domestic FPGA based on an XVC protocol, and belongs to the technical field of FPGA debugging. According to the remote debugging system and method suitable for the domestic FPGA, the remote debugging system and method suitable for the domestic FPGA are designed on the basis of an XVC (Xilinx Virtual Cable) protocol, the remote online debugging and updating problems of the FPGA are solved, and the design debugging process of the domestic FPGA is optimized.

Description

Technical Field

[0001] The invention belongs to the technical field of FPGA debugging, and in particular relates to a remote debugging system and method for a domestic FPGA based on an XVC protocol. Background Art

[0002] As domestic FPGA design technology becomes increasingly mature, FPGAs are currently widely used in fields such as weapons and equipment, aerospace, and industrial automation. However, due to limitations in scenarios, the FPGA debugging process is usually complicated after the whole machine is assembled. In most scenarios, it requires disassembly of the machine, wires, and other complex processes to complete. Summary of the invention

[0003] 1. Technical issues to be resolved

[0004] In order to solve the problems of complex FPGA debugging and even the inability to carry out debugging work in specific scenarios, the present invention designs a remote debugging system and method suitable for domestic FPGA.

[0005] (II) Technical solution

[0006] In order to solve the above technical problems, the present invention provides a design method for a remote debugging system of a domestic FPGA based on the XVC protocol, in which the FPGA is mounted on a remote debugging host through PCIe, and the corresponding XVC service software and PCIe driver are loaded on the remote debugging host; the FPGA converts the XVC protocol message through the IP core of PCIe in the following ways: ① connecting the XVC Bridge of the AXI_XVC interface type through the AXI4-Lite interface of the PCIe BAR space.

[0007] Preferably, method ① is implemented based on the XVC functional logic design of XDMA.

[0008] Preferably, the XVC functional logic is designed based on XDMA, wherein "connecting the XVC Bridge of the AXI_XVC interface type through the AXI4-Lite interface of the PCIeBAR space" is implemented through the following design, so as to realize the transmission of debugging information between the FPGA and the remote debugging host through the PCIe link: using the DebugBridge IP to connect the debugging network on the FPGA through the AXI4-Lite interface of the PCIe BAR space; then configuring a slave mode DebugBridge IP on the FPGA to realize the connection and management of the FPGA on-chip debugging resources; XDMA is a type of PCIe IP in the FPGA.

[0009] Preferably, the BSCAN resources synthesized by the debugging core in the debugging system can eventually communicate with the remote debugging host mounted with the FPGA through PCIe.

[0010] Preferably, the FPGA converts the XVC protocol message through the IP core of PCIe in the following manner: ② Connecting to the XVC Bridge of the PCIe_XVC interface type through the PCIe extended configuration interface.

[0011] The invention also provides a remote debugging system for a domestic FPGA designed based on the method.

[0012] The invention also provides an FPGA remote online debugging method implemented by utilizing the system.

[0013] The invention also provides an FPGA remote online updating method realized by utilizing the system.

[0014] The present invention also provides an application of the system in the aerospace field.

[0015] The invention also provides an application of the system in the field of industrial automation.

[0016] (III) Beneficial effects

[0017] The present invention designs a remote debugging system and method suitable for domestic FPGA based on XVC (Xilinx Virtual Cable) protocol, solves the problem of FPGA remote online debugging and updating, and optimizes the design and debugging process of domestic FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The XVC remote debugging system of the present invention is designed as a schematic diagram;

[0019] Figure 2 A schematic diagram of the XVC functional logic architecture implemented in the system design of the present invention;

[0020] Figures 3 to 6 This is a screenshot of the FPGA remote online debugging experiment of the present invention, wherein: Figure 3 , Figure 4 Set a map for the hostname, Figure 5 To configure the debug file map, Figure 6 This is the remote debugging effect diagram. DETAILED DESCRIPTION

[0021] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0022] 1. Design 1: Design of FPGA remote debugging system based on XVC protocol

[0023] In order to solve the problems of complex FPGA debugging and even the inability to carry out debugging work in specific scenarios, the present invention designs a remote debugging system and method suitable for domestic FPGAs based on the XVC (Xilinx Virtual Cable) protocol, which solves the problem of FPGA remote online debugging and updating, and optimizes the design and debugging process of domestic FPGAs.

[0024] The present invention first designs Figure 1 The FPGA remote debugging system based on the XVC protocol shown in the figure, in which the FPGA is mounted on the remote debugging host through PCIe, and the corresponding XVC service software and PCIe driver are loaded on the remote debugging host; the FPGA end can convert the XVC protocol message through the PCIe IP core in two ways: ① connect the XVC Bridge of the AXI_XVC interface type through the AXI4-Lite interface of the PCIe BAR space; ② connect the XVC Bridge of the PCIe_XVC interface type through the PCIe extended configuration interface. Limited by the FPGA model and resource support capabilities, this solution prefers the first method for design.

[0025] 1. Design 2: XVC functional logic system design based on XDMA

[0026] like Figure 2 As shown, the present invention designs XVC functional logic based on XDMA (XDMA is a type of PCIe IP in FPGA). Usually, FPGA builds a functional debugging environment through IP cores such as ILA and VIO. Such debugging cores will be integrated into JTAGBSCAN resources on the chip to perform debugging.

[0027] The present invention realizes "connecting the XVC Bridge of AXI_XVC interface type through the AXI4-Lite interface of PCIe BAR space" through the following XVC-OVER-PCIe design, so as to realize the transmission of debugging information between FPGA and remote debugging host through PCIe link: using Debug Bridge IP to connect the debugging network (debugging path) on FPGA through the AXI4-Lite interface of PCIeBAR space; then configuring a slave mode Debug Bridge IP on FPGA to realize the connection and management of FPGA on-chip debugging resources. Based on the above configuration, the BSCAN resources synthesized by the debugging core in the debugging system will eventually communicate with the remote debugging host mounted with FPGA through PCIe.

[0028] 3. Expected results

[0029] The debugging system based on the above design can realize FPGA remote online debugging and updating. The specific debugging experiment is as follows:

[0030] Start the open source XCVC Server service and mount the XDMA driver for remote debugging access. Start Vivado on the remote debugging host, open Open Hardware Manager, add XVC configuration, and set the hostname to the IP address of the host where the XVC Server is located, such as Figure 3 , Figure 4 As shown;

[0031] XVC function is enabled, and the .itx file for configuration and debugging is as follows: Figure 5 shown.

[0032] A window for capturing waveforms appears, and remote debugging is performed. The effect is as follows Figure 6 shown.

[0033] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A design method for a remote debugging system of a domestic FPGA based on the XVC protocol, characterized in that: In this system, FPGA is mounted on the remote debugging host through PCIe, and the corresponding XVC service software and PCIe driver are loaded on the remote debugging host; FPGA converts XVC protocol messages through the PCIe IP core in the following ways: ① Connect the XVC Bridge of AXI_XVC interface type through the AXI4-Lite interface of the PCIe BAR space.

2. The method according to claim 1, characterized in that Method ①: Design and implement XVC functional logic based on XDMA.

3. The method according to claim 2, characterized in that The XVC functional logic is designed based on XDMA, wherein "connecting the XVCBridge of the AXI_XVC interface type through the AXI4-Lite interface of the PCIe BAR space" is implemented through the following design, so as to realize the transmission of debugging information between the FPGA and the remote debugging host through the PCIe link: using the Debug Bridge IP to connect the debugging network on the FPGA through the AXI4-Lite interface of the PCIe BAR space; then configuring a slave mode Debug Bridge IP on the FPGA to realize the connection and management of the FPGA on-chip debugging resources; XDMA is a type of PCIe IP in the FPGA.

4. The method according to claim 3, characterized in that The BSCAN resources synthesized by the debugging core in the debugging system can eventually communicate with the remote debugging host mounted with the FPGA through PCIe.

5. The method according to claim 1, characterized in that FPGA converts XVC protocol messages through the PCIe IP core in the following ways: ② Connect to the XVC Bridge of PCIe_XVC interface type through the PCIe extended configuration interface.

6. A remote debugging system for a domestically produced FPGA designed based on the method as claimed in any one of claims 1 to 5.

7. A method for remote online debugging of FPGA implemented by the system as claimed in claim 6.

8. A method for remote online updating of FPGA implemented by using the system as claimed in claim 6.

9. Application of the system according to claim 6 in the aerospace field.

10. Application of the system according to claim 6 in the field of industrial automation.

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