Methods, systems, articles of manufacture and apparatus for performing video analysis

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes at least one memory; a machine readable instruction; and a processor circuit module to execute machine readable instructions to: generate macroblocks from an image frame, the macroblocks meeting at a convergence point; assigning a computing unit to the macroblock to process pixels of the macroblock in parallel; performing, with the computing unit, a convergence scan of the macroblock for processing pixels of the macroblock starting at a corner opposite the convergence point and ending at the convergence point; and performing, with the computing unit, a divergent scan of the macroblock for processing pixels of the macroblock starting from the convergence point and ending at a corner opposite the convergence point.

Description

Technical Field

[0001] The present disclosure relates generally to image and video analysis, and more particularly to methods, systems, articles of manufacture, and apparatus for processing image frames. Background Art

[0002] Computer vision is a subfield of artificial intelligence that seeks to extract and interpret information from digital images and / or videos. Computer vision often uses machine learning techniques to extract useful information from digital images and / or videos. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram of an example image processing circuit module.

[0004] Figure 2 Is Figure 1 Illustration of an example convergence scan performed by an example image processing circuit module.

[0005] Figure 3 Is Figure 1 Illustration of an example divergent scan performed by an example image processing circuit module.

[0006] Figure 4 Is Figure 1 Another example of a convergence scan performed on a macroblock by an example image processing circuit module.

[0007] Figure 5 Contains shown by Figure 1 An example table of example image processing circuit modules provides examples of performance improvements to computer hardware.

[0008] Figure 6 Contains the display and Figure 1 Another example table of example error rates associated with example image processing circuit modules.

[0009] Figure 7 is a representation that can be executed by an example processor circuit module to implement Figure 1 The present invention provides a flowchart of example machine-readable instructions and / or example operations of an image processing circuit module.

[0010] Figure 8 is a flow diagram representative of example machine readable instructions and / or example operations that may be executed by example processor circuit modules to implement divergent scanning.

[0011] Fig. 9 is a flow diagram representative of example machine readable instructions and / or example operations that may be executed by example processor circuit modules to implement convergent scanning.

[0012] Fig.10is a block diagram of an example processing platform including a processor circuit module configured to perform Figure 7-9 Example machine readable instructions and / or example operations to implement Figure 1 Image processing circuit module.

[0013] Fig.11 yes Fig.10 A block diagram of an example implementation of a processor circuit module.

[0014] Fig.12 yes Fig.10 A block diagram of another example implementation of a processor circuit module.

[0015] Fig.13 is used to distribute software (for example, corresponding to Figure 7-9 Block diagram of an example software distribution platform (e.g., one or more servers) for distributing software (e.g., software including example machine-readable instructions) to client devices associated with end users and / or consumers (e.g., for licensing, sale and / or use), retailers (e.g., for sale, resale, licensing and / or sublicensing), and / or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, for example, retailers and / or to other end users such as direct-purchase consumers).

[0016] In general, the same reference numerals will be used throughout the accompanying drawings and the written description to refer to the same or similar parts. The drawings are not to scale. Instead, the thickness of layers or regions may be exaggerated in the drawings. Although the drawings show layers and regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, boundaries and / or lines may be unobservable, blended, and / or irregular.

[0017] As used herein, unless otherwise specified, the term "above" describes the relationship of two parts relative to the earth. A first part is above a second part if the second part has at least one portion between the earth and the first part. Likewise, as used herein, a first part is "below" a second part when the first part is closer to the earth than the second part. As described above, a first part can be above or below a second part in one or more of the following situations: with other parts in between, without other parts in between, wherein the first and second parts are in contact, or wherein the first and second parts are not in direct contact with each other.

[0018] As used herein, "approximately" and "approximately" modify their subject matter / values ​​to recognize the potential for variations that occur in real-world applications. For example, "approximately" and "approximately" may modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections as would be understood by one of ordinary skill in the art. For example, "approximately" and "approximately" may indicate that such dimensions may be within a tolerance range of + / - 10%, unless otherwise specified in the description below. As used herein, "substantially real time" and / or "substantially simultaneously" refers to occurring in a near-instantaneous manner, recognizing that there may be real-world delays in computation time, transmission, propagation delays, etc. Therefore, unless otherwise specified, "substantially real time" and / or "substantially simultaneously" refers to real time + / - 1 second.

[0019] As used herein, the phrase "in communication," including variations thereof, includes direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but additionally includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals, and / or one-time events.

[0020] As used herein, a "processor circuit module" is defined as comprising (i) one or more dedicated electronic circuits that are constructed to perform (one or more) specific operations and comprising one or more semiconductor-based logic devices (e.g., electronic hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform specific operations and comprising one or more semiconductor-based logic devices (e.g., electronic hardware implemented by one or more transistors). Examples of processor circuit modules include programmable microprocessors, field programmable gate arrays (FPGAs) that can instantiate instructions, central processor units (CPUs), graphics processor units (GPUs), digital signal processors (DSPs), XPUs, or microcontrollers and integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system that includes multiple types of processor circuit modules (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc. and / or combinations thereof) and (one or more) application programming interfaces (APIs) that can assign (one or more) computing tasks to whichever (or which) of the multiple types of processor circuit modules is most suitable for performing the (one or more) computing tasks. DETAILED DESCRIPTION

[0021] In computer vision, models can be trained with data to recognize patterns and / or associations. The model can then follow such patterns and / or associations when processing new inputs, producing outputs consistent with the recognized patterns and / or associations. Optical flow and image segmentation are computationally intensive computer vision tasks that perform distance transforms to extract information from images.

[0022] Distance transforms (e.g., geodesic distance transforms) are computer vision tasks used in various computer vision workloads (e.g., autonomous driving, motion prediction, etc.). The distance transform accepts a grayscale cost image and a set of seed points. The distance transform then outputs a value for each pixel that represents the geodesic distance from each pixel to its nearest seed point. Distance transforms are used in various artificial intelligence (AI) applications. For example, distance transforms appear in AI applications such as medical analysis, robotics, and motion planning for autonomous vehicles.

[0023] Raster scanning is a conventional method for distance map computation. Conventional methods of performing distance transforms are computationally complex because distance transforms have traditionally been performed sequentially and often contain pixel-level dependencies. Such pixel-level dependencies are difficult to parallelize because information about the relationship between pixels may be lost during parallelization. Many conventional GPU-based distance transform implementations process small areas (e.g., small rectangular areas). In such conventional implementations, each GPU thread scans a small rectangular area, with performance improvements primarily coming from increases in GPU thread count.

[0024] Many conventional GPU implementations focus on the parallelism of a single scan (e.g., a single pass), where all GPU threads run simultaneously and each thread processes a macroblock of a regular size (e.g., 20 macroblocks per frame). However, many such implementations are limited and only determine the shortest path to a seed within a macroblock of a regular size. The failure to use information outside of a macroblock of a regular size often results in a local optimum rather than a global optimum.

[0025] Conventional methods that perform only a single iteration may produce inadequate results with large discrepancies between local optima and ground truth. Therefore, conventional solutions often require many iterations to achieve a global optimum with sufficient accuracy. Repeated iterations increase the computational load and result in unacceptable latency (e.g., execution time to generate a distance map). Therefore, many time-sensitive operations (e.g., autonomous driving, robotic control, etc.) cannot rely on conventional distance transform methods.

[0026] In the examples described herein, a pixel wave is a diagonal grouping of pixels that are processed together. For example, a rectangular macroblock with overlapping coordinate planes may have a lower left corner indexed as (0, 0) and an upper right corner indexed as (r, c), where r is the number of rows of the macroblock and c is the number of columns of the macroblock. The zeroth wave will contain all pixels that fall on the line connecting the points (0, 1) and (1, 0) of the coordinate plane. The first pixel wave will contain all pixels that fall on the line connecting the points (2, 0) and (0, 2) of the coordinate plane. In other words, a pixel wave can be understood as forming an isosceles right triangle with the angle of the macroblock.

[0027] From another perspective, if the pixels themselves are numbered, where the bottom left pixel of a macroblock is labeled (0, 0) and the top right pixel is labeled (r, c), then the pixels within a wave share certain geometric features. For example, pixels within a wave have coordinates that share a characteristic value of c–r+n, where c is the column, r is the row, and n is the width of the macroblock.

[0028] In some examples, waves are developed iteratively. Each successive wave of pixels contains pixels that are adjacent to and share rows or columns with a previously processed wave. For example, the zeroth wave contains pixel (0,0). Subsequent waves of pixels can be formed by taking each pixel of the first wave and adding 1 to either the row value or the column value (e.g., while ignoring repetitions). Thus, the first wave will contain the values ​​(1,0) and (0,1).

[0029] In some examples, waves are processed iteratively. As waves of pixels are processed, the wave in process is referred to as a wavefront (e.g., a leading wave). The above description of waves, seeds, and wavefronts is intended to illustrate the general presence in certain examples. Further description and variations of waves, wavefronts, and seeds will be provided in conjunction with the following figures.

[0030] Compared to conventional solutions, the examples disclosed herein perform distance transformation (e.g., generate a distance map) with only two scanning phases: a convergence phase and a divergence phase. The convergence phase includes a first scan starting at four corner pixels and propagating toward a convergence (e.g., center pixel, origin pixel) point. In some examples, the first scan determines the shortest path to a first seed at the vertical and horizontal symmetry axes. Then, the divergence phase scans from the convergence pixel (e.g., center pixel, origin pixel) toward the four corner pixels to determine the shortest path to a second seed that is farther away from the vertical and horizontal symmetry axes than the first seed.

[0031] Turning to the attached figure, Figure 1 1 is a block diagram of an example image processing circuit module 102. The example image processing circuit module 102 includes an example macroblock generator circuit module 104, an example convergent scanning circuit module 106, an example divergent scanning circuit module 108, an example distance transform circuit module 110, and an example communication circuit module 112.

[0032] Figure 1 is a block diagram of an example image processing circuit module 102 that performs image analysis. Figure 1 The image processing circuit module 102 may be instantiated (eg, created as an instance, generated for any length of time, materialized, realized, etc.) by a processor circuit module such as a central processing unit that executes instructions. Additionally or alternatively, Figure 1 The image processing circuit module 102 can be instantiated (e.g., create an instance, generate, materialize, realize, etc. for any length of time) by an ASIC or FPGA configured to perform operations corresponding to the instructions. It should be understood that Figure 1 Some or all of the circuit modules of can therefore be instantiated at the same or different times. Some or all of the circuit modules can be instantiated, for example, in one or more threads that are executed serially on hardware and / or concurrently on hardware. In addition, in some examples, Figure 1 Some or all of the circuit modules may be implemented by one or more virtual machines and / or containers executed on a microprocessor.

[0033] The example macroblock generator circuit module 104 divides a frame (e.g., an image frame, a video frame) into a plurality of non-overlapping regions (e.g., macroblocks). Specifically, the example macroblock generator circuit module 104 divides the frame into four macroblocks, wherein each of the four macroblocks has the same number of pixels. The example macroblock generator circuit module 104 may determine a convergence point (e.g., an origin, a center point) of the frame by determining the midpoint of the outer edges of the image frame and using the midpoint to find one or more center pixels. The example macroblock generator circuit module 104 may then generate vertical and horizontal symmetry axes for sorting the pixels into corresponding macroblocks.

[0034] Although the example macroblock generator circuit module 104 generates four macroblocks with an equal number of pixels, the examples disclosed herein are not limited to generating four macroblocks. For example, the macroblock generator circuit module 104 can divide the frame into any number of macroblocks (e.g., 2 macroblocks, 6 macroblocks, 50 macroblocks, etc.). Furthermore, in some examples, the macroblock generator circuit module 104 does not generate symmetric macroblocks. The example corner-to-origin wavefront-based processing techniques described herein can be used for asymmetric macroblocks, non-rectangular macroblocks, etc.

[0035] In some examples, the macroblock generator circuit module 104 is instantiated by a processor circuit module that executes macroblock generator instructions and / or is configured to perform operations such as by Figure 7-9 The operations are those represented by the flowcharts.

[0036] In some examples, the image processing circuit module 102 includes components for dividing an image into a plurality of macroblocks and / or generating a plurality of macroblocks from an image frame, the plurality of macroblocks meeting at a convergence point. For example, the components for generating may be implemented by the example macroblock generator circuit module 104. In some examples, the example macroblock generator circuit module 104 may be implemented by a processor circuit module such as Fig.10 For example, the example macroblock generator circuit module 104 may be instantiated by Fig.11 1100 that executes machine-executable instructions, such as at least Figure 7 In some examples, the example macroblock generator circuit module 104 may be instantiated by a hardware logic circuit module that may be configured to perform operations corresponding to the machine-readable instructions. Fig.12 The example macroblock generator circuit module 104 may be implemented by any other combination of hardware, software, and / or firmware. Additionally or alternatively, the example macroblock generator circuit module 104 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the example macroblock generator circuit module 104 may be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are configured to execute some or all of the machine-readable instructions and / or execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally suitable.

[0037] The example convergence scan circuit module 106 performs distance transform calculations on pixel waves (e.g., pixel groups, pixel sets) extending from directional scan lines. As described herein, directional scan lines are straight lines extending between a convergence point (e.g., an origin, a midpoint, a center point) and a point on the outside of a macroblock (e.g., a diagonal corner, an opposite side, a corner opposite to a convergence point). For example, in the square macroblocks disclosed herein, the directional scan lines bisect the angle formed by the horizontal and vertical axes of symmetry. Therefore, in a rectangular macroblock, the directional scan lines will not bisect the angle formed by the horizontal and vertical axes of symmetry. Example combinations of directional scan lines Figure 2 are illustrated and described, and are described in further detail below.

[0038] The example convergence scan circuit module 106 processes macroblock waves along a directional scan line. The example convergence scan circuit module 106 starts at a first end of the directional scan line, the first end being opposite to the convergence point. After the first pixel wave is processed, the example convergence scan circuit module 106 processes a second pixel wave adjacent to the first wave and closer to the convergence point. In other words, the second pixel wave contains pixels adjacent to pixels of the first wave in the row direction or the column direction and closer to the origin (e.g., one unit closer to the convergence point along the horizontal or vertical axis of symmetry).

[0039] The example convergence scanning circuit module 106 scans (e.g., processes) four macroblocks (e.g., upper left quadrant macroblock, upper right quadrant macroblock, lower left quadrant macroblock, and lower right quadrant macroblock) substantially simultaneously in pixel waves that are processed toward the center of the frame (e.g., the convergence point). For example, in a square macroblock, each pixel wave is arranged along a line orthogonal to the direction guide line. In a rectangular macroblock, each pixel wave is at a non-orthogonal angle to the direction guide line and is parallel to other pixel waves within the macroblock. When the wavefronts from each macroblock (e.g., the pixel waves that have not yet been processed that are closest to the convergence point) converge at the convergence point, the convergence scanning circuit module 106 ends the convergence scan.

[0040] In some examples, the convergence scanning circuit module 106 is instantiated by a processor circuit module that executes macroblock generator instructions and / or is configured to perform operations such as by Figure 7-9 The operations are those represented by the flowcharts.

[0041] In some examples, the convergence scanning circuit module 106 includes components for performing convergence scanning of multiple macroblocks using multiple computing units, the convergence scanning is used to start processing pixels of the multiple macroblocks at a corner opposite to the convergence point, and the convergence scanning is completed when all pixels of the multiple macroblocks are processed by the convergence scanning. For example, the components for processing can be implemented by the convergence scanning circuit module 106. In some examples, the example convergence scanning circuit module 106 can be implemented by a processor circuit module (such as Fig.10 For example, the example convergence scanning circuit module 106 may be implemented by executing machine executable instructions. Fig.11 1100, the machine executable instructions are such as at least Figure 8 In some examples, the convergence scanning circuit module 106 may be instantiated by a hardware logic circuit module that may be configured to perform operations corresponding to machine-readable instructions. Fig.12The convergence scanning circuit module 106 may be implemented by an FPGA circuit module 1200, an XPU or an ASIC. Additionally or alternatively, the convergence scanning circuit module 106 may be instantiated by any other combination of hardware, software and / or firmware. For example, the convergence scanning circuit module 106 may be implemented by at least one or more hardware circuits (e.g., a processor circuit module, a discrete and / or integrated analog and / or digital circuit module, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), a logic circuit, etc.), which are configured to execute some or all of the machine-readable instructions and / or execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally suitable.

[0042] The example image processing circuit module 102 includes an example diverging scan circuit module 108. The example diverging scan circuit module 108 performs distance transform calculations on groups of pixels (eg, waves of pixels, sets of pixels) extending from a directional scan line.

[0043] The example diverging scan circuit module 108 begins a diverging scan at the convergence point. The example diverging scan circuit module 108 then processes the first pixel wave. After the first pixel wave is processed, the example diverging scan circuit module 108 processes a second pixel wave (e.g., a second set of pixels along the directional guide line) that is adjacent to the first wave and closer to the end of the frame opposite the convergence point (e.g., farthest from the convergence point).

[0044] The example divergent scanning circuit module 108 scans four macroblocks (e.g., upper left quadrant macroblock, upper right quadrant macroblock, lower left quadrant macroblock, and lower right quadrant macroblock) substantially simultaneously in pixel waves that are processed from the center of the frame to the periphery of the frame, and the pixel waves form a series of parallel lines that intersect the direction guide lines. The divergent scanning circuit module 108 ends the divergent scanning when the wavefront from each macroblock (e.g., the pixel wave that has not yet been processed and is farthest from the convergence point) reaches the corresponding corner of the frame.

[0045] In some examples, the divergent scanning circuit module 108 is instantiated by a processor circuit module that executes macroblock generator instructions and / or is configured to perform operations such as those performed by Figure 7-9 The operations are those represented by the flowcharts.

[0046] In some examples, the divergent scanning circuit module 108 includes a second component for performing a divergent scan of the plurality of macroblocks using the plurality of computing units, the divergent scan being used to process pixels of the plurality of macroblocks (starting from a convergence point and ending at a corner opposite to the convergence point), and the divergent scan is completed when the pixels of the plurality of macroblocks are processed by the divergent scan. For example, the second component for performing can be implemented by the divergent scanning circuit module 108. In some examples, the example divergent scanning circuit module 108 can be implemented by a processor circuit module (such as Fig.10 For example, the example divergent scanning circuit module 108 can be instantiated by Fig.11 1100 that executes machine-executable instructions, such as at least Fig. 9 In some examples, the divergent scanning circuit module 108 may be instantiated by a hardware logic circuit module that may be configured to perform operations corresponding to the machine-readable instructions. Fig.12 The divergent scanning circuit module 108 may be implemented by an FPGA circuit module 1200, an XPU or an ASIC. Additionally or alternatively, the divergent scanning circuit module 108 may be instantiated by any other combination of hardware, software and / or firmware. For example, the divergent scanning circuit module 108 may be implemented by at least one or more hardware circuits (e.g., a processor circuit module, a discrete and / or integrated analog and / or digital circuit module, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), a logic circuit, etc.), which are configured to execute some or all of the machine-readable instructions and / or execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally suitable.

[0047] The example image processing circuit module 102 includes an example distance transform circuit module 110. The example distance transform circuit module 110 generates a distance map when the example convergent scanning circuit module 106 and the example divergent scanning circuit module 108 operate. The example distance transform circuit module 110 performs calculations on pixels to determine the shortest path from a seed value (e.g., a point of interest) to the pixels of the macroblock.

[0048] The example distance transform circuit module 110 generates a distance map based on both a converging scan and a diverging scan. During a converging scan, the distance transform circuit module 110 generates a shortest path from a pixel in the plurality of pixels of the macroblock to a first seed (e.g., closer to the vertical and horizontal axes of symmetry). During a diverging scan, the example distance transform circuit module 110 generates a shortest path from a pixel in the plurality of pixels to a second seed, the second seed being farther from the vertical and horizontal axes of symmetry of the image frame than the first seed. The example distance transform circuit module 110 can generate a distance map that combines information from the shortest paths to the first seed and the second seed.

[0049] In some examples, the image processing circuit module 102 does not include the example distance transform circuit module 110 , and operations of the example distance transform circuit module 110 are instead performed by the convergent scanning circuit module 106 and / or the divergent scanning circuit module 108 .

[0050] In some examples, the example converging scanning circuit module 106 and the example diverging scanning circuit module 108 may not perform distance transforms, and instead may perform other operations on macroblocks of the image. For example, the operations performed by the example converging scanning circuit module 106 and the example diverging scanning circuit module 108 may include operations that implement search / traversal algorithms or implement any type of pixel-level operations. In some examples, the distance transform circuit module 110 is instantiated by a processor circuit module that executes macroblock generator instructions and / or is configured to perform operations such as those performed by Figure 7-9 The operations are those represented by the flowcharts.

[0051] In some examples, the distance transform circuit module 110 includes components for generating a distance map based on a convergent scan and based on a divergent scan, wherein the convergent scan is used to generate a shortest path from a pixel in the plurality of pixels to a first seed, and the divergent scan is used to generate a shortest path from a pixel in the plurality of pixels to a second seed, the second seed being farther from the vertical and horizontal symmetry axes of the image frame than the first seed. For example, the components for generating can be implemented by the distance transform circuit module 110. In some examples, the example distance transform circuit module 110 can be implemented by a processor circuit module (such as Fig.10 For example, the example distance transformation circuit module 110 may be instantiated by Fig.11 1100 that executes machine-executable instructions, such as at least Figure 7 Frame 708, Figure 8 Boxes 806-808 and Fig. 9In some examples, the distance transformation circuit module 110 may be instantiated by a hardware logic circuit module, which may be configured to perform operations corresponding to machine-readable instructions. Fig.12 The distance transformation circuit module 110 may be implemented by an FPGA circuit module 1200, an XPU or an ASIC. Additionally or alternatively, the distance transformation circuit module 110 may be instantiated by any other combination of hardware, software and / or firmware. For example, the distance transformation circuit module 110 may be implemented by at least one or more hardware circuits (e.g., a processor circuit module, a discrete and / or integrated analog and / or digital circuit module, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), a logic circuit, etc.), which are configured to execute some or all of the machine-readable instructions and / or execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally suitable.

[0052] The example image processing circuit module 102 additionally includes an example communication circuit module 112. The example communication circuit module 112 facilitates communication between the macroblock generator circuit module 104, the example convergence scan circuit module 106, the example distance transform circuit module 110, and the example communication circuit module 112. The example communication circuit module 112 may also transmit and / or receive data from any helper computing unit (e.g., a GPU, a hardware accelerator, an additional CPU, etc.) that may assist in performing the distance transform.

[0053] Although in Figure 1 The implementation is shown in Figure 1 The image processing circuit module 102 is an example of an Figure 1 One or more of the elements, processes and / or devices shown in the drawings may be combined, divided, rearranged, omitted, eliminated and / or implemented in any other manner. Figure 1 The example macroblock generator circuit module 104, the example convergence scanning circuit module 106, the example divergence scanning circuit module 108, the example distance transformation circuit module 110 and the example communication circuit module 112, and / or more generally, the example image processing circuit module 102 can be implemented by hardware alone, or by hardware combined with software and / or firmware. Thus, for example, Figure 1Any of the example macroblock generator circuit module 104, the example convergence scanning circuit module 106, the example divergence scanning circuit module 108, the example distance transformation circuit module 110, and the example communication circuit module 112 and / or more generally the example image processing circuit module 102 can be implemented by a processor circuit module, (one or more) analog circuits, (one or more) digital circuits, (one or more) logic circuits, (one or more) programmable processors, (one or more) programmable microcontrollers, (one or more) graphics processing units ((one or more) GPUs), (one or more) digital signal processors ((one or more) DSPs), (one or more) application specific integrated circuits ((one or more) ASICs), (one or more) programmable logic devices ((one or more) PLDs) and / or (one or more) field programmable logic devices ((one or more) FPLDs) such as field programmable gate arrays (FPGAs). In addition, Figure 1 The example image processing circuit module 102 may include one or more components, processes and / or devices as Figure 1 The elements, processes, and / or devices may be additional to or alternative to those shown, and / or may include more than one of any or all of the elements, processes, and devices shown.

[0054] "Including" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim adopts any form of "includes" or "comprising" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or in any type of claim recitation, it is to be understood that additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transitional term, such as in the preamble of a claim, it is open-ended in the same manner as the terms "includes" and "comprising" are open-ended. When used in a form such as A, B, and / or C, the term "and / or" refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A and B” is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A or B” is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, acts, activities, and / or steps, the phrase “at least one of A and B” is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the implementation or execution of a process, instruction, action, activity, and / or step, the phrase "at least one of A or B" is intended to refer to an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0055] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude a plurality. As used herein, the term "a" (a or an) object refers to one or more of the object. The terms "a" (a or an), "one or more," and "at least one" are used interchangeably herein. In addition, although listed separately, multiple components, elements, or method actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not imply that a combination of features is not feasible and / or disadvantageous.

[0056] Figure 2 is an illustration of an image frame 200. The example image frame 200 includes an example convergence point 210, an example first corner 212 (e.g., upper left corner), an example second corner 214 (e.g., upper right corner), an example third corner 216 (e.g., lower right corner), an example fourth corner 218 (e.g., lower left corner), an example first directional arrow 220, an example second directional arrow 222, an example third directional arrow 224, an example fourth directional arrow 226, an example first pixel 228, an example second pixel 230, an example third pixel 232, an example fourth pixel 234, an example fifth pixel 236, an example sixth pixel 238, an example first converging wave 240, an example eighth converging wave 244, an example third converging wave 246, an example directional guide line 248, an example horizontal axis of symmetry 250, and an example vertical axis of symmetry 252.

[0057] The example image frame 200 includes an example horizontal axis of symmetry 250 and an example vertical axis of symmetry 252. The example horizontal axis of symmetry 250 and the example vertical axis of symmetry 252 divide the image frame 200 into four macroblocks: an example first macroblock 202, an example second macroblock 204, an example third macroblock 208, and an example fourth macroblock 206. The example vertical axis of symmetry 252 and the example horizontal axis of symmetry 250 meet and / or otherwise intersect at a convergence point 210. An example first directional guide line 248 connects to the convergence point 210 and extends to a third corner 216.

[0058] The example first macroblock 202 includes an example first corner 212 and an example directional arrow 220. The example directional arrow 220 indicates a general direction of convergence scanning (eg, wavefront propagation) performed by the example convergence scanning circuit module 106.

[0059] The example second macroblock 204 includes an example second direction arrow 222, which shows the direction in which the example convergence scan circuit module 106 processes the pixel wave. The example second macroblock includes an example first pixel 228, an example second pixel 230, an example third pixel 232, an example fourth pixel 234, an example fifth pixel 236, and an example sixth pixel 238. Each pixel is only a member of a single pixel wave. For example, the first pixel 228 is included in the zeroth pixel wave. The zeroth pixel wave is the initial pixel wave processed by the example convergence scan circuit module 106 when performing a convergence scan. Each of the four macroblocks has a zeroth wave (e.g., Figure 2 Pixels marked as “0” in ).

[0060] After processing the zeroth wave, the example convergence scan circuit module 106 processes the second pixel 230 and the third pixel 232, which form the first pixel wave. In some examples, the second pixel 230 and the third pixel 230 are processed by the SIMD processor circuit module for parallelization. The example pixels 234-238 are part of the example second pixel wave. The example second pixel wave is processed after the example first pixel wave.

[0061] The example third macroblock 208 includes an example third corner 216 connected to the example convergence point 210 by an example directional guide line 248. The example first pixel wave 240 includes rows of pixels that are adjacent to and share rows or columns with a previously processed wave (e.g., the first converging wave 240). In the example third macroblock 208, the example convergence scan circuit module 106 processes a wave of pixels starting at the example third corner 216 (e.g., the example zeroth wave) and continuing toward the convergence point 210 and along the example directional guide line 248 until all pixels of the example macroblock 208 are processed. For example, the eighth wave 244 will be processed seven waves after the example first wave 240.

[0062] The example frame 200 includes an example eighth convergence wave of an example fourth macroblock 206. The example fourth macroblock 206 includes an example fourth corner and an example fourth directional arrow 226 that generally indicates the direction in which the example convergence scan circuit module 106 will process the pixel wave. Figure 3 is a diagram of an example image frame 200 in which the example divergent scan circuit module 108 performs an example divergent scan. Figure 3 In the example shown, the image frame 200 includes an example fourth direction arrow 302 , an example fifth direction arrow 304 , an example sixth direction arrow 308 , and an example second direction guide line 322 . when Figure 3When diverging scanning is shown, the example directional arrows 302-308 point to the corresponding corners of each macroblock (e.g., corner 214 of the example second macroblock 204). The example second directional guide line 322 is the directional guide line of the example second macroblock 204. The example second macroblock 204 includes the example second diverging wave 316 and the example eighth diverging wave 318. Within each macroblock, the example diverging scanning circuit module 108 operates on consecutive waves. For example, the second diverging wave 316 will be processed six waves before the example eighth diverging wave 318.

[0063] The example first macroblock 202 includes a second plurality of pixels 310-314. The example seventh pixel 310 is a pixel from the zeroth diverging wave because the example seventh pixel 310 is closest to the convergence point 210. The example eighth pixel 312 and the example ninth pixel 313 are included in the example first diverging wave. The example tenth pixel 314 is a pixel of the example second diverging wave.

[0064] In operation, the example diverging scanning circuit module 108 first processes the example zeroth wave. After the example zeroth wave is processed, the example diverging scanning circuit module 108 processes the next wave that is closer to the corresponding diagonal corner (e.g., opposite to the convergence point) associated with the relevant macroblock. For example, the example diverging scanning circuit module 108 may next process the example first wave (e.g., Figure 3 In some examples, each wave of a macroblock is processed by providing all pixels of the wave to a single instruction multiple data (SIMD) computation unit to increase parallelism. In some examples, the example divergent computation circuit 108 performs the waves of the separate macroblocks substantially simultaneously. For example, the example eighth divergent wave 318 of the example second macroblock 204 can be processed substantially simultaneously with the example eighth divergent wave 320 of the example fourth macroblock 206.

[0065] Figure 4 4 is an illustration of an example fifth macroblock 400. The example fifth macroblock 400 includes an eleventh pixel 402, a twelfth pixel 404, a thirteenth pixel 406, a fourteenth pixel 408, a fifteenth pixel 410, a sixteenth pixel 412, a seventeenth pixel 414, an eighteenth pixel 416, a nineteenth pixel 418, an example first converging wave 420, an example second converging wave 422, and an example third converging wave 424.

[0066] In operation, the example convergence scan circuit module 106 performs a convergence scan, starting with the example eleventh pixel 402 (e.g., of the example zeroth convergence wave). After the example eleventh pixel 402 is processed, the example convergence scan circuit module 106 moves the wavefront to the example first pixel wave 420 that includes the example twelfth pixel 404 and the example thirteenth pixel 406. The example convergence scan circuit module 106 continues to perform distance transform operations on pixels in the wave until it reaches the example thirteenth pixel wave 424 that includes the example eighteenth pixel 414 and the example nineteenth pixel 416. The example convergence scan circuit module 106 will complete the operation at the example nineteenth pixel 418. Thus, the example convergence scan circuit module 106 starts processing a pixel wave at the upper left corner (e.g., the eleventh pixel 402) and processes the diagonal wave toward the lower right corner (e.g., the example nineteenth pixel 418).

[0067] Figure 5 Provides example data showing Figure 1 The example image processing circuit module 102 is associated with improvements to computer hardware. Figure 5 An example first table 502, an example second table 504, and an example third table 506 are included. The example first table 502 illustrates the improvements provided by the example image processing circuit module 102. The example first table 502 illustrates the example techniques described herein implemented on a 3.4 gigahertz (GHz) CPU. The example table 502 illustrates that, for example, on a 1080p image, the improved distance transform performed by the example image processing circuit module 102 is performed in 29.27 milliseconds (ms). This is an improvement of 612.91% over the conventional distance transform performed in 179.4ms.

[0068] The example second table 504 shows the additional performance improvement provided by the example image processing circuit module 102 when performing the distance transform on a 1 GHz GPU. On a 1080p image, the example image processing circuit module 102 performs the distance transform in only 2.98 ms, compared to 20.64 ms for conventional distance transform techniques. Thus, in this example, the image processing circuit module 102 provides a 692.62% improvement over conventional hardware / software techniques.

[0069] The example third table 506 shows further performance improvements provided by the example image processing circuit module 102. The example third table 506 shows that when executed on a 1 GHz GPU, the disclosed technology can perform distance transform on a 4K image in 9.5 ms. This is a 7006.32% performance improvement over the conventional solution that performs distance transform in 665.6 ms.

[0070] Figure 6is an example table 600 comparing endpoint error (EPE) rates associated with conventional techniques and EPE rates associated with the example image transformation circuit module 102. EPE is the average of the absolute errors between all pixels in an image. Thus, the example fourth table 600 shows that, on average, the average EPE for the conventional technique is 7.67, while the average for the example image processing circuit module 102 (e.g., performing low-latency distance transformation) is 7.983. This is an increase of only 1.27%. Therefore, when analyzed together Figure 5 and Figure 6 When compared to the example image transformation circuit module 102, in some examples, the example image transformation circuit module 102 provides a performance improvement of greater than 7000%, with an increase in EPE of only 1.27% (eg, on average).

[0071] Figure 7-9 The diagram shows a method for implementing Figure 1 102 of the image processing circuit module 102. The machine-readable instructions may be one or more executable programs or (one or more) parts of executable programs for execution by a processor circuit module, such as the following in combination with Fig.10 The processor circuit module 1012 shown in the example processor platform 1000 discussed below and / or in conjunction with Fig.11 and / or the example processor circuit modules discussed in 12. The program may be implemented in software stored on one or more non-transitory computer-readable storage media, such as a compact disk (CD), a floppy disk, a hard disk drive (HDD), a solid-state drive (SSD), a digital versatile disk (DVD), a Blu-ray disk, a volatile memory (e.g., any type of random access memory (RAM), etc.) or a non-volatile memory (e.g., an electrically erasable programmable read-only memory (EEPROM), flash memory, HDD, SSD, etc.), which is associated with a processor circuit module located in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed by one or more hardware devices other than the processor circuit module and / or implemented in firmware or dedicated hardware. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a user) or an intermediate client hardware device (e.g., a radio access network (RAN)) gateway that can facilitate communication between a server and an endpoint client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media located in one or more hardware devices. In addition, although reference is made to Figure 7-9The flowchart shown in describes an example program, but many other methods of implementing the example image processing circuit module 102 may be used alternatively. For example, the execution order of the boxes may be changed, and / or some of the boxes in the described boxes may be changed, eliminated, or combined. Additionally or alternatively, any or all of the boxes in the boxes may be implemented by one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured to perform corresponding operations without executing software or firmware. The processor circuit module may be distributed in a single machine, multiple processors distributed on multiple servers in a server rack, multiple processors distributed on one or more server racks, one or more hardware devices (e.g., single-core processors (e.g., single-core central processor units (CPUs)), multi-core processors (e.g., multi-core CPUs, XPUs, etc.)) in the same package (e.g., the same integrated circuit (IC) package or in two or more independent housings, etc.) in a CPU and / or FPGA) locally and / or in different network locations.

[0072] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions as described herein may be stored as data or data structures (e.g., as part of instructions, code, code representations, etc.) that can be used to create, manufacture, and / or produce machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices and / or computing devices (e.g., servers) located in the same or different locations of a network or collection of networks (e.g., in the cloud, in an edge device, etc.). The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, reassignment, compilation, etc., so that they can be directly read, interpreted, and / or executed by a computing device and / or other machine. For example, machine-readable instructions may be stored in multiple parts that are separately compressed, encrypted, and / or stored on separate computing devices, where the parts, when decrypted, decompressed, and / or combined, form a set of machine-executable instructions that implement one or more operations that together may form a program (such as the programs described herein).

[0073] In another example, the machine-readable instructions may be stored in a state in which they are readable by a processor circuit module, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine-readable instructions may need to be configured (e.g., settings are stored, data are entered, network addresses are recorded, etc.) before the machine-readable instructions and / or corresponding program(s) can be executed in whole or in part. Therefore, as used herein, a machine-readable medium may contain machine-readable instructions and / or program(s) regardless of the particular format or state of the machine-readable instructions and / or program(s) when stored or otherwise at rest or in transit.

[0074] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0075] As mentioned above, Figure 7-9The example operations of can be implemented using executable instructions (e.g., computer and / or machine-readable instructions) stored on one or more non-transitory computer and / or machine-readable media, such as optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage devices or storage disks, where information is stored for any duration (e.g., for an extended period of time, permanently, for transient instances, for temporary buffering, and / or for caching of information). As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and non-transitory machine-readable storage medium are expressly defined to include any type of computer-readable storage device and / or storage disk, and do not include propagating signals and do not include transmission media. As used herein, the terms "computer-readable storage device" and "machine-readable storage device" are defined to include any physical (mechanical and / or electronic) structure that stores information, but do not include propagating signals and do not include transmission media. Examples of computer-readable storage devices and machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant array of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical and / or electrical device, hardware, and / or circuit module, which may or may not be configured by computer-readable instructions, machine-readable instructions, etc. and / or manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0076] Figure 7 is a flow diagram representative of example machine readable instructions and / or example operations 700 that may be executed and / or instantiated by a processor circuit module to generate a distance map. Figure 7 The machine readable instructions and / or operations 700 of the present invention begin at block 702 where, Figure 1 The example macroblock generator circuit module 104 assigns macroblocks to computing units. For example, Figure 1 The macroblock generator circuit module 104 may divide the frame into four quadrants and assign each quadrant to a SIMD computing unit.

[0077] At block 704, the example convergence scan circuit module 106 performs a convergence scan. For example, Figure 1 The convergence scan circuit module 106 can perform convergence scan to process the pixels of the assigned macroblock (starting at the corner opposite to the convergence point) and process the diagonal pixel waves. Figure 8 The operations of block 704 are described in more detail.

[0078] At block 706, Figure 1 The example divergent scanning circuit module 108 performs a divergent scan. For example, Figure 1 The divergent scanning circuit module 108 may use the plurality of computing units to perform divergent scanning of the plurality of macroblocks. Figure 1 The example diverging scanning circuit module 108 can operate on a set of pixels, starting at a convergence point and ending at a corner opposite the convergence point. Fig. 9 Example operations of block 706 are described in greater detail.

[0079] At block 708, Figure 1 The example distance transformation circuit module 110 generates a distance map. For example, Figure 1 The distance transformation circuit module 110 can generate a distance map based on the distance calculations performed during the convergent and divergent scans. In some examples, Figure 1 The example distance transform circuit module 110 may iteratively generate the distance map during convergent and divergent scans. Instructions 700 end.

[0080] Figure 8 is a flow diagram representative of example machine readable instructions and / or example operations 704 that may be executed and / or instantiated by a processor circuit module to perform a converged scan. Figure 7 The machine readable instructions and / or operations 704 of begin at block 802 where, Figure 1 The example convergence scan circuit module 106 processes a set of pixels at a corner opposite to the convergence point. For example, multiple SIMD computation units can operate on a zeroth wave of pixels located at a corner opposite to the convergence point of the example frame. In some examples, all pixels of the zeroth wave are processed before continuing to the first wave, all pixels of the first wave are processed before continuing to the second wave, and so on.

[0081] At block 804, Figure 1 An example convergence scanning circuit module 106 identifies a set of pixels that are closer to the convergence point and that are substantially orthogonal (e.g., directly orthogonal in the case of a square macroblock, with slight deviations from direct orthogonality when the macroblock shape assumes a different rectangular configuration) to the direction guide line. For example, the convergence scanning circuit module may identify a set of pixels that are adjacent to the most recently processed set of pixels, but that are closer to the convergence point along a line extending from a frame corner to the convergence point.

[0082] At block 806, Figure 1 An example of a convergence scanning circuit module 106 and / or Figure 1 The example distance transform circuit module 110 processes the pixels in the identified set. For example, Figure 1The example distance transformation circuit module 110 may generate a distance map based on a converging scan and based on a diverging scan, the converging scan being used to generate a shortest path from a pixel of the plurality of pixels to a first seed along a horizontal and / or vertical axis of symmetry.

[0083] At block 808, Figure 1 The example distance transform circuit module 110 updates the distance map with the distances to the seeds along the vertical and horizontal axes of symmetry. For example, when Figure 1 An example of a convergence scan circuit module 106 identifies a pixel wave for processing when, Figure 1 The distance transformation circuit module 110 can update the distance map. In some examples, Figure 1 The image processing circuit module 102 may perform an alternative operation instead of the distance transform operation. For example, Figure 1 The convergence scan circuit module 106 may perform a pattern search instead of a distance transform.

[0084] At block 810, Figure 1 The example image processing circuit module 102 determines whether convergence of the waves for each macroblock has occurred. For example, four GPU threads may operate on waves for four different macroblocks. During the divergence phase, the final pixel wave for each macroblock may be the wave that is closest to (e.g., adjacent to or located at) a convergence point (e.g., a center point) of the frame. If the GPU threads have converged (e.g., processed all pixels of the frame), the example instructions continue at block 706. Otherwise, the instructions return to block 804, where the next set of pixels is identified for processing.

[0085] Fig. 9 is a flow diagram representative of example machine readable instructions and / or example operations 706 that may be executed and / or instantiated by a processor circuit module to perform a divergent scan. Figure 7 The machine readable instructions and / or operations 706 of begin at block 902 where, Figure 1 The example divergent scanning circuit module 108 processes a set of pixels at a convergence point. For example, multiple SIMD computing units can operate on the zeroth pixel wave located at the convergence point of the sample frame. In some examples, all pixels of the current wave are processed before continuing to the subsequent wave.

[0086] At block 904, Figure 1 The example divergent scanning circuit module 108 identifies a set of pixels that are closer to an outer corner and are substantially orthogonal (e.g., directly orthogonal in the case of a square macroblock, but slightly deviate from directly orthogonal when the macroblock shape assumes a different rectangular configuration) to the direction guide line. For example, Figure 1The diverging scan circuit module 108 may identify a set of pixels that are adjacent to a most recently processed set of pixels but are closer to a corresponding corner point along a line extending from the convergence point.

[0087] At block 906, Figure 1 An example divergent scan circuit module 108 and / or Figure 1 The example distance transform circuit module 110 processes the pixels in the identified set. For example, Figure 1 The example distance transformation circuit module 110 may generate a distance map based on a divergent scan, and a convergent scan is used to generate a shortest path from a pixel of the plurality of pixels to a second seed that is farther from the horizontal and / or vertical symmetry axis than the first seed.

[0088] At block 908, Figure 1 The example distance transformation circuit module 110 updates the distance map with the distances to seeds that are farther from the vertical and horizontal symmetry axes. For example, when Figure 1 An example divergent scan circuit module 108 identifies a pixel wave for processing when, Figure 1 The distance transformation circuit module 110 may update the distance map. In some examples, the image processing circuit module 102 may perform an alternative operation instead of the distance transformation operation. For example, Figure 1 The divergent scan circuit module 108 may perform a pattern search instead of a distance transform.

[0089] At block 910, Figure 1 The example image processing circuit module 102 determines whether the divergence of the wave for each macroblock has reached the corresponding corner. For example, four GPU threads can operate on the wave in four different macroblocks. During the divergence phase, the final pixel wave of each macroblock can be adjacent to or at the corner of the frame. If the GPU thread has processed all pixels of the frame, the example instructions continue at box 708. Otherwise, the instructions return to box 904, in which the next set of pixels is identified for processing.

[0090] Fig.10 is a block diagram of an example processor platform 1000 that is configured to execute and / or instantiate Figure 7-9 Machine-readable instructions and / or operations to implement Figure 1 The processor platform 1000 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cellular phone, a smart phone, an iPad, etc.). TMtablet computer), personal digital assistant (PDA), Internet appliance, DVD player, CD player, digital video recorder, Blu-ray player, game console, personal video recorder, set-top box, headsets (e.g., augmented reality (AR) headsets, virtual reality (VR) headsets, etc.) or other wearable devices, or any other type of computing device.

[0091] The processor platform 1000 of the illustrated example includes a processor circuit module 1012. The processor circuit module 1012 of the illustrated example is hardware. For example, the processor circuit module 1012 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired series or manufacturer. The processor circuit module 1012 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the processor circuit module 1012 implements the example macroblock generator circuit module 104, the example convergence scanning circuit module 106, the example divergence scanning circuit module 108, the example distance transformation circuit module 110, and the example communication circuit module 112.

[0092] The processor circuit module 1012 of the illustrated example includes a local memory 1013 (e.g., cache, registers, etc.). The processor circuit module 1012 of the illustrated example communicates with a main memory including a volatile memory 1014 and a non-volatile memory 1016 via a bus 1018. The volatile memory 1014 may be composed of a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), Dynamic Random Access Memory The non-volatile memory 1016 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memory 1014, 1016 of the illustrated example is controlled by a memory controller 1017.

[0093] The processor platform 1000 of the illustrated example further includes an interface circuit module 1020. The interface circuit module 1020 may be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0094] In the example shown, one or more input devices 1022 are connected to the interface circuit module 1020. The input device(s) 1022 allow a user to input data and / or commands into the processor circuit module 1012. The input device(s) 1022 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a track pad, a trackball, an isopoint device, and / or a voice recognition system.

[0095] One or more output devices 1024 are also connected to the interface circuit module 1020 of the illustrated example. The output device(s) 1024 may be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Therefore, the interface circuit module 1020 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit module such as a GPU.

[0096] The interface circuit module 1020 of the illustrated example also includes a communication device, such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and / or a network interface to facilitate the exchange of data with an external machine (e.g., any kind of computing device) over the network 1026. The communication may be through, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a field wireless system, a cellular telephone system, an optical connection, etc.

[0097] The processor platform 1000 of the illustrated example also includes one or more mass storage devices 1028 to store software and / or data. Examples of such mass storage devices 1028 include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid-state storage devices such as flash memory devices and / or SSDs, and DVD drives.

[0098] Can be Figure 7-9 The machine-readable instructions 1032 implemented by the machine-readable instructions may be stored in the mass storage device 1028, in the volatile memory 1014, in the non-volatile memory 1016, and / or on a removable non-transitory computer-readable storage medium such as a CD or DVD.

[0099] Fig.11 yes Fig.10 1012. In this example, Fig.10The processor circuit module 1012 is implemented by the microprocessor 1100. For example, the microprocessor 1100 may be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit module). The microprocessor 1100 executes Figure 7-9 Some or all of the machine-readable instructions of the flowchart to effectively Figure 1 The circuit modules of the machine readable instructions are instantiated as logic circuits to perform operations corresponding to those machine readable instructions. In some such examples, Figure 1 The circuit modules are instantiated by the hardware circuits of the microprocessor 1100 in combination with instructions. For example, the microprocessor 1100 may be implemented by a multi-core hardware circuit module, such as a CPU, DSP, GPU, XPU, etc. Although it may include any number of example cores 1102 (e.g., 1 core), the microprocessor 1100 of this example is a multi-core semiconductor device including N cores. The cores 1102 of the microprocessor 1100 may operate independently, or may cooperate to execute machine-readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores 1102, or may be executed by multiple cores in the cores 1102 at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is divided into threads and executed in parallel by two or more cores in the cores 1102. The software program may correspond to a program executed by Figure 7-9 A flowchart may represent a portion or all of machine-readable instructions and / or operations.

[0100] The core 1102 can communicate via a first example bus 1104. In some examples, the first bus 1104 can be implemented by a communication bus to implement communications associated with (one or more) cores in the core 1102. For example, the first bus 1104 can be implemented by at least one of an inter-integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1104 can be implemented by any other type of computing or electrical bus. The core 1102 can obtain data, instructions, and / or signals from one or more external devices via an example interface circuit module 1106. The core 1102 can output data, instructions, and / or signals to the one or more external devices via the interface circuit module 1106. Although the core 1102 of this example includes an example local memory 1120 (e.g., a level 1 (L1) cache that may be divided into a L1 data cache and an L1 instruction cache), the microprocessor 1100 also includes an example shared memory 1110 that may be shared by the cores (e.g., a level 2 (L2 cache)) for high-speed access to data and / or instructions. Data and / or instructions may be transferred (e.g., shared) by writing to and / or reading from the shared memory 1110. The local memory 1120 of each core in the core 1102 and the shared memory 1110 may be a plurality of levels of cache memory and main memory (e.g., Fig.10 Part of a hierarchy of storage devices (main memory 1014, 1016). Generally, memory at higher levels in the hierarchy exhibits shorter access times and has smaller storage capacity than memory at lower levels. Changes in various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0101] Each core 1102 may be referred to as a CPU, DSP, GPU, etc. or any other type of hardware circuit module. Each core 1102 includes a control unit circuit module 1114, an arithmetic and logic (AL) circuit module (sometimes referred to as an ALU) 1116, a plurality of registers 1118, a local memory 1120, and a second example bus 1122. Other structures may exist. For example, each core 1102 may include a vector unit circuit module, a single instruction multiple data (SIMD) unit circuit module, a load / store unit (LSU) circuit module, a branch / jump unit circuit module, a floating point unit (FPU) circuit module, etc. The control unit circuit module 1114 includes a semiconductor-based circuit configured to control (e.g., coordinate) data movement within the corresponding core 1102. The AL circuit module 1116 includes a semiconductor-based circuit configured to perform one or more mathematical and / or logical operations on data within the corresponding core 1102. The AL circuit module 1116 of some examples performs integer-based operations. In other examples, the AL circuit module 1116 also performs floating-point operations. In still other examples, the ALU circuit module 1116 may include a first AL circuit module that performs integer-based operations and a second AL circuit module that performs floating-point operations. In some examples, the AL circuit module 1116 may be referred to as an arithmetic logic unit (ALU). The register 1118 is a semiconductor-based structure for storing data and / or instructions (such as the results of one or more of the operations performed by the AL circuit module 1116 of the corresponding core 1102). For example, the register 1118 may include (one or more) vector registers, (one or more) SIMD registers, (one or more) general registers, (one or more) flag registers, (one or more) segment registers, (one or more) machine-specific registers, (one or more) instruction pointer registers, (one or more) control registers, (one or more) debug registers, (one or more) memory management registers, (one or more) machine check registers, etc. The register 1118 may be arranged in a manner such as Fig.11 1102. Alternatively, registers 1118 may be organized in any other arrangement, format, or structure, including being distributed throughout core 1102 to reduce access time. Second bus 1122 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0102] Each core 1102 and / or more generally the microprocessor 1100 may include additional and / or alternative structures to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHA), one or more convergence / common grid stops (CMS), one or more shifters (e.g., (one or more) barrel shifters) and / or other circuit modules may exist. The microprocessor 1100 is a semiconductor device made to include many transistors, which are interconnected to implement the structure described above in one or more integrated circuits (ICs) contained in one or more packages. The processor circuit module may include one or more accelerators and / or cooperate with one or more accelerators. In some examples, the accelerator is implemented by a logic circuit module to perform certain tasks faster and / or more efficiently than what can be done by a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. GPUs or other programmable devices may also be accelerators. The accelerator may be on a board of a processor circuit module, in the same chip package as the processor circuit module, and / or in one or more packages separated from the processor circuit module.

[0103] Fig.12 yes Fig.10 1012 is a block diagram of another example implementation of a processor circuit module 1012. In this example, the processor circuit module 1012 is implemented by an FPGA circuit module 1200. For example, the FPGA circuit module 1200 can be implemented by an FPGA. The FPGA circuit module 1200 can be used, for example, to perform operations that can be performed by executing corresponding machine-readable instructions in other cases. Fig.11 However, once configured, the FPGA circuit module 1200 instantiates the machine-readable instructions in hardware and can therefore often perform operations faster than if the operations could be performed by a general-purpose microprocessor executing corresponding software.

[0104] More specifically, as described above Fig.11 The microprocessor 1100 (which is programmable to execute Figure 7-9 Compared to a general purpose device that contains some or all of the machine-readable instructions represented by a flowchart, but whose interconnections and logic circuit modules are fixed once they are made, Fig.12 The example FPGA circuit module 1200 includes a plurality of circuits that can be configured and / or interconnected in different ways after fabrication to instantiate, for example, Figure 7-9In particular, FPGA circuit module 1200 can be thought of as an array of logic gates, interconnections, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnections, effectively forming one or more dedicated logic circuits (unless and until FPGA circuit module 1200 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on data received by the input circuit modules. Those operations may correspond to the operations performed by Figure 7-9 Therefore, the FPGA circuit module 1200 can be configured to Figure 7-9 Some or all of the machine-readable instructions of the flowchart of the invention are effectively instantiated as dedicated logic circuits to perform operations corresponding to those software instructions in a dedicated manner similar to an ASIC. Thus, a general-purpose microprocessor can perform operations corresponding to Figure 7-9 FPGA circuit module 1200 can execute the corresponding instructions faster than some or all of the machine-readable instructions. Figure 7-9 The operations of some or all of the machine-readable instructions.

[0105] exist Fig.12 In the example of , FPGA circuit module 1200 is configured to be programmed (and / or reprogrammed one or more times) by an end user via a hardware description language (HDL) such as Verilog. Fig.12 The FPGA circuit module 1200 includes an example input / output (I / O) circuit module 1202 to obtain data from and / or output data to an example configuration circuit module 1204 and / or external hardware 1206. For example, the configuration circuit module 1204 may be implemented by an interface circuit module that may obtain machine-readable instructions to configure the FPGA circuit module 1200 or (one or more) parts thereof. In some such examples, the configuration circuit module 1204 may obtain machine-readable instructions from a user, a machine (e.g., a hardware circuit module (e.g., a programmed or dedicated circuit module) that may implement an artificial intelligence / machine learning (AI / ML) model to generate instructions), etc. In some examples, the external hardware 1206 may be implemented by an external hardware circuit module. For example, the external hardware 1206 may be implemented by Fig.12 The FPGA circuit module 1200 also includes an array of example logic gate circuit modules 1208, multiple example configurable interconnects 1210, and example storage circuit modules 1212. The logic gate circuit modules 1208 and the configurable interconnects 1210 are configurable to instantiate Figure 7-9One or more operations of at least some of the machine-readable instructions and / or other desired operations. Fig.12 The logic gate circuit modules 1208 shown in are made in groups or blocks. Each block contains a semiconductor-based electronic structure that can be configured as a logic circuit. In some examples, the electronic structure contains logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present in each of the logic gate circuit modules 1208 to enable the configuration of the logic gates and / or electronic structures to form a circuit that performs the desired operation. The logic gate circuit module 1208 may include other electronic structures, such as a lookup table (LUT), a register (e.g., a flip-flop or a latch), a multiplexer, etc.

[0106] The example configurable interconnect 1210 shown is a conductive path, trace, via, or the like that may include an electrically controlled switch (e.g., a transistor), the state of which can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more logic gate circuit modules in the logic gate circuit module 1208, thereby programming the desired logic circuit.

[0107] The storage circuit module 1212 of the illustrated example is configured to store (one or more) results of one or more operations performed by the corresponding logic gates. The storage circuit module 1212 can be implemented by a register or the like. In the illustrated example, the storage circuit module 1212 is distributed in the logic gate circuit module 1208 to facilitate access and increase execution speed.

[0108] Fig.12 The example FPGA circuit module 1200 also includes an example dedicated operation circuit module 1214. In this example, the dedicated operation circuit module 1214 includes a dedicated circuit module 1216, which can be called to implement common functions to avoid the need to program those functions on site. Examples of such dedicated circuit modules 1216 include memory (e.g., DRAM) controller circuit modules, PCIe controller circuit modules, clock circuit modules, transceiver circuit modules, memory, and multiplier-accumulator circuit modules. Other types of dedicated circuit modules may exist. In some examples, the FPGA circuit module 1200 may also include an example general-purpose programmable circuit module 1218, such as an example CPU 1220 and / or an example DSP 1222. Additionally or alternatively, other general-purpose programmable circuit modules 1218 may exist, such as GPUs, XPUs, etc., which can be programmed to perform other operations.

[0109] Although Fig.11 and Fig.12 Show Fig.10 These are two example implementations of the processor circuit module 1012, but many other implementations are contemplated. For example, as mentioned above, a modern FPGA circuit module may include an onboard CPU, such as Fig.12 One or more of the example CPUs 1220. Thus, Fig.10 The processor circuit module 1012 can additionally be combined by Fig.11 An example microprocessor 1100 and Fig.13 In some such hybrid examples, the Figure 7-9 The first portion of the machine-readable instructions represented by the flowchart may be represented by Fig.11 1102 is executed by one or more cores of the core 1102. Figure 7-9 The second portion of the machine-readable instructions represented by the flowchart may be represented by Fig.13 FPGA circuit module 1300 to execute, and / or by Figure 7-9 The third portion of the machine-readable instructions represented by the flowchart may be executed by an ASIC. It should be understood that Figure 1 Some or all of the circuit modules of can therefore be instantiated at the same or different times. For example, some or all of the circuit modules can be instantiated in one or more threads that execute concurrently and / or serially. In addition, in some examples, Figure 1 Some or all of the circuit modules may be implemented within one or more virtual machines and / or containers executed on the microprocessor.

[0110] In some examples, Figure 4 The processor circuit module 1012 may be in one or more packages. For example, Fig.11 The processor circuit module 1100 and / or Fig.12 The FPGA circuit module 1200 may be in one or more packages. In some examples, the XPU may be composed of a Fig.10 The XPU may be implemented by a processor circuit module 1012. For example, the XPU may include a CPU in one package, a DSP in another package, a GPU in still another package, and an FPGA in yet another package.

[0111] Shown is a method for converting Fig.10 A block diagram of an example software distribution platform 1305 of example machine readable instructions 1032 for distributing software to a hardware device owned and / or operated by a third party is provided in Fig.13The example software distribution platform 1305 may be implemented by any computer server, data facility, cloud service, etc. that can store software and transfer software to other computing devices. A third party may be a consumer of an entity that owns and / or operates the software distribution platform 1305. For example, an entity that owns and / or operates the software distribution platform 1305 may be a Fig.10 The third party may be a consumer, user, retailer, OEM, etc. who purchases the software and / or licenses the software for use and / or resale and / or sublicense. In the example shown, the software distribution platform 1305 includes one or more servers and one or more storage devices. The storage device stores the machine-readable instructions 1032, which may correspond to Figure 7-9 The example machine-readable instructions 700 (described above) of the example software distribution platform 1305 are provided. One or more servers of the example software distribution platform 1305 communicate with an example network 1310, which may correspond to any one or more of the Internet and / or any of the example networks described above. In some examples, the one or more servers respond to a request to transfer software to a requesting party as part of a business transaction. Payment for the delivery, sale, and / or license of the software may be processed by the one or more servers of the software distribution platform and / or by a third-party payment entity. The server enables purchasers and / or licensees to download machine-readable instructions 1032 from the software distribution platform 1305. For example, the server may correspond to Figure 7-9 The example machine readable instructions 700 of the example processor platform 1000 may be downloaded to the example processor platform 1000, which is to execute the machine readable instructions 1032 to implement Figure 1 In some examples, one or more servers of the software distribution platform 1305 periodically supply, transmit and / or force updates to the software (e.g., Fig.10 Example machine readable instructions 1032) to ensure that improvements, patches, updates, etc. are distributed and applied to the software at the end-user device.

[0112] From the foregoing, it will be appreciated that example systems, methods, apparatus, and articles of manufacture for processing image frames have been disclosed. The disclosed systems, methods, apparatus, and articles of manufacture improve the efficiency of using a computing device by performing a low-latency range transform on a frame in two scans (a diverging scan and a converging scan). Thus, the disclosed systems, methods, apparatus, and articles of manufacture are directed to one or more improvements in the operation of a machine such as a computer or other electronic and / or mechanical device.

[0113] Example methods, devices, systems, and articles of manufacture for performing video analysis are disclosed herein. Further examples and combinations thereof include the following examples:

[0114] Example 1 includes a device comprising: at least one memory; machine-readable instructions; and a processor circuit module for executing the machine-readable instructions to: generate macroblocks from an image frame, the macroblocks meeting at a convergence point; assign computing units to the macroblocks to process pixels of the macroblocks in parallel; perform a convergent scan of the macroblocks with the computing units, the convergent scan being used to process the pixels of the macroblock starting at a corner opposite to the convergence point and ending at the convergence point; and perform a divergent scan of the macroblock with the computing units, the divergent scan being used to process the pixels of the macroblock starting from the convergence point and ending at the corner opposite to the convergence point.

[0115] Example 2 includes the apparatus described in any of the preceding examples, wherein the processor circuit module is to execute the machine-readable instructions to generate a distance map based on the convergent scan and based on the divergent scan, wherein the convergent scan is used to generate the shortest path from the pixel of the macroblock to the first seed, and the divergent scan is used to generate the shortest path from the pixel of the macroblock to the second seed, the second seed being farther from the vertical and horizontal symmetry axes of the image frame than the first seed.

[0116] Example 3 includes the apparatus of any of the preceding examples, wherein to perform the convergence scan, the processor circuit module is to execute the machine-readable instructions to process the pixels in a plurality of pixel waves, a first wave of the plurality of pixel waves being processed before a second wave of the plurality of pixel waves, the second wave comprising second pixels adjacent to the first wave and sharing a row or column with the first wave, and wherein a final wave of the plurality of pixel waves converges at the convergence point.

[0117] Example 4 includes the device described in any of the preceding examples, wherein, in order to perform the divergent scan, the processor circuit module is to execute the machine-readable instructions to process the pixels in a second plurality of pixel waves, a first wave of the second plurality of pixel waves is to be processed before a second wave of the second plurality of pixel waves, the second wave of the second plurality of pixel waves including second pixels that are adjacent to the first wave, share a row or column with the first wave, and have not yet been processed in the divergent scan.

[0118] Example 5 includes the apparatus described in any of the preceding examples, wherein to perform the convergence scan, the processor circuit module is to execute the machine-readable instructions to: process a first segment of the pixels forming a first line orthogonal to a second line, the second line extending from the convergence point to a corner opposite the convergence point; and process a second segment of the pixels adjacent to the first segment of the pixels and closer to the convergence point.

[0119] Example 6 includes the apparatus of any of the preceding examples, wherein to perform the divergent scan, the processor circuit module is to execute the machine-readable instructions to process a first segment of the pixels forming a straight line, and to process a second segment of pixels adjacent to the first segment of pixels.

[0120] Example 7 includes the device described in any of the preceding examples, wherein the processor circuit module is to execute the machine-readable instructions to perform a low-latency distance transformation by following the divergent scan with the convergent scan, wherein the computing unit is a single instruction multiple data (SIMD) computing unit, the macroblock includes four macroblocks having an equal number of pixels, and wherein the SIMD computing unit processes the pixels in parallel through SIMD computing instructions.

[0121] Example 8 includes a non-transitory computer-readable medium including instructions that, when executed, cause a processor circuit module to: generate macroblocks from an image frame, the macroblocks meeting at a convergence point; assign computing units to the macroblocks to process pixels of the macroblocks in parallel; perform a convergent scan of the macroblocks with the computing units, the convergent scan being used to process pixels of the macroblock starting at a corner opposite to the convergence point and ending at the convergence point; and perform a divergent scan of the macroblock with the computing units, the divergent scan being used to process the pixels of the macroblock starting from the convergence point and ending at the corner opposite to the convergence point.

[0122] Example 9 includes the computer-readable medium described in any of the preceding examples, wherein the instructions, when executed, cause the processor circuit module to generate a distance map based on the converging scan and based on the diverging scan, wherein the converging scan is used to generate the shortest path from the pixels of the macroblock to a first seed, and the diverging scan is used to generate the shortest path from the pixels of the macroblock to a second seed, wherein the second seed is farther from the vertical and horizontal symmetry axes of the image frame than the first seed.

[0123] Example 10 includes the computer-readable medium of any of the preceding examples, wherein the instructions, when executed to perform the convergence scan, cause the processor circuit module to process the pixels in a plurality of pixel waves, a first wave of the plurality of pixel waves being processed before a second wave of the plurality of pixel waves, the second wave including second pixels adjacent to the first wave and sharing a row or column with the first wave, and wherein a final wave of the plurality of pixel waves converges at the convergence point.

[0124] Example 11 includes the computer-readable medium described in any of the preceding examples, wherein the instructions, when executed to perform the diverging scan, cause the processor circuit module to process the pixels in a second plurality of pixel waves, a first wave of the second plurality of pixel waves to be processed before a second wave of the second plurality of pixel waves, the second wave of the second plurality of pixel waves including second pixels that are adjacent to the first wave, share a row or column with the first wave, and have not yet been processed in the diverging scan.

[0125] Example 12 includes the computer-readable medium of any of the preceding examples, wherein the instructions, when executed to perform the convergence scan, cause the processor circuit module to: process a first segment of the pixels that forms a first line orthogonal to a second line, the second line extending from the convergence point to a corner opposite the convergence point; and process a second segment of the pixels that is adjacent to the first segment of the pixels and closer to the convergence point.

[0126] Example 13 includes the computer-readable medium described in any of the preceding examples, wherein the instructions, when executed to perform the divergent scan, cause the processor circuit module to process a first segment of the pixels forming a straight line, and to process a second segment of pixels adjacent to the first segment of pixels.

[0127] Example 14 includes the computer-readable medium described in any of the preceding examples, wherein the instructions, when executed, cause the processor circuit module to perform a low-latency distance transformation by following the divergent scan with the convergent scan, wherein the computing unit is a single instruction multiple data (SIMD) computing unit, the macroblock includes four macroblocks having an equal number of pixels, and wherein the SIMD computing unit processes the pixels in parallel via SIMD computing instructions.

[0128] Example 15 includes a method comprising: generating macroblocks from an image frame by executing instructions with a processor circuit module, the macroblocks meeting at a convergence point; assigning computing units to the macroblocks to process pixels of the macroblocks in parallel by executing instructions with the processor circuit module; performing a convergence scan of the macroblock with the computing units by executing instructions with the processor circuit module, the convergence scan being used to process the pixels of the macroblock starting at a corner opposite to the convergence point and ending at the convergence point; and performing a divergence scan of the macroblock with the computing units by executing instructions with the processor circuit module, the divergence scan being used to process the pixels of the macroblock starting from the convergence point and ending at the corner opposite to the convergence point.

[0129] Example 16 includes the method of any of the preceding examples, further including executing the machine-readable instructions to generate a distance map based on the converging scan and based on the diverging scan, wherein the converging scan is used to generate a shortest path from the pixel of the macroblock to a first seed, and the diverging scan is used to generate a shortest path from the pixel of the macroblock to a second seed, wherein the second seed is farther from the vertical and horizontal symmetry axes of the image frame than the first seed.

[0130] Example 17 includes the method described in any of the preceding examples, further comprising processing the pixels in a plurality of pixel waves, a first wave of the plurality of pixel waves being processed before a second wave of the plurality of pixel waves, the second wave including second pixels adjacent to the first wave and sharing a row or column with the first wave, and wherein a final wave of the plurality of pixel waves converges at the convergence point.

[0131] Example 18 includes the method described in any of the preceding examples, further including executing the machine-readable instructions to process the pixels in a second plurality of pixel waves, a first wave of the second plurality of pixel waves to be processed before a second wave of the second plurality of pixel waves, the second wave of the second plurality of pixel waves including second pixels that are adjacent to the first wave, share a row or column with the first wave, and have not yet been processed in the divergent scan.

[0132] Example 19 includes the method described in any of the preceding examples, further comprising: processing a first segment of the pixels that forms a first line orthogonal to a second line, the second line extending from the convergence point to a corner opposite the convergence point; and processing a second segment of the pixels that is adjacent to the first segment of the pixels and closer to the convergence point.

[0133] Example 20 includes the method of any of the preceding examples, further comprising processing a first segment of the pixels forming a straight line; and processing a second segment of pixels adjacent to the first segment of the pixels.

[0134] Example 21 includes the method described in any of the preceding examples, further including performing a low-latency distance transformation by following the divergent scan after the convergent scan, wherein the computing unit is a single instruction multiple data (SIMD) computing unit, the macroblock includes four macroblocks having an equal number of pixels, and wherein the SIMD computing unit processes the pixels in parallel via SIMD computing instructions.

[0135] The accompanying claims are hereby incorporated by reference into this “Detailed Description.” Although certain example systems, methods, devices, and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, methods, devices, and articles of manufacture that fully fall within the scope of the claims of this patent.

Claims

1. A device comprising: at least one memory; machine-readable instructions; as well as A processor circuit module, the processor circuit module is used to execute the machine-readable instructions to: generating macroblocks from the image frame, the macroblocks meeting at a convergence point; Assigning computing units to the macroblocks to process pixels of the macroblocks in parallel; performing, with the computation unit, a convergence scan of the macroblock, the convergence scan for processing pixels of the macroblock starting at a corner opposite the convergence point and ending at the convergence point; as well as A diverging scan of the macroblock is performed with the computation unit, the diverging scan for processing the pixels of the macroblock starting at the convergence point and ending at the corner opposite the convergence point.

2. The device according to claim 1, wherein: The processor circuit module is to execute the machine-readable instructions to generate a distance map based on the convergent scan and based on the divergent scan, wherein the convergent scan is used to generate a shortest path from the pixels of the macroblock to a first seed, and the divergent scan is used to generate a shortest path from the pixels of the macroblock to a second seed, wherein the second seed is farther from the vertical and horizontal symmetry axes of the image frame than the first seed.

3. The device of claim 1, wherein: To perform the convergence scan, the processor circuit module is to execute the machine-readable instructions to process the pixels in a plurality of pixel waves, a first wave of the plurality of pixel waves being processed before a second wave of the plurality of pixel waves, the second wave comprising second pixels adjacent to the first wave and sharing a row or column with the first wave, and wherein a final wave of the plurality of pixel waves converges at the convergence point.

4. The device of claim 1, wherein: In order to perform the divergent scan, the processor circuit module is to execute the machine-readable instructions to process the pixels in a second plurality of pixel waves, a first wave of the second plurality of pixel waves being processed before a second wave of the second plurality of pixel waves, the second wave of the second plurality of pixel waves including second pixels that are adjacent to the first wave, share a row or column with the first wave, and have not yet been processed in the divergent scan.

5. The device of claim 1, wherein: To perform the convergence scan, the processor circuit module is to execute the machine readable instructions to: processing a first segment of the pixels forming a first line orthogonal to a second line extending from the convergence point to an angle opposite the convergence point; as well as A second segment of the pixels adjacent to the first segment of pixels and closer to the convergence point is processed.

6. The device of claim 1, wherein: To perform the diverging scan, the processor circuit module is to execute the machine readable instructions to process a first segment of the pixels forming a straight line; as well as A second segment of pixels adjacent to the first segment of pixels is processed.

7. The device of claim 1, wherein: The processor circuit module is to execute the machine-readable instructions to perform a low-latency distance transformation by following the divergent scan with the convergent scan, wherein the computing unit is a single instruction multiple data (SIMD) computing unit, the macroblock includes four macroblocks with an equal number of pixels, and wherein the SIMD computing unit processes the pixels in parallel through SIMD computing instructions.

8. A non-transitory computer readable medium comprising instructions which, when executed, cause a processor circuit module to: generating macroblocks from the image frame, the macroblocks meeting at a convergence point; Assigning computing units to the macroblocks to process pixels of the macroblocks in parallel; performing, with the computation unit, a convergence scan of the macroblock, the convergence scan for processing pixels of the macroblock starting at a corner opposite the convergence point and ending at the convergence point; as well as A diverging scan of the macroblock is performed with the computation unit, the diverging scan for processing the pixels of the macroblock starting from the convergence point and ending at the corner opposite to the convergence point.

9. The non-transitory computer readable medium of claim 8, wherein: The instructions, when executed, cause the processor circuit module to generate a distance map based on the converging scan for generating a shortest path from the pixels of the macroblock to a first seed and based on the diverging scan for generating a shortest path from the pixels of the macroblock to a second seed, the second seed being farther from the vertical and horizontal symmetry axes of the image frame than the first seed.

10. The non-transitory computer readable medium of claim 8, wherein: The instructions, when executed to perform the convergence scan, cause the processor circuit module to process the pixels in a plurality of pixel waves, a first wave of the plurality of pixel waves being processed before a second wave of the plurality of pixel waves, the second wave comprising second pixels adjacent to the first wave and sharing a row or column with the first wave, and wherein a final wave of the plurality of pixel waves converges at the convergence point.

11. The non-transitory computer readable medium of claim 8, wherein: The instructions, when executed to perform the divergent scan, cause the processor circuit module to process the pixels in a second plurality of pixel waves, a first wave of the second plurality of pixel waves to be processed before a second wave of the second plurality of pixel waves, the second wave of the second plurality of pixel waves including second pixels that are adjacent to the first wave, share a row or column with the first wave, and have not yet been processed in the divergent scan.

12. The non-transitory computer readable medium of claim 8, wherein: The instructions, when executed to perform the convergence scan, cause the processor circuit module to: processing a first segment of the pixels forming a first line orthogonal to a second line extending from the convergence point to an angle opposite the convergence point; as well as A second segment of the pixels adjacent to the first segment of pixels and closer to the convergence point is processed.

13. The non-transitory computer readable medium of claim 8, wherein: The instructions, when executed to perform the diverging scan, cause the processor circuit module to process a first segment of the pixels forming a straight line; as well as A second segment of pixels adjacent to the first segment of pixels is processed.

14. The non-transitory computer readable medium of claim 8, wherein: The instructions, when executed, cause the processor circuit module to perform a low-latency distance transformation by following the divergent scan with the convergent scan, wherein the computing unit is a single instruction multiple data (SIMD) computing unit, the macroblock includes four macroblocks with an equal number of pixels, and wherein the SIMD computing unit processes the pixels in parallel through SIMD computing instructions.

15. A method comprising: generating macroblocks from an image frame by executing instructions with a processor circuit module, the macroblocks meeting at a convergence point; Assigning computing units to the macroblocks by executing instructions with the processor circuit module to process pixels of the macroblocks in parallel; performing, with the computation unit, a convergence scan of the macroblock by executing instructions with the processor circuit module, the convergence scan for processing pixels of the macroblock starting at a corner opposite to the convergence point and ending at the convergence point; as well as By executing instructions with the processor circuit module, a diverging scan of the macroblock is performed with the computing unit, the diverging scan being used to process the pixels of the macroblock starting from the convergence point and ending at the corner opposite to the convergence point.

16. The method of claim 15, further comprising executing the machine-readable instructions to generate a distance map based on the convergent scan and based on the divergent scan, wherein the convergent scan is used to generate a shortest path from the pixel of the macroblock to a first seed, and the divergent scan is used to generate a shortest path from the pixel of the macroblock to a second seed, wherein the second seed is farther from the vertical and horizontal symmetry axes of the image frame than the first seed.

17. The method of claim 15, further comprising processing the pixels in a plurality of pixel waves, a first wave of the plurality of pixel waves being processed before a second wave of the plurality of pixel waves, the second wave comprising second pixels adjacent to the first wave and sharing a row or column with the first wave, and wherein a final wave of the plurality of pixel waves converges at the convergence point.

18. The method of claim 15, further comprising executing the machine-readable instructions to process the pixels in a second plurality of pixel waves, a first wave of the second plurality of pixel waves to be processed before a second wave of the second plurality of pixel waves, the second wave of the second plurality of pixel waves comprising second pixels that are adjacent to the first wave, share a row or column with the first wave, and have not yet been processed in the divergent scan.

19. The method of claim 15, further comprising: processing a first segment of the pixels forming a first line orthogonal to a second line extending from the convergence point to a corner opposite the convergence point; and A second segment of the pixels adjacent to the first segment of pixels and closer to the convergence point is processed.

20. The method of claim 15, further comprising processing a first segment of the pixels forming a straight line; and A second segment of pixels adjacent to the first segment of pixels is processed.

21. The method of claim 15, further comprising performing a low-latency distance transformation by following the divergent scan after the convergent scan, wherein the computing unit is a single instruction multiple data (SIMD) computing unit, the macroblock includes four macroblocks with an equal number of pixels, and wherein the SIMD computing unit processes the pixels in parallel through SIMD computing instructions.

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