Communication device and communication system

Abstract

[Problem] To reduce the memory capacity for storing address information and the like of an I2C communication device and the number of encoders and decoders. [Solution] A communication apparatus for establishing communication between a first I2C communication apparatus and a second I2C communication apparatus connected to a communication partner apparatus, the communication apparatus comprising: an encoder that generates header packet data containing a target ID of the communication partner apparatus and I2C packet data containing a slave address and an offset address of the second I2C communication apparatus; a communication unit that transmits a transmission packet including header packet data and I2C packet data generated by the encoder to a communication partner device by a TDD communication scheme, and receives a reception packet from the communication partner device by the TDD communication scheme; and a decoder that generates I2C packet data from the received packet.

Description

Technical Field

[0001] The present disclosure relates to a communication device and a communication system. Background Art

[0002] A technology for establishing high-speed serial communication between a plurality of devices has been proposed (Patent Document 1). This type of high-speed serial communication is used in various fields, and is used for communication between vehicle-mounted devices, for example.

[0003] Prior art literature

[0004] [Patent Document]

[0005] [Patent Document 1]

[0006] JP 2011-239011A Summary of the invention

[0007] [Technical issues]

[0008] With the development of autonomous driving technology and electronic technology, the demand for high-speed communication between vehicle-mounted devices is increasing. The Automotive SerDes Alliance (ASA) assumes that high-speed serial communication is established between a root (100) connected to a cable (hereinafter, referred to as root (100)) and a leaf device (hereinafter, referred to as leaf) through a time division duplex (TDD) communication scheme.

[0009] For example, a conceivable configuration of the communication system allows the root (100) to perform I2C communication with the CPU (110), and allows the leaf to perform I2C communication with the camera, and allows the root (100) and the leaf to perform high-speed serial communication compliant with the ASA standard.

[0010] In the case where multiple I2C communication devices are connected to the leaves, the root (100) may include an encoder and a decoder for each I2C communication device, so that high-speed serial communication can be established between the root (100) and the leaves, and I2C communication can be established with multiple I2C communication devices connected to the leaves.

[0011] However, providing multiple encoders and decoders for each leaf increases the size of the root (100). In addition, it is necessary to ensure storage space for storing data transmitted and received for each leaf in the root (100), and as the number of connected leaves increases, the storage capacity increases.

[0012] Therefore, the present invention provides a communication device and a communication system that do not require an increase in storage capacity for storing data sent and received for each leaf, and do not require an increase in the number of encoders and decoders, even if the number of leaves connected to a root increases.

[0013] [Solution to the problem]

[0014] According to an embodiment of the present disclosure, the present disclosure provides a communication device configured to establish communication between a first I2C communication device and a second I2C communication device connected to a communication counterpart device, the communication device comprising:

[0015] an encoder that generates header packet data including a target ID of a communication partner device and I2C packet data including a slave address and an offset address of a second I2C communication device;

[0016] a communication unit that transmits a transmission packet including header packet data generated by the encoder and I2C packet data to a communication counterpart device through a time division duplex (TDD) communication scheme, and receives a reception packet from the communication counterpart device through the TDD communication scheme; and

[0017] Decoder, generates I2C packet data from received packets.

[0018] The header packet data may include a plurality of destination IDs corresponding to a plurality of communication partner devices.

[0019] The storage space in which the header packet data and the I2C packet data are stored may include a storage space for communicating with a communication counterpart device.

[0020] The header packet data may contain four target IDs compliant with the Automotive SerDes Alliance (ASA) standard.

[0021] The encoder and the decoder may be set to be shared by a plurality of communication partner devices corresponding to a plurality of target IDs.

[0022] The memory in which the header packet data and the I2C packet data are stored may have a plurality of storage spaces, each storage space having a fixed length, for storing a plurality of target IDs included in the header packet data, and

[0023] Invalid IDs may be stored in a storage space corresponding to an unused target ID.

[0024] The header packet data may include variable length data including information indicating the number of valid target IDs, and wherein the valid target IDs are arranged after the information.

[0025] The header packet data may contain a target code specifying a combination of multiple target IDs.

[0026] The target code may include bit string data having a fixed length.

[0027] The target code may include 4 bits of data and specify a combination of four target IDs.

[0028] The memory storing therein the header packet data and the I2C packet data may store at least any one of the I2C configuration data including the operation setting of the second I2C communication device and the I2C data of the second I2C communication device as the I2C packet data.

[0029] The present disclosure provides a communication system, comprising:

[0030] A first communication device connected to a first I2C communication device; and

[0031] a second communication device connected to a second I2C communication device and alternately sending information to and receiving information from the first communication device within an allocated time period through a time division duplex (TDD) communication scheme, wherein:

[0032] The first communication device comprises:

[0033] a first encoder, generating a header packet data including a target ID of the second communication device and an I2C packet data including a slave address and an offset address of the second I2C communication device,

[0034] a communication unit that transmits a transmission packet including header packet data and I2C packet data generated by the first encoder to a second communication device through a time division duplex (TDD) communication scheme, and receives a reception packet from the second communication device through the TDD communication scheme; and

[0035] The first decoder generates I2C packet data from the received packet.

[0036] The second communication device may include:

[0037] a second encoder, generating header packet data including a target ID of the first communication device and I2C packet data including a slave address and an offset address of the first I2C communication device;

[0038] a communication unit that transmits a transmission packet including header packet data and I2C packet data generated by a second encoder to a first communication device through a time division duplex (TDD) communication scheme, and receives a reception packet from the first communication device through the TDD communication scheme; and

[0039] The second decoder generates I2C packet data from the received packet.

[0040] The second I2C communication device may further include an I2C slave unit to which the I2C master unit is connected via the I2C bus.

[0041] A plurality of second communication devices may be connected via a daisy chain, and

[0042] The header packet data may be divided into a plurality of groups, and each group may include a plurality of target IDs in compliance with the Automotive SerDes Alliance (ASA) standard.

[0043] A plurality of second communication devices may be connected via a daisy chain, and

[0044] The header packet data may include a bit string indicating a combination of a group number of a group and specifying a plurality of target IDs.

[0045] The present disclosure provides a communication device, which is configured to establish communication between a first I2C communication device and a second I2C communication device based on I2C configuration data sent from a communication partner device connected to a first I2C communication device, and the communication device includes:

[0046] an encoder that generates header packet data including a target ID of a communication partner device and I2C packet data including a slave address and an offset address of the first I2C communication device;

[0047] a communication unit that transmits a transmission packet including header packet data generated by the encoder and I2C packet data to a communication counterpart device through a time division duplex (TDD) communication scheme, and receives a reception packet from the communication counterpart device through the TDD communication scheme; and

[0048] The decoder generates I2C packet data from the received packet, where

[0049] The second I2C communication device further includes an I2C slave unit, and the I2C master unit is connected to the I2C slave unit via an I2C bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 is a block diagram showing a schematic configuration of a communication system according to the present disclosure.

[0051] Figure 2 is a diagram showing information stored in a leaf's ASEP register.

[0052] Figure 3 It shows Figure 1 A diagram of the memory map of the internal memory in .

[0053] Figure 4 is an explanatory diagram showing a processing operation of an information processing apparatus according to a basic mode of the present disclosure.

[0054] Figure 5 It shows that Figure 4 This figure illustrates the subsequent processing operations.

[0055] Figure 6 It shows that Figure 5This figure illustrates the subsequent processing operations.

[0056] Figure 7 It shows that Figure 6 This figure illustrates the subsequent processing operations.

[0057] Figure 8 It shows that Figure 7 This figure illustrates the subsequent processing operations.

[0058] Fig. 9 It shows that Figure 8 This figure illustrates the subsequent processing operations.

[0059] Fig.10 It shows that Fig. 9 This figure illustrates the subsequent processing operations.

[0060] Fig.11 It shows that Fig.10 This figure illustrates the subsequent processing operations.

[0061] Fig.12 It shows that Fig.11 This figure illustrates the subsequent processing operations.

[0062] Fig.13 It shows that Fig.12 This figure illustrates the subsequent processing operations.

[0063] Fig.14 is a data flow diagram showing the writing of I2C configuration data in basic mode.

[0064] Fig.15 is a data flow diagram showing I2C data writing for controlling the CIS in basic mode.

[0065] Fig.16 is a block diagram showing a schematic configuration of a communication system according to the first embodiment.

[0066] Fig.17 is a diagram showing a memory mapping table of an internal memory according to the first embodiment.

[0067] Fig.18 1 is an explanatory diagram showing a processing operation of the information processing apparatus according to the first embodiment.

[0068] Fig.19 It shows that Fig.18 This figure illustrates the subsequent processing operations.

[0069] Fig. 20 It shows that Fig.19 This figure illustrates the subsequent processing operations.

[0070] Fig.21It shows that Fig. 20 This figure illustrates the subsequent processing operations.

[0071] Fig. 22 is a data flow diagram showing writing of I2C configuration data according to the first embodiment.

[0072] Fig.23 : is a data flow chart showing a method for controlling writing of I2C data of the CIS according to the first embodiment.

[0073] Fig.24 is a diagram showing a portion of information stored in the ASEP register of the root according to the second embodiment.

[0074] Fig.25 is a diagram showing the correspondence between target codes and target IDs.

[0075] Fig.26 is a diagram showing the format of data written in the internal memory.

[0076] Fig. 27 is an explanatory diagram showing a processing operation of the information processing apparatus according to the second embodiment.

[0077] Fig.28 It shows that Fig. 27 This figure illustrates the subsequent processing operations.

[0078] Fig.29 It shows that Fig.28 This figure illustrates the subsequent processing operations.

[0079] Fig.30 is a data flow diagram showing writing of I2C configuration data according to the second embodiment.

[0080] Fig.31 : is a data flow chart showing a method for controlling writing of I2C data of the CIS according to the second embodiment.

[0081] Fig.32 is a block diagram showing a schematic configuration of a communication system applicable to the first embodiment and the second embodiment.

[0082] Fig.33 : is a diagram showing a part of information stored in the ASEP register of a leaf according to the third embodiment.

[0083] Fig.34 is a diagram showing the correspondence between the group number, the target code, and the target ID.

[0084] Fig.35 It is shown in Fig.29Block diagram of a configuration in which multiple cameras are connected via a daisy chain between camera A and camera B.

[0085] Fig.36 is shown corresponding to Fig.35 Diagram of the configured I2C address register. DETAILED DESCRIPTION

[0086] Hereinafter, embodiments of the communication device and the communication system will be described with reference to the accompanying drawings. Although the main components of the communication device and the communication system will be mainly described below, the communication device and the communication system may have components and functions not shown or described. The following description does not exclude components and functions not shown or described.

[0087] (Basic mode of communication system)

[0088] Figure 1 is a block diagram showing a schematic configuration of a communication system according to the present disclosure. Figure 1 The communication system shown in is an in-vehicle communication system, and includes an ECU (10) and two cameras A (20) and B (40) connected by a daisy chain.

[0089] The ECU (10) includes a CPU (110), an I2C master #1 (111), an I2C slave #1 (121), an internal memory (mem #1 (131)), and a DLL (root) (150). The root (100) includes a plurality of encoders (ASE (142, 146)), a plurality of decoders (ASD (141, 145)), an ASEP register (ASEP Regs (140) (144)), a DLL (150), and a PhyL (160).

[0090] Camera A (20) includes DLL (leaf) (250), I2C host #3 (221), internal memory (mem #3) (231), ASA node #2 (200), CMOS image sensor (CIS) #4 (401), internal memory (mem #4) (431), I2C slave #4 (421), CMOS image sensor (CIS) #5 (402), internal memory (mem #5) (432) and I2C slave #5 (422).

[0091] Leaf (200) includes an ASEP register (ASEP Reg (240)), an encoder (ASE (242)), a decoder (ASD (241)), a DLL (250), an OAM (255), a register (Reg (256)), and a PhyL (260). ASA node #3 (300) includes a DLL (350), a branch function (351), and a PhyL (360).

[0092] Camera B (40) includes leaf (500), I2C master #6, internal memory (mem#6), CMOS image sensor (CIS) #7, internal memory (mem#7), I2C slave #7, CMOS image sensor (CIS) #8, internal memory (mem#8) and I2C slave #8.

[0093] Leaf (500) includes an ASEP register (ASEP Reg (540)), an encoder (ASE (542)), a decoder (ASD (541)), a DLL (550), an OAM (555), a register (Reg (556)), and a PhyL (560).

[0094] like Figure 1 As shown, the communication system according to the present disclosure includes a root (100) and a leaf (200)(500), which performs high-speed serial communication in accordance with the ASA standard. Hereinafter, the root (100) may be referred to as node #1, the leaf (200) may be referred to as node #2, and the leaf (500) may be referred to as node #5.

[0095] Before I2C communication starts, I2C configuration data is written into the ASEP register (240) in the leaf (200) and the ASEP register (540) in the node 5 (500). The I2C configuration data includes the I2C CLK rate indicating the operating speed of the I2C bus, the slave address to be managed, and flag information indicating the relationship between the offset address length handled by the slave address.

[0096] Figure 2 is a diagram showing information stored in the ASEP register (I2C address register) (540) in the leaf (500). Figure 2 In the ASEP register (540), the slave address (7'h52) is assigned to the ASEP register (540). The offset address (200) stores therein a value (4'h4) indicating the I2C CLK rate (400kHz) at which the I2C bus (51) should operate, and the offset address (207) stores therein a slave address (7'h47) as a slave address managed by the ASA node 5 (500), flag information indicating that the offset address is 16 bits, the slave address (7'h48), and flag information (1'b0) indicating that its offset address is 8 bits.

[0097] In ASAV1.01, the CPU (110) in the ECU (10) obtains access to the internal memory #1 (131) via the I2C master (111) and the I2C slave (121). The internal memory #1 (131) is a memory map divided into a plurality of address areas, and each address area can access a different block.

[0098] Figure 3 It shows Figure 1 Figure 1 shows the memory map of the internal memory (mem#1) in . Figure 3 As shown, the I2C host #1 (111) writes the I2C packet data as the source of the I2C packet into each address area of ​​the internal memory #1 (131). Therefore, the relationship between the node (ASA node #2, ASA node #5) of the leaf (200) (500) and the slave address under its control is configured to be managed in the address area of ​​the internal memory #1 (131).

[0099] exist Figure 3 In the example, the address area ((0x0000-0xFFF) is an area in which communication with the ASA node #2 (200) is performed, and the address area (0x2000-0x2FFF) is an area in which communication with the ASA node #5 (500) is performed.

[0100] ASD (141) and ASE (142) perform I2C communication with ASA node #2 (200) using the address area (0x0000-0xFFF). ASD (145) and ASE (146) perform I2C communication with ASA node #5 (500) using the address area (0x2000-2xFFF). In addition, OAM (155) uses the address area (0x4000-0x4FFF).

[0101] Figures 4 to 13 is an explanatory diagram showing a processing operation of an information processing apparatus according to a basic mode of the present disclosure. Figures 4 to 13 Steps 1 to 16 are shown in the order in which the processing in the information processing apparatus is executed.

[0102] like Figure 3 As shown, since the I2C host #1 (111) should divide the address area of ​​the internal memory #1 (131) for each ASA node as a transmission destination before use, the utilization efficiency of the internal memory #1 (131) is deteriorated. For example, there is a problem that the amount of transmission data immediately transmitted by I2C is limited by the address area allocated in the internal memory #1 (131), and therefore, it is difficult to effectively use the memory space.

[0103] In addition, if Figure 3 As shown, it is necessary to provide ASE / ASD of the ASA node corresponding to each address area in the internal memory #1 (131), and there is a problem that the number of circuits as the root (100) of the ASA node #1 increases.

[0104] In ASA draft V1.01, the CPU (110) in the ECU (10) obtains access to the internal memory #1 (131) via the I2C master (111) and the I2C slave (121). Figure 3 As shown in FIG. 1 , the internal memory #1 (131) is a memory map divided into a plurality of address areas, and each address area can access a different block. For example, when the ECU (10) transmits control data of the CIS #7 (601) built in the camera B (50) to the internal memory #7 (631) through I2C communication, Figure 2 As shown, first, the CPU (110) needs to write the I2C CLK rate of the I2C bus (51) containing the camera B (50), the slave address processed by the ASA node #5 (500) and the I2C configuration data with the flag of the offset address length (8 bits / 16 bits) into the ASEP register (540).

[0105] Fig.14 is a data flow diagram showing the writing of I2C configuration data in basic mode. Figure 4 Step 1 in the above process includes three processing steps: step 1-1, step 1-2 and step 1-3. In step 1-1, the CPU (110) instructs the I2C master #1 (111) to write the I2C packet data including the I2C configuration data of the ASEP register (540) into the internal memory #1 (131) of the I2C slave #1 (121) ( Fig.14 (11-1)).

[0106] Next, in step 1-2, the I2C master #1 (111) sends the I2C packet data accompanied by the write address (0x2000) for the internal memory #1 (131) to the slave address (7'h41) of the I2C slave #1 (121) ( Fig.14 (11-1)).

[0107] Next, in step 1-3, the I2C slave #1 (121) writes the received I2C packet data into the internal memory #1 (131).

[0108] Figure 4 Step 2 in the above process includes three processing steps: step 2-1, step 2-2, and step 2-3. In step 2-1, once the I2C packet data is written into the internal memory #1 (131), the ASE (146) reads the I2C packet data, converts the I2C packet data into an I2C packet of the ASA, and sends the I2C packet to the DLL (150).

[0109] In step 2-2, the DLL (150) adds a header packet of the ASA node #1 as a transmission source and the ASA node #5 as a transmission destination to the I2C packet received from the ASE (146), and transmits the container (30-1) to the PhyL (160).

[0110] In step 2-3, PhyL (160) sends the container (30-1) to the opposite ASA node #2 (200) via ASA (30).

[0111] Figure 5 Step 3 in includes five processing steps: steps 3-1, 3-2, 3-3, 3-4 and 3-5. In step 3-1, the PhyL (260) in the ASA node #2 (200) recovers the received container (30-1) and sends the container (30-1) to the DLL (250).

[0112] In step 3-2, DLL (250) checks the header packet in the received container (30-1), determines that the container (30-1) is an I2C packet addressed to ASA node #5, and sends the container (30-1) to the branch function unit (351) as it is.

[0113] In step 3-3, the branch function unit (351) sends the received container (30-1) to the DLL (350).

[0114] In step 3-4, the DLL (350) sends the received container (30-1) as it is to the PhyL (360).

[0115] In step 3-5, PhyL (360) sends the received container (30-1) as container (40-1) to the opposite ASA node #5 (500) via ASA (40).

[0116] Figure 5 Step 4 in includes three processing steps: step 4-1, step 4-2 and step 4-3. In step 4-1, the PhyL (560) in the ASA node #5 (500) recovers the received container (40-1) and sends the container (40-1) to the DLL (550).

[0117] In step 4-2, DLL (550) checks the header packet in the received container (40-1), determines that the container (40-1) is an I2C packet addressed to ASA node #5, and sends the I2C packet to the corresponding ASD (541). In addition, DLL (550) maintains ASA node #1 as the transmission source contained in the received header packet.

[0118] In step 4-3, the ASD (541) recovers the original I2C packet data from the received I2C packet, and the ASD (541) analyzes the recovered I2C packet data and writes the I2C configuration data into the ASEP register (540) which is addressed to the slave address (7'h52) ( Figure 2 and Fig.14 (50-1)).

[0119] ASD (541) also writes I2C configuration data into internal memory #6 (531) so that I2C host #6 (521) sets the I2C operating speed of the I2C bus (51).

[0120] Furthermore, the I2C master #6 (521) can understand whether the offset address length of the slave address to be managed is 8 bits or 16 bits.

[0121] Figure 6 Step 5 in the above process includes three processing steps: Steps 5-1, 5-2, and 5-3. In Step 5-1, each time the ASD (541) writes the I2C configuration data in the ASEP register (540), the ASE (542) generates an ACK / NACK as a writing result, and converts the ACK / NACK into an ACK / NACK data packet in the ASA. The ASE (542) sends an I2C packet (542) obtained by adding a packet of the slave address as the writing destination to a packet of the ACK / NACK data to the DLL (550). Fig.14 (50-2)).

[0122] In step 5-2, the DLL (550) adds a header packet of the ASA node #5 as a transmission source and the ASA node #1 as a transmission destination to the I2C packet received from the ASE (542), and transmits the container (40-2) to the PhyL (560).

[0123] In step 5-3, the PhyL (560) sends the container (40-2) to the opposite ASA node #3 (300) via the ASA (40).

[0124] Figure 6 Step 6 in includes five processing steps: steps 6-1, 6-2, 6-3, 6-4 and 6-5. In step 6-1, the PhyL (360) in the ASA node #3 (300) recovers the received container (40-2) and sends the container (40-2) to the DLL (350).

[0125] In step 6-2, DLL (350) checks the header packet in the received container (40-2), determines that container (40-2) is an I2C packet addressed to ASA node #1, and sends container (40-2) to branch function unit (351) as is.

[0126] In step 6-3, the branch function unit (351) sends the received container (40-2) to the DLL (250).

[0127] In step 6-4, the DLL (250) sends the received container (40-2) to the PhyL (260) as it is.

[0128] In step 6-5, the PhyL (260) sends the received container (40-2) as container (30-2) to the opposite ASA node #1 (100) via the ASA (30).

[0129] Figure 7 Step 7 in includes six processing steps: steps 7-1, 7-2, 7-3, 7-4, 7-5 and 7-6. In step 7-1, the PhyL (160) in the ASA node #1 (100) recovers the received container (30-2) and sends the container (30-2) to the DLL (150).

[0130] In step 7-2, the DLL (150) checks the header packet in the received container (30-2), determines that the container (30-2) is an I2C packet addressed to the ASA node #1, and sends the I2C packet to the corresponding ASD (145).

[0131] In step 7-3, the ASD (145) restores the original I2C packet data from the received I2C packet, and the ASD (145) writes the restored I2C packet data at and after the write address (0x2800) of the internal memory #1 (131).

[0132] In step 7-4, the CPU (110) periodically issues a read command to the I2C master #1 (111) to check whether ACK / NACK data as a result of writing the I2C configuration data has been written into the internal memory #1 (131) of the I2C slave #1 (121).

[0133] In step 7-5, the I2C master #1 (111) reads the I2C packet data accompanied by the read address (0x2800) for the internal memory #1 (131) to the slave address (7'h41) of the I2C slave #1 (121) ( Fig.14 (11-2)).

[0134] In step 7-6, the CPU (110) checks the I2C packet data ( Fig.14 (12-2) in (12-2)) to check whether the I2C configuration data has been written into the ASEP register (540) in the ASA node #5 (500).

[0135] In ASAV1.01, the CPU (110) in the ECU (10) obtains access to the internal memory #1 (131) via the I2C master (111) and the I2C slave (121). Figure 3 As shown, the internal memory #1 (131) is a memory map divided into a plurality of address areas, and each address area can access a different block.

[0136] For example, in the above steps 1 to 7, when the I2C configuration data has been written into the ASEP register (540), and the ECU (10) sends the control data of the CIS #7 (601) built into the camera B (50) to the internal memory #7 (631) via the I2C communication, the execution Figure 8 The processing in step 8 in . Figure 8 Step 8 in includes three processing steps: steps 8-1, 8-2, and 8-3.

[0137] Fig.15 8-1, the CPU (110) instructs the I2C master #1 (111) to write the I2C packet data containing the control data of the CIS #7 (601) into the internal memory #1 (131) of the I2C slave #1 (121) ( Fig.15 (11-3)).

[0138] The I2C packet data includes the slave address (7'h47) of the I2C slave #7 (621) and the offset address of the internal memory #7 (631).

[0139] In step 8-2, the I2C master #1 (111) sends the I2C packet data accompanied by the write address (0x2000) for the internal memory #1 (131) to the slave address (7'h41) of the I2C slave #1 (121) ( Fig.15 (11-3)).

[0140] Next, in step 8-3, the I2C slave #1 (121) writes the received I2C packet data into the internal memory #1 (131).

[0141] Fig. 9Step 9 in the above process includes three processing steps: Step 9-1, 9-2 and 9-3. Step 9-1: After the I2C header data is written into the internal memory #1 (131), the ASE (146) reads the I2C header data, converts it into an I2C header of the ASA, and sends it to the DLL (150).

[0142] In step 9-2, the DLL (150) adds the header packets of the ASA node #1 as the transmission source and the ASA node #5 as the transmission destination to the I2C packet received from the ASE (146), and transmits the container (30-3) to the PhyL (160).

[0143] In step 9-3, PhyL (160) transmits container (30-3) to opposite ASA node #2 (200) via ASA (30).

[0144] Fig. 9 Step 10 in includes five processing steps: steps 10-1, 10-2, 10-3, 10-4 and 10-5. In step 10-1, the PhyL (260) in the ASA node #2 (200) recovers the received container (30-3) and sends the container (30-3) to the DLL (250).

[0145] In step 10-2, DLL (250) checks the header packet in the received container (30-3), determines that the container (30-3) is an I2C packet addressed to ASA node #5, and sends the container (30-3) to the branch function unit (351) as it is.

[0146] In step 10-3, the branch function unit (351) sends the received container (30-3) to the DLL (350).

[0147] In step 10-4, the DLL (350) sends the received container (30-3) to the PhyL (360) as it is.

[0148] In step 10-5, PhyL (360) transmits the received container (30-3) as container (40-3) to the opposite ASA node #5 (500) via ASA (40).

[0149] Fig.10 Step 11 in includes three processing steps: steps 11-1, 11-2, and 11-3. In step 11-1, the PhyL (560) in the ASA node #5 (500) recovers the received container (40-3) and sends the container (40-3) to the DLL (550).

[0150] In step 11-2, DLL (550) checks the header packet in the received container (40-3), determines that the container (40-3) is an I2C packet addressed to ASA node #5, and sends the I2C packet to the corresponding ASD (541). In addition, DLL (550) maintains ASA node #1 as the transmission source contained in the received header packet.

[0151] In step 11-3, the ASD (541) restores the original I2C packet data from the received I2C packet, and the ASD (541) analyzes the restored I2C packet data and determines that the I2C packet data is CIS control data addressed to the slave address (7'h47). The ASD (541) writes the restored I2C packet data to the internal memory #6 (531) ( Fig.15 (53-3)).

[0152] Fig.10 Step 12 in the above process includes three processing steps: steps 12-1, 12-2 and 12-3. In step 12-1, the I2C host #6 (521) reads the I2C packet data written in the internal memory #6 (531), and sends the I2C packet data as an I2C signal to the I2C bus (51) ( Fig.15 (51-3)).

[0153] In step 12-2, the I2C slave #7 (621) receives the I2C signal addressed to the slave address (7'h 47), and writes the received control data of the CIS #7 (601) into the internal memory #7 (631) ( Figure 6 (52-3)). Fig.16 (52-3))

[0154] In step 12-3, CIS #7 (601) reads the control data written in internal memory #7 (631).

[0155] Fig.11 Step 13 in the embodiment includes step 13-1. In step 13-1, each time the I2C slave #7 (621) writes control data to the internal memory #7 (631) in step 12-2, the I2C slave #7 (621) returns ACK / NACK to the I2C master #6 (521). The I2C master #6 (521) writes the received ACK / NACK to the internal memory #6 (531).

[0156] Fig.11Step 14 in the embodiment includes three processing steps: steps 14-1, 14-2, and 14-3. In step 14-1, once the writing of ACK / NACK in the internal memory #6 (531) is completed, the ASE (542) reads the ACK / NACK data. The ASE (542) converts the ACK / NACK data into an I2C packet of the ASA obtained by adding a packet of the slave address as the transmission source to the packet of the ACK / NACK data, and transmits the packet to the DLL (550) ( Fig.15 (53-4)).

[0157] In step 14-2, the DLL (550) attaches the header packet of the ASA node #5 as the transmission source and the ASA node #1 as the transmission destination to the I2C packet received from the ASE (542), and transmits the container (40-4) to the PhyL (560).

[0158] In step 14-3, the PhyL (560) sends the container (40-4) to the opposite ASA node #3 (300) via the ASA (40).

[0159] Fig.12 Step 15 in includes five processing steps: steps 15-1, 15-2, 15-3, 15-4 and 15-5. In step 15-1, the PhyL (360) in the ASA node #3 (300) recovers the received container (40-4) and sends the container (40-4) to the DLL (350).

[0160] In step 15-2, DLL (350) checks the header packet in the received container (40-4), determines that container (40-4) is an I2C packet addressed to ASA node #1, and sends container (40-4) to branch function unit (351) as is.

[0161] In step 15-3, the branch function unit (351) sends the received container (40-4) to the DLL (250).

[0162] In step 15-4, the DLL (250) sends the received container (40-4) to the PhyL (260) as it is.

[0163] In step 15-5, the PhyL (260) transmits the received container (40-4) as a container (30-4) to the opposite ASA node #1 (100) via the ASA (30).

[0164] Fig.13Step 16 in includes six processing steps: steps 16-1, 16-2, 16-3, 16-4, 16-5 and 16-6. In step 16-1, the PhyL (160) in the ASA node #1 (100) recovers the received container (30-4) and sends the container (30-4) to the DLL (150).

[0165] In step 16-2, the DLL (150) checks the header packet in the received container (30-4), determines that the container (30-4) is an I2C packet addressed to the ASA node #1, and sends the I2C packet to the corresponding ASD (145).

[0166] In step 16-3, the ASD (145) restores the original I2C packet data from the received I2C packet, and the ASD (145) writes the restored I2C packet data at and after the write address (0x2800) of the internal memory #1 (131).

[0167] In step 16-4, the CPU (110) periodically issues a read command to the I2C master #1 (111) to check whether ACK / NACK data as a result of writing the control data of the CIS #7 has been written into the internal memory #1 (131) of the I2C slave #1 (121).

[0168] In step 16-5, the I2C master #1 (111) reads the I2C packet data accompanied by the read address (0x2800) for the internal memory #1 (131) to the slave address (7'h41) of the I2C slave #1 (121) ( Fig.15 (11-4)).

[0169] In step 16-6, the CPU (110) checks the I2C packet data read by the I2C master #1 (111) to check whether the control data of the CIS #7 has been successfully written into the internal memory #7 (631) of the I2C slave #7 (621) ( Fig.15 In (12-4)).

[0170] (First Embodiment)

[0171] Fig.16 1 is a block diagram showing a schematic configuration of a communication system according to a first embodiment. The communication system according to the first embodiment includes an ECU (10) and two cameras A (20) and B (40) connected by a daisy chain, such as Fig.16 shown.

[0172] The ECU (10) includes a root (100), a CPU (110), an I2C master #1 (111), an I2C slave #1 (121), and an internal memory (mem#1) (131). The root (100) includes an encoder (ASE (142)), a decoder (ASD (141)), an ASEP register (ASEP Reg (140)), a DLL (150), and a PhyL (160). The internal memory (mem#1) (131) can be set inside the root (100).

[0173] Fig.16 The internal configuration of the root (100) according to the first embodiment is shown in FIG. Figure 1 The internal configuration of the root (100) in is partially different. Specifically, Fig.16 The root (100) is not included in Figure 1 The root (100) in FIG. 1 includes ASEP Reg (144), ASD (145) and ASE (146). In addition to this, Fig.16 The configuration of the communication system in Figure 1 The configuration of the communication system in is the same.

[0174] In the first embodiment, the CPU (110) in the ECU (10) obtains access to the internal memory #1 (131) via the I2C master (111) and the I2C slave (121).

[0175] Fig.17 1 is a diagram showing a memory map of the internal memory #1 (131) according to the first embodiment. The internal memory #1 (131) is a memory map shared by all ASA nodes. Therefore, the I2C host #1 (111) inserts the header packet data ( Fig.17 (1) in the I2C packet data and the I2C packet data as the source of the I2C packet ( Fig.17 (2)) in is written into the address area of ​​internal memory #1 (131).

[0176] Note that, in the event that there are multiple destination ASA nodes #, the header packet data contains multiple “destination ASA node IDs.” More specifically, the header packet data contains four destination IDs that conform to the Automotive SerDes Alliance (ASA) standard.

[0177] like Fig.17 As shown, the header packet data according to the first embodiment may be data with a fixed length in which an invalid ID is assigned to an unused node ID among four target IDs.

[0178] Alternatively, the header packet data may be data having a variable length, in which information indicating the number of valid target IDs is added to a header of the header packet, and then valid target IDs are allocated.

[0179] Therefore, in the first embodiment, the relationship between the node (ASA node #2, ASA node #5) of Leaf (200) (500) and the Slave address under its control is not managed in the address area of ​​the internal memory #1 (131). In the first embodiment, the address area (0x0000-0xFFF) is an area for establishing communication with the opposite ASA node.

[0180] ASD (141) and ASE (142) use the address area (0x0000-0xFFF) to generate and decompose packets for performing I2C communication with the opposite ASA node. In addition, OAM (155) uses the address area (0x1000-0x1FFF).

[0181] As described above, in the first embodiment, the relationship between the leaf node and the slave addresses under its control is managed as data in the internal memory #1 (131), and therefore, ASE / ASD of each ASA node is not required. Figure 1 Compared with the internal memory #1 (131) in the memory, the memory capacity can be reduced.

[0182] In the first embodiment, the CPU (110) in the ECU (10) obtains access to the internal memory #1 (131) via the I2C master (111) and the I2C slave (121).

[0183] like Fig.17 As shown, the internal memory #1 (131) according to the first embodiment is a memory map shared by the ASA nodes.

[0184] For example, when the ECU (10) sends control data of the CIS #7 (601) built into the camera B (50) to the internal memory #7 (631) via I2C communication, the CPU (110) first needs to write the I2C configuration data into the ASEP register (540) ( Figure 2 ), the I2C configuration data includes the I2C CLK rate of the I2C bus (51) of camera B (50) and the slave address processed by ASA node #5 (500) and having a flagged offset address length (8 bits / 16 bits).

[0185] Figures 18 to 21 1 and 2 are explanatory diagrams each showing a processing operation of the information processing apparatus according to the first embodiment. Figures 18 to 21Steps 1, 2, 7, 8, 9, and 16 are shown in the order in which the processing in the information processing device is executed. Figures 4 to 13 The processing in is similar.

[0186] Fig. 22 is a data flow diagram showing writing of I2C configuration data according to the first embodiment. Fig.23 : is a data flow chart showing a method for controlling writing of I2C data of the CIS according to the first embodiment.

[0187] Fig.18 Step 1 in the above process includes three processing steps: step 1-1, step 1-2 and step 1-3. In step 1-1, the CPU (110) instructs the I2C host #1 (111) to send the header packet data ( Fig.17 (1) in the ASEP register (540), and the I2C packet data ( Fig.17 (2) in the above) is written to the internal memory #1 (131) of the I2C slave #1 (121) ( Fig. 22 (11-1)).

[0188] Note that the I2C configuration data to the ASEP register (540) contains the I2C CLK rate of the I2C bus (51), the slave address (7'h47) managed by the ASA node #5 (500), and flag information (8 bits / 16 bits) indicating the length of its offset address.

[0189] In step 1-2, the I2C master #1 (111) sends the header packet data and the I2C packet data accompanied by the write address (0x0000) for the internal memory #1 (131) to the slave address (7'h41) of the I2C slave #1 (121) ( Fig. 22 (11-1)).

[0190] In step 1-3, the I2C slave #1 (121) writes the received header packet data and I2C packet data into the internal memory #1 (131).

[0191] Fig.18Step 2 in the above process includes three processing steps: Step 2-1, 2-2, and 2-3. In Step 2-1, once the header data is written to the internal memory #1 (131), the ASE (142) reads the header data and sends the header data to the DLL (150). Thereafter, once the I2C packet data is written to the internal memory #1 (131), the ASE (142) reads the I2C packet data, converts the I2C packet data into an I2C packet for the ASA, and sends the I2C packet to the DLL (150).

[0192] In step 2-2, DLL (150) generates a header packet based on the header packet data received from ASE (142) and its own ASA node #. In addition, DLL (150) adds the generated header packet to the I2C packet received from ASE (142) and sends the container (30-1) to PhyL (160).

[0193] In step 2-3, PhyL (160) sends the container (30-1) to the opposite ASA node #2 (200) via ASA (30).

[0194] Steps 3 to 6 in the first embodiment are the same as those in Figure 5 and Figure 6 Steps 3 to 6 in the basic mode shown in are the same, so their description is omitted.

[0195] Fig.19 Step 7 in includes six processing steps: Steps 7-1, 7-2, 7-3, 7-4, 7-5, and 7-6. In step 7-1, the PhyL (160) in the ASA node #1 (100) recovers the received container (30-2) and sends the container (30-2) to the DLL (150).

[0196] In step 7-2, DLL (150) checks the header packet in the received container (30-2), determines that the container (30-2) is an I2C packet addressed to ASA node #1, and sends the ASA node information about the transmission source and the I2C packet to the corresponding ASD (141).

[0197] In step 7-3, the ASD (141) restores the original data from the received I2C header, and the ASD (141) writes the ASA node information about the transmission source and the restored I2C header data to and after the write address (0x0800) of the internal memory #1 (131).

[0198] In step 7-4, the CPU (110) periodically issues a read command to the I2C master #1 (111) to check whether ACK / NACK data as a result of writing the I2C configuration data has been written into the internal memory #1 (131) of the I2C slave #1 (121).

[0199] In step 7-5, the I2C master #1 (111) reads the ASA node information about the transmission source and the I2C packet data accompanied by the read address (0x0800) for the internal memory #1 (131) to the slave address (7'h41) of the I2C slave #1 (121) ( Fig. 22 (11-2)).

[0200] In step 7-6, the CPU (110) checks the ASA node information and the I2C packet data about the transmission source read by the I2C host #1 (111) to check whether the I2C configuration data has been written into the ASEP register (540) in the ASA node #5 (500) ( Fig. 22 (12-2)).

[0201] Fig. 20 Step 8 in the above process includes three processing steps: Step 8-1, 8-2 and 8-3. For example, in the case where the I2C configuration data has been written to the ASEP register (540) in Steps 1 to 7, and the ECU (10) transmits the control data of the CIS #7 (601) built in the camera B (50) to the internal memory #7 (631) through the I2C communication, in Step 8-1 ( Fig. 22 In (11-3)), the CPU (110) instructs the I2C host #1 (111) to transmit the header packet data ( Fig.17 (1)) and I2C packet data containing control data of CIS#7 (601) ( Fig.17 (2)) is written to the internal memory #1 (131) in the I2C slave #1 (121).

[0202] It should be noted that the I2C packet data contains the slave address (7'h47) of the I2C slave #7 (621) and the offset address of the internal memory #7 (631).

[0203] In step 8-2, the I2C master #1 (111) sends the header packet data and the I2C packet data accompanied by the write address (0x0000) for the internal memory #1 (131) to the slave address (7'h41) of the I2C slave #1 (121) ( Fig. 22 (11-3)).

[0204] In step 8-3, the I2C slave #1 (121) writes the received header packet data and I2C packet data into the internal memory #1 (131).

[0205] Fig. 20 Step 9 in the above process includes three processing steps: Step 9-1, 9-2 and 9-3. In Step 9-1, once the header packet data is written to the internal memory #1 (131), the ASE (142) reads the header packet data and sends the header packet data to the DLL (150). Thereafter, once the I2C packet data is written to the internal memory #1 (131), the ASE (142) reads the I2C packet data, converts the I2C packet data into an I2C packet for the ASA, and sends the I2C packet to the DLL (150).

[0206] In step 9-2, the DLL (150) generates a header packet based on the header packet data received from the ASE (142) and its own ASA Node #.

[0207] Furthermore, the DLL (150) adds the generated header packet to the I2C packet received from the ASE (142), and sends the container (30-3) to the PhyL (160).

[0208] In step 9-3, PhyL (160) sends the container (30-3) to the opposite ASA node #2 (200) via ASA (30).

[0209] Steps 10 to 15 of the first embodiment are Figures 9 to 12 Steps 10 to 15 in the basic mode shown in FIG. 1 are the same, and therefore, description thereof is omitted.

[0210] Fig.21 Step 16 in includes six processing steps: steps 16-1, 16-2, 16-3, 16-4, 16-5 and 16-6. In step 16-1, the PhyL (160) in the ASA node #1 (100) recovers the received container (30-4) and sends the container (30-4) to the DLL (150).

[0211] In step 16-2, the DLL (150) checks the header packet in the received container (30-4), determines that the container (30-4) is an I2C packet addressed to the ASA node #1, and sends the ASA node information about the transmission source and the I2C packet to the corresponding ASD (141).

[0212] In step 16-3, the ASD (141) restores the original I2C packet data from the received I2C packet, and the ASD (141) writes the ASA node information about the transmission source and the restored I2C packet data at and after the write address (0x0800) of the internal memory #1 (131).

[0213] In step 16-4, the CPU (110) periodically issues a read command to the I2C master #1 (111) to check whether ACK / NACK data as a result of writing the control data of the CIS #7 has been written into the internal memory #1 (131) of the I2C slave #1 (121).

[0214] In step 16-5, the I2C master #1 (111) reads the ASA node information about the transmission source and the I2C packet data accompanied by the read address (0x0800) of the internal memory #1 (131) to the slave address (7'h41) of the I2C slave #1 (121) ( Fig. 22 (11-4)).

[0215] In step 16-6, the CPU (110) checks the ASA node information on the transmission source and the I2C packet data read by the I2C master #1 (111) to check whether the control data of the CIS #7 has been successfully written into the internal memory #7 (631) of the I2C slave #7 (621) ( Fig. 22 12-4).

[0216] As described above, according to the first embodiment, the root (100) is connected to a first I2C communication device (e.g., I2C master #1 (111) and I2C slave #1 (121)), and the root (100) enables communication to be established between the first I2C communication device (111, 121) and a second I2C communication device (221, 421, 422, 521, 621, 622) as a communication partner device (e.g., leaf (200) or (500)).

[0217] The root (100) includes an internal memory #1 (131), an encoder (ASE (142)), a decoder (ASD (140)), and a communication unit (DLL (150)). The internal memory #1 (131) stores therein header packet data including a target ID of a second communication device (200, 500) and I2C packet data including a slave address and an offset address of a second I2C communication device.

[0218] The encoder (ASE (142)) generates header packet data including a target ID of a communication partner device (200, 500) and I2C packet data including a slave address and an offset address of a second I2C communication device (221, 421, 422, 521, 621, 622). The communication unit (150, 160) transmits a transmission packet including the header packet data and I2C packet data generated by the encoder (142) to the communication partner device (200, 500) through a time division duplex (TDD) communication scheme, and receives a reception packet from the communication partner device (200, 500) via the TDD communication scheme. The decoder (ASD (140)) generates I2C packet data from the reception packet.

[0219] Typically, the header packet data includes a plurality of target IDs corresponding to a plurality of communication counterpart devices (200, 500). The storage space storing the header packet data and the I2C packet data includes a storage area for communicating with the communication counterpart devices (200, 500). For example, the header packet data includes four target IDs that comply with the Automotive SerDes Alliance (ASA) standard. The encoder (142) and the decoder (141) are configured to be shared by a plurality of second I2C communication devices corresponding to the plurality of target IDs.

[0220] The memory (131) storing the header packet data and the I2C packet data has a plurality of storage spaces, each of which has a fixed length and is used to store a plurality of target IDs contained in the header packet data. Invalid IDs are stored in the storage spaces corresponding to the unused target IDs.

[0221] The memory (131) storing the header packet data and the I2C packet data stores at least any one of the I2C configuration data including the operation setting of the second I2C communication device or the I2C data of the second I2C communication device as the I2C packet data.

[0222] More specifically, a first communication device (100) constituting a root (100) includes a first encoder (142), a communication unit (150, 160) and a first decoder (141). The first encoder (142) generates a header packet data containing a target ID of a second communication device (200, 500) and an I2C packet data containing a slave address and an offset address of a second I2C communication device (221, 421, 422, 521, 621, 622). The communication unit (150, 160) transmits a transmission packet containing the header packet data and the I2C packet data generated by the first encoder (142) to the second communication device (200, 500) through a time division duplex (TDD) communication scheme, and receives a reception packet from the second communication device (200, 500) via the TDD communication scheme. The first decoder (141) generates I2C packet data from the reception packet.

[0223] A second communication device (200, 500) constituting a leaf (200) or (500) includes a second encoder (242, 542), a communication unit (250, 260, 550, 560) and a second decoder (241, 541).

[0224] The second encoder (242, 542) generates header packet data including a target ID of the first communication apparatus (100) and I2C packet data including a slave address and an offset address of a first I2C communication device (111, 121).

[0225] The communication unit (250, 260, 550, 560) transmits a transmission packet including header packet data and I2C packet data generated by a second encoder (242, 542) to a first communication device (100) via a time division duplex (TDD) communication scheme, and receives a reception packet from the first communication device (100) via the TDD communication scheme.

[0226] The second decoder (241, 541) generates I2C packet data from the received packet.

[0227] Therefore, according to the first embodiment, it may not be necessary to individually provide I2C packet data for each leaf (200)(500), and thus, the storage capacity of the internal memory #1 (131) may be reduced.

[0228] In addition, since the memory space for storing header packet data and I2C packet data in the internal memory #1 (131) is shared by all I2C communication devices in the leaf (200) (500), it is not necessary to provide ASE (142) and ASD (141) for each I2C communication device in each communication device, thereby reducing the number of ASE (142) and ASD (141) and simplifying the configuration of the root (100).

[0229] (Second Embodiment)

[0230] Fig.24 is a diagram showing part of information stored in an ASEP register (I2C address register) of a root (100) according to the second embodiment. Fig.24 An example is shown in which target ID1 and target ID2 are stored in the offset address ( 209 ), and target ID3 and target ID4 are stored in the offset address ( 210 ).

[0231] Fig.25 : is a diagram showing the correspondence between target code [3:0] and target ID [1:4]. There are 16 types of target code [3:0], and combinations of target ID1 to target ID4 corresponding to the respective target codes are provided.

[0232] Fig.26 is a diagram showing the format of data written into the internal memory #1 (131). The header packet data and the I2C packet data are written into the internal memory #1 (131). The header packet data includes Fig.25 The target code shown in , and the I2C packet data includes a slave address and an offset address.

[0233] In the second embodiment, the CPU (110) in the ECU (10) obtains access to the internal memory #1 (131) via the I2C master (111) and the I2C slave (121). The internal memory #1 (131) according to the second embodiment is a memory map shared by the ASA nodes. Therefore, the I2C master #1 (111) writes in the address area of ​​the internal memory #1 (131) Fig.26 The data format shown in the header packet data and I2C packet data.

[0234] As described above, in the second embodiment, the relationship between the nodes (ASA node #2, ASA node #5) of the leaf (200) (500) and the slave addresses under its control is not managed in the address area of ​​the internal memory #1 (131).

[0235] In the second embodiment, the address area (0x0000-0xFFF) is an area for establishing communication with the opposite ASA node. ASD (141) and ASE (142) use the address area (0x0000-0xFFF) to perform I2C communication with the opposite ASA node. In addition, OAM (155) uses the address area (0x1000-0x1FFF).

[0236] Once the ASE (142) reads the target code ( Fig.26ASE (142) changes the code from the target ID of the corresponding ASEP Reg (140) to the header packet data format according to the first embodiment ( Fig.17 (1) in the code) and sends the code to the DLL (150).

[0237] As described above, in the second embodiment, similar to the first embodiment, the relationship between the leaf (200) node and the slave address controlled by it is managed as data in the internal memory #1, and therefore, ASE / ASD of each ASA node is not required, and the internal memory #1 ( Figure 3 ) compared to the previous example, the memory capacity can be reduced.

[0238] Furthermore, in the second embodiment, the header packet data required for each communication is reduced from 4 bytes in the first embodiment to 1 byte, which allows I2C communication to be established with a smaller data amount than that in the first embodiment.

[0239] In the second embodiment, the CPU (110) in the ECU (10) obtains access to the internal memory #1 (131) via the I2C master (111) and the I2C slave (121). Fig.26 As shown, internal memory #1 (131) is a memory map shared by the ASA nodes.

[0240] For example, when the ECU (10) transmits control data of the CIS #7 (601) built into the camera B (50) to the internal memory #7 (631) via I2C communication, first, Fig.24 As shown, the CPU (110) needs to write the target ID of the leaf (200) node as the communication partner into the ASEP register (140) of the ASA node #1 (100) (which is the root (100) node).

[0241] Figure 27 to Figure 29 1 and 2 are explanatory diagrams each showing a processing operation of the information processing apparatus according to the second embodiment. Figure 27 to Figure 29 Steps 0 to 2 show the execution order of the processing in the information processing device. Fig.30 is a data flow diagram showing writing of I2C configuration data according to the second embodiment. Fig.31 : is a data flow chart showing a method for controlling writing of I2C data of the CIS according to the second embodiment.

[0242] Fig. 27Step 0 in the above process includes three processing steps: Step 0-1, Step 0-2, Step 0-3 and Step 0-4. In Step 0-1, the CPU (110) instructs the I2C host #1 (111) to send the header packet data ( Fig.26 (1)) is written into the ASEP register (140), indicating ASA node #2 and ASA node #5 as the target ID of the communication partner, and writing the valid flag into the internal memory #1 (131) of the I2C slave #1 (121).

[0243] It should be noted that the I2C packet data of the write command ( Fig.26 (2)) in includes the slave address (7'h21) and offset address assigned to the ASEP register (140) together with the target ID including the valid flag.

[0244] In step 0-2, the I2C host #1 (111) sends the header packet data ( Fig.26 (1) in FIG. 1 and the I2C packet data ( 0x0000) accompanied by the write address (0x0000) for the internal memory #1 (131) Fig.26 (2) in the figure is sent to the slave address (7'h41) of I2C slave #1 (121).

[0245] In step 0-3, the I2C slave #1 (121) receives the header packet data ( Fig.26 (1)) and I2C packet data ( Fig.26 (2) in the internal memory #1 (131) ( Fig.26 ).

[0246] In step 0-4, once the header packet data is written into the internal memory #1 (131), the ASE (142) reads the header packet data and checks the target code (4'b0000). From the target code, it can be seen that the subsequent data is its own I2C packet data (Root (100) node).

[0247] Thereafter, once the I2C packet data is written into the internal memory #1 (131), the ASE (142) reads the I2C packet data and writes the ASA node #2 (target ID 1) and the ASA node #5 (target ID 2) together with the valid flag from the slave address (7'h21) included in the I2C packet data to the offset address (209) of the ASEP register (140).

[0248] Note that if the offset address (210) field is initialized to 16'h0000, then writing is not necessary.

[0249] In the second embodiment, the CPU (110) in the ECU (10) obtains access to the internal memory #1 (131) via the I2C master (111) and the I2C slave (121). The internal memory #1 (131) is a memory map shared by the ASA nodes ( Fig.26 ).

[0250] For example, in the case where the ECU (10) transmits control data of the CIS #7 (601) built in the camera B (50) to the internal memory #7 (631) through I2C communication, after step 0, the CPU (110) needs to write the I2C configuration data including the I2C CLK rate of the I2C bus (51) of the camera B (50), the slave address of the ASA node #5 (500) and the flag (8 bits / 16 bits) having the offset address length into the ASEP register (540) ( Figure 2 )middle.

[0251] Fig.28 Step 1 in the above process includes three processing steps: step 1-1, step 1-2 and step 1-3. In step 1-1, the CPU (110) instructs the I2C host #1 (111) to send the header packet data ( Fig.26 (1) in the ASEP register (540), and the I2C packet data ( Fig.26 (2) in the above) is written to the internal memory #1 (131) of the I2C slave #1 (121) ( Fig.30 (11-1)).

[0252] Note that the I2C configuration data to the ASEP register (540) includes the I2C CLK rate of the I2C bus (51), the slave address (7'h47) managed by the ASA node #5 (500), and flag information (8 bits / 16 bits) indicating the length of its offset address.

[0253] In step 1-2, the I2C master #1 (111) sends the header packet data and the I2C packet data accompanied by the write address (0x0000) for the internal memory #1 (131) to the slave address (7'h41) of the I2C slave #1 (121) ( Fig.30 (11-1)).

[0254] In step 1-3, the I2C slave #1 (121) writes the received header packet data and I2C packet data into the internal memory #1 (131).

[0255] Fig.29Step 2 in 2-1 includes three processing steps: Step 2-1, 2-2, and 2-3. In step 2-1, once the header data is written into the internal memory #1 (131), the ASE (142) reads the header data.

[0256] ASE (142) sends the target ID of the valid communication partner written into ASEP register (140) from the target code (Table 2-1) specified by the header packet to DLL (150) as converted header data.

[0257] Thereafter, once the I2C packet data is written to the internal memory #1 (131), the ASE (142) reads the I2C packet data, converts the I2C packet data into an I2C packet for the ASA, and sends the I2C packet to the DLL (150).

[0258] In the second embodiment, the data of the target ID 2 of the ASEP register (140) written in step 0 is read from the target code (4'b0010) received from the ASE (142).

[0259] If the en_flag of the target ID2 is enabled (1'b1), the ASE (142) transmits the data of the target ID2 (ASA node #5) as the header packet data to the DLL (150) after conversion.

[0260] Afterwards, once the I2C packet data is written into the internal memory #1 (131), the ASE (142) reads the I2C packet data, converts the I2C packet data into an I2C packet of the ASA, and sends the I2C packet to the DLL (150).

[0261] In case of a target code indicating multiple target IDs, multiple designated ASA node #s are sent to the DLL (150) as header packet data after conversion.

[0262] As described above, the target code ( Fig.25 ) can more efficiently transmit the header packet data of the first embodiment ( Fig.17 (1) in the figure.

[0263] In step 2-2, the DLL (150) generates a header packet based on the converted header packet data received from the ASE (142) and its own ASA node #.

[0264] In addition, the DLL (150) adds the generated header packet to the I2C packet received from the ASE (142) and Fig.14 The container (30-1) shown in FIG. 1 is sent to PhyL (160).

[0265] In step 2-3, PhyL (160) is transferred to Fig.14 The container (30-1) shown in FIG. 1 is sent to the opposite ASA node #2 (200).

[0266] Steps 3 to 16 of the second embodiment are the same as steps 3 to 16 of the first embodiment, and thus description thereof is omitted.

[0267] As described above, in the second embodiment, since the target code which is bit string data having a fixed length is used as the header packet data stored in the internal memory, a combination of a plurality of target IDs having a smaller storage capacity than the storage capacity of the header packet data in the first embodiment can be specified. Therefore, compared with the first embodiment, the amount of data communication between the I2C master and the I2C slave in the root (100) can be reduced, and the storage capacity of the internal memory can be reduced.

[0268] (Third Embodiment)

[0269] Fig.32 1 is a block diagram showing a schematic configuration of a communication system applicable to the first embodiment and the second embodiment described above. Fig.16 Differences in communication systems.

[0270] Fig.32 The communication system has a multi-master configuration in which an I2C master (821) of an I2C debugger (80) is connected to an I2C bus of an ECU (10).

[0271] Similar to the ECU ( 10 ), the I2C debugger ( 80 ) may perform I2C communication with the camera A ( 20 ) and the camera B ( 50 ) via the ASA ( 30 ).

[0272] also, Fig.32 The communication system in has a multi-master configuration in which an I2C master (921) of an I2C debugger (90) is connected to an I2C bus of a camera B (50).

[0273] exist Fig.32 In the communication system, the I2C debugger can also be investigated from the camera side which is relatively easy to connect, but an I2C slave (522) is also required to enable the I2C master (921) of the I2C debugger (90) to communicate with the I2C device in another ASA node via the ASA (40).

[0274] Therefore, when the ASA node #1 (100) is the root (100), the ASA node #5 (500) is the leaf (200). Therefore, in ASEP Reg (540), Figure 2 Information in.

[0275] On the other hand, in the case where the I2C debugger (90) is connected to the camera B (50) and the I2C host (921) is used as a host to communicate with another I2C device in the ASA node, the ASA node #5 (500) is used as the root (100), and the ASA node #1 is used as the leaf (500). Therefore, Fig.24 The information in is also written into ASEP Reg (540).

[0276] Fig.33 : is a diagram showing a part of information stored in an ASEP register (I2C address register) of a root according to the third embodiment. Fig.33 An example is shown in which target ID1 to target ID4 are stored for each of a plurality of groups. More specifically, Fig.33 An example is shown in which target ID1 and target ID2 of group #0 are stored in offset address (209), target ID3 and target ID4 of group #0 are stored in offset address (210), target ID1 and target ID2 of group #1 are stored in offset address (211), and target ID3 and target ID4 of group #1 are stored in offset address (212).

[0277] Fig.34 : is a diagram showing the correspondence between the group number, the target code [3:0] and the target ID [1:4]. There are 16 types of target codes [3:0], and a combination of target ID1 to target ID4 corresponding to each target code is provided for each group.

[0278] In the second embodiment, when communication is established with a target ID that is not registered in the I2C address register, it is necessary to rewrite the data of the target ID.

[0279] On the other hand, the I2C address register ( Fig.33 ) stores therein target ID1 to target ID4 of each group. Fig.34 In the target code [7:0] shown in FIG, the target code [7:4] as information for identifying the group is added to the target code [3:0] of the second embodiment.

[0280] according to Fig.33 and Fig.34 In the third embodiment, by first registering the target ID1 to the target ID4 of the plurality of groups, the number of unregistered target IDs is reduced, and the frequency of rewriting the unregistered target IDs can be reduced.

[0281] Fig.33 and Fig.34An example of providing two groups is shown, but in the third embodiment, a maximum of 64 target IDs in 16 groups can be registered in the ASEP register (140). Fig.33 and Fig.34 In the third embodiment, by first registering the target ID1 to the target ID4 of the plurality of groups, the number of unregistered target IDs is reduced, and the frequency of rewriting the unregistered target IDs can be reduced.

[0282] Fig.35 It is shown in Fig.29 A block diagram of a configuration in which a plurality of cameras (60, 61, 62) are connected via a daisy chain between camera A (20) and camera B (50).

[0283] Fig.36 is shown corresponding to Fig.35 Schematic diagram of the configured I2C address register. The target ID corresponding to the target code of group #0 is stored in offset addresses (209) and (210), and the target ID corresponding to the target code of group #1 is stored in offset addresses (211) and (212). More specifically, offset address (209) stores therein the target ID of ASA node #2, the target ID of ASA node #4, and information indicating that these target IDs are enabled. Offset address (210) stores therein the target ID of ASA node #7, the target ID of ASA node #9, and information indicating whether these target IDs are enabled or disabled. Offset address (211) stores therein the target ID of ASA node #9, the target ID of ASA node #5, and information indicating that these target IDs are enabled. In offset address (212), information about target ID3 of group #1 and target ID4 of group #1 is stored (in Fig.36 (disabled in ).

[0284] exist Fig.35 In the configuration of Fig.34 In the case of 8'h03, ASA node #1 (100) generates header packet data including ASA nodes #2 and #4. In the case of 8'h11, ASA node #1 (100) generates header packet data including ASA node #9. In the case of 8'h13, ASA node #1 (100) generates header packet data including ASA nodes #9 and #5.

[0285] As described above, for example, Leaf (500) establishes communication between the first I2C communication device (111, 121) and the second I2C communication device (221, 421, 422, 521, 621, 622) based on the I2C configuration data sent from the communication partner device (ASA node #1 (100)) to which the first I2C communication device (111, 121) is connected.

[0286] The ASA node #5 (500) according to the third embodiment includes an encoder (242, 542), a communication unit (221, 421, 422, 521, 621, 622), and a decoder (241, 541). The encoder (242, 542) generates a header packet data containing a target ID of a communication partner device (100) and an I2C packet data containing a slave address and an offset address of a first I2C communication device (111, 121). The communication unit (221, 421, 422, 521, 621, 622) sends a transmission packet containing the header packet data and the I2C packet data generated by the encoder (242, 542) to the communication partner device (100) through a time division duplex (TDD) communication scheme, and receives a reception packet from the communication partner device (100) via the TDD communication scheme. The decoder (241, 541) generates I2C packet data from the reception packet.

[0287] As described above, in the third embodiment, the second I2C communication device (221, 421, 422, 521, 621, 622) further includes an I2C slave unit (522) to which the I2C master unit (921) is connected via the I2C bus. Therefore, if necessary, the ASA node (200) or (500) can be operated as a Root, and the ASA node #1 (100) can be operated as a Leaf. In addition, in the third embodiment, multiple second communication devices are connected via a daisy chain, and the header packet data includes a bit string indicating a group number of a group and a combination of multiple target IDs. Therefore, the root (100) can establish I2C communication with the I2C communication device included in each of the multiple leaves (200, 500). In addition, any leaf among the multiple leaves connected in the daisy chain can be operated as a root.

[0288] It should be noted that the present technology can have the following configurations.

[0289] (1) A communication apparatus configured to establish communication between a first I2C communication device and a second I2C communication device connected to a communication counterpart device, the communication apparatus comprising:

[0290] an encoder that generates header packet data including a target ID of a communication partner device and I2C packet data including a slave address and an offset address of a second I2C communication device;

[0291] a communication unit that transmits a transmission packet including header packet data generated by the encoder and I2C packet data to a communication counterpart device through a time division duplex (TDD) communication scheme, and receives a reception packet from the communication counterpart device through the TDD communication scheme; and

[0292] Decoder, generates I2C packet data from received packets.

[0293] (2) The communication device according to (1), wherein

[0294] The header packet data includes a plurality of destination IDs corresponding to a plurality of communication partner devices.

[0295] (3) The communication device according to (2), wherein

[0296] The memory space in which the header packet data and the I2C packet data are stored includes a memory space for communicating with a communication partner device.

[0297] (4) The communication device according to (2) or (3), wherein

[0298] The header packet data contains four target IDs that comply with the Automotive SerDes Alliance (ASA) standard.

[0299] (5) The communication device according to any one of (2) to (4), wherein

[0300] The encoder and the decoder are provided so as to be shared by a plurality of communication partner devices corresponding to a plurality of target IDs.

[0301] (6) The communication device according to any one of (2) to (5), wherein

[0302] The memory storing therein the header packet data and the I2C packet data has a plurality of storage spaces, each storage space having a fixed length, for storing a plurality of target IDs included in the header packet data, and

[0303] Invalid IDs are stored in storage spaces corresponding to unused target IDs.

[0304] (7) The communication device according to any one of (2) to (5), wherein

[0305] The header packet data includes variable length data including information indicating the number of valid target IDs, and wherein the valid target IDs are arranged after the information.

[0306] (8) The communication device according to (1), wherein

[0307] The header packet data contains a target code specifying a combination of multiple target IDs.

[0308] (9) The communication device according to (8), wherein

[0309] The target code includes bit string data having a fixed length.

[0310] (10) The communication device according to (9), wherein

[0311] The target code includes 4 bits of data and specifies a combination of four target IDs.

[0312] (11) The communication device according to any one of (1) to (10), wherein

[0313] In the memory storing therein the header packet data and the I2C packet data, at least any one of the I2C configuration data including the operation setting of the second I2C communication device and the I2C data of the second I2C communication device is stored as the I2C packet data.

[0314] (12) A communication system comprising:

[0315] A first communication device connected to a first I2C communication device; and

[0316] The second communication device is connected to the second I2C communication device and alternately sends information to and receives information from the first communication device within an allocated time period through a time division duplex (TDD) communication scheme, wherein,

[0317] The first communication device comprises:

[0318] a first encoder, generating a header packet data including a target ID of a second communication device and I2C packet data including a slave address and an offset address of a second I2C communication device,

[0319] a communication unit that transmits a transmission packet including header packet data and I2C packet data generated by the first encoder to a second communication device through a time division duplex (TDD) communication scheme, and receives a reception packet from the second communication device through the TDD communication scheme; and

[0320] The first decoder generates I2C packet data from the received packet.

[0321] (13) A communication system according to (12), wherein:

[0322] The second communication device comprises:

[0323] a second encoder, generating header packet data including a target ID of the first communication device and I2C packet data including a slave address and an offset address of the first I2C communication device;

[0324] a communication unit that transmits a transmission packet including header packet data and I2C packet data generated by a second encoder to a first communication device through a time division duplex (TDD) communication scheme, and receives a reception packet from the first communication device through the TDD communication scheme; and

[0325] The second decoder generates I2C packet data from the received packet.

[0326] (14) A communication system according to (13), wherein:

[0327] The second I2C communication device further includes an I2C slave unit, and the I2C master unit is connected to the I2C slave unit via an I2C bus.

[0328] (15) A communication system according to (13) or (14), wherein:

[0329] A plurality of second communication devices are connected via a daisy chain, and

[0330] The header packet data is divided into a plurality of groups, each group including a plurality of target IDs conforming to the Automotive SerDes Alliance (ASA) standard.

[0331] (16) A communication system according to (13) or (14), wherein:

[0332] A plurality of second communication devices are connected via a daisy chain, and

[0333] The header packet data includes a bit string indicating a combination of a group number indicating a group and specifying a plurality of target IDs.

[0334] (17) A communication device configured to establish communication between a first I2C communication device and a second I2C communication device based on I2C configuration data transmitted from a communication partner device connected to the first I2C communication device, the communication device comprising:

[0335] an encoder that generates header packet data including a target ID of a communication partner device and I2C packet data including a slave address and an offset address of a first I2C communication device;

[0336] a communication unit that transmits a transmission packet including header packet data generated by the encoder and I2C packet data to a communication counterpart device through a time division duplex (TDD) communication scheme, and receives a reception packet from the communication counterpart device through the TDD communication scheme; and

[0337] The decoder generates I2C packet data from the received packet, where

[0338] The second I2C communication device further includes an I2C slave unit, and the I2C master unit is connected to the I2C slave unit via an I2C bus.

[0339] The mode of the present disclosure is not limited to the above-mentioned individual embodiments, and includes various modifications that can be thought of by those skilled in the art. In addition, the effects of the present disclosure are not limited to the above-mentioned effects. That is, various additions, modifications, and partial deletions may be made without departing from the conceptual concept and gist of the present disclosure derived from the contents defined in the claims and their equivalents.

[0340] [Explanation of symbols]

[0341] 10ECU 11I2C bus 12system bus 20camera

[0342] 21I2C bus 30ASA40ASA50 camera 51I2C bus

[0343] 80I2C debugger 90I2C debugger 100ASA node 111I2C host

[0344] 121I2C slave 131Internal memory 140ASEP register

[0345] 141 Application stream deep encapsulator 142 Application stream encapsulator 150 Data link layer (root / leaf)

[0346] 155 Operation, management, maintenance 156 Register 160 Physical layer 200 ASA node

[0347] 221I2C host 231Internal memory 240ASEP register

[0348] 241 Application stream deep encapsulator 242 Application stream encapsulator 250 Data link layer (leaf)

[0349] 255 Operation, management, maintenance 256 Register 260 Physical layer 300 ASA node

[0350] 350 Data link layer (branch) 351 Branch function unit 360 Physical layer

[0351] 401CMOS Image Sensor402CMOS Image Sensor421I2C Slave

[0352] 422I2C slave 431 internal memory 432 internal memory 500ASA node

[0353] 521I2C master 522I2C slave 531Internal memory 540ASEP register

[0354] 541 Application Stream Deep Encapsulator 542 Application Stream Encapsulator 550 Data Link Layer (Root / Leaf)

[0355] 555 Operation, management, maintenance 556 Register 560 Physical layer

[0356] 601CMOS Image Sensor602CMOS Image Sensor621I2C Slave

[0357] 622I2C slave 631 internal memory 632 internal memory 821I2C master

[0358] 831 internal memory 921 I2C host 931 internal memory.

Claims

1. A communication device configured to establish communication between a first I2C communication device and a second I2C communication device connected to a communication counterpart device, the communication device comprising: an encoder that generates header packet data including a target ID of the communication partner device and I2C packet data including a slave address and an offset address of the second I2C communication device; a communication unit that transmits a transmission packet including the header packet data and the I2C packet data generated by the encoder to the communication counterpart device through a time division duplex (TDD) communication scheme, and receives a reception packet from the communication counterpart device through the TDD communication scheme; as well as A decoder generates the I2C packet data from the received packet.

2. The communication device according to claim 1, wherein: The header packet data includes a plurality of the target IDs corresponding to a plurality of the communication partner devices.

3. The communication device according to claim 2, wherein: The storage space in which the header packet data and the I2C packet data are stored includes a storage space for communicating with the communication partner device.

4. The communication device according to claim 2, wherein: The header packet data includes the four target IDs conforming to the Automotive SerDes Alliance (ASA) standard.

5. The communication device according to claim 2, wherein: The encoder and the decoder are provided so as to be shared by a plurality of the communication partner devices corresponding to a plurality of the target IDs.

6. The communication device according to claim 2, wherein: The memory storing the header packet data and the I2C packet data has a plurality of storage spaces, each storage space having a fixed length, for storing a plurality of the target IDs contained in the header packet data, and An invalid ID is stored in the storage space corresponding to the unused target ID.

7. The communication device according to claim 2, wherein: The header packet data includes variable length data including information indicating the number of valid target IDs, and wherein the valid target IDs are arranged after the information.

8. The communication device according to claim 1, wherein: The header packet data includes a target code specifying a combination of a plurality of the target IDs.

9. The communication device according to claim 8, wherein: The target code includes bit string data having a fixed length.

10. The communication device according to claim 9, wherein: The target code includes 4-bit data and specifies a combination of four target IDs.

11. The communication device according to claim 1, wherein: In the memory storing therein the header packet data and the I2C packet data, at least any one of I2C configuration data including operation settings of the second I2C communication device and I2C data of the second I2C communication device is stored as the I2C packet data.

12. A communication system comprising: A first communication device, connected to a first I2C communication device; as well as a second communication device connected to a second I2C communication device and alternately sending information to and receiving information from the first communication device within an allocated time period through a time division duplex (TDD) communication scheme, in, The first communication device comprises: a first encoder, generating a header packet data including a target ID of the second communication device and an I2C packet data including a slave address and an offset address of the second I2C communication device, a communication unit that transmits a transmission packet including the header packet data and the I2C packet data generated by the first encoder to the second communication device through a time division duplex (TDD) communication scheme, and receives a reception packet from the second communication device through the TDD communication scheme, and A first decoder generates the I2C packet data from the received packet.

13. The communication system according to claim 12, wherein: The second communication device comprises: a second encoder, generating header packet data including a target ID of the first communication device and I2C packet data including a slave address and an offset address of the first I2C communication device; a communication unit that transmits a transmission packet including the header packet data and the I2C packet data generated by the second encoder to the first communication device through a time division duplex (TDD) communication scheme, and receives a reception packet from the first communication device through the TDD communication scheme; and The second decoder generates I2C packet data from the received packet.

14. The communication system according to claim 13, wherein: The second I2C communication device further includes an I2C slave unit, and the I2C master unit is connected to the I2C slave unit via an I2C bus.

15. The communication system according to claim 13, wherein: A plurality of said second communication devices are connected via a daisy chain, and The header packet data is divided into a plurality of groups, each group including a plurality of the target IDs conforming to the Automotive SerDes Alliance (ASA) standard.

16. The communication system according to claim 13, wherein: A plurality of said second communication devices are connected via a daisy chain, and The header packet data includes a group number indicating a group and a bit string specifying a combination of a plurality of the target IDs.

17. A communication device, configured to establish communication between a first I2C communication device and a second I2C communication device based on I2C configuration data sent from a communication partner device connected to the first I2C communication device, the communication device comprising: an encoder that generates header packet data including a target ID of a communication partner device and I2C packet data including a slave address and an offset address of the first I2C communication device; a communication unit that transmits a transmission packet including the header packet data and the I2C packet data generated by the encoder to a communication counterpart device through a time division duplex (TDD) communication scheme, and receives a reception packet from the communication counterpart device through the TDD communication scheme; as well as A decoder generates the I2C packet data from the received packet, wherein: The second I2C communication device further includes an I2C slave unit, and the I2C master unit is connected to the I2C slave unit via an I2C bus.

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