Identification information receiving device, power storage group, identification information receiving method, identification information receiving program, and recording medium on which program is recorded

Abstract

In an identification information receiving device for receiving identification information defined by a plurality of bits superimposed on a current or a voltage of a power line by an identification information transmission device connected through the power line, an edge detection unit detects an edge of an input signal that acquires the current or the voltage of the power line as a voltage value. The T flip-flop circuit inverts the output whenever an edge of the input signal is detected.

Description

Technical Field

[0001] The present disclosure relates to an identification information receiving device, a power storage pack, an identification information receiving method, and an identification information receiving program for receiving identification information superimposed on a current or a voltage of a power line. Background Art

[0002] In recent years, electric-assisted bicycles have become popular. Electric-assisted bicycles use portable battery packs that can be easily loaded and unloaded. The following system has been developed: In order to eliminate the terminals for communication lines from the connector of the battery pack, the battery pack and the electric-assisted bicycle are equipped with wireless communication functions to transmit control signals wirelessly.

[0003] If there are multiple electric-assisted bicycles within the range of wireless communication with the battery pack, the installed battery pack may be mistakenly controlled by other vehicles adjacent to the vehicle, and the safety and reliability of the entire system cannot be ensured. In particular, in rental services and sharing services, there are many cases where multiple electric-assisted bicycles are parked in a parking lot. In order to safely and reliably operate the entire system, each electric-assisted bicycle needs to correctly identify the installed battery pack.

[0004] It is conceivable that the battery pack supplies power to the vehicle through the power line, and at the same time, the identification information is superimposed on the power line using a binary current (other than 0) or a binary voltage (other than 0). On the receiving side, the measured value of the current or voltage is compared with a threshold value, and the measured value above the threshold value is set to 1, and the measured value below the threshold value is set to 0, so as to receive the identification information.

[0005] However, due to differences in component characteristics and changes in current consumption, the measured values ​​of current or voltage may be offset, and it may happen that the identification information cannot be received correctly. There are long-term and short-term factors that cause changes in current or voltage superimposed on the power line. Long-term factors include individual differences in electronic components and changes over time. Long-term factors are almost always caused by changes in the DC component. Short-term factors include unexpected changes in load current such as intermittent operation of microcontrollers. Short-term factors are caused by changes in the AC component, which is equivalent to current changes or voltage changes in one data packet.

[0006] Patent document 1 discloses the following method: a two-wire differential voltage logic signal transmitted via a communication line is waveform-shaped and received by using a differential circuit and a Schmitt trigger circuit composed of a hysteresis comparator. The Schmitt trigger circuit has a first threshold value Vr1 and a second threshold value Vr2 whose potential is lower than the first threshold value Vr1. When the input signal Sd exceeds the first threshold value Vr1, a high-level signal is output, and when the signal Sd is lower than the second threshold value Vr2, a low-level signal is output. When the potential of the signal Sd is between the first threshold value Vr1 and the second threshold value Vr2, the previous level is maintained (see Patent document 1). Figure 3 ).

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Publication No. 2019-146141 Summary of the invention

[0010] When a Schmitt trigger circuit is used to determine whether a signal Sd is at a high level or a low level, if noise exceeding the first threshold value Vr1 or below the second threshold value Vr2 is superimposed on the signal Sd, the output signal of the Schmitt trigger circuit may be reversed at an unexpected timing, thereby causing misdetection.

[0011] The present disclosure has been made in view of such circumstances, and an object of the present disclosure is to provide a technology for reducing erroneous determination when detecting identification information superimposed on a current or voltage of a power line.

[0012] In order to solve the above-mentioned problem, an identification information receiving device of a certain embodiment of the present invention is used to receive identification information specified by multiple bits superimposed on the current or voltage of the power line by an identification information sending device connected via a power line. The identification information receiving device comprises: an edge detection unit, which detects the edge of an input signal that obtains the current or voltage of the power line as a voltage value; and a T-flip-flop circuit, which inverts the output whenever an edge of the input signal is detected.

[0013] Furthermore, arbitrary combinations of the above-described constituent elements and modes in which the expression of the present disclosure is converted between devices, systems, methods, computer programs, recording media, and the like may also be additional modes of the present disclosure.

[0014] According to the present disclosure, it is possible to reduce erroneous determination when detecting identification information superimposed on a current or voltage of a power line. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The figure shows an electric assist bicycle equipped with a battery pack according to the embodiment.

[0016] Figure 2 This is a diagram for explaining an overview of a first example of an authentication process for a battery pack mounted on a vehicle.

[0017] Figure 3 It is a diagram showing a first configuration example of a battery pack and a vehicle according to an embodiment.

[0018] Figure 4 This is a diagram for explaining an overview of a second example of an authentication process for a battery pack mounted on a vehicle.

[0019] Figure 5 It is a diagram showing a second configuration example of a battery pack and a vehicle according to the embodiment.

[0020] Fig. 6A This is a diagram showing an example of a transmission current and a reception current superimposed on a power line.

[0021] Figure 6B This is a diagram showing an example of a transmission current and a reception current superimposed on a power line.

[0022] Figure 7 It is a diagram showing a configuration example 1 of a first ID detection circuit.

[0023] Figure 8 It is shown Figure 7 Diagram of the truth table of the T flip-flop circuit shown.

[0024] Fig. 9A 2 is a diagram showing a simulation waveform indicating the execution result of simulation 1.

[0025] Fig. 9B 2 is a diagram showing a simulation waveform indicating the execution result of simulation 1.

[0026] Fig. 9C 2 is a diagram showing a simulation waveform indicating the execution result of simulation 1.

[0027] Fig.9D 2 is a diagram showing a simulation waveform indicating the execution result of simulation 1.

[0028] Fig.10 It is shown Figure 7 The diagram is a diagram of an expanded example of the configuration example 1 of the first ID detection circuit shown.

[0029] Fig.11 It is shown Fig.10 Diagram of the truth table of the T flip-flop circuit shown.

[0030] Fig.12 FIG. 1 is a diagram showing a simulated waveform in which a noise pulse is mixed in the output signal of the edge detection unit.

[0031] Fig.13 : is a diagram showing a simulation waveform including a masking pulse.

[0032] Fig.14 It is a diagram showing a second configuration example of a first ID detection circuit.

[0033] Fig.15A 2 is a diagram showing a simulation waveform indicating the execution result of Simulation 2.

[0034] Fig. 15B 2 is a diagram showing a simulation waveform indicating the execution result of Simulation 2.

[0035] Fig. 15C 2 is a diagram showing a simulation waveform indicating the execution result of Simulation 2.

[0036] Fig.15D 2 is a diagram showing a simulation waveform indicating the execution result of Simulation 2.

[0037] Fig.15E 2 is a diagram showing a simulation waveform indicating the execution result of Simulation 2.

[0038] Fig.16 It is shown Fig.14 A diagram showing an expanded example of configuration example 2 of the first ID detection circuit shown. DETAILED DESCRIPTION

[0039] Figure 1 1 is a diagram showing an electric assist bicycle equipped with a battery pack according to an embodiment. The battery pack 10 is a portable / replaceable battery pack 10 that can be installed in a mounting slot of a vehicle 20 or a charger (not shown). In the following, an electric assist bicycle is assumed to be the vehicle 20 in the embodiment.

[0040] Since the replaceable battery pack 10 is frequently attached and detached from the vehicle 20 or the mounting slot of the charger, the connector portion of the battery pack 10 is prone to deterioration. Therefore, in this embodiment, a wireless communication function is provided in the battery pack 10, and control signals are transmitted by wireless communication. As a result, the terminals for the communication line can be eliminated from the connector of the battery pack 10, and only the terminals for the power line can be provided.

[0041] Short-range wireless communication is used for wireless communication between the vehicle 20 and the battery pack 10. As short-range wireless communication, Bluetooth (registered trademark), Wi-Fi (registered trademark), infrared communication, etc. can be used. Next, in this embodiment, it is assumed that BLE (Bluetooth Low Energy) is used as short-range wireless communication.

[0042] BLE is one of the extension standards of Bluetooth and is a low-power short-range wireless communication standard using the 2.4 GHz frequency band. BLE has low power consumption to the extent that it can be driven for several years by a button battery, so it is suitable for battery driving and can minimize the impact on the remaining capacity of the battery pack 10. In addition, BLE communication modules are available in large quantities on the market and can be obtained at a low cost.

[0043] When using general class 2 equipment, the radio wave reach range of BLE is about 10m. Therefore, there may be a situation where multiple vehicles 20 and multiple battery packs 10 exist in one BLE communication circle. In this case, radio wave interference sometimes occurs between vehicle systems, making the operation unstable. In addition, the vehicle 20 sometimes mistakenly connects to a battery pack 10 other than the battery pack 10 installed on itself, in which case it is possible to mistakenly control the battery pack 10 not installed on itself.

[0044] Therefore, a mechanism is required to ensure that the battery pack 10 installed in the vehicle 20 is the same as the battery pack 10 that is the communication object of the vehicle 20. In the present embodiment, identification information (ID) is used to confirm the identity of the battery pack 10 that is physically connected to the vehicle 20 by wire and the battery pack 10 that is connected by wireless communication. The identification information (ID) may be identification information inherent to each vehicle 20 or each battery pack 10, or may be temporary identification information. As the inherent identification information, for example, a BD (Bluetooth Device) address or a MAC (Medium Access Control) address may be used.

[0045] Figure 2 This is a diagram for explaining an overview of example 1 of the authentication process of the battery pack 10 mounted on the vehicle 20. When the connector of the battery pack 10 is connected to the connector of the mounting slot of the vehicle 20, the vehicle 20 transmits ID1 to the battery pack 10 via a wired method. When the battery pack 10 receives ID1 via a wired method, it transmits a broadcast packet (beacon packet) including the received ID1 and its own battery pack ID via short-range wireless communication. The broadcast packet is a signal for notifying the surroundings of its own presence via short-range wireless communication.

[0046] When the vehicle 20 receives a broadcast data packet, it compares the ID1 contained in the broadcast data packet with the ID1 sent to the battery pack 10 via a wired method. When the two are consistent, the vehicle 20 authenticates that the installed battery pack 10 is the same as the communication object of the short-range wireless communication. When the two are inconsistent, the vehicle 20 determines that the installed battery pack 10 is different from the communication object of the short-range wireless communication, and the battery pack 10 as the communication object has not passed the authentication. For example, when a broadcast data packet containing ID2 is received, since it is inconsistent with the ID1 sent to the battery pack 10 via a wired method, the battery pack 10 as the destination of the broadcast data packet containing ID2 has not passed the authentication.

[0047] Figure 3 1 is a diagram showing a first configuration example of a battery pack 10 and a vehicle 20 according to the embodiment. Figure 3 The structure example 1 shown corresponds to the authentication processing example 1. Figure 3 The components required for the authentication processing example 1 are drawn, and the components irrelevant to the authentication processing example 1 are omitted as appropriate. Figure 3 It is assumed that the battery pack 10 is mounted on the vehicle 20 .

[0048] The battery pack 10 includes a storage battery 11, a first relay 12, a first current sensor 13, a first power supply circuit 14, a first control unit 15, a first wireless communication unit 16, a first antenna 17, a first ID detection circuit 19, and a power supply terminal T1. The vehicle 20 includes a motor 21, an inverter 22, a second relay 23, a second power supply circuit 24, a second control unit 25, a second wireless communication unit 26, a second antenna 27, a second ID superimposition circuit 28, and a power receiving terminal T2. When the battery pack 10 is mounted on the vehicle 20, the power supply terminal T1 and the power receiving terminal T2 are in physical contact, and the power line Lp1 in the battery pack 10 and the power line Lp2 in the vehicle 20 are connected.

[0049] The storage battery 11 includes a plurality of cells connected in series or in series-parallel. As the cells, lithium-ion cells, nickel-metal hydride cells, lead-acid cells, etc. can be used. Hereinafter, in this specification, an example using lithium-ion cells (nominal voltage: 3.6V-3.7V) is assumed. The number of cells connected in series is determined according to the drive voltage of the motor 21 of the vehicle 20.

[0050] The first relay 12 is inserted into the power line Lp1 connecting the battery 11 and the power supply terminal T1. In addition, other types of switches such as semiconductor switches may be used instead of the relay.

[0051] The first current sensor 13 measures the current flowing in the power line Lp1 in the battery pack 10 and outputs it to the first ID detection circuit 19. The first current sensor 13 is composed of, for example, a combination of a shunt resistor and an amplifier. The voltage across the shunt resistor inserted in the power line Lp1 is amplified by the amplifier, thereby outputting a voltage value corresponding to the current flowing in the power line Lp1 from the first current sensor 13. In addition, a Hall element or a CT sensor can also be used instead of the shunt resistor.

[0052] The first power supply circuit 14 is a DC / DC converter that steps down the voltage of the battery 11 to generate a power supply voltage (e.g., about 3.3V to 5V) for the first control unit 15 and a power supply voltage (+15V and -15V in the specific example below) for the first ID detection circuit 19. The first power supply circuit 14 may be formed by a switching regulator or a linear regulator.

[0053] The first control unit 15 is a microcontroller that controls the entire battery pack 10. The first control unit 15 monitors the state of the storage battery 11 (specifically, the voltage, current, and temperature of each single cell included in the storage battery 11). The first control unit 15 estimates the SOC (State Of Charge), FCC (Full Charge Capacity), and SOH (State Of Health) of each single cell included in the storage battery 11 based on these monitoring data. In addition, when the single cell included in the storage battery 11 generates overvoltage, undervoltage, overcurrent, high temperature abnormality, or low temperature abnormality, the first control unit 15 disconnects the first relay 12 to protect the single cell.

[0054] The first wireless communication unit 16 performs short-range wireless communication processing. In this embodiment, the first wireless communication unit 16 is composed of a BLE module, and the first antenna 17 is composed of a patch antenna or a pattern antenna built into the BLE module. The first wireless communication unit 16 outputs the data received through short-range wireless communication to the first control unit 15, and sends the data input from the first control unit 15 through short-range wireless communication.

[0055] In the present embodiment, the vehicle 20 includes a three-phase AC motor as a driving motor 21. The inverter 22 converts the DC power supplied from the battery pack 10 into AC power during power operation and supplies it to the motor 21. During regeneration, the AC power supplied from the motor 21 is converted into DC power and supplied to the battery pack 10. During power operation, the motor 21 rotates according to the AC power supplied from the inverter 22. During regeneration, the motor 21 converts the rotational energy generated by deceleration into AC power and supplies it to the inverter 22.

[0056] A second relay 23 is inserted into the power line Lp2 connecting the inverter 22 and the power receiving terminal T2. In addition, other types of switches such as semiconductor switches may be used instead of the relay.

[0057] The second power supply circuit 24 is a DC / DC converter that generates a power supply voltage (e.g., about 3.3V to 5V) for the second control unit 25 by stepping down the voltage supplied from the storage battery 11 in the battery pack 10 installed in the vehicle 20. The second power supply circuit 24 can be composed of a switching regulator or a linear regulator. In the present embodiment, the vehicle 20 is not equipped with a self-contained battery (e.g., a lead battery) for generating a control power supply. Therefore, it is necessary to generate a control power supply based on the driving power supply supplied from the storage battery 11 in the installed battery pack 10.

[0058] The second control unit 25 is a microcontroller that controls the entire vehicle 20. The second wireless communication unit 26 performs short-range wireless communication processing. In this embodiment, the second wireless communication unit 26 is composed of a BLE module, and the second antenna 27 can be composed of a patch antenna or a pattern antenna built into the BLE module. The second wireless communication unit 26 outputs data received through short-range wireless communication to the second control unit 25, and transmits data input from the second control unit 25 through short-range wireless communication.

[0059] The first control unit 15 or the second control unit 25 is composed of, for example, a microcomputer having a CPU (Central Processing Unit) and a memory as its main structure. In other words, the first control unit 15 or the second control unit 25 is implemented by a computer having a CPU and a memory, and the computer functions as the first control unit 15 or the second control unit 25 by executing a program stored in the memory by the CPU. Here, the program is pre-recorded in the memory of the first control unit 15 or the second control unit 25, but it can also be provided through an electrical communication line such as the Internet, or recorded in a (non-transitory) recording medium such as a memory card.

[0060] The second ID superimposing circuit 28 superimposes the ID on the current flowing in the power line Lp2. The ID is defined by a plurality of bits, and each bit is represented by a binary current. When the second control unit 25 receives power supply from the storage battery 11 of the battery pack 10 instead of the self-contained battery built into the vehicle 20, it is impossible to specify the power on and off of the current flowing from the storage battery 11 to the vehicle 20 as the binary current of each bit representing the ID. Therefore, the binary current representing each bit needs to be set to two current values ​​other than 0.

[0061] The second ID superimposition circuit 28 includes two loads having different resistance values, and one or more switches for selecting one of the two loads or setting the two loads to non-conduction. In addition, the second ID superimposition circuit 28 may also be configured to include a variable load that can be switched to two resistance values, and one or more switches for switching the resistance value of the variable load or setting the variable load to non-conduction.

[0062] When the second relay 23 is disconnected, the current flowing in the power line Lp2 basically depends on the current consumption of the second control unit 25. When the second relay 23 is disconnected, the second control unit 25 sets the ID to the second ID superimposition circuit 28. The second ID superimposition circuit 28 superimposes the bit "1" of the ID on the current by turning on the load with the smaller resistance value of the two loads, and superimposes the bit "0" of the ID on the current by turning on the load with the larger resistance value. As a result, the value of the current introduced to the vehicle 20 side changes according to each bit of the ID.

[0063] The first current sensor 13 of the battery pack 10 measures the current flowing in the power line Lp1 and outputs it to the first ID detection circuit 19. The first ID detection circuit 19 detects the ID superimposed on the current flowing in the power line Lp1 based on the voltage value corresponding to the current measured by the first current sensor 13, and outputs the detected ID to the first control unit 15. A specific configuration example of the first ID detection circuit 19 will be described later.

[0064] Figure 4 This is a diagram for explaining an overview of example 2 of the authentication process of the battery pack 10 mounted on the vehicle 20. When the connector of the battery pack 10 is connected to the connector of the mounting slot of the vehicle 20, the battery pack 10 transmits ID1 to the vehicle 20 via a wired method. At the same time, the battery pack 10 transmits a broadcast packet including ID1 via short-range wireless communication.

[0065] When the vehicle 20 receives a broadcast data packet, it compares the ID1 contained in the broadcast data packet with the ID1 received via a wired method. When the two are consistent, the vehicle 20 authenticates that the installed battery pack 10 is the same as the communication object of the short-range wireless communication. When the two are inconsistent, the vehicle 20 determines that the installed battery pack 10 is different from the communication object of the short-range wireless communication, and the battery pack 10 as the communication object has not passed the authentication. For example, when a broadcast data packet containing ID2 is received, since it is inconsistent with ID1 received via a wired method, the battery pack 10 as the destination of the broadcast data packet containing ID2 has not passed the authentication.

[0066] Figure 5 It is a diagram showing a second configuration example of a battery pack 10 and a vehicle 20 according to the embodiment. Figure 5 The structure example 2 shown corresponds to the authentication processing example 2. Figure 5 Components required for authentication processing example 2 are drawn in FIG. 1 , and components irrelevant to authentication processing example 2 are omitted as appropriate. In configuration example 1, ID is superimposed on the current flowing in the power line. In configuration example 2, ID is superimposed on the voltage of the power line.

[0067] exist Figure 5 In the structural example 2 shown, compared with Figure 3 In the configuration example 1 shown, a first ID superimposition circuit 18 is provided on the battery pack 10 side, and a second ID detection circuit 29 and a voltage detection circuit 210 are provided on the vehicle 20 side. The first ID superimposition circuit 18 is constituted by an adder circuit using an operational amplifier, for example. The operational amplifier uses the voltage of the battery 11 as a power supply voltage, adds a base voltage lower than the power supply voltage to the ID voltage supplied from the first control unit 15, and outputs the added voltage to the power line Lp1. As a result, the value of the voltage supplied to the vehicle 20 side changes according to each bit of the ID.

[0068] The voltage detection circuit 210 on the vehicle 20 side measures the voltage of the power line Lp2 and outputs it to the second ID detection circuit 29. The voltage detection circuit 210 is composed of, for example, a resistor voltage divider circuit, and the divided voltage is input to the second ID detection circuit 29. The second ID detection circuit 29 detects the ID superimposed on the voltage flowing in the power line Lp2 based on the voltage value measured by the voltage detection circuit 210, and outputs the detected ID to the second control unit 25.

[0069] exist Figure 3 In the configuration example 1 shown in FIG. 1 , the ID is transmitted from the vehicle 20 to the battery pack 10, so the vehicle 20 becomes the identification information transmitting device and the battery pack 10 becomes the identification information receiving device. Figure 5 In the configuration example 2 shown, the ID is transmitted from the battery pack 10 to the vehicle 20, so the battery pack 10 becomes the identification information transmitting device and the vehicle 20 becomes the identification information receiving device. The identification information receiving device will be described below based on the configuration example 1 using the current superposition method.

[0070] Fig. 6A This is a diagram showing an example of a transmission current and a reception current superimposed on a power line. Fig. 6A An example of a transmission current superimposed by the identification information transmission device is shown. Figure 6BAn example of the received current detected by the identification information receiving device is shown. The identification information receiving device determines that the current value I is bit "1" when it is greater than the threshold value Ith, and determines that the current value I is bit "0" when it is less than the threshold value Ith. As an example, the threshold value Ith may be set to 50mA, the assumed value on the low level side of the current value I may be 30mA, and the assumed value on the high level side may be 70mA.

[0071] At this time, the current value I may be additionally offset due to differences in component characteristics and changes in current consumption. The differences in component characteristics are caused by at least one of individual differences, temperature changes, and changes over time. Unexpected changes in current consumption of the identification information sending device (vehicle 20) are caused, for example, by the second control unit 25 starting certain background processes or event processes (for example, software update processes) during the authentication process using the second control unit 25 (microcontroller). In addition, changes in the current consumption of the identification information sending device (vehicle 20) may also occur due to structural changes in the identification information sending device (vehicle 20) such as lighting of the headlights.

[0072] If the current consumption of the identification information transmitting device increases due to such changes in the system state or system structure, the current flowing in the power line increases. In other words, the current flowing in the power line is offset. Due to this offset, the bit determination of the ID superimposed on the current flowing in the power line may be erroneous. Figure 6A-6B In the example shown, the ID superimposed on the current by the identification information transmitting device is "00101011110000011101", while the ID detected by the identification information receiving device based on the current is "00101011110000011111", and a bit error occurs in the second bit from the bottom. Next, a method of detecting the edge of the current measurement value and restoring the original waveform by a flip-flop circuit to eliminate the influence of the change of the DC component is described.

[0073] Figure 7 1 is a diagram showing a configuration example 1 of a first ID detection circuit 19. The first ID detection circuit 19 includes an edge detection unit 191 and a T (Toggle) flip-flop circuit 192. The edge detection unit 191 detects the edge of an input signal (V1) that obtains the current flowing in the power line as a voltage value. The output signal (V3) of the edge detection unit 191 is input to a clock terminal CLK of the T flip-flop circuit 192. Whenever an edge of the input signal (V1) is detected, the T flip-flop circuit 192 inverts the output. In addition, Figure 7 In the example shown, the T flip-flop circuit is implemented using a logic circuit of a D flip-flop, but the T flip-flop circuit can also be implemented by other structures.

[0074] In structural example 1, the edge detection unit 191 includes a differential circuit 191a, a polarity reversal circuit 191b, and a diode OR circuit 191c. The differential circuit 191a differentiates the input signal (V1). The polarity reversal circuit 191b reverses the polarity of the output signal (V2) of the differential circuit 191a. The diode OR circuit 191c turns on the positive component of the output signal (V2) of the differential circuit 191a and the positive component of the output signal of the polarity reversal circuit 192c (the negative component is cut off) and outputs them to the clock terminal CLK of the T flip-flop circuit 192.

[0075] exist Figure 7 In the example shown, the differential circuit 191a includes a CR circuit and a voltage follower. In the CR circuit, a filter capacitor Cf and a filter resistor Rf are connected in series between the input terminal and the ground terminal, and the connection point of the filter capacitor Cf and the filter resistor Rf becomes the output terminal. The CR circuit outputs a signal after attenuating the components below the cutoff frequency.

[0076] The voltage follower is composed of a first operational amplifier OP1. The output terminal of the CR circuit is connected to the non-inverting input terminal of the first operational amplifier OP1, and the output terminal of the first operational amplifier OP1 is connected to the inverting input terminal. The voltage follower is a buffer that can be regarded as amplification factor = 1, input impedance = ∞, and output impedance = 0. By inserting a voltage follower between the CR circuit and the polarity reversal circuit 191b, it is possible to suppress the time constant of the CR circuit from changing due to the influence of the first resistor R1 and the second resistor R2 included in the polarity reversal circuit 191b.

[0077] In addition, Figure 7 , an example of using a passive filter (CR high-pass filter) and a voltage follower to form the differential circuit 191a is shown, but the differential circuit 191a may also be formed using an active filter (differential circuit using an operational amplifier). In the differential circuit using an operational amplifier, a capacitor is connected to the input terminal of the operational amplifier.

[0078] The polarity reversal circuit 191b includes a second operational amplifier OP2, a first resistor R1, and a second resistor R2. The first resistor R1 is connected between the inverting input terminal of the second operational amplifier OP2 and the output terminal of the first operational amplifier OP1 included in the differential circuit 191a. The second resistor R2 is connected to the feedback path between the output terminal and the inverting input terminal of the second operational amplifier OP2. The non-inverting input terminal of the second operational amplifier OP2 is connected to the ground.

[0079] The resistance values ​​of the first resistor R1 and the second resistor R2 are set to the same value (in Figure 7In the example shown, it is 10 kΩ). When the resistance values ​​of the first resistor R1 and the second resistor R2 are the same, the second operational amplifier OP2 becomes an inverting amplifier with a gain of 1, and only the polarity of the output signal (V2) of the differential circuit 191a is inverted. In addition, it is not necessary to make the height of the amplitude of the output signal (V2) of the differential circuit 191a and the height of the amplitude of the output signal of the polarity inversion circuit 191b consistent, so the gain of the inverting amplifier can also be set to a gain other than 1.

[0080] The diode OR circuit 191c includes a first diode D1 and a second diode D2.

[0081] The anode terminal of the first diode D1 is connected to the output terminal of the differential circuit 191a, and the cathode terminal is connected to the clock terminal CLK of the T flip-flop circuit 192. The anode terminal of the first diode D1 is connected to the output terminal of the polarity reversal circuit 191b, and the cathode terminal is connected to the clock terminal CLK of the T flip-flop circuit 192. Through the polarity reversal circuit 191b and the diode logical OR circuit 191c, the polarity of the rising edge and the falling edge of the input signal (V1) detected by the differential circuit 191a is unified. Specifically, the falling edge is converted into a rising edge, so that all become rising edges.

[0082] The T flip-flop circuit 192 is a flip-flop circuit that inverts the output when the rising edge of the input clock terminal CLK is used as a trigger. Figure 7 1 shows an example of an edge-triggered D flip-flop circuit. In the edge-triggered D flip-flop circuit, the inverting output terminal / Q is connected to the input terminal D. In addition, by fixing the inputs of the first input terminal J and the second input terminal K of the JK flip-flop circuit to 1, a T flip-flop circuit 192 can also be realized.

[0083] Figure 8 It is shown Figure 7 The truth table of the T flip-flop circuit 192 is shown in FIG. At the rising edge of the signal input to the clock terminal CLK, the values ​​of the output terminal Q and the inverting output terminal / Q are inverted. During the rest of the period, the values ​​of the output terminal Q and the inverting output terminal / Q are maintained.

[0084] Alternatively, the rising and falling edges of the input signal (V1) detected by the differentiating circuit 191a may be unified into a falling edge, and a T flip-flop circuit may be used that inverts the output with the falling edge of the input to the clock terminal CLK as a trigger.

[0085] exist Figure 7In the example shown, dual-power operational amplifiers are used for the first operational amplifier OP1 and the second operational amplifier OP2. Specifically, dual-power operational amplifiers of +15V and -15V are used. A first switch S1 is connected between the +15V power supply and the positive power supply terminals of the first operational amplifier OP1 and the second operational amplifier OP2. A second switch S2 is connected between the -15V power supply and the negative power supply terminals of the first operational amplifier OP1 and the second operational amplifier OP2. The +15V power supply and the -15V power supply are supplied from the first power supply circuit 14.

[0086] When the authentication period including the reception of the ID when the battery pack 10 is installed (for example, a period of 10 seconds from the installation of the battery pack 10) ends, the first control unit 15 disconnects the active element (in the edge detection unit 191) included in the edge detection unit 191 by turning off the first switch S1 and the second switch S2. Figure 7 In the example shown, the power supply is for the first operational amplifier OP1 and the second operational amplifier OP2. Thus, the power consumption during the period when the first ID detection circuit 19 is not used can be reduced, and the capacity of the battery 11 can be saved.

[0087] Furthermore, when the authentication period including the reception of the ID when the battery pack 10 is mounted ends, the first control unit 15 may cut off the power supply to the T flip-flop circuit 192. For example, when the T flip-flop circuit 192 operates with a 1V to 5V power supply, the first control unit 15 cuts off the power supply to the T flip-flop circuit 192 by turning off a switch (not shown) between the 1V to 5V power supply and the power supply terminal of the T flip-flop circuit 192.

[0088] Below, it is shown Figure 7 The results of simulation 1 of the first ID detection circuit 19 are shown. In simulation 1, a filter capacitor Cf of 0.1 μF and a filter resistor Rf of 10Ω are used. In this case, the time constant τ of the CR circuit is 0.1 μs, and the cutoff frequency fc of the CR circuit is ≈159.2 kHz.

[0089] Figure 9A-9D 2 is a diagram showing a simulation waveform indicating the execution result of simulation 1. Fig. 9A 1 shows the waveform of the input signal (V1) input to the first ID detection circuit 19, Fig. 9B 1 shows the waveform of the output signal (V2) of the differentiating circuit 191a, Fig. 9C 1 shows the waveform of the output signal (V3) of the edge detection unit 191, Fig.9D The waveform of the output signal (V4) of the T flip-flop circuit 192 is shown.

[0090] In this embodiment, 9600 bps is assumed as the communication speed of the ID. In simulation 1, a rectangular wave with a clock frequency of 5 kHz (a period of 0.2 ms) is used as the input signal (V1) to approximate the clock frequency when 9600 bits are transmitted in 1 second.

[0091] In simulation 1, the following example is shown: the current flowing in the power line is offset from the time point of 1.0 ms, so that the input signal (V1) rises by an amount corresponding to the offset. The amplitude of the output signal (V2) of the differential circuit 191a and the output signal (V3) of the edge detection unit 191 at the time point of 1.0 ms increases, but it does not affect the waveform of the output signal (V4) of the T flip-flop circuit 192. In this way, by inputting the differential waveform with unified polarity to the T flip-flop circuit 192, a similar waveform of the input signal (V1) can be restored without the influence of the offset (that is, the influence of the current fluctuation in communication).

[0092] Fig.10 It is shown Figure 7 FIG. 1 is a diagram showing an expanded example of configuration example 1 of the first ID detection circuit 19 shown in FIG. Fig.10 The structure of the first ID detection circuit 19 shown is Figure 7 The structure of the first ID detection circuit 19 shown in FIG. 1 is obtained by adding a mask circuit 193. Fig.10 The T flip-flop circuit 192 shown is provided with a set terminal PRE and a clear terminal CLR.

[0093] Fig.11 It is shown Fig.10 Graph of the truth table of the T flip-flop circuit 192 shown.

[0094] While "1" (high level) is input to the set terminal PRE and "0" (low level) is input to the clear terminal CLR, the value of the output terminal Q is fixed to "0" and the value of the inverting output terminal / Q is fixed to "1" regardless of the input value of the clock terminal CLK. Conversely, while "0" is input to the set terminal PRE and "1" is input to the clear terminal CLR, the value of the output terminal Q is fixed to "1" and the value of the inverting output terminal / Q is fixed to "0" regardless of the input value of the clock terminal CLK.

[0095] During the period when both the set terminal PRE and the clear terminal CLR are input with "0", Figure 7 The truth table of the T flip-flop circuit 192 shown in FIG. 1 is the same logic. In addition, inputting "1" to both the set terminal PRE and the clear terminal CLR is prohibited.

[0096] When the output signal of the T flip-flop circuit 192 is at a low level after passing through a certain edge detection interval, the mask circuit 193 inputs a high level signal to the clear terminal CLR and a low level signal to the set terminal PRE until the next edge detection interval. In addition, when the output signal of the T flip-flop circuit 192 is at a high level after passing through a certain edge detection interval, the mask circuit 193 inputs a high level signal to the set terminal PRE and a low level signal to the clear terminal CLR until the next edge detection interval.

[0097] The edge detection interval is set to include a position where the high level and the low level of the input signal (V1) may change (i.e., a position where an edge may be detected). In a unit cycle, the ratio of the edge detection interval to the non-edge detection interval is set to 1:9 or 2:8, for example. In this embodiment, it is assumed that the communication rate (bps) is fixed, so the edge detection interval can be periodically set according to the communication rate of the ID bit string.

[0098] The mask circuit 193 masks the output signal ( V3 ) of the edge detection unit 191 in the non-edge detection interval, thereby preventing the output of the T flip-flop circuit 192 from being inverted in the non-edge detection interval.

[0099] Fig.12 1 is a diagram showing a simulated waveform in which a noise pulse is mixed in the output signal (V3) of the edge detection unit 191. If a noise pulse is mixed in the non-edge detection interval of the input signal (V1), the output signal of the T flip-flop circuit 192 will be inverted due to the noise pulse, and the input signal (V1) cannot be correctly restored.

[0100] Fig.13 3 is a diagram showing a simulation waveform including masking pulses M1 and M2.

[0101] The first masking pulse M1 is a pulse for masking the change of the output signal (V3) of the edge detection unit 191 due to the noise pulse in the non-edge detection interval of the high-level input signal (V1). The second masking pulse M2 is a pulse for masking the change of the output signal (V3) of the edge detection unit 191 due to the noise pulse in the non-edge detection interval of the low-level input signal (V1). By inputting the masking pulses M1 and M2 to the T flip-flop circuit 192, the output signal (V4) of the T flip-flop circuit 192 in which the noise pulse is invalidated can be generated.

[0102] Fig.141 is a diagram showing a configuration example 2 of the first ID detection circuit 19. In the configuration example 2, the edge detection unit 191 includes a first differential circuit 191d, a second differential circuit 191e, and an inverting amplifier circuit 191f. The first differential circuit 191d differentiates an input signal (V5). The second differential circuit 191e differentiates an output signal (V6) of the first differential circuit 191d. The inverting amplifier circuit 191f inverts and amplifies an output signal (V7) of the second differential circuit 191e.

[0103] The first differential circuit 191d is composed of a CR circuit including a first filter capacitor Cf1 and a first filter resistor Rf1. In addition, a voltage follower may be connected to the subsequent stage of the CR circuit as in the structural example 1. The second differential circuit 191e is composed of a CR circuit including a second filter capacitor Cf2 and a second filter resistor Rf2. In addition, a voltage follower may be connected to the subsequent stage of the CR circuit as in the structural example 1.

[0104] The inverting amplifier circuit 191f includes a third operational amplifier OP3, a third resistor R3, and a fourth resistor R4. The third resistor R3 is connected between the inverting input terminal of the third operational amplifier OP3 and the output terminal of the second differential circuit 191e. The fourth resistor R4 is connected to the feedback path between the output terminal and the inverting input terminal of the third operational amplifier OP3. The non-inverting input terminal of the third operational amplifier OP3 is connected to the ground.

[0105] The inverting amplifier circuit 191f inverts and amplifies the output signal (V7) of the second differential circuit 191e at an amplification factor specified by (R4 / R3). Fig.14 In the example shown, the resistance value of the third resistor R3 is set to 10kΩ, and the resistance value of the fourth resistor R4 is set to 60kΩ, so the inverting amplifier circuit 191f amplifies the output signal (V7) of the second differential circuit 191e by -6 times and outputs it to the clock terminal CLK of the T trigger circuit 192.

[0106] The gain of the signal passing through the differentiating circuit formed by the CR circuit will decrease. Fig.14 In the example shown, the capacitance of the first filter capacitor Cf1 and the second filter capacitor Cf2 is set to 0.1 μF, and the resistance of the first filter resistor Rf1 and the second filter resistor Rf2 is set to 10Ω. For example, when the input signal (V5) of a clock frequency of 5 kHz passes through the first differential circuit 191d, the amplitude is reduced to about 5 / 9 to 1 / 3. Fig.14 In the embodiment, the first differential circuit 191d and the second differential circuit 191e are connected in two stages, so the amplitude of the input signal (V5) is reduced to about (5 / 9 to 1 / 3) 2 .

[0107] If the amplitude of the output signal (V7) of the second differentiating circuit 191e becomes lower than the threshold voltage of the T flip-flop circuit 192, the T flip-flop circuit 192 cannot correctly determine whether the output signal (V7) of the second differentiating circuit 191e is a high level signal or a low level signal. For example, when a 1V power supply is used for the T flip-flop circuit 192, the threshold voltage is set to 0.5V, and when a 5V power supply is used for the T flip-flop circuit 192, the threshold voltage is set to 2.5V.

[0108] exist Fig.14 In the configuration example 2 shown, an inverting amplifier circuit 191f is provided to amplify the output signal (V7) of the second differentiating circuit 191e so that the amplitude of the output signal (V7) of the second differentiating circuit 191e becomes a value sufficiently larger than the threshold voltage of the T flip-flop circuit 192. The gain of the inverting amplifier circuit 191f is set to a value for making the amplitude of the output signal (V7) of the second differentiating circuit 191e fall within the input voltage range of the T flip-flop circuit 192 and sufficiently larger than the threshold voltage of the T flip-flop circuit 192.

[0109] In addition, a non-inverting amplifier circuit may be used instead of the inverting amplifier circuit 191f. In the structural example 2, by performing a second differentiation on the input signal (V5), an edge detection signal defined by a waveform that crosses positive and negative at the edge detection position can be generated. Therefore, regardless of whether the polarity of the output signal (V7) of the second differential circuit 191e is inverted or not inverted before the output signal (V7) of the second differential circuit 191e is input to the T flip-flop circuit 192, the output signal (V9) of the T flip-flop circuit 192 becomes the same waveform. The operation of the T flip-flop circuit 192 is the same as that of the structural example 1.

[0110] exist Fig.14 In the example shown, a dual-power operational amplifier is used for the third operational amplifier OP3. Specifically, a dual-power operational amplifier of +15V and -15V is used. A first switch S1 is connected between the +15V power supply and the positive power supply terminal of the third operational amplifier OP3. A second switch S2 is connected between the -15V power supply and the negative power supply terminal of the third operational amplifier OP3. The +15V power supply and the -15V power supply are supplied from the first power supply circuit 14.

[0111] When the authentication period including the reception of the ID when the battery pack 10 is installed ends, the first control unit 15 cuts off the active element (in the edge detection unit 191) included in the edge detection unit 191 by turning off the first switch S1 and the second switch S2. Fig.14In the example shown, the power supply to the operational amplifier OP3 is cut off. When the first differential circuit 191d and the second differential circuit 191e are connected to a voltage follower, the first control unit 15 also cuts off the power supply to the voltage follower. The first control unit 15 may also cut off the power supply to the T flip-flop circuit 192.

[0112] Below, it is shown Fig.14 Execution results of simulation 2 of the first ID detection circuit 19 are shown.

[0113] In simulation 2, 0.1 μF first filter capacitor Cf1 and second filter capacitor Cf2 and 10Ω first filter resistor Rf1 and second filter resistor Rf2 were used. In this case, the time constant τ of each CR circuit is 0.1 μs, and the cutoff frequency fc≈159.2 kHz of each CR circuit.

[0114] Figure 15A-15E (e) is a diagram showing a simulation waveform indicating the execution result of Simulation 2. Fig.15A 1 shows the waveform of the input signal (V5) input to the first ID detection circuit 19, Fig. 15B 1 shows the waveform of the output signal (V6) of the first differentiating circuit 191d, Fig. 15C 1 shows the waveform of the output signal (V7) of the second differentiating circuit 191e, Fig.15D 191f shows the waveform of the output signal (V8) of the inverting amplifier circuit 191f. Fig.15E The waveform of the output signal (V9) of the T flip-flop circuit 192 is shown.

[0115] In this embodiment, 9600 bps is assumed as the communication speed of ID. In simulation 2, a rectangular wave with a clock frequency of 5 kHz (a period of 0.2 ms) is used as the input signal (V5) to approximate the clock frequency when 9600 bits are transmitted in 1 second.

[0116] In simulation 2, the following example is also shown: the current flowing in the power line is offset from the time point of 1.0 ms, so that the input signal (V5) rises by an amount corresponding to the offset. The amplitudes of the output signal (V6) of the first differential circuit 191d, the output signal (V7) of the second differential circuit 191e, and the output signal (V8) of the inverting amplifier circuit 191f at the time point of 1.0 ms increase, but do not affect the waveform of the output signal (V9) of the T flip-flop circuit 192. In this way, by inputting the secondary differential waveform that captures the edge timing to the T flip-flop circuit 192, a similar waveform of the input signal (V5) that eliminates the influence of the offset (that is, the influence of the current fluctuation in communication) can be restored.

[0117] Fig.16 It is shown Fig.14 FIG. 2 is a diagram showing an expanded example of configuration example 2 of the first ID detection circuit 19 shown in FIG.

[0118] Fig.16 The structure of the first ID detection circuit 19 shown is Fig.14 The structure of the first ID detection circuit 19 shown in FIG. 1 is obtained by adding a mask circuit 193. Fig.14 The T flip-flop circuit 192 shown is provided with a set terminal PRE and a clear terminal CLR. The operation of the mask circuit 193 and the effects brought about by adding the mask circuit 193 are the same as those in the first configuration example.

[0119] In the above description, an example is shown in which the ID superimposed on the current flowing in the power line is detected by hardware processing of the first ID detection circuit 19. In this regard, it is also possible to detect by software processing of the first control unit 15 (microcontroller). In this case, the first ID detection circuit 19 is omitted, and the input signal (V1, V5) corresponding to the current measured by the first current sensor 13 is directly input to the analog input port of the first control unit 15 (microcontroller).

[0120] The A / D converter in the first control unit 15 (microcontroller) converts the input signal (V1, V5) into a digital value at a sampling rate higher than the clock frequency corresponding to the communication speed of the ID (for example, a sampling rate of about 100 times the clock frequency). In order to carefully observe the waveform transition within the unit period of the input signal, high-speed sampling is required. The CPU in the first control unit 15 (microcontroller) differentiates the digital input signal (V1, V5) obtained by high-speed sampling to detect the edge of the input signal (V1, V5). Whenever an edge of the input signal (V1, V5) is detected, the CPU inverts the logic of the output signal specified by the binary signal. The CPU compares the generated output signal with the threshold value for bit determination to detect each bit of the ID.

[0121] The ID detection process by software processing is effective when the communication speed of the ID is low.

[0122] On the other hand, when the communication speed of the ID is high, it is necessary to use a high-performance component as the first control unit 15 (microcontroller). In addition, it is necessary to deal with heat. In the ID detection process based on software processing, it is easier to change the time constant than the ID detection process based on hardware processing. In addition, there is no need to amplify the secondary differential signal, so the noise generated by signal amplification is not mixed. In the CR circuit, the inclination of the amplitude regression during edge detection becomes gentle, so when performing secondary differentiation, it is necessary to amplify.

[0123] As described above, in this embodiment, by generating a signal that is outputted inverted each time an edge of the input signal is detected, it is possible to reproduce the input signal from which the influence of DC fluctuations has been removed. In addition, by setting the time constant of the high pulse filter to an optimum value, it is possible to remove the influence of short-term current fluctuations that are slower than the waveform change speed when the input signal is logically inverted. In addition, by using a trigger circuit, it is possible to shield the fluctuations of the input signal during the period outside the edge detection interval. Thus, it is possible to prevent the output signal from being erroneously inverted due to noise during this period. In contrast, when a Schmitt trigger circuit is used, it is impossible to shield the fluctuations of the input signal during the period outside the edge detection interval, so the probability of erroneous judgment due to noise is higher than when a trigger circuit is used. In this way, in this embodiment, it is possible to reduce erroneous judgments when detecting ID from a current signal.

[0124] In addition, the ID detection method of the present embodiment can be realized by a simple circuit or simple software, which has great advantages in actual use. In addition, the ID detection method of the present embodiment has high versatility and a wide range of applications.

[0125] The present disclosure has been described above based on the embodiments. It should be easily understood by those skilled in the art that the embodiments are illustrative and that various modifications can be made to the combinations of the constituent elements and the processing procedures, and such modifications are also within the scope of the present disclosure.

[0126] In the above embodiment, the following example is described: the battery pack 10 installed in the installation slot of the vehicle 20 is authenticated to be the same as the battery pack 10 that is the communication target of the vehicle 20. In this regard, the ID detection method involved in the above embodiment can also be used in the case where the battery pack 10 installed in the installation slot of the charger is authenticated to be the same as the battery pack 10 that is the communication target of the charger. In this case, the charger can be the identification information sending device and the battery pack 10 can be the identification information receiving device, or the battery pack 10 can be the identification information sending device and the charger can be the identification information receiving device.

[0127] In the above embodiment, an example of using the battery pack 10 with built-in storage battery 11 is described. In this regard, a capacitor pack with built-in capacitors including double-layer capacitor units, lithium-ion capacitor units, etc. may also be used. In this specification, the battery pack and the capacitor pack are collectively referred to as a storage pack.

[0128] The present disclosure is suitable for application to a vehicle 20 that is not equipped with a self-contained power supply, but does not exclude application to a vehicle 20 that is equipped with a self-contained power supply. Therefore, the vehicle 20 is not limited to an electric power-assisted bicycle, but also includes an electric motorcycle (electric scooter), an electric kick scooter, an electric car (including a golf cart, a low-speed electric car such as a landcar), a railway vehicle, etc. In addition, the object on which the power storage group is installed is not limited to the vehicle 20, but also includes, for example, an electric ship, a multi-rotor aircraft (drone), and other electric mobile bodies.

[0129] In addition, the implementation mode can also be determined by the following items.

[0130] [Project 1]

[0131] An identification information receiving device (10) for receiving identification information defined by a plurality of bits superimposed on a current or voltage of a power line by an identification information transmitting device (20) connected via a power line, wherein the identification information receiving device (10) is characterized in that it comprises:

[0132] an edge detection unit (191) for detecting an edge of an input signal for acquiring the current or voltage of the power line as a voltage value; and

[0133] A T flip-flop circuit (192) inverts an output whenever an edge of the input signal is detected.

[0134] This makes it possible to receive identification information in which the influence of current fluctuations or voltage fluctuations during communication is reduced.

[0135] [Project 2]

[0136] The identification information receiving device (10) described in item 1 is characterized in that:

[0137] When the output signal of the T flip-flop circuit (192) is low level after passing through the edge detection interval, a high level signal is input to the clear terminal and a low level signal is input to the set terminal until the next edge detection interval.

[0138] When the output signal of the T flip-flop circuit (192) is high level after passing through the edge detection interval, a high level signal is input to the set terminal and a low level signal is input to the clear terminal until the next edge detection interval.

[0139] This can reduce erroneous determinations due to noise.

[0140] [Item 3]

[0141] The identification information receiving device (10) described in item 1 is characterized in that:

[0142] The edge detection unit (191) comprises:

[0143] a differentiating circuit (191a) for differentiating the input signal;

[0144] a polarity inversion circuit (191b) that inverts the polarity of an output signal of the differential circuit (191a); and

[0145] A diode logic OR circuit (191c) conducts the positive component of the output signal of the differential circuit (191a) and the positive component of the output signal of the polarity inversion circuit (191b) and outputs them to the clock terminal of the T flip-flop circuit (192).

[0146] This makes it possible to generate a differential waveform of the input signal with uniform polarity.

[0147] [Item 4]

[0148] The identification information receiving device (10) described in item 3 is characterized in that:

[0149] The differential circuit (191a) includes a CR circuit (Cf, Rf) and a voltage follower (OP1).

[0150] According to this, a high pulse filter can be constructed at low cost.

[0151] [Item 5]

[0152] The identification information receiving device (10) described in item 1 is characterized in that:

[0153] The edge detection unit (191) comprises:

[0154] a first differentiating circuit (191d) for differentiating the input signal; and

[0155] A second differentiating circuit (191e) is configured to differentiate the output signal of the first differentiating circuit (191d).

[0156] According to this, it is possible to generate an edge detection signal defined by a waveform that straddles positive and negative edges at the edge detection position of the input signal.

[0157] [Item 6]

[0158] The identification information receiving device (10) described in item 5 is characterized in that:

[0159] The edge detection unit (191) further includes a non-inverting amplifier circuit for amplifying an output signal of the second differential circuit (191e), or an inverting amplifier circuit (191f) for inverting and amplifying an output signal of the second differential circuit (191e).

[0160] According to this, the amplitude of the secondary differential waveform can be converted to a voltage exceeding the threshold voltage of the T flip-flop circuit (192).

[0161] [Item 7]

[0162] The identification information receiving device (10) described in item 1 is characterized in that:

[0163] When the authentication period including the reception of the identification information ends, the power supply to the active elements (OP1, OP2) included in the edge detection unit (191) is cut off.

[0164] According to this, useless power consumption can be eliminated.

[0165] [Item 8]

[0166] A portable power storage pack (10) that can be attached or detached is used as the identification information receiving device (10) described in any one of items 1 to 7.

[0167] This makes it possible to realize a power storage group (10) capable of receiving identification information with reduced influence of current fluctuations or voltage fluctuations during communication.

[0168] [Item 9]

[0169] A method for receiving identification information is provided in an identification information receiving device (10), the identification information receiving device (10) being used to receive identification information defined by a plurality of bits and superimposed on a current or voltage of a power line by an identification information sending device (20) connected via a power line, the method for receiving identification information being characterized in that it comprises the following steps:

[0170] detecting an edge of an input signal for acquiring the current or voltage of the power line as a voltage value; and

[0171] Every time an edge of the input signal is detected, the output specified by the binary signal is inverted.

[0172] This makes it possible to receive identification information in which the influence of current fluctuations or voltage fluctuations during communication is reduced.

[0173] [Item 10]

[0174] An identification information receiving program is an identification information receiving program in an identification information receiving device (10), the identification information receiving device (10) being used to receive identification information specified by a plurality of bits superimposed on a current or voltage of a power line by an identification information transmitting device (20) connected via a power line, the identification information receiving program being characterized in that it causes a computer to execute the following processing:

[0175] detecting an edge of an input signal for acquiring the current or voltage of the power line as a voltage value; and

[0176] Every time an edge of the input signal is detected, the output specified by the binary signal is inverted.

[0177] Description of Reference Numerals

[0178] 10: battery pack; 20: vehicle; 11: storage battery; 12: first relay; 13: first current sensor; 14: first power supply circuit; 15: first control unit; 16: first wireless communication unit; 17: first antenna; 18: first ID superimposition circuit; 19: first ID detection circuit; 21: motor; 22: inverter; 23: second relay; 24: second power supply circuit; 25: second control unit; 26: second wireless communication unit; 27: second antenna; 28: second ID superimposition circuit; 29: second ID detection circuit; 210: voltage detection circuit; T1: power supply terminal; T2: power receiving terminal; Lp: power line; 191: edge detection unit; 191a: differential circuit; 191b: polarity reversal circuit; 191c: diode logic OR circuit; 191d: first differential circuit; 191e: second differential circuit; 191f: inverting amplifier circuit; 192: T trigger circuit; 193: shielding circuit; Rf-Rf2: filter resistor; R1-R4: resistor; Cf-Cf2: filter capacitor; OP1-OP3: third operational amplifier; D1-D2: diode; S1-S2: switch.

Claims

1. An identification information receiving device for receiving identification information defined by a plurality of bits superimposed on a current or voltage of a power line by an identification information transmitting device connected via a power line, the identification information receiving device comprising: an edge detection unit that detects an edge of an input signal that acquires the current or voltage of the power line as a voltage value; and A T flip-flop circuit inverts an output whenever an edge of the input signal is detected.

2. The identification information receiving device according to claim 1, characterized in that: When the output signal of the T flip-flop circuit is low level after passing through the edge detection interval, a high level signal is input to the clear terminal and a low level signal is input to the set terminal until the next edge detection interval. When the output signal of the T flip-flop circuit is high level after the edge detection interval has passed, a high level signal is input to the set terminal and a low level signal is input to the clear terminal until the next edge detection interval.

3. The identification information receiving device according to claim 1, characterized in that: The edge detection unit comprises: a differentiating circuit for differentiating the input signal; a polarity inversion circuit that inverts the polarity of an output signal of the differentiating circuit; and A diode logic OR circuit that conducts the positive component of the output signal of the differentiation circuit and the positive component of the output signal of the polarity inversion circuit and outputs them to the clock terminal of the T flip-flop circuit.

4. The identification information receiving device according to claim 3, characterized in that: The differential circuit includes a capacitor-resistor circuit, namely, a CR circuit, and a voltage follower.

5. The identification information receiving device according to claim 1, characterized in that: The edge detection unit comprises: A first differentiating circuit that differentiates the input signal; and A second differentiating circuit is configured to differentiate the output signal of the first differentiating circuit.

6. The identification information receiving device according to claim 5, characterized in that: The edge detection unit further includes a non-inverting amplifier circuit for amplifying an output signal of the second differential circuit, or an inverting amplifier circuit for inverting and amplifying an output signal of the second differential circuit.

7. The identification information receiving device according to claim 1, characterized in that: When an authentication period including reception of the identification information ends, power supply to an active element included in the edge detection unit is cut off.

8. A detachable portable power storage pack, which serves as the identification information receiving device according to any one of claims 1 to 7.

9. A method for receiving identification information, in an identification information receiving device, the identification information receiving device being used to receive identification information defined by a plurality of bits superimposed on a current or voltage of the power line by an identification information transmitting device connected via a power line, the identification information receiving method being characterized in that it comprises the following steps: detecting an edge of an input signal for obtaining the current or voltage of the power line as a voltage value; as well as Every time an edge of the input signal is detected, the output specified by the binary signal is inverted.

10. An identification information receiving program, the identification information receiving program in an identification information receiving device, the identification information receiving device being used to receive identification information defined by a plurality of bits superimposed on a current or voltage of the power line by an identification information transmitting device connected via a power line, the identification information receiving program being characterized in that it causes a computer to execute the following processing: detecting an edge of an input signal for acquiring the current or voltage of the power line as a voltage value; and Every time an edge of the input signal is detected, the output specified by the binary signal is inverted.

11. A non-transitory recording medium recording an identification information receiving program in an identification information receiving device, the identification information receiving device being used to receive identification information defined by a plurality of bits superimposed on a current or voltage of the power line by an identification information transmitting device connected via a power line, the recording medium being characterized in that the identification information receiving program causes a computer to execute the following processing: detecting an edge of an input signal for acquiring the current or voltage of the power line as a voltage value; and Every time an edge of the input signal is detected, the output specified by the binary signal is inverted.

Images