Clock constraint definition method and device, electronic equipment and storage medium

Abstract

The invention discloses a clock constraint definition method and device, electronic equipment and a storage medium. The method comprises the steps that top-layer description information of each clock in a plurality of clocks is obtained, the top-layer description information comprises definition information of top-layer clock constraints of each clock and position information of each clock in a bottom-layer module, and the definition information is obtained by conducting top-layer clock definition on each clock in a top layer of chip design; the position information is determined based on the position of each clock in at least one bottom layer module corresponding to the top layer, and the position information comprises at least one bottom layer starting point of each clock in the at least one bottom layer module; and based on the top layer description information of at least one clock in the plurality of clocks, automatically defining a bottom layer clock constraint of a target clock in the at least one clock in the corresponding at least one bottom layer module. According to the method, the clock constraint of the clock in the bottom layer module can be automatically defined based on the top layer description information of the clock, manpower is saved, and the correctness of the early clock constraint is ensured.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a clock constraint definition method, device, electronic device, and storage medium. Background Art

[0002] In the field of integrated circuit (IC) design, as the complexity of chips continues to grow, traditional design methods can no longer meet the needs of efficient development. In order to meet this challenge, a variety of design strategies have emerged, including top-down design methods, bottom-up design methods, and hierarchy-flow design methods.

[0003] The top-down design method generally only constrains the top-level design, and only synthesizes special modules separately, while the rest of the modules are synthesized together at the top level. The bottom-up design method usually designs each module separately, constrains each module independently, and then splices the modules together at the top level for synthesis.

[0004] However, as chip designs become larger and larger, the number of gate levels increases, and both the top-down design method and the bottom-up design method cannot complete the synthesis of all designs at one time. In large-scale integrated circuit design, especially for high-performance central processing unit (CPU) or graphics processing unit (GPU) design, due to the huge scale of the chip (for example, the number of transistors is as high as tens of billions), the design complexity is very high, and the existing electronic design automation (EDA) tools and hardware resources cannot realize such a huge design at one time. Therefore, the hierarchical process design method is often used in chip design.

[0005] The hierarchical process design method first splits the design into multiple modules, then constrains and synthesizes each module separately, and finally stitches the modules together at the top level. For example, in the stage from register transfer level (RTL) to graphic data system (GDS), the chip is usually divided into different modules for separate synthesis and layout and routing. Only a few connections and input and output (IO) logic are retained at the top level to reduce the complexity of the top level, and finally the different modules are stitched together at the top level. However, in this case, it is necessary to constrain different modules separately in order to perform synthesis and layout and routing, and it is also necessary to retain the constraints at the top level to complete a series of timing signoffs at the top level. Summary of the invention

[0006] At least one embodiment of the present disclosure provides a clock constraint definition method, the clock constraint definition method comprising: obtaining top-level description information of each clock among a plurality of clocks, wherein the top-level description information comprises definition information of the top-level clock constraint of each clock and position information of each clock in a bottom-level module, the definition information is obtained based on top-level clock definition of each clock in the top level of chip design, the position information is determined based on the position of each clock in at least one bottom-level module corresponding to the top level, and the position information comprises at least one bottom-level starting point of each clock in at least one bottom-level module; based on the top-level description information of at least one clock among the plurality of clocks, automatically defining the bottom-level clock constraint of a target clock in the at least one clock in the corresponding at least one bottom-level module.

[0007] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the definition information of the top-level clock constraints of each clock is obtained based on the top-level clock definition of each clock in the top level of the chip design, including: in response to any clock among the multiple clocks being a master clock in the top level, determining that the definition information of the top-level clock constraints of any clock includes: the top-level clock period, the top-level clock duty cycle, and the top-level clock definition point; or in response to any clock among the multiple clocks being a generated clock in the top level, determining that the definition information of the top-level clock constraints of any clock includes: the top-level master clock name, the top-level clock source definition point, the top-level generation type, and the top-level generation end definition point.

[0008] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the top-level description information also includes a top-level clock type, and the top-level clock type includes a first top-level type and a second top-level type. The first top-level type indicates that any clock in the top level is a master clock, and the second top-level type indicates that any clock in the top level is a generated clock.

[0009] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the bottom-level clock constraints of the target clock among the multiple clocks in the corresponding at least one bottom-level module are automatically defined based on the top-level description information of at least one clock among the multiple clocks, including: in response to the top-level clock type of the target clock being the first top-level type, determining that the at least one clock only includes the target clock; based on the top-level description information of the target clock, automatically defining the bottom-level clock constraints of the target clock in the current bottom-level module in the corresponding at least one bottom-level module, wherein the bottom-level clock constraints of the target clock include a bottom-level clock period, a bottom-level clock duty cycle, and a bottom-level clock definition point.

[0010] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the bottom-level clock constraint of the target clock in the current bottom-level module in the corresponding at least one bottom-level module is automatically defined based on the top-level description information of the target clock, including: setting the bottom-level clock period of the target clock equal to the top-level clock period of the target clock; setting the bottom-level clock duty cycle of the target clock equal to the top-level clock duty cycle of the target clock; setting the name of the bottom-level clock definition point of the target clock to the name of the bottom-level starting point of the target clock in the current bottom-level module, and determining the pin type of the bottom-level clock definition point according to the name of the bottom-level starting point of the target clock in the current bottom-level module, wherein the pin type of the bottom-level clock definition point includes a first pin type and a second pin type, the first pin type indicating that the target clock is located at a port of the current bottom-level module, and the second pin type indicating that the target clock is located at an internal point of the current bottom-level module.

[0011] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the bottom-level clock constraints of the target clock in the at least one clock in the corresponding at least one bottom-level module are automatically defined based on the top-level description information of at least one clock among the multiple clocks, including: in response to the top-level clock type of the target clock being the second top-level type, determining that the at least one clock includes the target clock and the upper-level clock set of the target clock, the upper-level clock set includes at least a first-level clock, and the first-level clock is the master clock of the target clock; based on the top-level description information of the target clock and the top-level description information of the upper-level clock set, automatically defining the bottom-level clock constraints of the target clock in the current bottom-level module in the corresponding at least one bottom-level module.

[0012] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the bottom-level clock constraint of the target clock in the current bottom-level module in the corresponding at least one bottom-level module is automatically defined based on the top-level description information of the target clock and the top-level description information of the upper-level clock set, including: judging the bottom-level clock type of the target clock in the current bottom-level module based on the name of the bottom-level starting point of the target clock in the current bottom-level module; and automatically defining the bottom-level clock constraint of the target clock in the current bottom-level module based on the bottom-level clock type of the target clock in the current bottom-level module, the top-level description information of the target clock, and the top-level description information of the upper-level clock set, wherein the bottom-level clock type includes a first bottom-level type and a second bottom-level type, the first bottom-level type indicating that the target clock is a master clock in the current bottom-level module, and the second bottom-level type indicating that the target clock is a generated clock in the current bottom-level module.

[0013] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the bottom-level clock constraint of the target clock in the current bottom-level module is automatically defined based on the bottom-level clock type of the target clock in the current bottom-level module, the top-level description information of the target clock, and the top-level description information of the upper-level clock set, including: in response to the bottom-level clock type of the target clock being the second bottom-level type, determining that the bottom-level clock constraint of the target clock includes a bottom-level master clock name, a bottom-level clock source definition point, a bottom-level generation type, and a bottom-level generation end definition point; obtaining the definition information of the top-level clock constraint of the first-level clock in the upper-level clock set; setting the bottom-level master clock name of the target clock to the clock name of the first-level clock; setting the name of the bottom-level clock source definition point of the target clock to the name of the bottom-level starting point of the first-level clock in the current bottom-level module; setting the bottom-level generation type of the target clock to the top-level generation type of the target clock; and setting the name of the bottom-level generation end definition point of the target clock to the name of the bottom-level starting point of the target clock in the current bottom-level module.

[0014] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the bottom-level clock constraint of the target clock in the current bottom-level module is automatically defined based on the bottom-level clock type of the target clock in the current bottom-level module, the top-level description information of the target clock, and the top-level description information of the upper-level clock set, including: in response to the bottom-level clock type of the target clock being the first bottom-level type, determining that the bottom-level clock constraint of the target clock includes a bottom-level clock period, a bottom-level clock duty cycle, and a bottom-level clock definition point; obtaining the definition information of the top-level clock constraint of the upper-level clock set of the target clock; calculating the bottom-level clock period and the bottom-level clock duty cycle of the target clock according to the top-level generation type of the target clock and the definition information of the top-level clock constraint of the upper-level clock set; setting the name of the bottom-level clock definition point of the target clock to the name of the bottom-level starting point of the target clock in the current bottom-level module, and determining that the pin type of the bottom-level clock definition point of the target clock is the first pin type.

[0015] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the bottom-level clock period and the bottom-level clock duty cycle of the target clock are calculated according to the top-level generation type of the target clock and the definition information of the top-level clock constraints of the upper-level clock set, including: according to the top-level generation type of the target clock being at least one of frequency division, frequency multiplication, inversion, and phase shift, determining that the first objective function corresponding to the top-level generation type of the target clock is at least one of a frequency division function, a frequency multiplication function, a inversion function, and a phase shift function; based on the first objective function and the definition information of the top-level clock constraints of the upper-level clock set, calculating the bottom-level clock period and the bottom-level clock duty cycle of the target clock.

[0016] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the calculation of the bottom-level clock period and the bottom-level clock duty cycle of the target clock based on the definition information of the top-level clock constraint of the first objective function and the upper-level clock set includes: in response to the top-level clock type of the first-level clock being the first top-level type, directly applying the first objective function to the top-level clock period and the top-level clock duty cycle of the first-level clock, thereby calculating the bottom-level clock period and the bottom-level clock duty cycle of the target clock;

[0017] Alternatively, in response to the top-level clock type of the first-level clock being the second top-level type, the top-level clock constraint information of the second-level clock which is the master clock of the first-level clock is obtained; in response to the top-level clock type of the second-level clock being the first top-level type, a second objective function is determined according to the top-level generation type of the first-level clock; and the first objective function and the second objective function are nestedly applied to calculate the bottom-level clock period and the bottom-level clock duty cycle of the target clock.

[0018] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the bottom-level clock period and the bottom-level clock duty cycle of the target clock are calculated based on the frequency division function, including: obtaining the frequency division coefficient Q; setting the bottom-level clock period Period of the target clock equal to the top-level clock period Period_Master of the first-level clock multiplied by the frequency division coefficient Q; setting the vector Waveform of the bottom-level clock duty cycle of the target clock equal to the vector Waveform_Master of the top-level clock duty cycle of the first-level clock multiplied by the frequency division coefficient Q.

[0019] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the bottom-level clock period and the bottom-level clock duty cycle of the target clock are calculated based on the multiplication function, including: obtaining the multiplication coefficient P; setting the bottom-level clock period Period of the target clock equal to the top-level clock period Period_Master of the first-level clock divided by the multiplication coefficient P; setting the vector Waveform of the bottom-level clock duty cycle of the target clock equal to the vector Waveform_Master of the top-level clock duty cycle of the first-level clock divided by the multiplication coefficient P.

[0020] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the underlying clock period and the underlying clock duty cycle of the target clock are calculated based on the reverse function, including: setting the underlying clock period Period of the target clock equal to the top-level clock period Period_Master of the first-level clock; obtaining the vector representation [x1, x2,…, xn] of the vector Waveform_Master of the top-level clock duty cycle of the first-level clock; in response to x2 being less than Period_Master, determining that the vector representation of the vector Waveform of the underlying clock duty cycle of the target clock is [x2, x3,…, xn, x1+Period_Master]; or in response to x2 being greater than or equal to Period_Master, determining that the vector representation of the vector Waveform of the underlying clock duty cycle of the target clock is [x2-Period_Master, x3-Period_Master,…, xn-Period_Master, x1].

[0021] For example, at least one embodiment of the present disclosure provides a clock constraint definition method further comprising: when invert and other generation types other_generate_type exist at the same time, nestedly applying the inverse function f <invert>and other functions f<other_generate_type> , thereby calculating the underlying clock period and the underlying clock duty cycle of the target clock, wherein the other types include the frequency division or the frequency multiplication.

[0022] For example, at least one embodiment of the present disclosure provides a clock constraint definition method further comprising: in response to first other types and then reverse, determining the underlying clock period Period=f of the target clock <invert>(f<other_generate_type> (Period_Master)), determine the vector Waveform of the underlying clock duty cycle of the target clock = f <invert>(f<other_generate_type> (Waveform_Master)); in response to the reverse first and then other types, determine the underlying clock period Period=f of the target clock<other_generate_type> (f <invert>(Period_Master)), determine the vector Waveform of the underlying clock duty cycle of the target clock = f<other_generate_type> (f <invert>(Waveform_Master)).

[0023] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the underlying clock period and the underlying clock duty cycle of the target clock are calculated based on the phase shift function, including: obtaining the vector representation of the edge vector edges_list [e1, e2, ..., el], the vector representation of the offset vector edge_shift_list [r1, r2, ..., rl], and the vector representation of the top-level clock duty cycle vector Waveform_Master of the first-level clock [x1, x2, ..., xn]; based on the vector representation of the top-level clock duty cycle vector Waveform_Master [x1, x2, ..., xn], the expanded master clock waveform vector [y1, y2, ..., ym] is obtained, where m = edg es_list[-1]; let the underlying clock period Period of the target clock be equal to Time_Master[edges_list[-1]-1]+edge_shift_list[-1]-Time_Master[edges[0]-1]-edge_shift_list[0]; determine that the vector representation of the underlying clock duty cycle vector Waveform of the target clock is [z1,z2,…,zl-1], where the length of the Waveform is 1 less than that of edges_list, Waveform[i]=Time_Master[edges_list[i]-1]+edge_shift_list[i].

[0024] For example, in the clock constraint definition method provided by at least one embodiment of the present disclosure, the expanded master clock waveform vector [y1, y2, ..., ym] is obtained based on the vector representation [x1, x2, ..., xn] of the vector Waveform_Master of the top-level clock duty cycle, including: obtaining the top-level clock period Period_Master of the first-level clock; when m%n-1==0, determining ym=Period_Master*int(m / n); when m%n-1!=0, determining ym=Period_Master*int((m-1) / n)+Waveform_Master[(m-1)%n].

[0025] For example, the clock constraint definition method provided by at least one embodiment of the present disclosure also includes: finding all bottom-level clocks to be defined from the top-level clock description file, the top-level clock description information of the bottom-level clocks to be defined including at least one bottom-level starting point of the bottom-level clock to be defined in the at least one bottom-level module; taking all the bottom-level clocks to be defined as the target clocks in turn to automatically define the bottom-level clock constraints of all the bottom-level clocks to be defined.

[0026] At least one embodiment of the present disclosure also provides a clock constraint definition device, which includes: an acquisition module, configured to acquire top-level description information of each clock among multiple clocks from a top-level clock description file of a chip, wherein the top-level description information includes definition information of the top-level clock constraint of each clock and position information of each clock in a bottom-level module, the definition information is obtained based on a top-level clock definition of each clock in the top level of a chip design, the position information is determined based on the position of each clock in at least one bottom-level module corresponding to the top level, and the position information includes at least one bottom-level starting point of each clock in at least one bottom-level module; a definition module, configured to automatically define a bottom-level clock constraint of a target clock in at least one clock in a corresponding at least one bottom-level module based on the top-level description information of at least one clock among the multiple clocks.

[0027] At least one embodiment of the present disclosure further provides an electronic device, comprising: at least one memory, which non-transiently stores computer-executable instructions; and at least one processor, which is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the clock constraint definition method provided in any of the above embodiments.

[0028] At least one embodiment of the present disclosure further provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by at least one processor, the clock constraint definition method provided by any of the above embodiments is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0030] Figure 1 A schematic diagram of the structure of a clock tree;

[0031] Figure 2A is a schematic diagram of an exemplary definition of a master clock;

[0032] Figure 2B It is a structural schematic diagram of a module A;

[0033] Figure 3A A schematic diagram showing a waveform comparison between a master clock and a generated clock under a frequency division operation is shown;

[0034] Figure 3B It is a structural schematic diagram of a module B;

[0035] Figure 4A A schematic diagram showing the location of clocks in a clock tree in an underlying module;

[0036] Figure 4B A schematic diagram of a design including multiple levels is shown;

[0037] Figure 5A A flowchart of a clock constraint definition method provided for at least one embodiment of the present disclosure;

[0038] Figure 5B A flowchart for deriving underlying clock constraints provided for at least one embodiment of the present disclosure;

[0039] Fig. 6A A schematic diagram showing a waveform comparison of a master clock and a generated clock under a frequency multiplication operation is shown;

[0040] Figure 6B A schematic diagram showing a waveform comparison of a master clock and a generated clock under a reverse operation;

[0041] Figure 6C A schematic diagram showing a waveform comparison of a master clock and a generated clock under a phase shift operation is shown;

[0042] Fig.6D A schematic diagram showing waveform comparison of a master clock and a generated clock under another phase shift operation is shown;

[0043] Figure 7 A schematic diagram of the structure of a clock constraint definition device provided by at least one embodiment of the present disclosure;

[0044] Figure 8 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure;

[0045] Fig. 9 A schematic diagram of the structure of an electronic device provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0047] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall be understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly. It should be understood that the various steps recorded in the method implementation of the present disclosure may be performed in different orders and / or in parallel. In addition, the method implementation may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0048] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the detailed description of known functions and known components (elements) may be omitted. When any part (element) of the embodiments of the present disclosure appears in more than one figure, the part (element) is represented by the same or similar reference numeral in each figure.

[0049] To ensure the correctness and reliability of the design, the design team needs to clearly and accurately define the clock constraints. Clock definition is an abstract description of the clock (for example, describing the clock through a command). Defining clock constraints requires describing the clock waveform and specifying the clock name, such as defining the clock source, clock name, period, edge time (the moment of the rising edge and the falling edge), etc. The source clock (create-clock) is used to describe the clock source, including basic information such as period, duty cycle, and clock jitter. The generated clock (generated-clock) refers to a new clock signal generated by the existing master clock (master-clock) in the design through operations such as multiplication, division, inversion, or phase shift (for example, through specific clock circuits such as dividers, multipliers, selectors, and gates in the clock tree), such as a multiplied clock signal generated by a multiplication circuit or a divided clock signal generated by a division circuit. In the clock tree, there is a hierarchical relationship between the master clock and the generated clock.

[0050] Figure 1 The figure is a schematic diagram of the structure of a clock tree. The clock tree includes the source (root) of the main clock signal, clock tree branches, and clock tree endpoints. Figure 1 As shown, the clock outputted by the clock output terminal CLKO of the PLL is the source clock CLK1, the output of the frequency multiplication circuit BUF is the generated clock CLK2, and the output of the frequency division circuit DIV is the generated clock CLK3.

[0051] The parent clock of a generated clock is the master clock of the generated clock. The master clock of a generated clock may be the source clock or another clock located between the source clock and the generated clock on the clock tree. For example, clock CLK3 is a generated clock, and its master clock is its parent clock CLK2. Clock CLK2 is also a generated clock, and its master clock is its parent clock CLK1.

[0052] Clock definition is critical in multiple stages of the integrated circuit design process. It usually needs to be formulated in the early design stage and continuously updated and maintained during the subsequent design and verification process to ensure that clock requirements are met throughout the design flow.

[0053] The following is a brief introduction on how to manually define the master clock and generated clock in a typical design.

[0054] For example, the command create_clock may be used to define the clock constraints of the main clock, where the definition information of the clock constraints of the main clock includes the clock name, period, duty cycle, and definition point.

[0055] The clock name is used to distinguish the constraints of different clocks. It must be unique and can be specified by -name. The period is the oscillation period of the clock, usually the reciprocal of the clock frequency. The period is used to define the most basic and smallest time unit in the timing analysis of the clock domain. It can be specified by –period in the clock constraint. The duty cycle mainly defines the distribution of the high and low levels of the clock within a period. It can be specified by -waveform in the clock constraint.

[0056] Figure 2A FIG. 1 is a schematic diagram of an exemplary definition of a master clock. Figure 2A As shown, the period T of the master clock is 100 picoseconds (ps), the high level accounts for 50ps, the low level accounts for 50ps, and the duty cycle is 50%. The duty cycle vector in the clock constraint can be described as -waveform{0 50}, where 0 represents the moment when the high level rising edge is in the first cycle, and 50 represents the moment when the high level falling edge is in the first cycle.

[0057] The clock source is the source of the clock, for example Figure 1 The clock source point of the main clock CLK1 in the module is ClkO. The source of the main clock in the module may be the port of the module or the internal point of the module. When the source is the port of the module, the clock source point can be described as [get_ports*], and when the source is the internal point of the module, the clock source point can be described as [get_pins* / *], where " / " is a hierarchical symbol used to represent the hierarchical structure of the underlying module. The hierarchical symbol can also be represented by other custom special symbols, and the embodiments of the present disclosure do not limit the representation of the hierarchical symbol.

[0058] It should be noted that the "*" in this document is used to replace some information, which is only used for the convenience of description and has no specific meaning and will not impose any limitation on the embodiments of the present disclosure.

[0059] Figure 2B FIG. 1 is a schematic diagram of the structure of a module A. Figure 2B As shown, the source of the main clock CLK4 in module A is port P1, the period of CLK4 is 100ps, and the duty cycle is 50%. The clock constraint of CLK4 can be expressed as:

[0060] create_clock–name CLK–period 100-waveform{0 50}[get_ports P1].

[0061] As mentioned earlier, the properties of a generated clock come directly from its master clock. When defining a generated clock, you do not specify the period or waveform of the generated clock, but describe how to convert from the master clock to the generated clock. For example, the relationship between the generated clock and the master clock can be simple frequency division, simple frequency multiplication, a combination of frequency division and frequency multiplication, phase shift or phase inversion, duty cycle change, or any combination of these relationships. Therefore, the clock constraints of the generated clock do not need to define the period and duty cycle, but only need to clearly define the relationship between the generated clock and the master clock.

[0062] For example, the command creat_generated_clock can be used to define the clock constraints of the generated clock. The definition information of the clock constraints of the generated clock includes the clock name of the generated clock, the clock name of the master clock of the generated clock, the clock source definition point, the generation type, and the generation end definition point. The clock name of the generated clock can be specified by -name, the clock name of the master clock can be specified by -master_clock, and the clock source definition point can be specified by -source. The generation type can be defined according to the specific generation relationship. For example, if the generated clock is generated by a frequency division operation and the frequency division coefficient is P, it can be represented by -divide_by P. Figure 3A A schematic diagram showing the waveform comparison of the master clock and the generated clock under a frequency division operation is shown, Figure 3A As shown in the figure, the period of the master clock is 100ps, and the division factor P is 2. Then the period of the generated clock generated by the 2-division is twice that of the master clock, that is, the period of the generated clock is 200ps. Similarly, if the generated clock is generated by the multiplication operation, the multiplication factor is Q, which can be represented by -multiply_by Q.

[0063] Figure 3B FIG. 1 is a schematic diagram of the structure of a module B. Figure 3B As shown, the clock CLK5 in module B is the source clock generated by PLL, CLK5 is the main clock, CLKDIV2 is the generated clock, CLKDIV2 is generated by dividing the main clock CLK5 by two through the frequency division circuit DIV2FF, so the clock source definition point of CLKDIV2 is PLL / OUTPUT, the generation type is "two-frequency division", and the generation end definition point is DIV2FF / Q, so the clock constraint of CLKDIV2 can be expressed as:

[0064] create_generated_clock-name CLKDIV2-master_clock CLK5-source[get_pinsPLL / OUTPUT]-divide_by 2[get_pins DIV2FF / Q]–add.

[0065] For the clock constraints at the top and bottom layers, although the clock design remains unchanged, changes in the design hierarchy and clock ports will also lead to different clock constraints for the two. Therefore, it is necessary to define the clock constraints at the top and bottom layers separately.

[0066] For example, Figure 4A A schematic diagram showing the location of clocks in the clock tree in the underlying modules. Figure 4A As shown, although the clock CLKA is the main clock in the top layer and in the bottom layer module 1, the clock constraint of CLKA in the top layer is different from that in the bottom layer module 1.

[0067] For example, the clock constraint definition for CLKA in the top level is:

[0068] create_clock–name CLKA–period***-waveform{**}[get_ports PPL / OUTPUT].

[0069] The clock constraint of CLKA in the bottom module 1 is defined as:

[0070] create_clock-name CLKA-period***-waveform{**}[get_ports PORTA].

[0071] That is, after defining CLKA at PLL in the top-level constraint, CLKA also needs to be defined at port PORTA of the bottom-level module 1 in the bottom-level constraint.

[0072] For example, Figure 4A As shown in the figure, although the clock CLKB is the generated clock of CLKA in both the top-level and bottom-level modules 1, there is no need to define the period and duty cycle, and only the relationship between CLKB and CLKA needs to be defined. However, the clock constraints of the clock CLKB in the top-level and bottom-level modules 1 are different and need to be defined separately. Moreover, when the clock CLKB enters the bottom-level module 2, since CLKA cannot be seen, the clock CLKB needs to be defined as a master clock directly at the port PORTB of the bottom-level module 2. At this time, the period and duty cycle of CLKB need to be defined. Therefore, for the clock CLKB, three clock constraints need to be defined, namely the clock constraint of CLKB in the top-level, the clock constraint of CLKB in the bottom-level module 1, and the clock constraint of CLKB in the bottom-level module 2.

[0073] For example, the clock constraint definition for CLKB in the top level is:

[0074] create_generated_clock-name CLKB-master_clock CLKA–source[get_pinsPLL / OUTPUT]-divide_by 2[get_pins BLOCK1 / CELL1 / OUTPUT]–add.

[0075] The clock constraint of CLKB in the bottom module 1 is defined as:

[0076] create_generated_clock-name CLKB-master_clock CLKA-source[get_pinsPORTA]-divide_by 2[get_pins CELL1 / OUTPUT]-add.

[0077] The clock constraint of CLKB in the bottom module 2 is defined as:

[0078] create_clock-name CLKB-period***-waveform{**}[get_ports PORTB].

[0079] The main differences between a clock at the top level and the bottom level are as follows:

[0080] (1) The defined source point may change;

[0081] (2) A clock is a generated clock at the top level, but it may become a master clock at the bottom level, so it is necessary to additionally define the period and duty cycle.

[0082] Due to the different layers, EDA cannot automatically identify the difference between the top and bottom layers, so designers need to define two different clock constraints, one for the bottom layer (as shown in bold above) and the other for the top layer. Defining two clock constraints will increase the workload of technicians. Moreover, the design can be split not only into 2 layers, but also into 3, 4 or more layers. Figure 4B A schematic diagram of a design including multiple levels is shown. Figure 4B As shown in the figure, the design is divided into three layers, layer 1 is the top layer of layer 2, and layer 2 is the top layer of layer 3. For example, layer 2 is the bottom layer of layer 1; the modules in layer 2 can be further divided into dozens or even hundreds of sub-modules, which belong to layer 3, that is, layer 3 is the bottom layer of layer 2. Since the clock constraints of each module in the bottom layer need to be consistent with the top layer, if the clock constraints in multiple layers are defined manually, the workload and complexity will increase exponentially. More importantly, in the design of high-performance CPUs and GPUs, different modules, peripherals, and low-power designs have different clock requirements, so the clock structure is often complex. From the perspective of clock constraints, such designs usually need to define hundreds or thousands of clocks.

[0083] In addition, in addition to manual inspection, consistency checks of top-level clock constraints and sub-module clock constraints will be performed after the top-level timing work is carried out. Generally, designers will complete constraint consistency checks through the top-level module port connection relationship and the timing of the module ports, but the top-level design depends on the completion of each module. Therefore, this work is carried out relatively late. In the early stage, it is very likely that errors will occur in the top-level and bottom-level clock constraint definitions due to human negligence, resulting in the discovery of related clock constraint problems in the later stage of the project, causing unnecessary iterations and waste of resources.

[0084] In view of the difference between the clock source point, period and duty cycle at the top and bottom layers, which leads to the need to define two or more clock constraints at the top and bottom layers respectively, at least one embodiment of the present disclosure provides a clock constraint definition method, device, electronic device and storage medium. The clock constraint definition method includes: obtaining top-level description information of each clock among multiple clocks, wherein the top-level description information includes definition information of the top-level clock constraint of each clock and position information of each clock in the bottom module, the definition information is obtained based on the top-level clock definition of each clock in the top layer of the chip design, the position information is determined based on the position of each clock in at least one bottom module corresponding to the top layer, and the position information includes at least one bottom starting point of each clock in at least one bottom module; based on the top-level description information of at least one clock among the multiple clocks, automatically defining the bottom-level clock constraint of the target clock in at least one clock in the corresponding at least one bottom module.

[0085] The clock constraint definition method provided by at least one embodiment of the present disclosure only needs to manually define the top-level description information of the clock at the top level, so as to automatically complete the derivation of the clock waveform from the top level to the bottom level, and pass the top-level clock constraints to the bottom level, thereby automatically completing the definition of the bottom-level clock constraints. There is no need to manually define the bottom-level clock constraints, and unnecessary iterations and waste of resources caused by manually defining multiple bottom-level constraint files are avoided, thereby effectively saving manpower and ensuring the correctness of early clock constraints.

[0086] Figure 5A A flowchart of a clock constraint definition method provided by at least one embodiment of the present disclosure. Figure 5A As shown, a clock constraint definition method provided by at least one embodiment of the present disclosure includes the following steps S100 to S300.

[0087] Step S100: obtaining top-level description information of each clock among a plurality of clocks.

[0088] Step S200: Based on the top-level description information of at least one clock among the multiple clocks, automatically define the bottom-level clock constraints of a target clock among the at least one clock in the corresponding at least one bottom-level module.

[0089] In an embodiment of the present disclosure, the top-level description information includes the definition information of the top-level clock constraint of each clock and the location information of each clock in the bottom-level module. The definition information is obtained based on the top-level clock definition of each clock in the top-level of the chip design. For example, in one example, the definition information can be obtained based on manually performing the top-level clock definition on the clock. Figure 4A Taking the shown embodiment as an example, if the design is divided into 2 layers, the designer needs to first define the clocks CLKA, CLKB and CLKC separately in the top layer of the chip, so as to determine the definition information in the top-level description information of each clock. The format of the definition information can be json, yaml, xml, etc. The embodiment of the present disclosure does not limit the definition format.

[0090] For example, in another example, the definition information may also be obtained from a pre-saved file, or may be obtained by automatically performing a top-level clock definition on the clock based on the clock constraint definition method. Figure 4B As shown, the design is divided into three layers. The clock definition constraint method can determine the definition information 1 of the clock in layer 1 from a pre-saved file, and then use layer 1 as the top layer and layer 2 as the bottom layer, and automatically define multiple clock constraints in layer 2 based on the definition information 1 and the position information of the clock in the module of layer 2, thereby determining the definition information 2 of the clock in layer 2, and finally use layer 2 as the top layer and layer 3 as the bottom layer, and automatically define multiple clock constraints in layer 3 based on the definition information 2 and the position information of the clock in the sub-module of layer 3.

[0091] When determining the definition information of the top-level clock constraints of each clock, if the clock is a master clock in the top level, the definition information of the top-level clock constraints of the clock includes: top-level clock period, top-level clock duty cycle, and top-level clock definition point; if the clock is a generated clock in the top level, the definition information of the top-level clock constraints of the clock includes the top-level master clock name, top-level clock source definition point, top-level generation type, and top-level generation end definition point.

[0092] In an embodiment of the present disclosure, the position information is determined based on the position of each clock in at least one bottom module corresponding to the top layer, and the position information includes at least one bottom starting point of each clock in at least one bottom module. Figure 4A As shown, the chip design is divided into a top layer and a bottom layer. The bottom layer includes two modules, namely, bottom layer module 1 and bottom layer module 2. The clock CLKA is only located in the bottom layer module 1. The bottom layer starting point of the clock CLKA in the bottom layer module 1 is PORTA. Therefore, it can be determined that the location information of the clock CLKA includes "PORTA of bottom layer module 1". For example, the location information of CLKA can be expressed as "block":{"block1":{"startpoint":"PORTA"}} in the script. Clock CLKB is located in both underlying module 1 and underlying module 2. The underlying starting point of clock CLKB in underlying module 1 is the output terminal OUTPUT of CELL1 (OUTPUT is used here to represent the output terminal of the module, and the same is true below), and the underlying starting point in underlying module 2 is the port point PORTB. Therefore, it can be determined that the location information of clock CLKB includes "the output terminal OUTPUT of CELL1 of underlying module 1" and "the port point PORTB of underlying module 2". For example, in the script, the location information of CLKB can be expressed as "block":{"BLOCK1":{"startpoint":"CELL1 / OUTPUT"},"BLOCK2":{"startpoint":"PORTB"}}.

[0093] In some embodiments of the present disclosure, in order to facilitate the distinction between whether a clock is a master clock or a generated clock in the top layer, the top-level clock type can be set in the top-level description information, thereby being able to directly and quickly determine whether it is necessary to automatically define the bottom-level clock constraints of the clock according to the type of the clock in the top layer. The top-level clock type includes a first top-level type and a second top-level type, the first top-level type indicating that any clock in the top layer is a master clock, and the second top-level type indicating that any clock in the top layer is a generated clock. For example, the top-level clock type can be specified with "generate", "generate": 0 indicates that the clock is of the first top-level type and is a master clock in the top layer; "generate": 1 indicates that the clock is of the second top-level type and is a generated clock in the top layer. The embodiments of the present disclosure do not limit the specification method and expression form of the top-level clock type.

[0094] For example, in at least one embodiment of the present disclosure, Figure 4A The CLKA in the top layer is the main clock, and its top-level description information can be expressed as:

[0095] {"CLKA":{"generate":0,"startpoint":"PPL / OUTPUT","period":"***","waveform":"**","block":{"block1":{"startpoint":"PORTA"}}}}.

[0096] Figure 4A The CLKB in the top level is a generated clock, and its top level description information can be expressed as:

[0097] {CLKB":{"generate":1,"startpoint":"BLOCK1 / CELL1 / OUTPUT","master":"CLKA","generate_type":"-divide_by2","block":{"BLOCK1":{"startpoint":"CELL1 / OUTPUT"},"BLOCK2":{"startpo int":"PORTB"}}}}.

[0098] After obtaining the top-level description information of each clock in step S100, step S200 can be performed to automatically define the bottom-level clock constraints of the target clock in at least one of the multiple clocks in the corresponding at least one bottom-level module based on the top-level description information of at least one of the multiple clocks. Here, the target clock can be the clock that needs to be automatically defined at present, and it can be the master clock or the generated clock in the top-level. When the target clock is the master clock in the top-level, the bottom-level clock constraints of the target clock in the bottom-level module can be automatically defined only based on the top-level description information of the target clock; when the target clock is a generated clock in the top-level, not only the top-level description information of the target clock but also at least the top-level description information of the upper-level clock of the target clock is required to automatically define the bottom-level clock constraints of the target clock in the bottom-level module. In addition, the target clock may be located in one or more bottom-level modules. When the target clock is located in multiple bottom-level modules, multiple bottom-level clock constraints of the target clock in multiple bottom-level modules can be automatically defined respectively. The bottom-level starting points of the target clock in different bottom-level modules are different, so the bottom-level clock constraints of the target clock in different bottom-level modules are different.

[0099] In some embodiments of the present disclosure, the clock constraint definition method also includes: finding all bottom-level clocks to be defined from a top-level clock description file, wherein the top-level clock description information of the bottom-level clocks to be defined includes at least one bottom-level starting point of the bottom-level clocks to be defined in at least one bottom-level module; and taking all bottom-level clocks to be defined as target clocks in turn to automatically define the bottom-level clock constraints of all bottom-level clocks to be defined.

[0100] For example, in step S100, the top-level description information of each clock can be obtained from the top-level clock description files of multiple clocks, and it is determined whether the top-level description information of each clock includes location information. If the top-level description information of a clock includes location information in addition to definition information, the clock constraint definition method provided in the embodiment of the present disclosure can be used to automatically define the bottom-level clock constraints of the clock in the bottom-level module. In other words, if the top-level description information of a clock includes the bottom-level starting point of the clock in at least one bottom-level module, the clock can be identified as a bottom-level clock to be defined, and then the bottom-level clock to be defined is used as the target clock, and the clock constraint definition method provided in the embodiment of the present disclosure is used to automatically define the bottom-level clock constraints of the target clock.

[0101] For example, you can use multiple bottom-level clocks to be defined as target clocks in the order of clock generation in the top-level clock tree, and then Figure 4A In the direction indicated by the arrow, starting from the bottom-level starting point, the clock is propagated backward to find the top-level master clock and generated clock information corresponding to the target clock, so as to determine how to define the bottom-level clock constraints of the target clock according to the corresponding top-level description information.

[0102] Figure 5B A flowchart for deriving underlying clock constraints is provided for at least one embodiment of the present disclosure. Figure 5B As shown in the figure, after completing the top-level clock description of multiple clocks, you can find all the bottom-level clocks to be defined in the current bottom-level module from the obtained top-level description information. These clocks need to define bottom-level clock constraints in the current bottom-level module. Figure 4A Taking the illustrated embodiment as an example, the bottom-level module 1 may be used as the current bottom-level module, and the bottom-level clocks to be defined in the bottom-level module 1 include the clock CLKA and the clock CLKB.

[0103] like Figure 5B As shown, after finding all the underlying clocks to be defined in the current underlying module, each clock can be traversed, and each clock can be used as a target clock. According to the top-level description information of at least one clock corresponding to the target clock, the underlying clock constraints of the target clock in the current underlying module are automatically defined. The following steps are looped for all target clocks in sequence until the underlying clock constraints of all target clocks in the current underlying module are completed. For example, before automatically defining the clock in the next underlying module, it is necessary to first complete the underlying clock definition of multiple clocks before the underlying module in the top-level design, and then the clock constraint definition method can be looped for all underlying modules until the underlying clock constraints of all clocks are completed.

[0104] like Figure 5B As shown, when traversing each target clock, it can be determined whether the target clock is a master clock or a generated clock in the top layer according to the top layer clock type of the target clock. If the target clock is a master clock in the top layer, the bottom layer master clock can be defined according to the top layer description information of the target clock.

[0105] For example, in some embodiments of the present disclosure, step S200, i.e., automatically defining the bottom-level clock constraints of a target clock in at least one clock in the corresponding at least one bottom-level module based on the top-level description information of at least one clock among multiple clocks, may include a specific example of: in response to the top-level clock type of the target clock being the first top-level type, determining that at least one clock only includes the target clock; and automatically defining the bottom-level clock constraints of the target clock in the current bottom-level module in the corresponding at least one bottom-level module based on the top-level description information of the target clock, wherein the bottom-level clock constraints of the target clock include a bottom-level clock period, a bottom-level clock duty cycle, and a bottom-level clock definition point.

[0106] That is, if the target clock is the main clock in the top level, you only need to define the bottom-level clock constraints in the current bottom-level module based on the top-level description information of the target clock. Figure 4A In the illustrated embodiment, "generate" of the clock CLKA is 0, indicating that the clock CLKA is the master clock in the top layer. Therefore, when automatically defining the bottom-level clock constraints of the clock CLKA in the bottom-level module 1, the top-level clock period and top-level clock duty cycle of the clock CLKA can be automatically inherited, and its bottom-level starting point in the bottom-level module 1 can be defined as its bottom-level clock definition point.

[0107] For example, you can set the target clock's bottom-level clock period to be equal to the target clock's top-level clock period; set the target clock's bottom-level clock duty cycle to be equal to the target clock's top-level clock duty cycle; and set the name of the target clock's bottom-level clock definition point to the name of the target clock's bottom-level starting point in the current bottom-level module.

[0108] For example, the pin type of the bottom-level clock definition point can also be directly determined according to the name of the bottom-level starting point of the target clock in the current bottom-level module. The pin type of the bottom-level clock definition point includes a first pin type and a second pin type, the first pin type indicates that the target clock is located at the port of the current bottom-level module, and the second pin type indicates that the target clock is located at an internal point of the current bottom-level module.

[0109] For example, if the name of the bottom-level start point includes the level symbol " / ", it means that it is an internal point of the bottom-level module. Then, you can use "pins" to specify the pin type of the bottom-level clock definition point of the target clock as the second pin type. The bottom-level clock constraint of the target clock is automatically defined as:

[0110] create_clock–name***–period$period-waveform{$waveform}[get_pins$startpoint].

[0111] If the name of the bottom-level starting point does not include the hierarchical symbol " / ", it means that it is a port of the bottom-level module. You can use "ports" to specify the pin type of the bottom-level clock definition point of the target clock as the first pin type. The bottom-level clock constraint of the target clock is automatically defined as:

[0112] create_clock–name***–period$period-waveform{$waveform}[get_ports$startpoint].

[0113] In the embodiments of the present disclosure, "$period" is used to represent the top-level clock period of the target clock, "$waveform" is used to represent the top-level clock duty cycle of the target clock, and "$startpoint" is used to represent the bottom-level starting point of the target clock in the current bottom-level module.

[0114] For example, in Figure 4A In the embodiment shown, the clock CLKA is the main clock in the top level, and its top-level description information is:

[0115] {"CLKA":{"generate":0,"startpoint":"PPL / OUTPUT","period":"***","waveform":"**","block":{"block1":{"startpoint":"PORTA"}}}}.

[0116] Therefore, the bottom-level clock constraint of clock CLKA in bottom-level module 1 can be automatically defined as:

[0117] create_clock–name CLKA–period***-waveform{**}[get_ports PORTA].

[0118] For example, in some embodiments of the present disclosure, step S200, i.e., automatically defining the bottom-level clock constraints of a target clock in at least one clock in the corresponding at least one bottom-level module based on the top-level description information of at least one clock among multiple clocks, may include: in response to the top-level clock type of the target clock being the second top-level type, determining that at least one clock includes a target clock and an upper-level clock set of the target clock, the upper-level clock set includes at least a first-level clock, and the first-level clock is the master clock of the target clock; based on the top-level description information of the target clock and the top-level description information of the upper-level clock set, automatically defining the bottom-level clock constraints of the target clock in the current bottom-level module in the corresponding at least one bottom-level module.

[0119] That is, if the target clock is a generated clock in the top layer, in addition to the top-level description information of the target clock, the top-level description information of the target clock's parent clock or more parent clocks is also required to automatically define the target clock's bottom-level clock constraints in the current bottom-level module. The parent clock of the target clock is the master clock of the target clock, which is called the first-level clock. The parent clock of the first-level clock is called the second-level clock, and the second-level clock is the master clock of the first-level clock, and so on.

[0120] like Figure 5B As shown, when traversing each target clock, if the target clock is a generated clock in the top layer, it is necessary to further determine the bottom layer clock type of the generated clock. For example, based on the name of the bottom layer starting point of the target clock in the current bottom layer module, determine the bottom layer clock type of the target clock in the current bottom layer module. The bottom layer clock type includes a first bottom layer type and a second bottom layer type, the first bottom layer type indicates that the target clock is a master clock in the current bottom layer module, and the second bottom layer type indicates that the target clock is a generated clock in the current bottom layer module.

[0121] For example, if the name of the bottom-level starting point includes the level symbol " / ", it means that it is an internal point of the bottom-level module, the target clock is a generated clock in the current bottom-level module, and the bottom-level clock type of the target clock in the current bottom-level module is the second bottom-level type. If the name of the bottom-level starting point does not include the level symbol " / ", it means that it is a port of the bottom-level module, the target clock is a master clock in the current bottom-level module, and the bottom-level clock type of the target clock in the current bottom-level module is the first bottom-level type.

[0122] After determining the bottom-level clock type of the target clock in the current bottom-level module, the bottom-level clock constraints of the target clock in the current bottom-level module may be automatically defined based on the top-level description information of the target clock and the top-level description information of the upper-level clock set.

[0123] For example, in response to the target clock's underlying clock type being the second underlying type, determine that the target clock's underlying clock constraints include the underlying master clock name, the underlying clock source definition point, the underlying generation type, and the underlying generation end definition point; obtain definition information of the top-level clock constraint of the first-level clock in the upper-level clock set; set the target clock's underlying master clock name to the clock name of the first-level clock; set the name of the target clock's underlying clock source definition point to the name of the first-level clock's underlying starting point in the current underlying module; set the target clock's underlying generation type to the target clock's top-level generation type; and set the name of the target clock's underlying generation end definition point to the name of the target clock's underlying starting point in the current underlying module.

[0124] For example, when the target clock is a generated clock in the current bottom-level module, the bottom-level clock constraint of the target clock in the current bottom-level module can be automatically defined as:

[0125] create_generated_clock-name***-master_clock$master-source[get_pins$master.startpoint]-divide_by 2[get_pins$startpoint]–add.

[0126] In the embodiments of the present disclosure, "$master" is used to represent the name of the top-level master clock (first-level clock) of the target clock, "$master.startpoint" is used to represent the bottom-level starting point of the first-level clock in the current bottom-level module, and "$startpoint" is used to represent the bottom-level starting point of the target clock in the current bottom-level module.

[0127] For example, in Figure 4A In the embodiment shown, the clock CLKB is a generated clock in the bottom module 1, and the top-level master clock of the clock CLKB is CLKA, so the top-level description information of the clock CLKA and the clock CLKB is obtained:

[0128] {"CLKA":{"generate":0,"startpoint":"PPL / OUTPUT","period":"***","waveform":"**","block":{"block1":{"startpoint":"PORTA"}}}} and

[0129] {CLKB":{"generate":1,"startpoint":"BLOCK1 / CELL1 / OUTPUT","master":"CLKA","generate_type":"-divide_by2","block":{"BLOCK1":{"startpoint":"CELL1 / OUTPUT"},"BLOCK2":{"startpo int":"PORTB"}}}}.

[0130] Therefore, it can be determined that the bottom-level starting point of the first-level clock CLKA in the bottom-level module 1 is PORTA, the top-level clock type of the clock CLKB is divided by two, and the bottom-level starting point of the clock CLKB in the bottom-level module 1 is CELL1 / OUTPUT, so the bottom-level clock constraint of the clock CLKB in the bottom-level module 1 can be automatically defined as:

[0131] create_generated_clock-name CLKB-master_clock CLKA-source[get_pinsPORTA]-divide_by 2[get_pins CELL1 / OUTPUT]–add.

[0132] like Figure 5B As shown, if the name of the bottom-level starting point of the target clock does not include the level symbol " / ", it means that it is a port of the bottom-level module, the target clock is the main clock in the current bottom-level module, and the bottom-level clock type of the target clock in the current bottom-level module is the first bottom-level type. Since the target clock is a generated clock in the top-level, it does not contain information about the clock period and duty cycle, so these definition information needs to be calculated through the period and duty cycle information of the first top-level type of the target clock in the top-level.

[0133] For example, in response to the target clock's underlying clock type being a first underlying type, determine that the target clock's underlying clock constraints include underlying clock period, underlying clock duty cycle, and underlying clock definition point; obtain definition information of the target clock's top-level clock constraint of the target clock's parent clock set; calculate the target clock's underlying clock period and underlying clock duty cycle based on the target clock's top-level generation type and the parent clock set's top-level clock constraint definition information; set the name of the target clock's underlying clock definition point to the name of the target clock's underlying starting point in the current underlying module, and determine that the pin type of the target clock's underlying clock definition point is a first pin type.

[0134] For example, in some embodiments of the present disclosure, in response to the top-level clock type of the first-level clock being the first top-level type, the first objective function f1 is directly applied to the top-level clock period and the top-level clock duty cycle of the first-level clock, thereby calculating the bottom-level clock period and the bottom-level clock duty cycle of the target clock; or, in response to the top-level clock type of the first-level clock being the second top-level type, the top-level clock constraint information of the second-level clock serving as the master clock of the first-level clock is obtained; in response to the top-level clock type of the second-level clock being the first top-level type, the second objective function f2 is determined according to the top-level generation type of the first-level clock; the first objective function f1 and the second objective function f2 are nestedly applied, thereby calculating the bottom-level clock period and the bottom-level clock duty cycle of the target clock.

[0135] For example, if the first-level clock of the target clock is the master clock in the top level, the calculation formula for the bottom-level clock period Period of the target clock is as follows:

[0136] Period=f1(Period_Master)

[0137] Among them, f1 is the function expression of the target clock and the first-level clock, and Period_Master is the top-level clock period of the first-level clock.

[0138] For example, if the first-level clock of the target clock is not the master clock in the top level, the relationship between the first-level clock and its upper-level clock (the second-level clock) needs to be calculated until a clock is found that is the master clock in the top level (for example, the nth-level clock). In this case, the calculation formula for the bottom-level clock period Period of the target clock is as follows:

[0139] Period=f1(f2(…fn(Period_Master_n)))

[0140] Among them, f1 is the function expression of the target clock and the first-level clock, f2 is the function expression of the first-level clock and the second-level clock, fn is the function expression of the n-1th-level clock and the nth-level clock, and Period_Master_n is the top-level clock period of the nth-level clock.

[0141] Similarly, if the first-level clock of the target clock is the master clock in the top level, the upper-level clock set only includes the first-level clock, and the calculation formula of the vector Waveform of the bottom-level clock duty cycle of the target clock is as follows:

[0142] Waveform=f1(Waveform_Master)

[0143] Where f1 is the function expression of the target clock and the first-level clock, and Waveform_Master is the vector of the top-level clock duty cycle of the first-level clock.

[0144] For example, if the first-level clock of the target clock is not the master clock in the top level, the relationship between the first-level clock and its upper-level clock (second-level clock) needs to be calculated until a clock is found to be the master clock in the top level (for example, the nth-level clock), that is, the upper-level clock set includes the first-level clock, the second-level clock, and the nth-level clock. In this case, the calculation formula of the vector Waveform of the bottom-level clock duty cycle of the target clock is as follows:

[0145] Waveform=f1(f2(…fn(Waveform_Master_n)))

[0146] Among them, f1 is the function expression of the target clock and the first-level clock, f2 is the function expression of the first-level clock and the second-level clock, fn is the function expression of the n-1th-level clock and the nth-level clock, and Waveform_Master_n is the vector of the top-level clock duty cycle of the nth-level clock.

[0147] In the embodiments of the present disclosure, the specific function expression is closely related to the generation type of the generated clock. According to the generated clock format that can be described by SDC, the generation type of the generated clock includes clock division, clock multiplication, reverse clock and phase offset. All generated clocks can be obtained by combining these four types. Therefore, by mastering the derivation formula of the waveform function of the master clock to the generated clock of these four generation types, the derivation of the top-level clock to the bottom-level clock in all cases can be calculated according to the above calculation formula, thereby completing the automatic constraint of the bottom layer.

[0148] The top-level generation type corresponding to the target clock is frequency division, frequency multiplication, inversion or phase shift, and the function expression in the above calculation formula can be a frequency division function, a frequency multiplication function, a inversion function or a phase shift function.

[0149] For example, the calculation of the bottom clock period and bottom clock duty cycle of the target clock based on the frequency division function includes: obtaining the frequency division coefficient Q; setting the bottom clock period Period of the target clock equal to the top clock period Period_Master of the first-level clock multiplied by the frequency division coefficient Q; setting the bottom clock duty cycle vector Waveform of the target clock equal to the top clock duty cycle vector Waveform_Master of the first-level clock multiplied by the frequency division coefficient Q. For example, the calculation formula of the bottom clock period Period of the target clock and the bottom clock duty cycle vector Waveform is:

[0150] Period=f <divide>(Period_Master)=Period_Master*Q;

[0151] Waveform=f <divide>(Waveform_Master)=Waveform_Master*Q.

[0152] like Figure 3A As shown, the division factor of the two-division frequency is 2, the clock period of the master clock is 100ps, and the clock period of the generated clock is 200ps; the vector of the clock duty cycle of the master clock is [0,50], and the vector of the clock duty cycle of the generated clock is [0,100].

[0153] For example, the calculation of the bottom clock period and bottom clock duty cycle of the target clock based on the frequency multiplication function includes: obtaining the frequency multiplication coefficient P; setting the bottom clock period Period of the target clock equal to the top clock period Period_Master of the first-level clock divided by the frequency multiplication coefficient P; setting the bottom clock duty cycle vector Waveform of the target clock equal to the top clock duty cycle vector Waveform_Master of the first-level clock divided by the frequency multiplication coefficient P. For example, the calculation formulas of the bottom clock period Period of the target clock and the bottom clock duty cycle vector Waveform are:

[0154] Period=f <multiply>(Period_Master)=Period_Master / P;

[0155] Waveform=f <multiply>(Waveform_Master)=Waveform_Master / P.

[0156] Fig. 6A FIG. 1 is a schematic diagram showing a waveform comparison of a master clock and a generated clock under a frequency multiplication operation. Fig. 6A As shown, the frequency multiplication factor P of the double frequency is 2, the clock period of the master clock is 200ps, and the clock period of the generated clock is 100ps; the vector of the clock duty cycle of the master clock is [0,100], and the vector of the clock duty cycle of the generated clock is [0,50].

[0157] For example, calculating the underlying clock period and underlying clock duty cycle of the target clock based on the reverse function includes: setting the underlying clock period Period of the target clock equal to the top-level clock period Period_Master of the first-level clock; obtaining the vector representation [x1, x2, …, xn] of the vector Waveform_Master of the top-level clock duty cycle of the first-level clock; in response to x2 being less than Period_Master, determining the vector representation of the vector Waveform of the underlying clock duty cycle of the target clock to be [x2, x3, …, xn, x1+Period_Master]; or in response to x2 being greater than or equal to Period_Master, determining the vector representation of the vector Waveform of the underlying clock duty cycle of the target clock to be [x2-Period_Master, x3-Period_Master, …, xn-Period_Master, x1].

[0158] Figure 6B FIG. 1 is a schematic diagram showing a waveform comparison of the master clock and the generated clock under reverse operation. Figure 6B As shown, the clock period of the master clock is 100 ps, ​​and the clock period of the generated clock is 100 ps; the vector of the clock duty cycle of the master clock is [0,50], and the vector of the clock duty cycle of the generated clock is [50,100].

[0159] For example, in some embodiments of the present disclosure, when invert and other generation types other_generate_type exist at the same time, the inverse function f can be nestedly applied. <invert>and other functions f<other_generate_type> , thereby calculating the bottom-level clock period and bottom-level clock duty cycle of the target clock, wherein other types include frequency division or frequency multiplication. That is, according to whether the top-level generation type of the target clock is at least one of frequency division, frequency multiplication, inversion, and phase shift, it can be determined that the first target function corresponding to the top-level generation type of the target clock is at least one of a frequency division function, a frequency multiplication function, a reverse function, and a phase shift function.

[0160] For example, in some embodiments of the present disclosure, in response to the other type first and then the reverse direction, the underlying clock period of the target clock Period=f <invert>(f<other_generate_type> (Period_Master)), determine the underlying clock duty cycle vector Waveform = f <invert>(f<other_generate_type> (Waveform_Master)); In response to the reverse first and other types later, determine the underlying clock period of the target clock Period = f<other_generate_type> (f <invert>(Period_Master)), determine the underlying clock duty cycle vector Waveform = f<other_generate_type> (f <invert>(Waveform_Master)).

[0161] For example, in some embodiments of the present disclosure, the underlying clock period and the underlying clock duty cycle of the target clock are calculated based on the phase shift function, including: obtaining the vector representation of the edge vector edges_list [e1, e2, ..., el], the vector representation of the offset vector edge_shift_list [r1, r2, ..., rl], and the vector representation of the top-level clock duty cycle vector Waveform_Master of the first-level clock [x1, x2, ..., xn]; based on the vector representation of the top-level clock duty cycle vector Waveform_Master [x1, x2, ..., xn], the expanded master clock waveform vector [y1, y2, ..., ym] is obtained, where m = edges_list t[-1]; let the underlying clock period Period of the target clock be equal to Time_Master[edges_list[-1]-1]+edge_shift_list[-1]-Time_Master[edges[0]-1]-edge_shift_list[0]; determine that the vector Waveform of the underlying clock duty cycle of the target clock is represented as [z1,z2,…,zl-1], where the length of Waveform is 1 less than that of edges_list, Waveform[i]=Time_Master[edges_list[i]-1]+edge_shift_list[i].

[0162] Here, -edges is usually used to specify the number of the new rising and falling edges of the generated clock relative to the rising and falling edges of the main clock, usually expressed as {rising, falling, rising}. Figure 6C A schematic diagram showing a waveform comparison of a master clock and a generated clock under a phase shift operation is shown. For example, the rising edge and falling edge of the master clock are numbered 1, 2, 3, ..., n, the first rising edge in the first cycle of the master clock is numbered 1, the first falling edge is numbered 2, and so on. Figure 6C The example of generate_type="-edges{3 5 9}" shows the case where the generated clock generates the first rising edge at the third edge of the master clock, the first falling edge at the fifth edge of the master clock, and the second rising edge at the ninth edge of the master clock. That is, the vectors defined after edges must be in ascending order and be an odd number, with the last number being the clock edge number that starts the loop.

[0163] In addition, SDC can also define the same number of vectors through -edge_shift to represent the offset of each clock edge of the generated clock. Fig.6D FIG. 4 is a schematic diagram showing the waveform comparison of the master clock and the generated clock under another phase offset operation. Fig.6D As shown, the offset of the first rising edge of the generated clock relative to the third edge of the master clock is r1, for example, r1 = 20; the offset of the first falling edge of the generated clock relative to the fifth edge of the master clock is r2, for example, r2 = 20; the offset of the second rising edge of the generated clock relative to the ninth edge of the master clock is r3, for example, r3 = 40. Each element in edge_shift is the offset value of the element in edges, the length of edge_shift is consistent with the length of edges, and the offsets in edge_shift can be equal or unequal.

[0164] In the embodiment of the present disclosure, the expanded master clock waveform vector [y1, y2, ..., ym] can be understood as expanding the waveform of the master clock to include multiple cycles and a length that can cover the first cycle of the generated clock. For example, Figure 2A As shown, the vector of the clock duty cycle of the master clock Waveform_Master is represented as [0,50], Figure 2A The waveform of 2 cycles is shown. After expanding it into the expanded master clock waveform vector [0, 50, ..., 400], the following can be directly drawn based on the expanded master clock waveform vector: Figure 6C The master clock waveform shown includes four cycles, making it easy to determine the vector representation of the generated clock.

[0165] When determining the extended master clock waveform vector, the m value of ym can be determined first, that is, m=edges_list[-1]. In the embodiment of the present disclosure, the programming format is applied, and the "-1" in edges_list[-1] represents the last element in edges_list. Similarly, if "[]" is 0, it represents the first element in edges_list, and if "[]" is k, it represents the k+1th element in edges_list.

[0166] For example, in Figure 6C In the example shown, edges_list is [3, 5, 9], and m = 9. After the value of m is determined, the values ​​of y1 to y9 can be calculated based on the vector representation [0, 50] of the vector Waveform_Master of the first-level clock and the top-level clock cycle of the first-level clock.

[0167] For example, in one example, the expanded master clock waveform vector can be calculated based on the following method: first, based on the vector representation [0,50] of the first-level clock vector Waveform_Master, it is determined that y1 is 0 and y2 is 50; then, since the top-level clock period of the first-level clock is 100 and the duty cycle is 50%, it can be determined that the interval between each edge is 50, so y3=y2+50=100, y4=y3+50=150, and so on, each element in the expanded master clock waveform vector can be calculated.

[0168] For example, in another example, the top-level clock period Period_Master of the first-level clock can be obtained; when m%n-1==0, it is determined that ym=Period_Master*int(m / n); when m%n-1!=0, it is determined that ym=Period_Master*int((m-1) / n)+Waveform_Master[(m-1)%n]. For example, since the vector representation [0,50] of the vector Waveform_Master of the first-level clock includes two elements, n=2; m=edges_list[-1]=9, y1=0, y2=50, and the results of calculating y3-y9 respectively are as follows:

[0169] y3=100*int(3 / 2)=100;

[0170] y4=100*int(4-1) / 2)+Waveform_Master[(4-1)%2]=100+

[0171] Waveform_Master[1]=100+50=150;

[0172] y5=100*int(5 / 2)=200;

[0173] y6=100*int(6-1) / 2)+Waveform_Master[(6-1)%2]=100*2+

[0174] Waveform_Master[1] = 250;

[0175] y7=100*int(7 / 2)=300;

[0176] y8=100*int(8-1) / 2)+Waveform_Master[(8-1)%2]=100*3+

[0177] Waveform_Master[1] = 350;

[0178] y9=100*int(9 / 2)=400.

[0179] After calculating y1-y9, the underlying clock period Period of the target clock can be calculated according to Time_Master[edges_list[-1]-1]+edge_shift_list[-1]-Time_Master[edges[0]-1]-edge_shift_list[0]. In the embodiment of the present disclosure, the programming format is applied, and Time_Master[k] represents the k+1th element.

[0180] For example, in Figure 6C In the embodiment shown, the values ​​in edge_shift_list are all 0, and Period=f <edge>(Waveform_Master)=Time_Master[edges_list[-1]-1]+edge_shift_list[-1]-Time_Master[edges[0]-1]-edge_shift_list[0]=Time_Master[8]+0-Time_Master[2]–0=y9-y3=300.

[0181] For the target clock's underlying clock duty cycle vector Waveform, since the Waveform length is 1 less than edges_list, it can be determined that the Waveform is [z1, z2]. According to the formula Waveform[i] = Time_Master[edges_list[i]-1] + edge_shift_list[i], the target clock's underlying clock duty cycle vector Waveform can be calculated. That is,

[0182] Waveform[0]=z1=Time_Master[edges_list[0]-1]+edge_shift_list[0]=Time_Master[2]+0=y3=100;

[0183] Waveform[1]=z2=Time_Master[edges_list[1]-1]+edge_shift_list[1]=Time_Master[4]+0=y6=200.

[0184] For example, after Waveform is calculated, the following check can be performed: if Waveform[0]>=Period_Master, then set Waveform=Waveform-a vector with a length of l-1 and elements of Period_Master, thereby ensuring that the Waveform vectors after complex calculations are all within the first period.

[0185] like Figure 4A As shown, when the design is divided into two layers, through the above clock constraint definition method, the designer only needs to define the top-level clock constraints without manually defining the bottom-level clock constraints, which can reduce at least 50% of the workload.

[0186] like Figure 4B As shown, when the design needs to be split into more layers for synthesis or layout and routing, the designer only needs to define the clock constraints of the top layer (layer 1), and then through the above clock constraint definition method, the clock constraints of each module in layer 2 can be automatically defined and saved as files in json, yaml, xml and other formats; after automatically defining the clock constraints of the clock in layer 2, layer 2 can be used as the top layer of layer 3, and the definition information of the clock in layer 2 can be obtained from the saved file, combined with the position information of the clock in each sub-module in layer 3, and the clock constraints of the clock in each sub-module can be automatically defined. By automatically defining the clock definition of the clock in layer 2, layer 3 or more layers from top to bottom and layer by layer, unnecessary iterations and waste of resources caused by manually defining multiple constraint files can be avoided, saving manpower and ensuring the correctness of early clock constraints.

[0187] At least one embodiment of the present disclosure further provides a clock constraint definition device. Figure 7 A schematic diagram of the structure of a clock constraint definition device provided by at least one embodiment of the present disclosure. Figure 7 As shown, the clock constraint definition device 700 includes an acquisition module 701 and a definition module 702 .

[0188] For example, the acquisition module 701 is configured to acquire top-level description information of each clock among the multiple clocks from the top-level clock description file of the chip, wherein the top-level description information includes definition information of the top-level clock constraint of each clock and position information of each clock in the bottom-level module, the definition information is obtained based on the top-level clock definition of each clock in the top level of the chip design, the position information is determined based on the position of each clock in at least one bottom-level module corresponding to the top level, and the position information includes at least one bottom-level starting point of each clock in at least one bottom-level module;

[0189] For example, the definition module 702 is configured to automatically define a bottom-level clock constraint of a target clock in at least one clock in a corresponding at least one bottom-level module based on top-level description information of at least one clock in the plurality of clocks.

[0190] The clock constraint definition device 700 can achieve technical effects similar to those of the aforementioned clock constraint definition method, which will not be described in detail here.

[0191] At least one embodiment of the present disclosure further provides an electronic device, including a memory and a processor, wherein the memory non-transiently stores computer executable instructions, and the processor is configured to run the computer executable instructions, wherein the computer executable instructions are executed by the processor to implement the clock constraint definition method of any of the above embodiments. The technical effect of the electronic device is the same as the technical effect of the above clock constraint definition method, which will not be repeated here.

[0192] At least one embodiment of the present disclosure also provides a non-transitory computer-readable storage medium. Figure 8 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Figure 8 As shown, one or more computer executable instructions 801 may be non-transitory stored on the storage medium 800. For example, when the computer executable instructions 801 are executed by the processor, one or more steps in the clock constraint definition method described above may be executed. The technical effect of the non-transitory storage medium is the same as the technical effect of the clock constraint definition method described above, and will not be repeated here.

[0193] For example, the above-mentioned non-transient readable storage medium is implemented as a memory, such as a volatile memory and / or a non-volatile memory. In the above-mentioned embodiment, the memory may be a volatile memory, such as a random access memory (RAM) and / or a cache, etc. Non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. Various applications (codes, instructions) and data, as well as various data used and / or generated by the application, etc. may also be stored in the memory.

[0194] The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device executes the method of the present disclosure.

[0195] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0196] Some embodiments of the present disclosure further provide an electronic device, which includes the clock constraint definition device of any of the above embodiments or can execute the clock constraint definition method of any of the above embodiments.

[0197] Fig. 9 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. The electronic device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig. 9 The electronic device 900 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0198] For example, Fig. 9 As shown, in some examples, the electronic device 900 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 901, which may include a clock constraint definition device of any of the above-mentioned embodiments, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage device 908 to a random access memory (RAM) 903. Various programs and data required for the operation of the computer system are also stored in the RAM 903. The processor 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0199] For example, the following components may be connected to the I / O interface 905: an input device 906 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 907 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 908 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 909 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 909 may allow the electronic device 900 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. A drive 910 is also connected to the I / O interface 905 as needed. A removable storage medium 911, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 910 as needed, so that a computer program read therefrom is installed into the storage device 908 as needed. Although Fig. 9 The electronic device 900 is shown to include various devices, but it should be understood that it is not required to implement or include all of the devices shown, and more or fewer devices may be implemented or included instead.

[0200] For example, the electronic device 900 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 909 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0201] For example, the electronic device 900 may be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, etc., or may be any combination of data processing devices and hardware, which is not limited by the embodiments of the present disclosure.

[0202] Although the disclosure has been described in detail above with general descriptions and specific implementation methods, it is obvious to those skilled in the art that some modifications or improvements may be made to the embodiments of the disclosure. Therefore, these modifications or improvements made without departing from the spirit of the disclosure are within the scope of protection claimed by the disclosure.

[0203] In addition to the above exemplary contents, the following points need to be explained in this disclosure:

[0204] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0205] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0206] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0207] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.< / edge> < / invert> < / invert> < / invert> < / invert> < / invert> < / multiply> < / multiply> < / divide> < / divide> < / invert> < / invert> < / invert> < / invert> < / invert>

Claims

1. A clock constraint definition method, comprising: Acquire top-level description information of each clock among a plurality of clocks, wherein the top-level description information includes definition information of top-level clock constraints of each clock and location information of each clock in a bottom-level module, the definition information is obtained based on top-level clock definition of each clock in a top-level of chip design, the location information is determined based on the location of each clock in at least one bottom-level module corresponding to the top-level, and the location information includes at least one bottom-level starting point of each clock in at least one bottom-level module; Based on the top-level description information of at least one clock among the multiple clocks, bottom-level clock constraints of a target clock among the at least one clock in the corresponding at least one bottom-level module are automatically defined.

2. The clock constraint definition method according to claim 1, wherein: The definition information of the top-level clock constraint of each clock is obtained based on performing the top-level clock definition on each clock in the top-level of the chip design, including: In response to any clock among the multiple clocks being a master clock in the top level, determining that the definition information of the top-level clock constraint of the any clock includes: a top-level clock period, a top-level clock duty cycle, and a top-level clock definition point; or In response to any clock among the multiple clocks being a generated clock in the top level, the definition information of the top-level clock constraint of the any clock is determined to include: the top-level main clock name, the top-level clock source definition point, the top-level generation type and the top-level generation terminal definition point.

3. The clock constraint definition method according to claim 2, wherein: The top-level description information also includes a top-level clock type, and the top-level clock type includes a first top-level type and a second top-level type. The first top-level type indicates that any clock in the top level is a master clock, and the second top-level type indicates that any clock in the top level is a generated clock.

4. The clock constraint definition method according to claim 3, wherein: The method of automatically defining the bottom-level clock constraint of the target clock in the at least one clock in the corresponding at least one bottom-level module based on the top-level description information of at least one clock among the multiple clocks includes: In response to the top-level clock type of the target clock being the first top-level type, determining that the at least one clock includes only the target clock; Based on the top-level description information of the target clock, automatically define the bottom-level clock constraints of the target clock in the current bottom-level module in the corresponding at least one bottom-level module, The underlying clock constraints of the target clock include underlying clock period, underlying clock duty cycle and underlying clock definition point.

5. The clock constraint definition method according to claim 4, wherein: The step of automatically defining the bottom-level clock constraint of the target clock in the current bottom-level module in the corresponding at least one bottom-level module based on the top-level description information of the target clock includes: Let the bottom-level clock period of the target clock be equal to the top-level clock period of the target clock; Setting the bottom-level clock duty cycle of the target clock to be equal to the top-level clock duty cycle of the target clock; The name of the bottom-level clock definition point of the target clock is set to the name of the bottom-level starting point of the target clock in the current bottom-level module, and the pin type of the bottom-level clock definition point is determined according to the name of the bottom-level starting point of the target clock in the current bottom-level module. Among them, the pin type of the bottom-level clock definition point includes a first pin type and a second pin type, the first pin type indicates that the target clock is located at the port of the current bottom-level module, and the second pin type indicates that the target clock is located at an internal point of the current bottom-level module.

6. The clock constraint definition method according to claim 3, wherein: The method of automatically defining the bottom-level clock constraint of the target clock in the at least one clock in the corresponding at least one bottom-level module based on the top-level description information of at least one clock among the multiple clocks includes: In response to the top-level clock type of the target clock being the second top-level type, determining that the at least one clock includes the target clock and an upper-level clock set of the target clock, the upper-level clock set includes at least a first-level clock, and the first-level clock is a master clock of the target clock; Based on the top-level description information of the target clock and the top-level description information of the upper-level clock set, the bottom-level clock constraint of the target clock in the current bottom-level module in the corresponding at least one bottom-level module is automatically defined.

7. The clock constraint definition method according to claim 6, wherein: The step of automatically defining the bottom-level clock constraint of the target clock in the current bottom-level module in the corresponding at least one bottom-level module based on the top-level description information of the target clock and the top-level description information of the upper-level clock set includes: Determining the underlying clock type of the target clock in the current underlying module based on the name of the underlying starting point of the target clock in the current underlying module; and Automatically define the bottom-level clock constraint of the target clock in the current bottom-level module based on the bottom-level clock type of the target clock in the current bottom-level module, the top-level description information of the target clock, and the top-level description information of the upper-level clock set, Among them, the underlying clock type includes a first underlying type and a second underlying type, the first underlying type indicates that the target clock is a master clock in the current underlying module, and the second underlying type indicates that the target clock is a generated clock in the current underlying module.

8. The clock constraint definition method according to claim 7, wherein: The method of automatically defining the bottom-level clock constraint of the target clock in the current bottom-level module based on the bottom-level clock type of the target clock in the current bottom-level module, the top-level description information of the target clock, and the top-level description information of the upper-level clock set includes: In response to the underlying clock type of the target clock being the second underlying type, determining that the underlying clock constraints of the target clock include an underlying master clock name, an underlying clock source definition point, an underlying generation type, and an underlying generation end definition point; Obtaining definition information of top-level clock constraints of the first-level clock in the upper-level clock set; Setting the bottom-level master clock name of the target clock to the clock name of the first-level clock; Setting the name of the bottom-level clock source definition point of the target clock to the name of the bottom-level starting point of the first-level clock in the current bottom-level module; Setting the bottom generation type of the target clock to the top generation type of the target clock; and The name of the bottom-level generation end definition point of the target clock is set to the name of the bottom-level starting point of the target clock in the current bottom-level module.

9. The clock constraint definition method according to claim 7, wherein: The method of automatically defining the bottom-level clock constraint of the target clock in the current bottom-level module based on the bottom-level clock type of the target clock in the current bottom-level module, the top-level description information of the target clock, and the top-level description information of the upper-level clock set includes: In response to the underlying clock type of the target clock being the first underlying type, determining that the underlying clock constraints of the target clock include an underlying clock period, an underlying clock duty cycle, and an underlying clock definition point; Obtaining definition information of the top-level clock constraint of the parent clock set of the target clock; Calculating the bottom-level clock period and the bottom-level clock duty cycle of the target clock according to the top-level generation type of the target clock and the definition information of the top-level clock constraint of the upper-level clock set; The name of the underlying clock definition point of the target clock is set to the name of the underlying starting point of the target clock in the current underlying module, and the pin type of the underlying clock definition point of the target clock is determined to be the first pin type.

10. The clock constraint definition method according to claim 9, wherein: The calculating the bottom-level clock period and the bottom-level clock duty cycle of the target clock according to the top-level generation type of the target clock and the definition information of the top-level clock constraint of the upper-level clock set includes: According to the top-level generation type of the target clock being at least one of frequency division, frequency multiplication, inversion, and phase shift, determining that the first target function corresponding to the top-level generation type of the target clock is at least one of frequency division function, frequency multiplication function, inversion function, and phase shift function; The bottom-level clock period and the bottom-level clock duty cycle of the target clock are calculated based on the first objective function and the definition information of the top-level clock constraint of the upper-level clock set.

11. The clock constraint definition method according to claim 10, wherein: The calculating the bottom-level clock period and the bottom-level clock duty cycle of the target clock based on the first objective function and the definition information of the top-level clock constraint of the upper-level clock set includes: In response to the top-level clock type of the first-level clock being the first top-level type, directly applying the first target function to the top-level clock period and the top-level clock duty cycle of the first-level clock, thereby calculating the bottom-level clock period and the bottom-level clock duty cycle of the target clock; or, In response to the top-level clock type of the first-level clock being the second-level type, acquiring top-level clock constraint information of a second-level clock that is a master clock of the first-level clock; In response to the top-level clock type of the second-level clock being the first-level type, determining a second objective function according to the top-level generation type of the first-level clock; The first objective function and the second objective function are applied in a nested manner, so as to calculate the underlying clock period and the underlying clock duty cycle of the target clock.

12. The clock constraint definition method according to claim 10, wherein: Calculating the underlying clock period and the underlying clock duty cycle of the target clock based on the frequency division function includes: Get the frequency division coefficient Q; Let the bottom clock period Period of the target clock be equal to the top clock period Period_Master of the first-level clock multiplied by the frequency division coefficient Q; The vector Waveform of the bottom-level clock duty cycle of the target clock is equal to the vector Waveform_Master of the top-level clock duty cycle of the first-level clock multiplied by the frequency division coefficient Q.

13. The clock constraint definition method according to claim 10, wherein: Calculating the underlying clock period and the underlying clock duty cycle of the target clock based on the frequency multiplication function includes: Get the frequency multiplication factor P; Let the bottom clock period Period of the target clock be equal to the top clock period Period_Master of the first-level clock divided by the frequency multiplication factor P; The vector Waveform of the bottom-level clock duty cycle of the target clock is set equal to the vector Waveform_Master of the top-level clock duty cycle of the first-level clock divided by the frequency multiplication coefficient P.

14. The clock constraint definition method according to claim 10, wherein: Calculating the underlying clock period and the underlying clock duty cycle of the target clock based on the reverse function includes: Let the bottom-level clock period Period of the target clock be equal to the top-level clock period Period_Master of the first-level clock; Get the vector representation [x1, x2, ..., xn] of the vector Waveform_Master of the top-level clock duty cycle of the first-level clock; In response to x2 being less than Period_Master, determining that the vector Waveform of the duty cycle of the underlying clock of the target clock is represented by [x2, x3, ..., xn, x1 + Period_Master]; or In response to x2 being greater than or equal to Period_Master, it is determined that the vector Waveform of the duty cycle of the underlying clock of the target clock is represented by [x2-Period_Master, x3-Period_Master, ..., xn-Period_Master, x1].

15. The clock constraint definition method according to claim 14, further comprising: When invert and other generated types other_generate_type exist at the same time, the reverse function f is applied nestedly. <invert> and other functions f<other_generate_type> , thereby calculating the underlying clock period and the underlying clock duty cycle of the target clock, wherein the other types include the frequency division or the frequency multiplication.< / invert> 16. The clock constraint definition method according to claim 15, further comprising: In response to the other type first and then the reverse direction, the underlying clock period Period of the target clock is determined to be Period=f <invert>(f<other_generate_type> (Period_Master)), determine the vector Waveform of the underlying clock duty cycle of the target clock = f <invert> (f<other_generate_type> (Waveform_Master));< / invert> < / invert> In response to the reverse first, then other types, determine the underlying clock period Period of the target clock = f<other_generate_type> (f <invert>(Period_Master)), determine the vector Waveform of the underlying clock duty cycle of the target clock = f<other_generate_type> (f <invert> (Waveform_Master)).< / invert> < / invert> 17. The clock constraint definition method according to claim 10, wherein: Calculating the underlying clock period and the underlying clock duty cycle of the target clock based on the phase offset function includes: Get the vector representation of the edge vector edges_list [e1, e2, ..., el], the vector representation of the offset vector edge_shift_list [r1, r2, ..., rl], and the vector representation of the top-level clock duty cycle vector Waveform_Master of the first-level clock [x1, x2, ..., xn]; Based on the vector representation [x1, x2, ..., xn] of the top-level clock duty cycle vector Waveform_Master, an expanded master clock waveform vector [y1, y2, ..., ym] is obtained, where m = edges_list[-1]; Let the bottom clock period Period of the target clock be equal to Time_Master[edges_list[-1]-1]+edge_shift_list[-1]-Time_Master[edges[0]-1]-edge_shift_list[0]; The vector representation of the vector Waveform that determines the duty cycle of the underlying clock of the target clock is [z1, z2, ..., zl-1], where the length of the Waveform is 1 less than edges_list, Waveform[i] = Time_Master[edges_list[i]-1]+edge_shift_list[i].

18. The clock constraint definition method according to claim 17, wherein: The expanded master clock waveform vector [y1, y2, ..., ym] is obtained based on the vector representation [x1, x2, ..., xn] of the top-level clock duty cycle vector Waveform_Master, including: Get the top-level clock period Period_Master of the first-level clock; When m%n-1==0, determine ym=Period_Master*int(m / n); When m%n-1!=0, it is determined that ym=Period_Master*int((m-1) / n)+Waveform_Master[(m-1)%n].

19. The clock constraint definition method according to claim 1, further comprising: Find all bottom-level clocks to be defined from the top-level clock description file, wherein the top-level clock description information of the bottom-level clocks to be defined includes at least one bottom-level starting point of the bottom-level clocks to be defined in the at least one bottom-level module; All the underlying clocks to be defined are used as the target clocks in sequence to automatically define the underlying clock constraints of all the underlying clocks to be defined.

20. A clock constraint definition device, comprising: an acquisition module configured to acquire top-level description information of each clock among a plurality of clocks from a top-level clock description file of a chip, wherein the top-level description information includes definition information of top-level clock constraints of each clock and location information of each clock in a bottom-level module, the definition information is obtained based on top-level clock definition of each clock in a top-level of a chip design, the location information is determined based on the location of each clock in at least one bottom-level module corresponding to the top-level, and the location information includes at least one bottom-level starting point of each clock in at least one bottom-level module; The definition module is configured to automatically define the bottom-level clock constraint of the target clock in the at least one clock in the corresponding at least one bottom-level module based on the top-level description information of at least one clock in the multiple clocks.

21. An electronic device comprising: at least one memory non-transitorily storing computer executable instructions; at least one processor configured to execute the computer executable instructions, Wherein, when the computer executable instructions are executed by the processor, the clock constraint definition method according to any one of claims 1-19 is implemented.

22. A non-transitory computer-readable storage medium, wherein: The non-transitory computer-readable storage medium stores computer-executable instructions, When the computer executable instructions are executed by at least one processor, the clock constraint definition method according to any one of claims 1 to 19 is implemented.

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