Display device

Abstract

A display device includes a display panel and a display driver circuit. The display driver circuit includes a drive controller configured to receive an image signal at a variable frame rate and output image data obtained by converting the image signal in response to a display synchronization signal. The driving controller includes a light emission control block. The light emission control block compares a reference period of a reference period interval of a light emission period of a preset display panel with a display period of a current frame interval, changes the reference period to an adjustment period according to a comparison result, and outputs a drive control signal, the driving control signal is used for controlling the display panel to emit light from a start time point of a next frame interval during an adjustment period interval in which the display panel has the adjustment period.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a display device capable of improving image quality. Background Art

[0002] An emissive display device displays an image by using a light emitting diode that generates light through recombination of electrons and holes. The emissive display device has a fast response speed and is driven with low power consumption.

[0003] An emissive display device includes pixels connected to data lines and scan lines. The pixels generally include a light emitting diode and a circuit unit for controlling the amount of current flowing through the light emitting diode. The circuit unit controls the amount of current in response to a data signal so that the current passes through the light emitting diode at a first drive voltage and flows at a second drive voltage. In this case, light having a specific brightness is generated to correspond to the amount of current flowing through the light emitting diode. Summary of the invention

[0004] An embodiment of the present invention provides a display device, wherein the display device is capable of improving image quality when operating in a variable frequency mode.

[0005] According to an embodiment, a display device includes a display panel including a plurality of pixels emitting light in response to a data signal, and a display driver circuit configured to provide the data signal to the display panel.

[0006] In an embodiment, a display driver circuit includes: a drive controller configured to receive an image signal at a variable frame rate and output image data obtained by converting the image signal in response to a display synchronization signal; and a data driver configured to convert the image data into a data signal and output the data signal.

[0007] In an embodiment, the driving controller includes a data conversion block and a light emitting control block. The data conversion block converts an image signal into image data and outputs the image data of the current frame interval determined based on the display synchronization signal. The light emitting control block compares a reference period of a reference cycle interval of a preset light emitting cycle of the display panel with a display period of the current frame interval, changes the reference period to an adjustment period according to the comparison result, and outputs a driving control signal, the driving control signal being used to control the display panel to emit light during an adjustment cycle interval in which the display panel has the adjustment period from the start time point of the next frame interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects and features of the present invention will become apparent by describing in detail the embodiments of the present invention with reference to the accompanying drawings.

[0009] Figure 1 is a block diagram of an electronic device according to an embodiment.

[0010] Figure 2 is a block diagram of a drive controller according to an embodiment.

[0011] Figure 3A is a timing chart showing the operation of the display device according to the embodiment.

[0012] Figure 3B is a timing chart showing the operation of the display device according to the embodiment.

[0013] Figure 4A is a timing chart showing the operation of the display device according to the embodiment.

[0014] Figure 4B is a timing chart showing the operation of the display device according to the embodiment.

[0015] Figure 5 is a timing diagram describing a reference duty cycle and first and second adjusted duty cycles according to an embodiment.

[0016] Fig. 6A is a timing chart showing the operation of the display device according to the embodiment.

[0017] Figure 6B is a timing chart showing the operation of the display device according to the embodiment.

[0018] Figure 7 is a schematic block diagram of a display device according to an embodiment.

[0019] Figure 8 is a circuit diagram of a pixel according to an embodiment.

[0020] Fig.9A is a timing chart showing the operation of the display device according to the embodiment.

[0021] Fig. 9B is a timing chart showing the operation of the display device according to the embodiment.

[0022] Fig. 9C is a timing chart showing the operation of the display device according to the embodiment.

[0023] Fig.10 is a flowchart illustrating the operation of the display device according to the embodiment.

[0024] Fig.11 is a flowchart illustrating the operation of the display device according to the embodiment. DETAILED DESCRIPTION

[0025] The present invention will now be described more fully below with reference to the accompanying drawings showing various embodiments. However, the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art.

[0026] In this specification, the statement that a first component (or region, layer, part, interval, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or means that a third component is between the first component and the second component.

[0027] The same reference numerals will be assigned to the same components. In addition, in the drawings, the thickness, proportion and size of the components may be exaggerated in order to effectively describe the technical features. The term "and / or" includes any and all combinations of one or more related components.

[0028] Although the terms "first", "second", etc. may be used to describe various components, these components should not be construed as being limited by these terms. These terms are only used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope and spirit of the present invention. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0029] In addition, the terms "below", "at the lower part", "on", and "at the upper part" are used to describe the relationship between the components shown in the drawings. These terms are relative and are described with reference to the directions indicated in the drawings.

[0030] It will be further understood that the terms “includes,” “comprising,” “containing,” or “having” or “having” indicate the presence of the stated features, quantities, steps, operations, components, parts, or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, and / or combinations thereof.

[0031] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formalized meaning.

[0032] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0033] Figure 1 is a block diagram of a display device according to an embodiment.

[0034] In the examples and with reference to Figure 1 The electronic device ED may be a device that outputs various pieces of information through the display module DM in an operating system (OS). For example, the electronic device ED may be an electronic device such as a smart phone, a smart watch, a computer (such as a tablet personal computer (PC) or a laptop computer), a smart television (TV), or a navigation device.

[0035] In an embodiment, the electronic device ED may communicate with an external electronic device through a network (eg, a short-range wireless communication network or a long-range wireless communication network).According to an embodiment, the electronic device ED may include a main processor MCU, a display driver circuit DDIC, and a display module DM.

[0036] In an embodiment, the main processor MCU may include at least one of a central processing unit (CPU) and an application processor (AP). The main processor MCU may further include at least one of a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP).

[0037] In an embodiment, the display driver circuit DDIC (or display driver chip) may include a drive controller 100 (or drive control circuit) and a data driver 200 (or data drive circuit). The drive controller 100 receives an image signal RGB and a control signal CTRL from a main processor MCU. The drive controller 100 generates image data DATA by converting the data format of the image signal RGB to match the interface specification of the data driver 200. The drive controller 100 may output various drive control signals (e.g., a first drive control signal DCS, a second drive control signal SCS, or a third drive control signal ECS) required to drive the display module DM in response to the control signal CTRL.

[0038] In an embodiment, the data driver 200 receives the image data DATA and the first driving control signal DCS from the driving controller 100. The data driver 200 may compensate the image data DATA to display an image with desired brightness according to the characteristics of the electronic device ED or user settings or may convert the image data DATA to reduce power consumption or compensate for afterimages.

[0039] In an embodiment, the display driver circuit DDIC may further include a voltage generator 400 (or a voltage generating circuit) (see Figure 7The voltage generator 400 may output various types of voltages required to drive the display panel DP (eg, a first driving voltage ELVDD and a second driving voltage ELVSS (see Figure 7 )).

[0040] In an embodiment, the display module DM visually provides information to a user.The display module DM may include a display panel DP, a scan driver 300 (or a scan driving circuit), and a light emitting driver 350 (or a light emitting driving circuit).

[0041] In an embodiment, the display panel DP may be a light-emitting display panel, but the present invention is not particularly limited thereto. For example, the display panel DP may include an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods. Hereinafter, the following description will be made based on an embodiment in which the display panel DP is an organic light-emitting display panel. The display panel DP may include a plurality of pixels PX (see Figure 7 ), a plurality of scan lines, a plurality of data lines, a plurality of light emitting control lines, and a plurality of voltage lines. Each of the pixels PX may include a light emitting element ED (see Figure 8 ) and a pixel circuit portion PXC connected to the light emitting element ED (see Figure 8 ).

[0042] In an embodiment, the scan driver 300 receives the second driving control signal SCS from the driving controller 100. The scan driver 300 may output the scan signal to the scan line in response to the second driving control signal SCS.

[0043] In an embodiment, the light emitting driver 350 receives the third driving control signal ECS from the driving controller 100. The light emitting driver 350 may output the light emitting control signal to the light emitting control line in response to the third driving control signal ECS. In another embodiment, the scan driver 300 may be connected to the light emitting control line. In this case, the light emitting driver 350 may be omitted, and the scan driver 300 may output the light emitting control signal to the light emitting control line.

[0044] In an embodiment, the display module DM may further include a window, a chassis, and a bracket to protect the display panel DP. In addition, the electronic device ED may further include at least some components in addition to the above components.

[0045] Figure 2 is a block diagram of a drive controller according to an embodiment.

[0046] In the examples and with reference to Figure 1 and Figure 2 , the driving controller 100 may support a variable frequency mode. In the variable frequency mode, the main processor MCU provides the image signal RGB to the driving controller 100 at a variable frame rate. The driving controller 100 supporting the variable frequency mode controls the driving of the data driver 200 and the display module DM in synchronization with the variable frame rate, so that the electronic device ED displays an image at a variable frame rate. According to an embodiment, the highest frame rate of the variable frame rate supported in the variable frequency mode may be referred to as a reference frame rate.

[0047] In an embodiment, a period during which the driving controller 100 outputs the image data DATA to the data driver 200 may be defined as a frame interval. In a variable frequency mode, the duration of the frame interval may vary depending on the frame rate. For example, when the frame rate is about 240 Hz, the duration of the frame interval may be about 4.167 ms, and when the frame rate is about 60 Hz, the duration of the frame interval may be about 16.7 ms. According to an embodiment, the reference frame rate may be set to about 480 Hz, about 360 Hz, or about 240 Hz.

[0048] In an embodiment, during the current frame interval, the driving controller 100 may receive the image signal RGB at a current frame rate. The current frame rate may be less than or equal to the reference frame rate.

[0049] In an embodiment, the driving controller 100 includes a data conversion block 110 and a light emitting control block 120. The data conversion block 110 may convert the image signal RGB into the image data DATA, and display the image data DATA based on the display synchronization signal Vsync (see Figure 3A ) The image data DATA outputted from the data conversion block 110 may be provided to the data driver 200.

[0050] In an embodiment, the light emitting control block 120 may output a light emitting drive control signal (i.e., a third drive control signal ECS) for controlling the light emitting period of the display panel DP among various drive control signals. The light emitting control block 120 may Figure 3A ) is compared with the display period of the current frame interval, and the reference period can be changed to the adjustment period based on the comparison result. The light emitting control block 120 can control the display panel DP to emit light during the adjustment cycle interval in which the display panel DP has the adjustment period from the start time point of the next frame interval.

[0051] In an embodiment, the light emitting control block 120 may include a calculation unit 121 and a setting unit 122. The calculation unit 121 may compare the display period with an integer multiple of a reference period, and when the display period is different from the integer multiple of the reference period, the calculation unit 121 may calculate the difference between the display period and the integer multiple of the reference time based on the comparison result. The setting unit 122 may set the duty cycle of the adjustment period and the adjustment cycle interval based on the calculated difference and may output a third driving control signal ECS corresponding to the adjustment period and the duty cycle.

[0052] In an embodiment, the third driving control signal ECS may be provided to the light emitting driver 350 of the display module DM, and the light emitting driver 350 may control a light emitting period (AID period) of the display panel DP in response to the third driving control signal ECS.

[0053] In another embodiment, when the display period is different from an integral multiple of the reference period based on the comparison result, the light control block 120 may maintain the light emission period (AID period) in a specific state (active state or inactive state) from the next frame interval.

[0054] In an embodiment, the driving controller 100 may further include a variable frequency block 130 and a brightness control block 140. The variable frequency block 130 may calculate the display period of the current frame interval based on the variable frame rate, and may provide information F_I related to the calculated display period (hereinafter, period information F_I) to the calculation unit 121 of the light emitting control block 120. Therefore, the calculation unit 121 may compare the display period with the reference period based on the period information F_I provided from the variable frequency block 130.

[0055] In an embodiment, the brightness control block 140 may set a reference duty ratio of a reference cycle interval based on the dimming signal Dim. The brightness control block 140 may provide information B_I (hereinafter, duty information B_I) related to the set reference duty ratio to the setting unit 122 of the light emitting control block 120. Therefore, the setting unit 122 may generate a third driving control signal ECS for controlling the adjustment cycle interval to have an adjustment duty ratio different from the reference duty ratio of the reference cycle interval based on the duty information B_I provided from the brightness control block 140.

[0056] Figure 3A and Figure 3B is a timing chart showing the operation of the display device according to the embodiment. Figure 4A and Figure 4B is a timing chart showing the operation of the display device according to the embodiment. Figure 5 is a timing diagram describing a reference duty cycle and first and second adjusted duty cycles according to an embodiment.

[0057] In the examples and with reference to Figure 3A and Figure 4A , electronic device ED (see Figure 1 ) can operate in variable frequency mode where the frame rate varies. Figure 3A The first frame interval DF1, the second frame interval DF2, the third frame interval DF3, the fourth frame interval DF4 and the fifth frame interval DF5 are respectively shown. For example, the electronic device ED operates at a first frame rate for the first frame interval DF1 and the second frame interval DF2, operates at a second frame rate for the third frame interval DF3 and the fourth frame interval DF4, and operates at a third frame rate for the fifth frame interval DF5.

[0058] According to an embodiment, the first frame rate may be less than or equal to the highest reference frame rate at which the electronic device ED can operate. For example, the reference frame rate may be about 240 Hz, about 360 Hz, or about 480 Hz. The second frame rate and the third frame rate may be less than the first frame rate. The second frame rate and the third frame rate may be different from each other.

[0059] In an embodiment and as described above, when the first to third frame rates are different from each other, the time periods of the first frame interval DF1 and the second frame interval DF2 (hereinafter, display periods DT1 and DT2) may be different from the display periods DT3 and DT4 of the third frame interval DF3 and the fourth frame interval DF4, respectively. In addition, the display period DT5 of the fifth frame interval DF5 may be different from the display periods DT1 to DT4 of the first frame interval DF1, the second frame interval DF2, the third frame interval DF3, and the fourth frame interval DF4, respectively. For example, each of the first to fifth frame intervals DF1 to DF5 may include a display period and a blanking period. The duration of the blanking period may vary depending on the operating frequency, and the duration of the display period may be constant without varying depending on the driving frequency. In this case, the display period may be the drive controller 100 (see Figure 1 ) actually to the data driver 200 (see Figure 1 ) provides image data DATA (see Figure 1 ) period.

[0060] In an embodiment, the image data DATA respectively provided to the data driver 200 for the first to fifth frame intervals DF1 to DF5 may be respectively referred to as first, second, third, fourth, and fifth image data DATA_1, DATA_2, DATA_3, DATA_4, and DATA_5.

[0061] In an embodiment, the display periods DT1 to DT5 of the first frame interval DF1, the second frame interval DF2, the third frame interval DF3, the fourth frame interval DF4, and the fifth frame interval DF5 may be determined by the display synchronization signal Vsync (or vertical synchronization signal). For example, each of the display periods DT1 to DT5 may be defined as from the current falling edge time point of the display synchronization signal Vsync to the next falling edge time point of the display synchronization signal Vsync. In the variable frequency mode, the period of the display synchronization signal Vsync may vary depending on the frame rate. The display synchronization signal Vsync may be included in the first drive control signal DCS (see FIG. 1 ) provided by the drive controller 100 to the data driver 200. Figure 1 ) in the signal.

[0062] In the embodiment, the display panel DP (see Figure 1 ) can emit light in a preset light emission cycle (AID cycle). The reference cycle interval of the light emission cycle (AID cycle) has a reference period RT. An integer multiple of the reference period RT can be set to be equal to a display period (i.e., a reference display period) of a frame interval having a reference frame rate. For example, the reference display period can be set to one or two times the reference period RT.

[0063] In an embodiment, the light emitting control block 120 may compare the display periods DT1 to DT5 with the reference period RT in each frame interval. When each of the display periods DT1 to DT5 is different from an integer multiple of the reference period RT, the light emitting control block 120 may calculate the difference between the integer multiple of the reference period RT and each of the display periods DT1 to DT5. For example, when the first display period DT1 is different from an integer multiple (e.g., 4×RT) of the reference period RT during the first frame interval DF1, the light emitting control block 120 may calculate the difference (i.e., the first difference d1) between the first display period DT1 and the integer multiple (e.g., 4×RT) of the reference period RT.

[0064] In an embodiment, the first frame interval DF1 may correspond to "k" reference period intervals and one compensation period interval. In this case, "k" may be an integer equal to or greater than "1", and Figure 3A It is shown that "k" is "3". The period of the compensation cycle interval (i.e., the first compensation period CT1) may be greater than the period of the reference cycle interval (i.e., the reference period RT) by a first difference d1. The duty cycle of the compensation cycle interval may be different from the duty cycle of each of the "k" reference cycle intervals. The compensation cycle interval may be after the "k" reference cycle intervals.

[0065] In the embodiments and as Figure 3BAs shown in , each reference cycle interval includes a first non-luminous interval NEP1 and a first luminous interval EP1, and the compensation cycle interval includes a second non-luminous interval NEP2 and a second luminous interval EP2. According to an embodiment, the duration of the second non-luminous interval NEP2 may be equal to the duration of the first non-luminous interval NEP1, and the duration of the second luminous interval EP2 may be greater than the duration of the first luminous interval EP1 by a first difference d1. Therefore, the duty cycle of the compensation cycle interval (i.e., the compensation duty cycle) may be different from the duty cycle of the reference cycle interval (e.g., the reference duty cycle). In this case, the compensation duty cycle may be defined as the proportion occupied by the second luminous interval EP2 of the first compensation period CT1, and the reference duty cycle may be defined as the proportion occupied by the first luminous interval EP1 of the reference period RT.

[0066] In the embodiment, although Figure 3A and Figure 3B The second light-emitting interval EP2 of the compensation period interval is shown to extend the first difference d1, but the present invention is not limited thereto. Figure 4A and Figure 4B As shown in , the compensation period interval may include a second non-luminous interval NEP2, a second luminous interval EP2, and a third non-luminous interval EP3. According to an embodiment, the duration of the second non-luminous interval NEP2 may be equal to the duration of the first non-luminous interval NEP1, and the duration of the second luminous interval EP2 may be equal to the duration of the first luminous interval EP1. At the same time, when Figure 3B When compared with the compensation cycle interval shown in Figure 4B The compensation period interval may further include a third non-light emitting interval NEP3, and a duration of the third non-light emitting interval NEP3 may correspond to the first difference d1.

[0067] In the embodiment and as described above, since the compensation period interval has the first compensation period CT1 or CT1a which is greater than the reference period RT by the first difference d1, the termination time point of the compensation period interval can match the termination time point of the first frame interval DF1. Therefore, even if the first display period DT1 does not match the integer multiple of the reference period RT, the termination time point of the compensation period interval can be matched with the termination time point of the first frame interval DF1 by adjusting the first compensation period CT1 or CT1a. Therefore, this can eliminate or reduce the flicker phenomenon that occurs when the first display period DT1 does not match the integer multiple of the reference period RT.

[0068] In the examples and returning to reference Figure 3A and Figure 4A , light control block 120 (see Figure 2) can adjust the reference period RT and (or) the reference duty ratio of the reference period interval of the light emitting period (AID period) based on the first difference d1, and can control the display panel DP (see Figure 1 ) during the next frame interval with an adjustment period interval. For example, the display panel DP may emit light during a first adjustment period interval having an adjustment period AT1 (i.e., a first adjustment period AT1) in the second frame interval DF2. The second display period DT2 may be equal to an integer multiple of the first adjustment period AT1 (i.e., 4×AT1).

[0069] In an embodiment, in the second frame interval DF2, the difference between the second display period DT2 and the integer multiple (e.g., 4×RT) of the reference period RT may be maintained as the first difference d1. In this case, even in the next frame interval, the light emitting control block 120 may allow the display panel DP to emit light during the first adjustment period interval having the first adjustment period AT1. In the third frame interval DF3, the difference between the third display period DT3 and the integer multiple (e.g., 4×RT) of the reference period RT may be changed to the second difference d2.

[0070] In an embodiment, the third frame interval DF3 may correspond to "k" reference cycle intervals and one compensation cycle interval. The period of the compensation cycle interval (i.e., the second compensation period CT2) may be greater than the first adjustment period AT1 by a value d2-1 obtained by subtracting the first difference d1 from the second difference d2. The duty cycle of the compensation cycle interval may be different from the duty cycle of each of the "k" reference cycle intervals. The compensation cycle interval may be after the "k" reference cycle interval.

[0071] In addition, in an embodiment, the light control block 120 may readjust the reference period RT and (or) the reference duty ratio of the reference period interval of the light emission period (AID period) based on the second difference d2. For example, the display panel DP may emit light during the second adjustment period interval having the readjustment period AT2 (i.e., the second adjustment period AT2) in the fourth frame interval DF4. The fourth display period DT4 may be equal to an integer multiple of the second adjustment period AT2 (i.e., 4×AT2).

[0072] In an embodiment, in the fourth frame interval DF4, the difference between the fourth display period DT4 and the integer multiple of the reference period RT (e.g., 4×RT) may be maintained as the second difference d2. In this case, the light emitting control block 120 may allow the display panel DP to emit light during the second adjustment period interval having the second adjustment period AT2 even in the next frame interval (i.e., the fifth frame interval DF5). In the fifth frame interval DF5, when the difference between the fifth display period DT5 and the integer multiple of the reference period RT (e.g., 4×RT) is maintained as the second difference d2, the fifth display period DT5 may be equal to the integer multiple of the second adjustment period AT2 (i.e., 4×AT2).

[0073] In the examples and with reference to Figure 3B , Figure 4B and Figure 5 , each reference cycle interval includes a first non-luminous interval NEP1 and a first luminous interval EP1, and the first adjustment cycle interval includes a first adjustment non-luminous interval NEPa and a first adjustment luminous interval EPa. According to an embodiment, the duration of the first adjustment non-luminous interval NEPa may be equal to the duration of the first non-luminous interval NEP1, and the duration of the first adjustment luminous interval EPa may be greater than the duration of the first luminous interval EP1 by a first sub-difference d1 / 4. Therefore, the first adjustment period AT1 may be greater than the reference period RT by a first sub-difference d1 / 4. However, the present invention is not limited thereto. For example, in a state where the first adjustment period AT1 is greater than the reference period RT by a first sub-difference d1 / 4, the duration of the first adjustment non-luminous interval NEPa and the duration of the first adjustment luminous interval EPa may be different from the duration of the first non-luminous interval NEP1 and the duration of the first luminous interval EP1, respectively. In an embodiment, the duty cycle of the first adjustment cycle interval may be different from the duty cycle of the reference cycle interval.

[0074] In an embodiment, the second adjustment cycle interval includes a second adjustment non-luminous interval NEPb and a second adjustment luminous interval EPb. According to an embodiment, the duration of the second adjustment non-luminous interval NEPb may be equal to the duration of the first non-luminous interval NEP1, and the duration of the second adjustment luminous interval EPb may be greater than the duration of the first luminous interval EP1 by a second sub-difference d2 / 4. Therefore, the second adjustment period AT2 may be greater than the reference period RT by a second sub-difference d2 / 4. However, the present invention is not limited thereto. For example, in a state where the second adjustment period AT2 is greater than the reference period RT by a second sub-difference d2 / 4, the duration of the second adjustment non-luminous interval NEPb and the duration of the second adjustment luminous interval EPb may be different from the duration of the first non-luminous interval NEP1 and the duration of the first luminous interval EP1, respectively. In an embodiment, the duty cycle of the second adjustment cycle interval may be different from the duty cycle of the reference cycle interval.

[0075] As described above, in the embodiment, the display period of the current frame interval is compared with the integer multiple of the reference period in each frame interval. When a difference is generated between the display period of the current frame interval and the integer multiple of the reference period, the reference period is changed to an adjustment period based on the difference, so that the end time point of the adjustment period interval matches the end time point of each frame interval. Therefore, even if the display periods DT1 to DT5 do not match the integer multiple of the reference period RT, the flicker phenomenon can be prevented or reduced.

[0076] Fig. 6A and Figure 6B is a timing chart showing the operation of the display device according to the embodiment. Fig. 6A and Figure 6B The components shown in Figure 3A and Figure 4A The same components as those shown in FIG. 1 are assigned the same reference numerals, and details thereof will be omitted to avoid redundancy.

[0077] In the examples and with reference to Fig. 6A and Figure 6B , light control block 120 (see Figure 2) The display periods DT1 to DT5 may be compared with an integer multiple of the reference period RT in each frame interval. When each of the display periods DT1 to DT5 is different from an integer multiple of the reference period RT, based on the comparison result, the difference (hereinafter, a first difference d1, a second difference d2, a third difference d3, and a fourth difference d4) between each of the display periods DT1 to DT5 and the integer multiple of the reference period RT may be calculated. For example, when the first display period DT1 is different from an integer multiple (4×RT) of the reference period RT in the first frame interval DF1, the light emitting control block 120 may calculate the difference between the first display period DT1 and the integer multiple (e.g., 4×RT) of the reference period RT as the first difference d1. For example, when the second display period DT2 is different from the integer multiple (4×RT) of the reference period RT in the second frame interval DF2, the light emitting control block 120 may calculate the difference between the second display period DT2 and the integer multiple (4×RT) of the reference period RT as the second difference d2. For example, when the third display period DT3 is different from the integer multiple (4×RT) of the reference period RT in the third frame interval DF3, the light emitting control block 120 may calculate the difference between the third display period DT3 and the integer multiple (4×RT) of the reference period RT as the third difference d3. For example, when the fourth display period DT4 is different from the integer multiple (4×RT) of the reference period RT in the fourth frame interval DF4, the light emitting control block 120 may calculate the difference between the fourth display period DT4 and the integer multiple (4×RT) of the reference period RT as the fourth difference d4. In the fifth frame interval DF5, the fifth display period DT5 and the integer multiple (e.g., 4×RT) of the reference period RT may match each other.

[0078] In the embodiment, the driving controller 100 (see FIG. 10A ) is configured to drive the controller 100 from the frame interval (ie, the second frame interval DF2) after the first frame interval DF1 in which the first difference d1 is generated until the fifth frame interval DF5 in which no difference is generated. Figure 1 ) can output the black image data DATA_B to the data driver 200 (see Figure 1 ) or output the image data of the previous frame to the data driver 200 (see Figure 1 ). The black image data DATA_B may be image data having a black grayscale.

[0079] In an embodiment, the light emitting period (AID period) may be maintained (or maintained) in a specific state during the second frame interval DF2 to the fourth frame interval DF4. According to an embodiment, the specific state may be one of an inactive state (e.g., a low level state) and an active state (e.g., a high level state). According to an embodiment, when the black image data DATA_B is output during the second frame interval DF to the fourth frame interval DF4 where the differences d1 to d4 are respectively generated, the light emitting period (AID period) may be maintained in an active state. Therefore, the display panel DP (see Figure 1 ) can display a black image during the second frame interval DF to the fourth frame interval DF4. Therefore, it is possible to prevent a flicker phenomenon from being observed due to the differences d1 to d4.

[0080] According to an embodiment, the image data of the previous frame may be image data (eg, first image data DATA_1) in a frame interval (ie, first frame interval DF1) in which a difference is first generated. Figure 6B As shown in , during the second frame interval DF2 to the fourth frame interval DF4 where the differences d1 to d4 are generated, the light emitting period (AID period) can be maintained in an inactive state. Therefore, even if the first image data DATA_1 is output during the second frame interval DF2 to the fourth frame interval DF4, the display panel DP can display a black image. Therefore, it is possible to prevent the flicker phenomenon from being observed due to the differences d1 to d4.

[0081] Figure 7 is a block diagram of a display device according to an embodiment.

[0082] In the examples and with reference to Figure 7 , the display device DD includes a display module DM and a display driver circuit DDIC. The display driver circuit DDIC may include a driving controller 100, a data driver 200, and a voltage generator 400. The display module DM may include a display panel DP, a scan driver 300, and a light emitting driver 350.

[0083] In an embodiment, the display panel DP includes a plurality of pixels PX, a plurality of initialization scan lines SIL1, SIL2, SIL3, ... and SILn, a plurality of compensation scan lines SCL1, SCL2, SCL3, ... and SCLn, a plurality of write scan lines SWL1, SWL2, SWL3, ..., SWLn and SWLn+1, a plurality of emission control lines EML1, EML2, EML3, ... and EMLn, and a plurality of data lines DL1, DL2, ... and DLm, n and m are each a positive integer. The display panel DP may be defined as having an active area AA and a non-active area NAA. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, the emission control lines EML1 to EMLn, the data lines DL1 to DLm, and the pixels PX may overlap the active area AA. Initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn+1, and emission control lines EML1 to EMLn may extend in the first direction DR1. Initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn+1, and emission control lines EML1 to EMLn may be arranged to be spaced apart from each other in the second direction DR2. Data lines DL1 to DLm are arranged to be spaced apart from each other in the first direction DR1 while extending in the second direction DR2.

[0084] In an embodiment, the plurality of pixels PX are electrically connected to the initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, the emission control lines EML1 to EMLn, and the data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected to four scan lines. For example, Figure 7 As shown in , the pixels of the first row can be connected to the first initialization scan line SIL1, the first compensation scan line SCL1, and the first write scan line SWL1 and the second write scan line SWL2. For example, the pixels of the second row can be connected to the second initialization scan line SIL2, the second compensation scan line SCL2, and the second write scan line SWL2 and the third write scan line SWL3. However, the number of scan lines connected to each pixel PX is not limited thereto, and the number of scan lines connected to each pixel PX may vary. In another embodiment, each of the plurality of pixels PX may be electrically connected to five scan lines. In this case, the display panel DP may further include a black scan line.

[0085] In an embodiment, the scan driver 300 and the light emitting driver 350 may be disposed in the non-active area NAA of the display panel DP. In response to the second driving control signal SCS, the scan driver 300 may output an initialization scan signal to the initialization scan lines SIL1 to SILn, output a compensation scan signal to the compensation scan lines SCL1 to SCLn, and output a write scan signal to the write scan lines SWL1 to SWLn+1.

[0086] In an embodiment, the light emitting driver 350 receives a third driving control signal ECS from the driving controller 100. The light emitting driver 350 may output a light emitting control signal to the light emitting control lines EML1 to EMLn in response to the third driving control signal ECS. In another embodiment, the scan driver 300 may be connected to the light emitting control lines EML1 to EMLn. In this case, the scan driver 300 may output a light emitting control signal to the light emitting control lines EML1 to EMLn.

[0087] In an embodiment, each of the pixels PX may include a light emitting element ED (see Figure 8 ) and a pixel circuit portion PXC for controlling the light emitting element ED (see Figure 8 ) to emit light from the light emitting element ED. The pixel circuit portion PXC may include a plurality of transistors and capacitors. The scan driver 300 and the light emitting driver 350 may include transistors formed by the same process as the pixel circuit portion PXC.

[0088] In an embodiment, each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage AINT from the voltage generator 400 .

[0089] In an embodiment, the display device DD may operate in a normal frequency mode (or first mode) in which a frame rate is fixed or a variable frequency mode (or second mode) in which a frame rate is varied.

[0090] Figure 8 is a circuit diagram of a pixel according to an embodiment, and Fig.9A , Fig. 9B and Fig. 9C is a timing chart showing the operation of the display device according to the embodiment.

[0091] In an embodiment, Figure 8 Shown in Figure 7 An equivalent circuit diagram of one pixel PXij among the plurality of pixels PX is shown in . Because each of the plurality of pixels PX has the same circuit structure, only the circuit structure of the pixel PXij will be representatively described in the following description and details of the remaining pixels PX will be omitted.

[0092] In the examples and with reference to Figure 8 , the pixels PXij are connected to the data lines DL1 to DLm (see Figure 7 ) and the i-th data line DLi (hereinafter, data line DLi) and the light emission control lines EML1 to EMLn (see Figure 7 ) in the j-th emission control line EMLj (hereinafter, emission control line EMLj). The pixel PXij is connected to the initialization scan lines SIL1 to SILn (see Figure 7 ) in the j-th initialization scanning line SILj (hereinafter, the initialization scanning line SILj), the writing scanning lines SWL1 to SWLn+1 (see Figure 7 ) in the j-th write scan line SWLj (hereinafter, write scan line SWLj) and the j-th black scan line SBLj (hereinafter, black scan line SBLj). In addition, the pixel PXij is connected to the compensation scan lines SCL1 to SCLn (see Figure 7 ). In another embodiment, the pixel PXij may be connected to the (j+1)th writing scan line instead of the jth black scan line SBLj.

[0093] In an embodiment, the pixel PXij includes a light emitting element ED and a pixel circuit portion PXC. The light emitting element ED may include a light emitting diode. The light emitting diode may include an organic light emitting material, an inorganic light emitting material, a quantum dot or a quantum rod as a light emitting layer.

[0094] In an embodiment, the pixel circuit portion PXC includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 and a capacitor Cst. Each of the first transistor T1 to the seventh transistor T7 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. Some of the first transistor T1 to the seventh transistor T7 may be P-type transistors, and the remaining transistors of the first transistor T1 to the seventh transistor T7 may be N-type transistors. For example, the first transistor T1, the second transistor T2, and the fifth transistor T5 to the seventh transistor T7 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors including an oxide semiconductor used as a semiconductor layer. However, the configuration of the pixel circuit portion PXC according to the present invention is not limited to Figure 8 The embodiment shown in . Figure 8The pixel circuit portion PXC shown in the figure is provided for illustration purposes only, and the configuration of the pixel circuit portion PX may be modified and implemented. For example, in an embodiment, all transistors from the first transistor T1 to the seventh transistor T7 may be P-type transistors or N-type transistors. In addition, the number of transistors and the number of capacitors included in the pixel circuit portion PXC are not particularly limited and may vary.

[0095] In an embodiment, the initialization scan line SILj, the compensation scan line SCLj, the write scan line SWLj, the black scan line SBLj and the light emission control line EMLj may respectively transmit the jth initialization scan signal SIj (hereinafter, the initialization scan signal SIj), the jth compensation scan signal SCj (hereinafter, the compensation scan signal SCj), the jth write scan signal SWj (hereinafter, the write scan signal SWj), the jth black scan signal SBj (hereinafter, the black scan signal SBj) and the jth light emission control signal EMj (hereinafter, the light emission control signal EMj) to the pixel PXij. The data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have the same value as that input to the display device DD (see Figure 7 ) of the image signal RGB (see Figure 7 ). The first driving voltage line VL1, the second driving voltage line VL2, the third driving voltage line VL3 and the fourth driving voltage line VL4 can transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT and the second initialization voltage AINT to the pixel PXij, respectively.

[0096] In an embodiment, the first transistor T1 includes a first electrode connected to the first driving voltage line VL1 through the fifth transistor T5, a second electrode electrically connected to the anode of the light emitting element ED through the sixth transistor T6, and a gate electrode connected to one terminal of the capacitor Cst. The first transistor T1 can receive the i-th data signal Di received through the data line DLi and supply the driving current Id to the light emitting element ED according to the switching operation of the second transistor T2.

[0097] In an embodiment, the second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the write scan line SWLj. The second transistor T2 can be turned on in response to a write scan signal SWj received through the write scan line SWLj to transmit the i-th data signal Di received through the data line DLi to the first electrode of the first transistor T1.

[0098] In an embodiment, the third transistor T3 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the gate electrode of the first transistor T1, and a gate electrode connected to the scan line SCLj. The third transistor T3 can be turned on in response to a compensation scan signal SCj received through the compensation scan line SCLj to connect the gate electrode of the first transistor T1 to the second electrode of the first transistor T1, so that the first transistor T1 is diode-connected.

[0099] In an embodiment, the fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to a third driving voltage line VL3 for transmitting a first initialization voltage VINT, and a gate electrode connected to an initialization scan line SILj. The fourth transistor T4 may be turned on in response to an initialization scan signal SIj received through the initialization scan line SILj to perform an initialization operation for transmitting the first initialization voltage VINT1 to the gate electrode of the first transistor T1 to initialize the voltage of the gate electrode of the first transistor T1.

[0100] In an embodiment, the fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the light emitting control line EMLj.

[0101] In an embodiment, the sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting element ED, and a gate electrode connected to the light emitting control line EMLj.

[0102] In an embodiment, the fifth transistor T5 and the sixth transistor T6 may be turned on simultaneously in response to the emission control signal EMj received through the emission control line EMLj. The first driving voltage ELVDD received through the turned-on fifth transistor T5 may be compensated by the diode-connected first transistor T1 and transmitted to the light emitting element ED.

[0103] In an embodiment, the seventh transistor T7 includes a first electrode connected to the second electrode of the first transistor T6, a second electrode connected to the fourth driving voltage line VL4 for transmitting the second initialization voltage AINT, and a gate electrode connected to the black scan line SBLj.

[0104] In the embodiment, as described above, one terminal of the capacitor Cst is connected to the gate electrode of the first transistor T1, and the other terminal of the capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS.

[0105] In the examples and with reference to Figure 8 and Fig.9A , display panel DP (see Figure 7 ) can display an image for a first frame interval DF1 corresponding to a first frame rate. The first frame interval DF1 may include "k" reference cycle intervals (hereinafter, a first reference cycle interval RCP1, a second reference cycle interval RCP2, and a third reference cycle interval RCP3) and a compensation cycle interval CCP. In this case, "k" may be an integer equal to or greater than "1". Although Fig.9A It is shown that "k" is "3", but "k" may vary depending on the frame rate. Each of the first reference cycle interval RCP1, the second reference cycle interval RCP2, and the third reference cycle interval RCP3 has a reference period RT (see Figure 3A ), and the compensation cycle interval has a compensation period CT1 (see Figure 3B ). The light-emitting control signal EMj supplied from the light-emitting control line EMLj may include a first light-emitting interval EP1 and a first non-light-emitting interval NEP1 in each of the first reference cycle interval RCP1, the second reference cycle interval RCP2, and the third reference cycle interval RCP3. According to an embodiment, the first light-emitting interval EP1 may be a low-level interval, and the first non-light-emitting interval NEP1 may be a high-level interval. The first non-light-emitting interval NEP1 of the light-emitting control signal EMj may overlap with the first activation interval AP1, the second activation interval AP2, the third activation interval AP3, and the fourth activation interval AP4 in the first reference cycle interval RCP1, respectively. The first light-emitting interval EP1 of the light-emitting control signal EMj of the first reference cycle interval RCP1 may be in a non-overlapping state with the first activation interval AP1, the second activation interval AP2, the third activation interval AP3, and the fourth activation interval AP4, respectively.

[0106] In an embodiment, a plurality of scan signals SIj, SCj, SWj, and SBj may be activated during a first non-luminous interval NEP1 of a first reference cycle interval RCP1. In more detail, the initialization scan signal SIj includes a first activation interval AP1 having a high level in the first non-luminous interval NEP1 of the first reference cycle interval RCP1, and the compensation scan signal SCj includes a second activation interval AP2 having a high level in the first non-luminous interval NEP1 of the first reference cycle interval RCP1. The write scan signal SWj includes a third activation interval AP3 having a low level in the first non-luminous interval NEP1 of the first reference cycle interval RCP1, and the black scan signal SBj includes a fourth activation interval AP4 having a low level in the first non-luminous interval NEP1 of the first reference cycle interval RCP1. According to an embodiment, in addition to the first non-luminous interval NEP1 of the first reference cycle interval RCP1, the black scan signal SBj may further include a fourth activation interval AP4 having a low level in the second reference cycle interval RCP2 and the third reference cycle interval RCP3 and the compensation cycle interval CCP. In other words, some scan signals Slj, SCi, and SWj among the plurality of scan signals SIj, SCj, SWj, and SBj may have a frequency lower than that of the light emitting control signal EMj, and the remaining scan signals SBj may have the same frequency as that of the light emitting control signal EMj. In another embodiment, the plurality of scan signals SIj, SCj, SWj, and SBj may have the same frequency as that of the light emitting control signal EMj.

[0107] In an embodiment, when the initialization scan signal SIj having a high level is provided through the initialization scan line SILj during the first active interval AP1, the fourth transistor T4 is turned on in response to the initialization scan signal SIj having a high level. The first initialization voltage VINT is transmitted to the gate electrode of the first transistor T1 through the turned-on fourth transistor T4, and the gate electrode of the first transistor T1 is initialized by the first initialization voltage VIN.

[0108] In an embodiment, when the compensation scan signal SCj having a high level is supplied through the compensation scan line SCLj during the second activation interval AP2, the third transistor T3 is turned on. During the second activation interval AP2, the first transistor T1 is diode-connected by the third transistor T3 that is turned on and forward biased. The second activation interval AP2 of the compensation scan signal SCj may be in a non-overlapping state with the first activation interval AP1 of the initialization scan signal SIj. In addition, the first activation interval AP1 of the initialization scan signal SIj leads the second activation interval AP2 of the compensation scan signal SCj.

[0109] According to an embodiment, the second activation interval AP2 of the compensation scan signal SCj is defined as an interval in which the compensation scan signal SCj has a high level, and the first activation interval AP1 of the initialization scan signal SIj is defined as an interval in which the initialization scan signal SIj has a high level. When the third transistor T3 and the fourth transistor T4 are P-type transistors, the second activation interval AP2 of the compensation scan signal SCj is defined as an interval in which the compensation scan signal SCj has a low level, and the first activation interval AP1 of the initialization scan signal SIj is defined as an interval in which the initialization scan signal SIj has a low level.

[0110] In an embodiment, the second activation interval AP2 may overlap with the third activation interval AP3 in which the write scan signal SWj having a low level is generated. The second transistor T2 is turned on by the write scan signal SWj having a low level for the third activation interval AP3. However, a compensation voltage (Di-Vth) obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the data signal Di supplied from the data line DLi is applied to the gate electrode of the first transistor T1. In other words, the potential of the gate electrode of the first transistor T1 may be the compensation voltage (Di-Vth).

[0111] In an embodiment, the first driving voltage ELVDD and the compensation voltage (Di-Vth) may be applied to opposite ends of the capacitor Cst, and charges corresponding to a difference in voltage between the opposite ends may be stored in the capacitor Cst.

[0112] In an embodiment, the seventh transistor T7 may receive a low-level black scan signal SBj through the black scan line SBLj and may be turned on during the fourth active interval AP4. A portion of the driving current Id may be discharged as a bypass current Ibp through the seventh transistor T7.

[0113] In an embodiment, when the pixel PXij displays a black image, and when the light emitting element ED emits light, even if the minimum driving current flows through the first transistor T1 as the driving current Id, the pixel PXij is difficult to display a black image normally. Therefore, according to an embodiment, the seventh transistor T7 in the pixel PXij can allocate the part of the minimum driving current of the first transistor T1 used as the bypass current Ibp to a current path other than the current path toward the light emitting element ED. In this case, the minimum driving current of the first transistor T1 refers to the current flowing to the first transistor T1 when the gate-source voltage (Vgs) in the first transistor T1 is lower than the threshold voltage (Vth) when the first transistor T1 is turned off. As described above, when the first transistor T1 is turned off, the minimum driving current (for example, a current of 10pA or less) flowing to the first transistor T1 is transmitted to the light emitting element ED to display an image of a black grayscale. When the pixel PXij displays a black image, the bypass current Ibp has a relatively large effect on the minimum driving current Id, while when an image such as a normal image or a white image is displayed, the bypass current Ibp has a relatively small effect on the driving current Id. Therefore, when a black image is displayed, a current (i.e., a light-emitting current Ied) reduced from the driving current Id by the amount of the bypass current Ibp flowing out of the seventh transistor T7 is provided to the light-emitting element ED to firmly express the black image. Therefore, the pixel PXij can use the seventh transistor T7 to realize an accurate black grayscale image. Therefore, the contrast can be improved.

[0114] In the embodiment, the fifth transistor T5 and the sixth transistor T6 are turned on by the light emitting control signal EMj having a low level. Thereafter, a driving current Id is generated due to a voltage difference between a gate voltage of the gate electrode of the first transistor T1 and the first driving voltage ELVDD, and the driving current Id is supplied to the light emitting element ED through the sixth transistor T6. Therefore, during the first light emitting interval EP1, the light emitting current Ied flows through the light emitting element ED. Therefore, light having a brightness corresponding to the light emitting current Ied can be output from the light emitting element ED.

[0115] In the examples and with reference to Figure 8 and Fig. 9B , display panel DP (see Figure 7 ) may display an image during a second frame interval DF2 corresponding to a second frame rate. The second frame interval DF2 may include "k" first adjustment cycle intervals ACP1. In this case, "k" may be an integer equal to or greater than "1". Although Fig. 9B The case where "k" is 4 is shown, but "k" may vary depending on the frame rate. Each of the first adjustment cycle sections ACP1 has a period of 4 equal to the reference period RT (see Figure 3A ) Different first adjustment period AT1 (see Figure 3A). The light emitting control signal EMj supplied from the light emitting control line EMLj may include a first adjustment light emitting interval EPa and a first adjustment non-light emitting interval NEPa in each first adjustment cycle interval ACP1. According to an embodiment, the first adjustment light emitting interval EPa may be a low level interval, and the first adjustment non-light emitting interval NEPa may be a high level interval. According to an embodiment, the duration of the first adjustment light emitting interval EPa may be different from the duration of the first light emitting interval EP1.

[0116] In an embodiment, the first adjustment non-luminous interval NEPa of the luminous control signal EMj may overlap with the first activation interval AP1, the second activation interval AP2, the third activation interval AP3 and the fourth activation interval AP4 in at least one of the first adjustment cycle interval ACP1. During the first adjustment cycle interval ACP1, the first adjustment luminous interval EPa of the luminous control signal EMj may be in a non-overlapping state with the first activation interval AP1, the second activation interval AP2, the third activation interval AP3 and the fourth activation interval AP4.

[0117] In the examples and with reference to Figure 8 and Fig. 9C , display panel DP (see Figure 7 ) may display an image for a fourth frame interval DF4 corresponding to a fourth frame rate. The fourth frame interval DF4 may include "k" second adjustment cycle intervals ACP2. In this case, "k" may be an integer equal to or greater than "1". Although Fig. 9C The case where "k" is 4 is shown, but "k" may vary depending on the frame rate. Each of the second adjustment cycle intervals ACP2 has a period corresponding to the reference period RT (see Figure 3A ) Different second adjustment period AT2 (see Figure 3A ). The light emitting control signal EMj supplied through the light emitting control line EMLj may include a second adjustment light emitting interval EPb and a second adjustment non-light emitting interval NEPb in each of the second adjustment cycle intervals ACP2. According to an embodiment, the second adjustment light emitting interval EPb may be a low level interval, and the second adjustment non-light emitting interval NEPb may be a high level interval. According to an embodiment, the duration of the second adjustment light emitting interval EPb may be different from the duration of the first light emitting interval EP1 and the duration of the first adjustment light emitting interval EPa.

[0118] In an embodiment, the second adjustment non-luminous interval NEPb of the light-emitting control signal EMj may overlap with the first activation interval AP1, the second activation interval AP2, the third activation interval AP3, and the fourth activation interval AP4 in at least one of the second adjustment cycle interval ACP2. During the second adjustment cycle interval ACP2, the second adjustment luminous interval EPb of the light-emitting control signal EMj may be in a non-overlapping state with the first activation interval AP1, the second activation interval AP2, the third activation interval AP3, and the fourth activation interval AP4.

[0119] In an embodiment and as described above, from the light emitting driver 350 (see Figure 7 ) varies according to the above difference, thereby improving the problem of image quality degradation caused by the flicker phenomenon in the variable frequency mode.

[0120] Fig.10 is a flowchart illustrating the operation of the display device according to the embodiment.

[0121] In the embodiments, reference Figure 1 , Figure 2 , Figure 3A , Figure 4A and Fig.10 , the driving controller 100 of the display device DD may determine whether the display device DD is operated in the variable frequency mode (S110). As a result of the determination, when the display device DD is operated in the variable frequency mode, the operation of reducing the flicker phenomenon according to the present invention may be performed. When the display device DD is not operated in the variable frequency mode, the operation of reducing the flicker phenomenon may be terminated without performing the flicker reduction operation.

[0122] In an embodiment, when performing an operation to reduce the flicker phenomenon, first, the driving controller 100 may compare the display periods DT1 to DT5 with an integer multiple of the reference period RT (S120). The driving controller 100 may compare the display periods DT1 to DT5 with the reference period RT in each frame interval. When the display periods DT1 to DT5 are equal to the reference period RT according to the comparison result, the light emitting period (AID period) may maintain the reference period RT (S130).

[0123] However, in an embodiment, when each of the display periods DT1 to DT5 is different from the reference period RT based on the comparison result, the driving controller 100 may calculate the difference between each of the display periods DT1 to DT5 and an integer multiple of the reference period RT (S140). For example, when the first display period DT1 is different from an integer multiple (4×RT) of the reference period RT in the first frame interval DF1, the driving controller 100 may calculate the difference (i.e., the first difference d1) between the first display period DT1 and the integer multiple (e.g., 4×RT) of the reference period RT.

[0124] In an embodiment, the driving controller 100 may set the compensation periods CT1 and CT2 and the adjustment periods AT1 and AT2 of the light emitting period (AID period) based on the difference between each of the display periods DT1 to DT5 and the integer multiples of the reference period RT (S150). For example, when a first difference d1 is generated between the first display period DT1 and the integer multiples of the reference period RT in the first frame interval DF1, the driving controller 100 may adjust the last reference period interval corresponding to the first frame interval DF1 using a compensation period interval having a compensation period CT1 greater than the reference period RT by the first difference d1.

[0125] In addition, in an embodiment, the driving controller 100 may change the period of the light-emitting period (AID period) in the next frame interval based on the difference. For example, the driving controller 100 may adjust the light-emitting period (AID period) to include an adjustment period interval having the first adjustment period AT1 in the second frame interval DF2. The second display period DT2 of the second frame interval DF2 may be equal to an integer multiple of the first adjustment period AT1 (i.e., 4×AT1).

[0126] In the embodiment and as described above, each of the display periods DT1 to DT5 of the current frame interval is compared with an integer multiple of the reference period RT in each frame interval. When a difference (i.e., a first difference d1) is generated between each of the display periods DT1 to DT5 and an integer multiple (4×RT) of the reference period RT, the reference period RT is changed to the adjustment period AT1 to AT2 based on the difference. Therefore, the time point of terminating the light-emitting cycle (AID cycle) can match the time point of terminating the frame intervals DF1 to DF5. Therefore, even when the display periods DT1 to DT5 do not match the integer multiples of the reference period RT, the flicker phenomenon can be prevented or reduced.

[0127] Fig.11 is a flowchart illustrating the operation of the display device according to the embodiment.

[0128] In the examples and with reference to Figure 1 , Figure 2 , Fig. 6A , Figure 6B and Fig.11 , the driving controller 100 of the display device DD may determine whether the display device DD is operated in the variable frequency mode (S210). When the display device DD is operated in the variable frequency mode based on the determination result, according to the present invention, an operation of reducing the flicker phenomenon is performed. When the display device DD is not operated in the variable frequency mode based on the determination result, according to the present invention, the operation of reducing the flicker phenomenon may be terminated and not performed.

[0129] In an embodiment, when performing an operation to reduce a flicker phenomenon, first, the driving controller 100 may compare the display periods DT1 to DT5 with an integer multiple of a reference period RT (S220). The driving controller 100 may compare the display periods DT1 to DT5 with an integer multiple of a reference period RT in each frame interval. When each of the display periods DT1 to DT5 is equal to an integer multiple of the reference period RT, the driving controller 100 may output image data of the relevant frame interval during the next frame interval (S230). In other words, when the first display period DT1 is equal to an integer multiple of the reference period RT, the driving controller 100 may output the second image data DATA_2 during the second frame interval DF2.

[0130] However, in an embodiment, when the display periods DT1 to DT5 are different from the integer multiples of the reference period RT, the drive controller 100 may output the black image data DATA_B during the next frame interval, or may output the image data of the previous frame interval (S240). For example, when the first display period DT1 is not equal to the integer multiples of the reference period RT, the drive controller 100 may output the black image data DATA_B instead of the second image data DATA_2 during the second frame interval DF2. In another embodiment, when the first display period DT1 is not equal to the integer multiples of the reference period RT, the drive controller 100 may output the first image data DATA_1 corresponding to the first frame interval DF1 instead of the second image data DATA_2 during the second frame interval DF2.

[0131] In an embodiment, even if the light emitting period (AID period) is maintained (kept) in an activated state during the second frame interval DF2 to the fourth frame interval DF4 in which the black image data DATA_B is output, the display panel DP may display a black image. The driving controller 100 may output the black image data DATA_B until the display periods DT1 to DT5 are equal to an integer multiple of the reference period RT.

[0132] In an embodiment, even if the first image data DATA_1 is output for the second to fourth frame intervals DF2 to DF4 , since the light emitting period (AID period) is maintained (held) in an inactive state, the display panel DP may display a black image or may maintain a previous image.

[0133] In the embodiment and as described above, the display period of the current frame interval is compared with an integer multiple of the reference period RT in each frame interval. When there is a difference between the display period of the current frame interval and the integer multiple of the reference period RT, since the light-emitting period (AID period) is maintained in a specific state, the flicker phenomenon can be prevented or reduced.

[0134] According to an embodiment, the display period of the current frame interval is compared with an integer multiple of the reference period in each frame interval. When there is a difference between the display period of the current frame interval and the integer multiple of the reference period, the last reference cycle interval can be changed to a compensation cycle interval, and the compensation cycle interval has a compensation period increased by the difference from the reference period. Therefore, the time point of terminating the compensation cycle interval can match the time point of terminating the current frame interval. Therefore, the flicker phenomenon caused when the display period does not match the integer multiple of the reference period can be eliminated or reduced.

[0135] In addition, in an embodiment, the reference cycle interval of the next frame interval is changed to an adjustment cycle interval having an adjustment period according to the difference, thereby preventing or reducing a flicker phenomenon.

[0136] Although the embodiments of the present invention are described for illustrative purposes, it will be appreciated by those skilled in the art that various modifications and substitutions are possible without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention is not limited to the detailed description of this specification, but is determined by the appended claims.

[0137] Although the present invention has been described with reference to embodiments of the present invention, it is obvious to those skilled in the art that various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. In addition, embodiments or parts of embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A display device, wherein: The display device comprises: a display panel including a plurality of pixels emitting light in response to a data signal; and a display driver circuit configured to provide the data signal to the display panel, Wherein, the display driver circuit comprises: a drive controller configured to receive an image signal at a variable frame rate and output image data obtained by converting the image signal in response to a display synchronization signal; and a data driver configured to convert the image data into the data signal and output the data signal, Wherein, the drive controller comprises: a data conversion block that converts the image signal into the image data and outputs the image data for a current frame interval determined based on the display synchronization signal; and A light emitting control block, wherein the light emitting control block is configured as follows: Comparing a reference period of a reference cycle interval of a preset light emitting cycle of the display panel with a display period of the current frame interval; changing the reference period to an adjustment period according to the comparison result; and A driving control signal is outputted, wherein the driving control signal is used to control the display panel to emit light during an adjustment cycle interval in which the display panel has the adjustment period starting from a start time point of a next frame interval.

2. The display device according to claim 1, wherein: The light emitting control block comprises: a calculation unit that, when the display period is different from the integer multiple of the reference period, calculates a difference between the integer multiple of the reference period and the display period; and Setting unit: setting the duty cycle of the adjustment period and the adjustment cycle interval based on the difference; and The driving control signal corresponding to the adjustment period and the duty ratio is output.

3. The display device according to claim 2, wherein: The duty cycle of the adjustment cycle interval is different from the duty cycle of the reference cycle interval.

4. The display device according to claim 1, wherein: The current frame interval corresponds to k reference period intervals and one compensation period interval that appear sequentially, where k is an integer equal to or greater than 1, and The duty cycle of the adjustment period interval is different from the duty cycle of each of the k reference period intervals.

5. The display device according to claim 4, wherein: The display period varies according to the variable frame rate, wherein the display period is different from an integer multiple of the reference period, and The difference between the compensation period of the compensation cycle interval and the reference period corresponds to the difference between the integer multiple of the reference period and the display period.

6. The display device according to claim 5, wherein: Each of the k reference cycle intervals includes: a first non-luminous interval and a first luminous interval, The compensation period includes a second non-luminous interval and a second luminous interval, and The difference between the duration of the second light-emitting interval and the duration of the first light-emitting interval corresponds to the difference between the integer multiple of the reference period and the display period.

7. The display device according to claim 5, wherein: Each of the k reference cycle intervals includes: a first non-luminous interval and a first luminous interval, The compensation period includes a second non-luminous interval, a second luminous interval and a third non-luminous interval, and The duration of the third non-luminescent interval corresponds to the difference between the integer multiple of the reference period and the display period.

8. The display device according to claim 1, wherein: The display device further includes: a scan driver, the scan driver outputting a scan signal to the display panel; and a light emitting driver, wherein the light emitting driver outputs a light emitting control signal to the display panel, Wherein, the light emitting driver is configured as follows: The driving control signal is received from the light emitting control block to determine the light emitting period of the display panel.

9. The display device according to claim 1, wherein: The drive controller also includes: a variable frequency block that calculates the display period of the current frame interval based on the variable frame rate; and A brightness control block is configured to set a reference duty cycle of the reference cycle interval based on a dimming signal.

10. The display device according to claim 9, wherein: The light emitting control block is configured as follows: receiving information related to the display period from the variable frequency block; and The adjustment cycle interval is controlled to have an adjustment duty ratio different from the reference duty ratio of the reference cycle interval.

Images