Display device, display panel and display driving method

Abstract

The invention relates to a display device, a display panel and a display driving method. Disclosed herein is a display device including: a display panel in which a light emitting element, a driving transistor configured to supply a driving current to the light emitting element using a driving voltage, and a plurality of switching transistors configured to control driving of the driving transistor are provided; a gate driving circuit configured to provide a plurality of scanning signals to the display panel through a plurality of gate lines; a light emission driving circuit configured to provide a plurality of light emission signals to the display panel through the plurality of light emission signal lines; a data driving circuit configured to provide a data voltage to the display panel; and a timing controller configured to: control a driving current applied to the driving transistor during a first light emission control period after a bias voltage is applied to the driving transistor in a low speed mode in which the display panel operates at a low driving frequency; and control a driving current applied to the light emitting element through the driving transistor during the second light emission control period.

Description

[0001] This application is a divisional application of patent application 202211355822.2, whose application date is November 1, 2022 and whose invention name is "Display device, display panel and display driving method".

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to Korean Patent Application No. 10-2021-0153851 filed on November 10, 2021, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0004] The present disclosure relates to a display device, a display panel and a display driving method, and more particularly, to a display device, a display panel and a display driving method capable of reducing image quality defects caused by voltage fluctuations of a light-emitting element during an operation process at a low driving frequency. Background Art

[0005] With the development of the information society, various demands on display devices that display images have been increasing, and various types of display devices, such as liquid crystal display (LCD) devices and organic light emitting display devices, have been put into use.

[0006] Among these display devices, an organic light emitting diode (OLED) device employs an organic light emitting diode that emits light by itself, and thus has advantages of high response speed, contrast, light emitting efficiency, brightness, and viewing angle.

[0007] The OLED device includes an organic light emitting diode arranged on each of a plurality of sub-pixels (a plurality of sub-pixels are arranged on a display panel), and controls a current flowing in the organic light emitting diode to allow the organic light emitting diode to emit light, so that the OLED device can control the brightness of each sub-pixel, thereby displaying an image.

[0008] In this case, the image data provided to the display device may be a still image or a moving image that changes at a predetermined speed, and the moving image may correspond to various types of images such as sports images, movies, and game images.

[0009] In addition, the display device can be switched to various driving modes according to a user's input or an operation state.

[0010] At the same time, the display device can change the driving frequency according to the type of input image data or the driving mode. During operation at a low driving frequency, there will be a problem that image quality degradation, such as black excitation, occurs because of voltage fluctuations of the light emitting element. Summary of the invention

[0011] Accordingly, the inventors of the present invention have invented a display device, a display panel, and a display driving method capable of reducing image quality defects occurring during operation at a low driving frequency.

[0012] One aspect of the present disclosure is to provide a display device, a display panel, and a display driving method capable of reducing image quality defects (eg, black excitation) by stably maintaining a voltage of a light emitting element in a time section operating at a low driving frequency.

[0013] Another aspect of the present disclosure is to provide a display device, a display panel, and a display driving method capable of reducing image quality defects (eg, black excitation) by applying timing control of a light emitting signal in a time section operating at a low driving frequency.

[0014] Problems to be solved by the present disclosure to be described below are not limited to the above-mentioned problems, and other problems that are not described can be clearly understood by those skilled in the art through the following description.

[0015] In one aspect, an embodiment of the present disclosure may provide a display device capable of operating in a low-speed mode at a low driving frequency and in a high-speed mode at a high driving frequency, comprising: a display panel in which a light-emitting element, a driving transistor configured to provide a driving current to the light-emitting element using a driving voltage, and a plurality of switching transistors configured to control the driving of the driving transistor; a gate driving circuit configured to provide a plurality of scanning signals to the display panel through a plurality of gate lines; a light-emitting driving circuit configured to provide a plurality of light-emitting signals to the display panel through a plurality of light-emitting signal lines; a data driving circuit configured to provide a data voltage to the display panel; and a timing controller configured to: in a low-speed mode in which the display panel operates at a low driving frequency, control the driving current to be applied to the driving transistor during a first light-emitting control time period after a bias voltage is applied to the driving transistor; and control the driving current to be applied to the light-emitting element through the driving transistor during a second light-emitting control time period.

[0016] In the display device, the plurality of switching transistors may include: a first switching transistor having a gate electrode to which a first scanning signal is applied, a drain electrode connected to the gate electrode of a driving transistor and a storage capacitor, and a source electrode connected to the source electrode of the driving transistor; a second switching transistor having a gate electrode to which a second scanning signal is applied, a drain electrode to which a data voltage is applied, and a source electrode connected to the drain electrode of the driving transistor; a third switching transistor having a gate electrode to which a first light-emitting signal is applied, a drain electrode to which a driving voltage is applied, and a source electrode connected to the drain electrode of the driving transistor; a fourth switching transistor having a gate electrode to which a second light-emitting signal is applied, a drain electrode connected to the source electrode of the driving transistor, and a source electrode connected to the anode electrode of the light-emitting element; a fifth switching transistor having a gate electrode to which a third scanning signal is applied, a drain electrode to which the bias voltage is provided, and a source electrode connected to the source electrode of the driving transistor; and a sixth switching transistor having a gate electrode to which a fourth scanning signal is applied, a drain electrode to which a reset voltage is provided, and a source electrode connected to the anode electrode of the light-emitting element.

[0017] In the display device, the first light emission control period may correspond to a time section in which the third switching transistor is turned on by the first light emission signal in a state in which the fourth switching transistor is turned off.

[0018] In the display device, the first light emission control period may correspond to a time section in which a voltage of a source electrode of the driving transistor is lowered from a level of the bias voltage to a level of the driving voltage.

[0019] In the display device, the second light emission control period may correspond to a time section in which the fourth switching transistor is turned on by the second light emission signal in a state in which the third switching transistor is turned on.

[0020] In the display device, the third switching transistor and the fourth switching transistor are respectively the nth third switching transistor and the nth fourth switching transistor in the nth sub-pixel, where n is a natural number; the second light-emitting signal may correspond to a signal applied to the gate electrode of the fourth switching transistor through the nth light-emitting signal line; and the first light-emitting signal may correspond to a signal applied to the gate electrode of the third switching transistor through the (nX)th light-emitting signal line, where X is a natural number less than n.

[0021] In the display device, the fifth switching transistor is the nth fifth switching transistor in the nth sub-pixel, where n is a natural number; the third scanning signal may correspond to a signal applied to the gate electrode of the fifth switching transistor through the nth gate line; and the fourth scanning signal may also correspond to a signal applied to the gate electrode of the (n+1)th fifth switching transistor in the (n+1)th sub-pixel through the (n+1)th gate line.

[0022] In the display device, the bias voltage may be applied at a level higher than the driving voltage.

[0023] In the display device, the low speed mode may include a refresh frame period in which a data voltage for driving the light emitting element is applied and a skip frame period in which the data voltage is not applied.

[0024] A method for driving a display panel, in which a light-emitting element, a driving transistor configured to provide a driving current to the light-emitting element using a driving voltage, and a plurality of switching transistors configured to control the driving of the driving transistor are provided. The method comprises: switching a first mode of high driving frequency to a second mode of low driving frequency; applying a bias voltage to a source electrode of the driving transistor; applying the driving voltage to the driving transistor in response to a first light-emitting signal during a first light-emitting control time period; applying a reset voltage to an anode electrode of the light-emitting element during the first light-emitting control time period; and providing the driving current to the light-emitting element in response to a second light-emitting signal during a second light-emitting control time period later than the first light-emitting control time period.

[0025] A display panel capable of operating in a low-speed mode at a low driving frequency and a high-speed mode at a high driving frequency, comprising: a light-emitting element; a driving transistor configured to provide a driving current to the light-emitting element using a driving voltage; a first switching transistor having a gate electrode to which a first scanning signal is applied, a drain electrode connected to the gate electrode of the driving transistor and a storage capacitor, and a source electrode connected to the source electrode of the driving transistor; a second switching transistor having a gate electrode to which a second scanning signal is applied, a drain electrode to which a data voltage is applied, and a source electrode connected to the drain electrode of the driving transistor; a third switching transistor having a gate electrode to which a first light-emitting signal is applied, a drain electrode to which a driving voltage is applied, and a source electrode connected to the drain electrode of the driving transistor; a fourth switching transistor having a gate electrode to which a first light-emitting signal is applied, a drain electrode to which a driving voltage is applied, and a source electrode connected to the drain electrode of the driving transistor; a gate electrode to which a second light-emitting signal is applied, a drain electrode connected to the source electrode of the driving transistor, and a source electrode connected to the anode electrode of the light-emitting element; a fifth switching transistor, which has a gate electrode to which a third scan signal is applied, a drain electrode to which the bias voltage is provided, and a source electrode connected to the source electrode of the driving transistor; and a sixth switching transistor, which has a gate electrode to which a fourth scan signal is applied, a drain electrode to which a reset voltage is provided, and a source electrode connected to the anode electrode of the light-emitting element, wherein, in a low-speed mode operating at a low driving frequency, the driving current is applied to the driving transistor during a first light-emitting control time period after the bias voltage is applied to the driving transistor, and during a second light-emitting control time period, the driving current is applied to the light-emitting element through the driving transistor.

[0026] In the display panel, the first light-emitting control time period may be a time period in which the third switching transistor is turned on by the first light-emitting signal when the fourth switching transistor is turned off; and the second light-emitting control time period may be a time period in which the fourth switching transistor is turned on by the second light-emitting signal when the third switching transistor is turned on.

[0027] According to the embodiments of the present disclosure, a display device, a display panel, and a display driving method capable of reducing image quality defects occurring during operation at a low driving frequency can be provided.

[0028] According to the embodiments of the present disclosure, a display device, a display panel, and a display driving method can be provided that are capable of reducing image quality defects (eg, black excitation) by stably maintaining the voltage of a light emitting element during a time period operating at a low driving frequency.

[0029] According to the embodiments of the present disclosure, a display device, a display panel, and a display driving method capable of reducing image quality defects (eg, black excitation) by applying timing control of a light emitting signal in a time section operating at a low driving frequency can be provided.

[0030] The effects of the embodiments disclosed in the present disclosure are not limited to the effects mentioned above. In addition, the embodiments disclosed in the present disclosure may produce other effects not mentioned above, which will be clearly understood by those skilled in the art through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description considered in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a diagram showing a schematic configuration of a display device according to an embodiment of the present disclosure;

[0033] Figure 2 is an exemplary diagram showing a system of a display device according to an embodiment of the present disclosure;

[0034] Figure 3 is a diagram showing an example of a display panel in a display device according to an embodiment of the present disclosure, in which a gate driving circuit and a light emitting driving circuit are implemented as a gate-in-panel (GIP) type;

[0035] Figure 4 is a diagram showing an example of a sub-pixel circuit of a display device according to an embodiment of the present disclosure;

[0036] Figure 5is a schematic diagram showing a driving mode according to a frequency change in a display device according to an embodiment of the present disclosure;

[0037] Figure 6 is a schematic diagram showing driving timing in a second mode of driving at a low driving frequency in a display device according to an embodiment of the present disclosure;

[0038] Figure 7 is a diagram showing the operation of a sub-pixel SP in a bias time section in which a first bias voltage is applied in a refresh frame in a display device according to an embodiment of the present disclosure;

[0039] Figure 8 is a diagram showing a sub-pixel operation in a first light emission control period for controlling a source electrode of a driving transistor to a high potential level of a driving voltage within a refresh frame in a display device according to an embodiment of the present disclosure;

[0040] Fig. 9 is a diagram showing a sub-pixel operation in a second light emission control period in which a driving current is supplied to a light emitting element within a refresh frame in a display device according to an embodiment of the present disclosure;

[0041] Fig.10 is a signal waveform diagram showing a voltage change of an anode electrode of a light emitting element when the levels of a first light emitting signal and a second light emitting signal are simultaneously switched;

[0042] Fig.11 is a signal waveform diagram showing a voltage change of an anode electrode of a light emitting element when a first light emitting signal is converted before a second light emitting signal in a display device according to an embodiment of the present disclosure;

[0043] Fig.12 is a graph showing a luminance change caused by a reset voltage according to driving timings of a first light emitting signal and a second light emitting signal in a display device according to an embodiment of the present disclosure; and

[0044] Fig.13 is a flow chart showing a display driving method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] By referring to the detailed description of the drawings and embodiments, the advantages and features of the present disclosure and their implementation methods will become apparent. The present disclosure should not be understood to be limited to the embodiments set forth herein, and the present disclosure can be embodied in various different forms. On the contrary, these embodiments are provided to make the present disclosure thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. The scope of the present disclosure should be limited by the appended claims.

[0046] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings illustrating exemplary embodiments serve only as examples, and the present disclosure is not limited to the embodiments illustrated in the drawings. The same reference numerals and symbols will be used throughout this article to represent the same or similar parts. In the following description of the present disclosure, if a detailed description of known functions and components incorporated into the present disclosure would make the subject matter of the present disclosure unclear, such detailed description will be omitted. It should be understood that the words "include", "comprise", "have" and any variations thereof used herein are intended to cover non-exclusive inclusions, unless explicitly described to the contrary. The description of a component in the singular form used herein is intended to include a description of the plural form of the component, unless explicitly described to the contrary.

[0047] In the analysis of components, it should be understood that a margin of error is included even in the absence of an explicit description thereof.

[0048] When spatially relative terms such as "on", "above", "below", "under", and "on the side of" are used herein to describe the relationship between one element or component and another element or component, one or more intervening elements or components may be present between the one element or component and the other element or component, unless terms such as "directly" are used.

[0049] When time-relative terms such as "after", "next", "after" and "before" are used to define a time relationship, discontinuities may be included unless the terms "immediately" or "directly" are used.

[0050] In the description of signal transmission, for example, “a signal is transmitted from node A to node B”, the signal may be transmitted from node A to node B via another node unless the word “directly” or “directly” is used.

[0051] In addition, various components may be described herein using words such as "first" and "second". However, it should be understood that these components are not limited by these words. These words are only used to distinguish one element or component from other elements or components. Thus, a first component referred to as "first" hereinafter may be a second component within the spirit of the present disclosure.

[0052] The features of the exemplary embodiments of the present disclosure may be partially or completely coordinated or combined with each other, and may work in conjunction with each other or may be operated according to a variety of technical methods. In addition, each exemplary embodiment may be implemented separately, or may be associated with other embodiments and implemented in conjunction with them.

[0053] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 is a diagram showing a schematic configuration of a display device according to an embodiment of the present disclosure.

[0055] refer to Figure 1 According to an embodiment of the present disclosure, a display device 100 may include: a display panel 110, a plurality of gate lines GL and a plurality of data lines DL connected to the display panel 110, and a plurality of sub-pixels SP arranged in a matrix form in the display panel 110; a gate driving circuit 120 for driving the plurality of gate lines GL; a light emitting driving circuit 122 for driving the plurality of light emitting signal lines EL; a data driving circuit 130 for providing a data voltage through the plurality of data lines DL; a timing controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130; and a power management integrated circuit (IC) 150.

[0056] The display panel 110 displays an image based on the scan signals transmitted from the gate driving circuit 120 through the plurality of gate lines GL and the data voltages transmitted from the data driving circuit 130 through the plurality of data lines DL.

[0057] In the case of a liquid crystal display (LCD) device, the display panel 110 includes a liquid crystal layer formed between two substrates and may be operated in any known mode, such as a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in-plane switching (IPS) mode, or a fringe field switching (FFS) mode. Meanwhile, in the case of an organic light emitting display device, the display panel 110 may be implemented in a top emission method, a bottom emission method, or a dual emission method.

[0058] In the display panel 110, a plurality of pixels may be arranged in a matrix form, each pixel may be formed by sub-pixels SP having different colors (e.g., white sub-pixel, red sub-pixel, green sub-pixel, and blue sub-pixel), and each sub-pixel may be defined by a plurality of data lines DL and a plurality of gate lines GL.

[0059] One sub-pixel SP may be formed in an area where the data line DL and the gate line GL intersect, and one sub-pixel SP may include a plurality of thin film transistors (TFTs) for driving the sub-pixel SP, a light emitting element (e.g., an organic light emitting diode (OLED)) for charging a data voltage, and a storage capacitor electrically connected to the light emitting element and configured to maintain a voltage.

[0060] For example, when a display device 100 having a resolution of 2,160×3,840 is formed of four sub-pixels SP, namely, white (W) sub-pixels, red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, since 2,160 gate lines GL and 3,840 data lines DL are connected to each of the four sub-pixels (WRGB), a total of 3,840×4=15,360 data lines DL may be provided, and the sub-pixels SP may be disposed at the intersection of the gate lines GL and the data lines DL.

[0061] The gate driving circuit 120 is controlled by the timing controller 140 and sequentially outputs scanning signals to the plurality of gate lines GL provided in the display panel 110 to control driving timings of the plurality of sub-pixels SP.

[0062] In the display panel 100 having a resolution of 2,160×3,840, the case where the scan signal is sequentially output from the first gate line to the 2,160th gate line for 2,160 gate lines GL may be referred to as 2,160-phase driving. Alternatively, the case where the scan signal is sequentially output from the first gate line to the fourth gate line, and then the scan signal is sequentially output from the fifth gate line to the eighth gate line, the case where the scan signal is sequentially output in units of four gate lines GL may be referred to as four-phase driving. That is, the case where the scan signal is sequentially output for every N gate lines GL may be referred to as N-phase driving.

[0063] In this case, the gate driving circuit 120 may include one or more gate driving integrated circuits GDIC, and according to the driving method, the gate driving circuit 120 may be located only on one side of the display panel 110 or may be located on both sides of the display panel 110. Alternatively, the gate driving circuit 120 may be embedded in a bezel area of ​​the display panel 110, thereby being implemented in the form of a gate in panel (GIP).

[0064] Here, although an example is shown in which the gate driving circuit 120 is located on the left side of the display panel 110 and the light emitting driving circuit 122 is located on the right side of the display panel 110, the gate driving circuit 120 and the light emitting driving circuit 122 may be located at the same position.

[0065] The light emission driving circuit 122 outputs a light emission signal EM under the control of the timing controller 140 , and provides the light emission signal EM to the display panel 110 through the light emission signal line EL.

[0066] The light emitting driving circuit 122 may sequentially provide the light emitting signal EM to the light emitting signal line EL by shifting the light emitting signal EM using a shift register. In this case, the light emitting driving circuit 122 repeatedly triggers the light emitting signal EM during the image driving period under the control of the timing controller 140, thereby driving the display panel 110 at a predetermined duty cycle, for example, a duty cycle of 50%.

[0067] In this case, the light emitting driving circuit 122 may include one or more light emitting control circuits ECC, and according to a driving method, the light emitting driving circuit 122 may be located only on one side of the display panel 110 or may be located on both sides of the display panel 110. The light emitting driving circuit 122 may be directly formed on the substrate of the display panel 110 together with the gate driving circuit 120 through a GIP process.

[0068] One frame period can be divided into a writing time section, in which a data voltage is applied to each sub-pixel SP and recorded, and a light-emitting time section after the writing time section, in which the sub-pixel SP emits light at a predetermined duty ratio according to the light-emitting signal EM. Generally speaking, the light-emitting signal EM allows the sub-pixel SP to emit light at a duty ratio of 50% or less during the light-emitting time section. Since the writing time section is only about one horizontal period 1H, most of one frame period corresponds to the light-emitting time section.

[0069] The sub-pixel SP charges the data voltage in the storage capacitor during the writing time section, and the sub-pixel SP is repeatedly turned on and off according to the light emitting signal EM. That is, the sub-pixel SP is repeatedly turned on and off within one frame period, thereby emitting light at a duty ratio of 50% or less, thereby repeatedly turning on / off.

[0070] As described above, the subpixel SP emits light due to the voltage charged at the storage capacitor after being turned off, and thus during one frame period, after the writing time section, the subpixel SP can display data at the same brightness during one frame period at a duty ratio of 50% or less without receiving an additional data voltage.

[0071] The data driving circuit 130 receives the image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, the data voltage is output to each data line DL according to the timing of applying the scanning signal through the gate line GL, and each sub-pixel SP connected to the data line DL displays a light emitting signal having a brightness corresponding to the data voltage according to the timing of applying the light emitting signal EM.

[0072] Similarly, the data driving circuit 130 may include one or more source driver integrated circuits SDIC, and the source driver integrated circuits SDIC may be connected to bonding pads of the display panel 110, or may be directly set on the display panel 110 using a tape automated bonding (TAB) method or a chip on glass (COG) method.

[0073] In some cases, each source driver integrated circuit SDIC may be integrated and disposed on the display panel 110. In addition, each source driver integrated circuit SDIC may be implemented in accordance with a chip on film (COF) method. In this case, each source driver integrated circuit SDIC may be mounted on a circuit film and may be electrically connected to the data line DL of the display panel 110 through the circuit film.

[0074] The timing controller 140 provides various control signals to the gate driving circuit 120, the light emitting driving circuit 122, and the data driving circuit 130, and controls the operations of the gate driving circuit 120, the light emitting driving circuit 122, and the data driving circuit 130. That is, the timing controller 140 controls the output of the scanning signal of the gate driving circuit 120 and the output of the light emitting signal EM of the light emitting driving circuit 122 according to the timing implemented in each frame. On the other hand, the timing controller 140 transmits the image data DATA received from the host system 200 to the data driving circuit 130.

[0075] In this case, the timing controller 140 receives various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK from the external host system 200 in addition to the image data DATA.

[0076] The host system 200 may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device system.

[0077] Accordingly, the timing controller 140 generates control signals using various timing signals received from the host system 200 , and transmits the control signals to the gate driving circuit 120 , the light emitting driving circuit 122 , and the data driving circuit 130 .

[0078] For example, in order to control the gate drive circuit 120, the timing controller 140 outputs various gate control signals including a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE. Here, the gate start pulse GSP controls the timing at which one or more gate drive integrated circuits GDIC constituting the gate drive circuit 120 start to operate. In addition, the gate clock GCLK is a clock signal that is commonly input to the one or more gate drive integrated circuits GDIC and controls the shift timing of the scan signal. In addition, the gate output enable signal GOE specifies the timing information of the one or more gate drive integrated circuits GDIC.

[0079] In addition, in order to control the light-emitting driving circuit 122, the timing controller 140 outputs various light-emitting signals including a light-emitting start pulse ESP, a light-emitting clock ECLK, and a light-emitting output enable signal EOE. Here, the light-emitting start pulse ESP controls the timing at which one or more light-emitting control circuits ECC constituting the light-emitting driving circuit 122 start to operate. In addition, the light-emitting clock ECLK is a clock signal that is commonly input to the one or more light-emitting control circuits ECC and controls the shift timing of the light-emitting signal. In addition, the light-emitting output enable signal EOE specifies the timing information of the one or more light-emitting control circuits ECC.

[0080] In addition, in order to control the data driving circuit 130, the timing controller 140 outputs various data control signals including a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE. Here, the source start pulse SSP controls the timing at which one or more source driver integrated circuits SDIC constituting the data driving circuit 130 start to operate. The source sampling clock SCLK is a clock signal that controls the timing of data sampling in the source driver integrated circuit SDIC. The source output enable signal SOE controls the output timing of the data driving circuit 130.

[0081] The display device 100 may include a power management integrated circuit (PMIC) 150, which provides various voltages or currents to the display panel 110, the gate driving circuit 120, the light emitting driving circuit 122 and the data driving circuit 130, or controls various voltages or currents to be provided to the display panel 110, the gate driving circuit 120, the light emitting driving circuit 122 and the data driving circuit 130.

[0082] The PMIC 150 controls a direct current (DC) input voltage Vin provided from the host system 200 to generate power required to drive the display panel 110 , the gate driving circuit 120 , the light emitting driving circuit 122 , and the data driving circuit 130 .

[0083] Meanwhile, the sub-pixel SP may be located at a position where the gate line GL and the data line DL intersect, and a light emitting element may be provided at each sub-pixel SP. For example, the organic light emitting display device may include a light emitting element, such as an OLED, located at each sub-pixel SP, and display an image by controlling a current flowing in the light emitting element according to a data voltage.

[0084] The display device 100 may be any of various types of devices, such as an LCD device, an organic light emitting display device, and a plasma display device.

[0085] Figure 2 is an exemplary diagram showing a system of a display device according to an embodiment of the present disclosure.

[0086] Figure 2 A display device 100 according to an embodiment of the present disclosure is shown, wherein a source driver integrated circuit SDIC included in a data driver circuit 130 is implemented by a COF method among various methods (TAB, COG, and COF), and a gate driver circuit 120 and a light emitting driver circuit 122 are implemented by a GIP form among various methods (TAB, COG, COF, and GIP).

[0087] When the gate driving circuit 120 is implemented in the form of a GIP, the plurality of gate driving integrated circuits GDIC included in the gate driving circuit 120 may be directly formed in the frame region of the display panel 110. In this case, the gate driving integrated circuit GDIC may receive various signals (clock signals, gate high signals, and gate low signals) required for generating a scanning signal through gate driving-related signal lines provided in the frame region.

[0088] In addition, when the light emitting driving circuit 122 is implemented in the GIP form, the plurality of light emitting control circuits ECC included in the light emitting driving circuit 122 may be directly formed in the frame region of the display panel 110. In this case, the light emitting control circuit ECC may receive various signals (clock signals and light emitting driving signals) required for generating light emitting signals through light emitting driving related signal lines provided in the frame region.

[0089] Similarly, the one or more source driver integrated circuits SDIC included in the data driver circuit 130 may be mounted on the source film SF, and one side of the source film SF may be electrically connected to the display panel 110. In addition, a line for electrically connecting the source driver integrated circuit SDIC to the display panel 110 may be disposed on the source film SF.

[0090] The display device 100 may include at least one source printed circuit board SPCB configured to circuit-connect the plurality of source driving integrated circuits SDIC with other devices and a control printed circuit board CPCB configured to mount a control part and various electrical devices thereon.

[0091] In this case, the other side of the source film SF on which the source driver integrated circuit SDIC is mounted may be connected to at least one source printed circuit board SPCB. That is, one side of the source film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to the display panel 110, and the other side of the source film SF may be electrically connected to the source printed circuit board SPCB.

[0092] The timing controller 140 and the PMIC 150 may be mounted on the control printed circuit board CPCB. The timing controller 140 may control the operations of the data driving circuit 130, the gate driving circuit 120, and the light emitting driving circuit 122. The PMIC 150 may provide a driving voltage or current to the display panel 110, the data driving circuit 130, the gate driving circuit 120, and the light emitting driving circuit 122, and control the driving voltage or current to be provided.

[0093] The at least one source printed circuit board SPCB and the control printed circuit board CPCB may be circuit-connected by at least one connecting member, and the connecting member may be formed as, for example, a flexible printed circuit FPC, a flexible flat cable FFC, etc. In addition, the at least one source printed circuit board SPCB and the control printed circuit board CPCB may be integrated into one printed circuit board.

[0094] The display device 100 may further include a set board 170 electrically connected to the control printed circuit board CPCB. In this case, the set board 170 may be referred to as a power board. A main power management circuit (M-PMC) 160 configured to manage the total power of the display device 100 may exist in the set board 170. The M-PMC 160 may be interlocked with the PMIC 150.

[0095] In the case where the display device 100 has the above configuration, a driving voltage is generated from the setting board 170 and transmitted to the PMIC 150 in the control printed circuit board CPCB. The PMIC 150 transmits the driving voltage required for driving the display or sensing the characteristic value to the source printed circuit board SPCB through the flexible printed circuit FPC or the flexible flat cable FFC. The driving voltage transmitted to the source printed circuit board SPCB is provided by the source driver integrated circuit SDIC, thereby allowing a specific sub-pixel SP in the display panel 110 to emit light or detect the specific sub-pixel SP.

[0096] In this case, each sub-pixel SP provided in the display panel 110 of the display device 100 may be configured as a light emitting element and a circuit element, for example, a driving transistor for driving the light emitting element.

[0097] The type and number of circuit elements constituting each sub-pixel SP may be determined in various ways according to provided functions and design methods.

[0098] Figure 3 is a diagram showing an example of a display panel in a display device according to an embodiment of the present disclosure, in which a gate driving circuit and a light emitting driving circuit are implemented in a GIP type.

[0099] refer to Figure 3 According to an embodiment of the present disclosure, a display device 100 includes n gate lines GL1 to GLn (n is a natural number) and n light emitting signal lines EL1 to ELn (n is a natural number), and the n gate lines GL1 to GLn and the n light emitting signal lines EL1 to ELn can be arranged in an effective area A / A for displaying an image.

[0100] Here, the active area A / A is an area for displaying an image, and a plurality of sub-pixels SP for emitting light of corresponding colors, for example, W sub-pixels, R sub-pixels, G sub-pixels, and B sub-pixels are arranged in the area. In addition, a plurality of dummy pixels (dummypixels) may be located at some positions of the active area A / A, and the dummy pixels do not emit light because the scan signal SCAN or the data voltage Vdata is not applied, but each of them has a load similar to that of the sub-pixel SP.

[0101] In the embodiment of the present disclosure, the plurality of sub-pixel regions emitting corresponding color lights and the region where the pseudo pixels not emitting light are set are referred to as the effective area A / A. Alternatively, the plurality of sub-pixel regions emitting corresponding color lights and the region where the pseudo pixels not emitting light are set can be referred to as a pixel array.

[0102] The gate driving circuit 120 is disposed and embedded in a frame area on one side of the active area A / A where no pixels are formed, and may include n source driving integrated circuits SDIC1 to SDICn corresponding to the n gate lines GL1 to GLn.

[0103] Accordingly, the n source driver integrated circuits SDIC1 to SDICn may output scan signals SCAN to the n gate lines GL1 to GLn.

[0104] Furthermore, the light emission driving circuit 122 is provided and embedded in a frame region where no pixels are formed on the other side of the active region A / A, and may include n light emission control circuits ECC1 to ECCn corresponding to n light emission signal lines EL1 to ELn.

[0105] Accordingly, the n light emission control circuits ECC1 to ECCn may output light emission signals EM to the n light emission signal lines EL1 to ELn.

[0106] In this way, when both the gate driving circuit 120 and the light emitting driving circuit 122 are implemented as a GIP type, since it is not necessary to manufacture a separate integrated circuit having a gate driving function or a light emitting driving function and to bond the separate integrated circuit to the display panel 110, the number of integrated circuits can be reduced and the process of connecting the integrated circuit to the display panel 110 can be omitted. In addition, the size of the frame area of ​​the display panel 110 to which the integrated circuit is bonded can be reduced.

[0107] Alternatively, the n source driving integrated circuits SDIC1 to SDICn and the n light emission control circuits ECC1 to ECCn may be disposed together in a bezel region located on one side of the display panel 110 .

[0108] A plurality of gate clock lines GCL for transmitting a gate clock GCLK required to generate and output a scan signal SCAN to the gate driving circuit 120 may be disposed in a frame region where no pixels are formed on one side of the active region A / A.

[0109] Furthermore, a plurality of emission clock lines ECL for transmitting the emission clock ECLK required to generate and output the emission signal EM to the emission driving circuit 122 may be provided in a frame region where no pixels are formed on the other side of the active region A / A.

[0110] Figure 4 is a diagram showing an example of a sub-pixel circuit of a display device according to an embodiment of the present disclosure.

[0111] refer to Figure 4 , the sub-pixel SP of the display device 100 according to one embodiment of the present disclosure includes first to sixth switching transistors T1 to T6 , a driving transistor DRT, a storage capacitor Cst, and a light emitting element ED.

[0112] Here, an n-th sub-pixel SP in which the light emitting element ED emits light according to the second light emitting signal EM[n] will be assumed and described.

[0113] In this case, the light emitting element ED may be, for example, a self-luminous element capable of emitting light by itself, such as an OLED.

[0114] In the sub-pixel SP according to one embodiment of the present disclosure, the second to sixth switching transistors T2 to T6 and the driving transistor DRT may be P-type transistors. In addition, the first switching transistor T1 may be an N-type transistor.

[0115] The P-type transistor is relatively more reliable than the N-type transistor. Since the drain electrode of the P-type transistor T3 is electrically connected to the high potential driving voltage VDDEL, it has the following advantages: the current flowing in the light emitting element ED does not fluctuate due to the storage capacitor Cst. Therefore, it is easy to stably provide current.

[0116] For example, the fourth switching transistor T4 and the sixth switching transistor T6 may be connected to the anode electrode of the light emitting element ED. In this case, when the switching transistors T4 and T6 connected to the light emitting element ED operate in a saturation region, a constant current may flow regardless of changes in the current and threshold voltage of the light emitting element ED, thereby obtaining relatively high reliability.

[0117] In such a sub-pixel SP structure, the N-type transistor T1 can be formed as an oxide transistor formed using a semiconductor oxide (for example, a transistor having a channel formed of a semiconductor oxide such as an oxide of indium, gallium or zinc, or indium gallium zinc oxide (IGZO)), and the remaining P-type transistors DRT and T2 to T6 can all be silicon transistors formed using a semiconductor such as silicon (for example, transistors having a polycrystalline silicon channel formed using a low-temperature process called low-temperature polycrystalline silicon (LTPS)).

[0118] Since oxide transistors have relatively lower leakage current than silicon transistors, when the transistor is implemented using oxide transistors, current leakage from the gate electrode of the driving transistor DRT is prevented, thereby achieving the effect of reducing image defects (eg, flicker).

[0119] Meanwhile, the remaining P-type transistors DRT and T2 to T6 except the first switch transistor T1 corresponding to the N-type transistor may all be formed of LTPS.

[0120] The gate electrode of the first switch transistor T1 receives the first scan signal SCAN1. The drain electrode of the first switch transistor T1 is connected to the gate electrode of the driving transistor DRT through the second node N2. The source electrode of the first switch transistor T1 is connected to the source electrode of the driving transistor DRT.

[0121] The first switching transistor T1 is turned on by the first scan signal SCAN1 and controls the operation of the driving transistor DRT by the high potential driving voltage VDDEL stored in the storage capacitor Cst. The high potential driving voltage VDDEL may have a value in the range of 2V to 3V and may have a level lower than the bias voltage VOBS.

[0122] To constitute an oxide transistor, the first switch transistor T1 may be formed as an N-type metal oxide semiconductor (MOS) transistor. Since the N-type MOS transistor uses electrons instead of holes as carriers, the mobility is faster than that of the P-type MOS transistor, and thus the switching speed can be faster.

[0123] A gate electrode of the second switch transistor T2 receives a second scan signal SCAN2. A drain electrode of the second switch transistor T2 may receive a data voltage Vdata. A source electrode of the second switch transistor T2 is connected to a drain electrode of the driving transistor DRT through a first node N1.

[0124] The second switching transistor T2 is turned on by the second scan signal SCAN2 to supply the data voltage Vdata to the drain electrode of the driving transistor DRT.

[0125] The gate electrode of the third switch transistor T3 receives the first light emitting signal EM[nX] (X is a natural number less than n) before the second light emitting signal EM[n]. The drain electrode of the third switch transistor T3 receives the high potential driving voltage VDDEL. The source electrode of the third switch transistor T3 is connected to the drain electrode of the driving transistor DRT through the first node N1.

[0126] The third switching transistor T3 is turned on by the first light emitting signal EM[nX], thereby supplying the high potential driving voltage VDDEL to the drain electrode of the driving transistor DRT.

[0127] The gate electrode of the fourth switch transistor T4 receives the second light emitting signal EM[n]. The drain electrode of the fourth switch transistor T4 is connected to the source electrode of the driving transistor DRT through the third node N3. The source electrode of the fourth switch transistor T4 is connected to the anode electrode of the light emitting element ED through the fourth node N4.

[0128] The fourth switching transistor T4 is turned on by the second light emitting signal EM[n], thereby providing a driving current to the anode electrode of the light emitting element ED.

[0129] In this case, since the third switching transistor T3 is turned on by the first light emitting signal EM[nX] and the fourth switching transistor T4 is turned on by the second light emitting signal EM[n], the third switching transistor T3 is turned on a predetermined time earlier than the fourth switching transistor T4.

[0130] A gate electrode of the fifth switch transistor T5 receives the third scan signal SCAN3 .

[0131] The drain electrode of the fifth switch transistor T5 receives the bias voltage VOBS. The bias voltage VOBS may have a value between 5.5V and 7V and may have a level higher than the high potential drive voltage VDDEL. The source electrode of the fifth switch transistor T5 is connected to the source electrode of the drive transistor DRT through the third node N3.

[0132] The fifth switching transistor T5 is turned on by the third scan signal SCAN3 , thereby providing the bias voltage VOBS to the source electrode of the driving transistor DRT.

[0133] A gate electrode of the sixth switch transistor T6 receives the fourth scan signal SCAN4 .

[0134] Here, the fourth scan signal SCAN4 may be the third scan signal SCAN3 provided to the sub-pixel SP at a different position. For example, when the third scan signal SCAN3 is applied to the nth gate line GL, the fourth scan signal SCAN4 may be the third scan signal SCAN3 applied to the (n+1)th gate line GL. That is, the fourth scan signal SCAN4 may use the third scan signal SCAN3 that changes the gate line GL according to the phase at which the display panel 110 is driven.

[0135] A drain electrode of the sixth switch transistor T6 receives the reset voltage VAR. A source electrode of the sixth switch transistor T6 is connected to the anode electrode of the light emitting element ED through a fourth node N4.

[0136] The sixth switching transistor T6 is turned on by the fourth scan signal SCAN4 to supply the reset voltage VAR to the anode electrode of the light emitting element ED.

[0137] The gate electrode of the driving transistor DRT is connected to the drain electrode of the first switching transistor T1. The drain electrode of the driving transistor DRT is connected to the source electrode of the second switching transistor T2. The source electrode of the driving transistor DRT is connected to the source electrode of the first switching transistor T1.

[0138] The driving transistor DRT is turned on by the voltage difference between the source electrode and the drain electrode of the first switching transistor T1 , and accordingly, a driving current is applied to the light emitting element ED.

[0139] The high potential driving voltage VDDEL is applied to one side of the storage capacitor Cst, and the other side of the storage capacitor Cst is connected to the gate electrode of the driving transistor DRT. The storage capacitor Cst stores the voltage of the gate electrode of the driving transistor DRT.

[0140] The anode electrode of the light emitting element ED is connected to the source electrode of the fourth switching transistor T4 and the source electrode of the sixth switching transistor T6. The low potential base voltage VSSEL is applied to the cathode electrode of the light emitting element ED.

[0141] The light emitting element ED emits light with predetermined brightness by a driving current flowing through the driving transistor DRT.

[0142] In the next case, the reset voltage VAR is supplied to reset the anode electrode of the light emitting element ED.

[0143] In a state where the fourth switching transistor T4 located between the anode electrode of the light emitting element ED and the driving transistor DRT is turned off by the second light emitting signal EM[n], when the reset voltage VAR is supplied to the anode electrode of the light emitting element ED, the anode electrode of the light emitting element ED may be reset.

[0144] In order to allow the driving operation of the driving transistor DRT and the operation of resetting the anode electrode of the light-emitting element ED to be performed separately, the third scan signal SCAN3 used to drive the driving transistor DRT or apply the bias voltage VOBS can have a phase different from the phase of the fourth scan signal SCAN4, and the fourth scan signal SCAN4 is used to control the supply of the reset voltage VAR to the anode electrode of the light-emitting element ED.

[0145] In this case, when the switching transistors T5 and T6 that respectively provide the bias voltage VOBS and the reset voltage VAR are turned on, the fourth switching transistor T4 that connects the source electrode of the driving transistor DRT to the anode electrode of the light emitting element ED is turned off, so that the driving current of the driving transistor DRT can be prevented from flowing into the anode electrode of the light emitting element ED, and the sub-pixel SP can be configured so that the anode electrode of the light emitting element ED is not affected by voltages other than the reset voltage VAR.

[0146] As described above, the sub-pixel SP including the seven transistors DRT, T1, T2, T3, T4, T5, and T6 and one capacitor Cst may be referred to as having a 7T1C structure.

[0147] Among the sub-pixel SP circuits having various structures, an example of the 7T1C structure is shown here, and various changes can be made to the structure and number of transistors and capacitors constituting the sub-pixel SP. At the same time, the plurality of sub-pixels SP may have the same structure, and some of the plurality of sub-pixels SP may have different structures.

[0148] In such a sub-pixel SP structure, by making the turn-on time of the first light emitting signal EM[nX] used to control the third switching transistor T3 so as to provide the high potential driving voltage VDDEL to the drain electrode of the driving transistor DRT different from the turn-on time of the second light emitting signal EM[n] used to control the fourth switching transistor T4 so as to provide the driving current to the anode electrode of the light emitting element ED, image quality defects, such as black excitation, can be reduced in the time period when low driving frequency operation is performed.

[0149] Figure 5 is a schematic diagram illustrating a driving mode according to a frequency change in a display device according to an embodiment of the present disclosure.

[0150] refer to Figure 5 The display device 100 according to one embodiment of the present disclosure may operate in a mode divided into a first mode Mode 1 for changing and displaying an image at a high-speed first frequency and a second mode Mode 2 for displaying a still image or a low-speed image at a low-speed second frequency.

[0151] For example, in the first mode Mode 1, image data is displayed in full color at a frequency of 120 Hz corresponding to the first frequency on the display panel 110. When the display device 100 operates in the first mode Mode 1, the subpixels SP of the display panel 110 display the image data DATA transmitted from the timing controller 140 at 120 frames / second.

[0152] As described above, the time period for continuously displaying images on the display panel 110 at a high-speed driving frequency may be referred to as a refresh frame. For example, when the driving frequency is 120 Hz, all 120 frames during one second in the first mode Mode 1 may be refresh frames for displaying the image data DATA.

[0153] On the other hand, when the display panel 110 is operated in the second mode Mode 2 for displaying a still image or a low-speed image, the display device 100 may display a specified image on the display panel 110 during an initial time period of the second mode Mode 2 and not output an image to the display panel 110 during the remaining time period of the second mode Mode 2.

[0154] For example, when the display device 100 enters the second mode Mode 2, the driving frequency may be changed from the first frequency of 120 Hz to the second frequency of 1 Hz. In this case, in the second mode Mode 2 where the driving frequency is changed to the frequency of 1 Hz, the image displayed in the last time segment of the first mode Mode 1 is displayed on the display panel 110.

[0155] For example, in the second mode Mode 2 driven at a frequency of 1 Hz, the display device 100 may display an image displayed in the last time section of the first mode Mode 1 once on the display panel 110 and may not output an image during the remaining time section.

[0156] In this case, the subpixel SP may display an image once in the second mode Mode 2 and may maintain the voltage stored in the storage capacitor Cst for the remaining time period.

[0157] As described above, the time period in which the voltage stored in the storage capacitor Cst is maintained without transmitting image data to the display panel 110 may be referred to as a skip frame. For example, when the driving frequency is 120 Hz, in the second mode Mode 2, the first frame may be a refresh frame for displaying image data, and the remaining frames may be skip frames for not outputting image data.

[0158] In this way, in the second mode Mode 2 of low-speed driving, the image data DATA is not displayed for a predetermined period of time (skipping frames), so that power consumption can be reduced.

[0159] Figure 6 1 is a schematic diagram showing driving timing in a second mode of driving at a low driving frequency in a display device according to an embodiment of the present disclosure.

[0160] refer to Figure 6 In the display device 100 according to one embodiment of the present disclosure, in the second mode Mode 2 operating at a low driving frequency, one frame period may be divided into a first frame period and a second frame period according to a synchronization signal SYNC.

[0161] The first frame period may be a refresh frame period in which the image data DATA is displayed on the display panel 110 , and the second frame period may be a skip frame period in which the image data DATA is not output to the display panel 110 .

[0162] During the refresh frame, in order to drive the sub-pixel SP, a data voltage Vdata, a stabilization voltage (not shown), and a reset voltage VAR may be applied.

[0163] During the refresh frame, the voltage charged or maintained in the storage capacitor Cst may be initialized. The refresh frame may be partially provided in the start time section of each frame in the low-speed second mode Mode 2. In the refresh frame, the influence of the data voltage Vdata and the driving voltage stored in the sub-pixel SP during the high-speed first mode Mode 1 may be eliminated.

[0164] After the refresh operation is completed within the refresh frame, the light emitting element ED may emit light according to the data voltage Vdata applied to the sub-pixel SP.

[0165] At the same time, a sampling process for compensating a characteristic value (threshold voltage or mobility) of the driving transistor DRT may be performed in the refresh frame.

[0166] For example, when the first switching transistor T1 is turned on by the first scan signal SCAN1 and thus electrically connects the gate electrode and the source electrode of the driving transistor DRT, the gate electrode and the source electrode of the driving transistor DRT have substantially the same potential.

[0167] In this case, when the second switching transistor T2 is turned on by the second scan signal SCAN2 and thus provides the data voltage Vdata, a current path is formed until the voltage difference between the gate electrode and the source electrode of the driving transistor DRT reaches the threshold voltage of the driving transistor DRT. Accordingly, the voltage charging of the gate electrode and the source electrode of the driving transistor DRT is completed.

[0168] That is, when the data voltage Vdata is supplied to the drain electrode of the driving transistor DRT, the voltages of the gate and source electrodes of the driving transistor DRT rise to the voltage difference between the data voltage Vdata and the threshold voltage, thereby compensating for the threshold voltage of the driving transistor DRT.

[0169] As described above, the process of compensating the characteristic value of the driving transistor DRT through the sampling process may correspond to internal compensation.

[0170] Meanwhile, in order to reduce a hysteresis effect that may occur in the driving transistor DRT and to improve response characteristics, a bias voltage VOBS may be applied during a refresh frame.

[0171] For example, a peak white grayscale voltage may be applied to the gate electrode of the driving transistor DRT, and the driving transistor DRT may thus be in an on-bias state, wherein a large current flows between the drain electrode and the source electrode of the driving transistor DRT.

[0172] On the other hand, a peak black grayscale voltage is applied to the gate electrode of the driving transistor DRT, and the driving transistor DRT may thus be in an off bias state in which almost no current flows between the drain electrode and the source electrode of the driving transistor DRT.

[0173] The peak white grayscale voltage is a voltage applied to the gate electrode of the driving transistor DRT to allow the light emitting element ED to emit light having a peak white grayscale, and the peak black grayscale voltage is a voltage applied to the gate electrode of the driving transistor DRT to allow the light emitting element ED to emit light having a peak black grayscale. For example, when the grayscale value is expressed as an 8-bit digital value, the peak black grayscale may be "0" as the minimum value, and the peak white grayscale may be "255" as the maximum value.

[0174] In this case, since sweep curves of an on bias state and an off bias state of the P-type driving transistor DRT are different, a difference may occur in a current flowing between a drain electrode and a source electrode of the driving transistor DRT.

[0175] In this case, due to the voltage difference between the gate electrode and the source electrode of the driving transistor DRT in gray representation, the characteristic difference of the current flowing between the drain electrode and the source electrode of the driving transistor DRT occurring in the on-bias state and the off-bias state can be called a hysteresis phenomenon, and this difference can be the cause of an afterimage.

[0176] Furthermore, a difference in the driving current flowing between the drain electrode and the source electrode of the driving transistor DRT may not keep the driving characteristics of the light emitting element ED stable and may cause a difference in brightness.

[0177] Specifically, when the display device 100 is driven in the first mode Mode 1 of a high driving frequency and the display device 100 is then switched to the second mode Mode 2 of a low driving frequency, an afterimage caused by the hysteresis phenomenon may be easily perceived.

[0178] Accordingly, when the display device 100 is operated in the second mode Mode 2 at a low driving frequency, in order to minimize the perception of afterimages caused by the hysteresis phenomenon, before the light-emitting period is started by the second light-emitting signal EM[n] of the low logic level L, bias time segments OBS1 and OBS2 can be configured, and during the bias time segments OBS1 and OBS2, the driving transistor DRT is set to a conductive bias state.

[0179] The offset time sections OBS1 and OBS2 may be configured only once within the refresh frame, or may be configured two or more times.

[0180] To this end, before the light emitting period starts, the first bias voltage VOBS1 is applied to the source electrode of the driving transistor DRT, so that the driving transistor DRT can be set to a conductive bias state.

[0181] For example, during a refresh frame of the second mode Mode 2 operating at a low driving frequency, the first bias voltage VOBS1 may be applied to the source electrode of the driving transistor DRT before the light emitting period starts.

[0182] In this case, when the second light emitting signal EM[n] is converted to a low logic level while the first bias voltage VOBS1 is applied to the source electrode of the driving transistor DRT, the voltage level of the fourth node N4 corresponding to the anode electrode of the light emitting element ED may increase due to a kickback phenomenon.

[0183] As a result, the voltage level of the anode electrode of the light emitting element ED rises to be higher than the on level of the light emitting element ED, and a black excitation phenomenon occurs.

[0184] In order to solve the above problem, the first light emitting signal EM[nX] of the low logic level L may be applied to the third switch transistor T3 during the first light emitting control period P1 having a predetermined time interval before the time point when the second light emitting signal EM[n] is converted to the low logic level L. Accordingly, the first light emitting signal EM[nX] and the second light emitting signal EM[n] sequentially turn on the third switch transistor T3 and the fourth switch transistor T4 at a time interval of the first light emitting control period P1.

[0185] That is, by converting the first light emitting signal EM[nX] to the low logic level L during the first light emitting control period P1 before the second light emitting signal EM[n] is converted to the low logic level L, the voltage level of the source electrode of the driving transistor DRT can be lowered by the high potential driving voltage VDDEL.

[0186] In this case, after the first light-emitting signal EM[nX] is converted to the low logic level L, the first light-emitting control time period P1 until the second light-emitting signal EM[n] is converted to the low logic level L can be set to be shorter than or equal to the time when the voltage level of the anode electrode of the light-emitting element ED reaches the high potential driving voltage VDDEL.

[0187] In a state where the voltage level of the anode electrode of the light emitting element ED is lowered, the second light emitting signal EM[n] is converted to a low logic level L in the second light emitting control period P2.

[0188] Even when the fourth switch transistor T4 is turned on by the second light emitting signal EM[n] of the low logic level L in the second light emitting control period P2, since the voltage level of the source electrode of the driving transistor DRT is lowered by the high potential driving voltage VDDEL, even when the voltage level of the anode electrode of the light emitting element ED is increased, the voltage level of the anode electrode thereof does not exceed the turn-on level of the light emitting element ED. As a result, the black excitation phenomenon that occurs when the voltage level of the anode electrode of the light emitting element ED is greater than the turn-on level of the light emitting element ED can be solved.

[0189] The skip frame is a time period for charging or setting the data voltage Vdata and the driving voltage of each frame. The skip frame lasts after the refresh frame ends until the next refresh frame starts.

[0190] During the skipped frame, the anode electrode of the light emitting element ED is reset to the reset voltage VAR. In this case, during the skipped frame, in order to solve the flicker problem caused by the extended skipped frame due to low-speed driving, the anode electrode of the light emitting element ED can be reset to a predetermined voltage.

[0191] Specifically, the data voltage Vdata is maintained at a low logic level L during the skip frame.

[0192] Furthermore, in order to reduce a hysteresis effect that may occur in the driving transistor DRT and to improve response characteristics, the second bias voltage VOBS2 may be applied during the skip frame.

[0193] That is, when the display device 100 is operated in the second mode Mode 2 at a low driving frequency, in order to minimize the perception of afterimages caused by the hysteresis phenomenon, a bias time segment OBS3 can be configured during a skipped frame time period before starting the light emitting time period with the light emitting signal EM at a low logic level L, during which the driving transistor DRT is set to a conductive bias state.

[0194] To this end, before the light emitting period starts, the second bias voltage VOBS2 is applied to the source electrode of the driving transistor DRT, so that the driving transistor DRT can be set to a conductive bias state.

[0195] For example, during a skip frame of the second mode Mode 2 operating at a low driving frequency, the second bias voltage VOBS2 may be applied to the source electrode of the driving transistor DRT before the light emitting period starts.

[0196] The first scan signal SCAN1 and the third scan signal SCAN3 may both be maintained at a low logic level L during the skip frame, and the second scan signal SCAN2 and the fourth scan signal SCAN4 may both be maintained at a high logic level H. Accordingly, the data voltage Vdata is not provided during the skip frame. In addition, the first and fourth transistors T1 and T4 are maintained in a turned-off state during the skip frame.

[0197] The third scan signal SCAN3 and the fourth scan signal SCAN4 may both have a low logic level L during a partial time section of the skipped frame, and may both be maintained at a high logic level H in a remaining time section of the skipped frame.

[0198] The fifth switching transistor T5 is turned on in a time section in which the third scan signal SCAN3 has a low logic level L, and the sixth switching transistor T6 is turned on in a time section in which the fourth scan signal SCAN4 has a low logic level L.

[0199] The turned-on fifth switching transistor T5 supplies the second bias voltage VOBS2 to the source electrode of the driving transistor DRT during the skip frame, and the turned-on sixth switching transistor T6 supplies the reset voltage VAR to the anode electrode of the light emitting element ED.

[0200] During the skipped frame, the second light emitting signal EM[n] mostly maintains a high logic level H. In a time section in which the second light emitting signal EM[n] has a low logic level L, the fourth switching transistor T4 is turned on.

[0201] When the second light emitting signal EM[n] is maintained at the high logic level H during the skip frame, the fourth switch transistor T4 is turned off. Accordingly, when the anode electrode of the light emitting element ED is reset, the current of the driving transistor DRT can be cut off.

[0202] Similarly, even during the skipped frame, the voltage level of the anode electrode of the light emitting element ED rises to be higher than the turn-on level of the light emitting element ED, and a black excitation phenomenon may occur.

[0203] Therefore, even during the skipped frame, the first light emitting signal EM[nX] applied to the third switching transistor T3 is converted to the low logic level L during the first light emitting control period P1 before the time point when the second light emitting signal EM[n] is converted to the low logic level L, so that the voltage level of the source electrode of the driving transistor DRT can be reduced to the level of the high potential driving voltage VDDEL. As a result, the black excitation phenomenon that occurs when the voltage level of the anode electrode of the light emitting element ED is greater than the turn-on level of the light emitting element ED can be solved.

[0204] The following describes the operation of the sub-pixel SP in the bias time section OBS2 in which the first bias voltage VOBS1 is applied during the refresh frame, the operation in the first light control time period P1 after the first light emitting signal EM[nX] is converted to the low logic level L until the second light emitting signal EM[n] is converted to the low logic level L, and the operation in the second light emitting control time period P2 after the second light emitting signal EM[n] is converted to the low logic level L.

[0205] Figure 7 is a diagram illustrating an operation of a subpixel SP in a bias time section in which a first bias voltage is applied during a refresh frame in a display device according to an embodiment of the present disclosure.

[0206] Here, the offset time segments OBS1 and OBS2 are configured twice during the refresh frame and Figure 7 Only the second offset time segment OBS2 is shown.

[0207] refer to Figure 7 When the display device 100 according to an embodiment of the present disclosure operates in the second mode Mode 2 at a low driving frequency, in order to minimize the perception of afterimages caused by hysteresis, before the light-emitting period starts by the second light-emitting signal EM[n] of the low logic level L, a bias time section OBS2 for setting the driving transistor DRT to a conductive bias state can be configured.

[0208] Since the bias time section OBS2 is configured before the first light emitting signal EM[nX] and the second light emitting signal EM[n] are both converted to the low logic level L, the third switch transistor T3 to which the first light emitting signal EM[nX] is applied and the fourth switch transistor T4 to which the second light emitting signal EM[n] is applied are both maintained in the off state.

[0209] Furthermore, since the first scan signal SCAN1 is applied at a low logic level L and the second scan signal SCAN2 is applied at a high logic level H, both the first switching transistor T1 and the second switching transistor T2 are maintained in a turned-off state.

[0210] In this case, the fifth switching transistor T5 is turned on by the third scan signal SCAN3 of the low logic level L, and the first bias voltage VOBS1 is thus applied to the source electrode of the driving transistor DRT.

[0211] As described above, the first bias voltage VOBS1 is applied to the source electrode of the driving transistor DRT, so that the driving transistor DRT can be set to a conductive bias state.

[0212] The first bias voltage VOBS1 may have a higher level than the high potential driving voltage VDDEL.

[0213] In this case, during the bias time period OBS2 when the first bias voltage VOBS1 is applied to the source electrode of the driving transistor DRT, the sixth switching transistor T6 is turned on by the fourth scan signal SCAN4 of the low logic level L, so that the reset voltage VAR is applied to the anode electrode of the light emitting element ED.

[0214] The reset voltage VAR may have a value in the range of -5V to -6V.

[0215] Since the second light emitting signal EM[n] is at the high logic level H during the bias time section OBS2, the fourth switch transistor T4 remains in the off state, and the source electrode of the driving transistor DRT to which the first bias voltage VOBS1 is applied is electrically isolated from the anode electrode of the light emitting element ED.

[0216] Accordingly, during the bias time period OBS2 , the source electrode of the driving transistor DRT and the anode electrode of the light emitting element ED exhibit a voltage difference corresponding to the difference ( VOBS1 −VAR) between the first bias voltage VOBS1 and the reset voltage VAR.

[0217] Figure 8 is a diagram showing a sub-pixel operation in a first light emission control period P1 for controlling a source electrode of a driving transistor to a high potential level of a driving voltage within a refresh frame in a display device according to an embodiment of the present disclosure.

[0218] refer to Figure 8 In the process of operating in the second mode Mode 2 at a low driving frequency, the display device 100 according to an embodiment of the present disclosure may apply a first light emitting signal EM[nX] at a low logic level L during a first light emitting control period P1 having a predetermined time interval before a time point when the second light emitting signal EM[n] is converted to a low logic level L, wherein the first light emitting signal EM[nX] is applied to the third switching transistor T3.

[0219] Since the third switching transistor T3 is turned on by the first light emitting signal EM[nX] during the first light emitting control period P1, the source electrode of the driving transistor DRT decreases from the level of the first bias voltage VOBS1 toward the level of the high potential driving voltage VDDEL. That is, the source electrode of the driving transistor DRT exhibits a voltage level (VDDEL+a) close to the high potential driving voltage VDDEL, and "a" in the voltage level (VDDEL+a) represents a smaller value, so that the voltage level (VDDEL+a) is close to the high potential driving voltage VDDEL.

[0220] In this case, a final voltage level of the source electrode of the driving transistor DRT may be determined according to a time interval of the first light emitting control period P1 during which the third switching transistor T3 is turned on by the first light emitting signal EM[nX].

[0221] When the time interval of the first light emission control period P1 is greater than or equal to the reference time interval, the final voltage level of the source electrode of the driving transistor DRT may become equal to the level of the high potential driving voltage VDDEL.

[0222] That is, by converting the first light emitting signal EM[nX] to the low logic level L during the first light emitting control period P1 before the second light emitting signal EM[n], the voltage level of the source electrode of the driving transistor DRT can be lowered by the high potential driving voltage VDDEL.

[0223] In this case, during part or all of the first light emission control period P1 , the sixth switch transistor T6 is turned on by the fourth scan signal SCAN4 of the low logic level L, thereby maintaining the anode electrode of the light emitting element ED at the reset voltage VAR.

[0224] Since the second light emitting signal EM[n] is at the high logic level H during the first light emitting control period P1, the fourth switching transistor T4 remains in the off state, and the source electrode of the driving transistor DRT to which the high potential driving voltage VDDEL is applied is electrically isolated from the anode electrode of the light emitting element ED.

[0225] Therefore, during the first light-emitting control time period P1, the source electrode of the driving transistor DRT and the anode electrode of the light-emitting element ED exhibit a voltage difference corresponding to the difference (VDDEL+a–VAR) between the reset voltage VAR and the voltage level (VDDEL+a), wherein the voltage level (VDDEL+a) is close to the high potential driving voltage VDDEL.

[0226] In this case, since the high potential driving voltage VDDEL has a level lower than the first bias voltage VOBS1, the voltage difference (VDDEL+a–VAR) between the source electrode of the driving transistor DRT and the anode electrode of the light-emitting element ED in the first light-emitting control time period P1 has a value lower than the voltage difference (VOBS1–VAR) between the source electrode of the driving transistor DRT and the anode electrode of the light-emitting element ED in the bias time section OBS2.

[0227] Fig. 9 1 is a diagram showing a sub-pixel operation in a second light emission control period P2 in which a driving current is supplied to a light emitting element within a refresh frame in a display device according to an embodiment of the present disclosure.

[0228] refer to Fig. 9 In the process of operating in the second mode Mode 2 at a low driving frequency, the display device 100 according to an embodiment of the present disclosure may apply a second light emitting signal EM[n] at a low logic level L after a first light emitting control period P1 having a predetermined time interval, wherein the second light emitting signal EM[n] is applied to the fourth switching transistor T4.

[0229] Since the fourth switching transistor T4 is turned on by the second light emitting signal EM[n] in the second light emitting control period P2, the source electrode of the driving transistor DRT is electrically connected to the anode electrode of the light emitting element ED.

[0230] In a state where the sixth switching transistor T6 is turned off, a kickback voltage may be instantaneously generated at the anode electrode of the light emitting element ED charged with the reset voltage VAR due to the voltage level (VDDEL+a) of the source electrode of the driving transistor DRT.

[0231] However, since the source electrode of the driving transistor DRT is lowered to a voltage level (VDDEL+a) close to the high potential driving voltage VDDEL due to the first light emitting control time period P1, the kick-back voltage generated at the anode electrode of the light emitting element ED is lowered to a value proportional to the voltage difference (VDDEL+a–VAR) between the source electrode of the driving transistor DRT and the anode electrode of the light emitting element ED, as shown below.

[0232]

[0233] Here, C[N3] represents a parasitic capacitance formed at a third node N3 corresponding to a source electrode of the driving transistor DRT, and C[N4] represents a parasitic capacitance formed at a fourth node N4 corresponding to an anode electrode of the light emitting element ED.

[0234] As described above, before the second light emitting signal EM[n] is converted to the low logic level L, the first light emitting signal EM[nX] applied to the third switch transistor T3 is converted to the low logic level L during the first light emitting control period P1, so that the voltage level of the source electrode of the driving transistor DRT can be reduced to a voltage level (VDDEL+a) close to the high potential driving voltage VDDEL. As a result, the black excitation phenomenon that occurs when the voltage level of the anode electrode of the light emitting element ED becomes higher than the conduction level of the light emitting element ED in the time section where the voltage level of the second light emitting signal EM[n] changes can be solved.

[0235] Fig.10is a signal waveform diagram showing a voltage change of the anode electrode of the light emitting element when the levels of the first light emitting signal and the second light emitting signal are simultaneously switched, and Fig.11 is a signal waveform diagram showing a voltage change of an anode electrode of a light emitting element when a first light emitting signal is converted before a second light emitting signal in a display device according to an embodiment of the present disclosure.

[0236] First, refer to Fig.10 In order to reduce the hysteresis of the driving transistor DRT during a refresh frame in which the data voltage Vdata is applied to the display panel 110 during operation in the second mode Mode 2 of the low driving frequency, a first bias voltage VOBS1 is applied to the source electrode of the driving transistor DRT, thereby setting the driving transistor DRT to a conductive bias state.

[0237] In this case, the first bias voltage VOBS1 applied to the source electrode of the driving transistor DRT may have a level higher than the high potential driving voltage VDDEL.

[0238] During the bias time period OBS when the first bias voltage VOBS1 is applied to the source electrode of the driving transistor DRT, the sixth switch transistor T6 is turned on by the fourth scan signal SCAN4 of the low logic level L, so that the reset voltage VAR is applied to the anode electrode of the light emitting element ED.

[0239] The reset voltage VAR may have a value in the range of -5V to -6V.

[0240] Accordingly, in the bias time section OBS, the source electrode of the driving transistor DRT is maintained at the level of the first bias voltage VOBS1, and the anode electrode of the light-emitting element ED is maintained at the level of the reset voltage VAR, so that the source electrode of the driving transistor DRT and the anode electrode of the light-emitting element ED exhibit a voltage difference corresponding to the difference (VOBS1–VAR) between the first bias voltage VOBS1 and the reset voltage VAR.

[0241] In the above state, when the third switching transistor T3 and the fourth switching transistor T4 are simultaneously turned on by the first light emitting signal EM[nX] and the second light emitting signal EM[n], due to the voltage difference (VOBS1–VAR) between the source electrode of the driving transistor DRT and the anode electrode of the light emitting element ED, a high-level kickback voltage can be generated at the anode electrode of the light emitting element ED, as shown below.

[0242]

[0243] Here, C[N3] represents a parasitic capacitance formed at a third node N3 corresponding to a source electrode of the driving transistor DRT, and C[N4] represents a parasitic capacitance formed at a fourth node N4 corresponding to an anode electrode of the light emitting element ED.

[0244] As a result, the voltage level of the anode electrode of the light emitting element ED rises to be higher than the on level of the light emitting element ED, and a black excitation phenomenon may occur.

[0245] In contrast, before the second light-emitting signal EM[n] is converted to the low logic level L, the display device 100 of the present invention first converts the first light-emitting signal EM[nX] applied to the third switching transistor T3 to the low logic level L during the first light-emitting control time period P1, thereby reducing the voltage level of the source electrode of the driving transistor DRT to the level of the high-potential driving voltage VDDEL, thereby solving the black excitation phenomenon.

[0246] refer to Fig.11 In order to turn on the fourth switching transistor T4, the display device 100 according to an embodiment of the present disclosure may apply the first light emitting signal EM[nX] at a low logic level L during the first light emitting control time period P1 before the time point when the second light emitting signal EM[n] is converted to a low logic level L to turn on the third switching transistor T3.

[0247] Since the third switch transistor T3 is first turned on by the first light emitting signal EM[nX] during the first light emitting control period P1, the source electrode of the driving transistor DRT decreases from the level of the first bias voltage VOBS1 toward the level of the high potential driving voltage VDDEL. That is, the source electrode of the driving transistor DRT exhibits a voltage level (VDDEL+a) close to the high potential driving voltage VDDEL.

[0248] That is, by converting the first light emitting signal EM[nX] to the low logic level L during the first light emitting control period P1 before converting the second light emitting signal EM[n] to the low logic level L, the voltage level of the source electrode of the driving transistor DRT can be lowered by the high potential driving voltage VDDEL.

[0249] In this case, during the first light emission control period P1 , the sixth switching transistor T6 is turned on by the fourth scan signal SCAN4 of the low logic level L, thereby maintaining the anode electrode of the light emitting element ED at the reset voltage VAR.

[0250] Therefore, during the first light emitting control period P1, the source electrode of the driving transistor DRT and the anode electrode of the light emitting element ED exhibit a voltage difference corresponding to the difference (VDDEL+a-VAR) between the reset voltage VAR and a voltage level (VDDEL+a) close to the high potential driving voltage VDDEL.

[0251] In this case, since the high potential driving voltage VDDEL has a level lower than the first bias voltage VOBS1, the voltage difference (VDDEL+a–VAR) between the source electrode of the driving transistor DRT and the anode electrode of the light-emitting element ED in the first light-emitting control time period P1 has a value lower than the voltage difference (VOBS1–VAR) between the source electrode of the driving transistor DRT and the anode electrode of the light-emitting element ED in the bias time section OBS2.

[0252] Since the source electrode of the driving transistor DRT is lowered to a voltage level (VDDEL+a) close to the high potential driving voltage VDDEL due to the first light emitting control time period P1, the kick-back voltage generated at the anode electrode of the light emitting element ED is lowered to a value proportional to the voltage difference (VDDEL+a–VAR) between the source electrode of the driving transistor DRT and the anode electrode of the light emitting element ED, as shown below.

[0253]

[0254] Finally, before the time point when the second light emitting signal EM[n] is converted to the low logic level L, the first light emitting signal EM[nX] applied to the third switch transistor T3 is converted to the low logic level L during the first light emitting control period P1, so that the voltage level of the source electrode of the driving transistor DRT can be reduced to a voltage level (VDDEL+a) close to the high potential driving voltage VDDEL. As a result, the black excitation phenomenon that occurs when the voltage level of the anode electrode of the light emitting element ED becomes higher than the conduction level of the light emitting element ED in the time section where the voltage level of the second light emitting signal EM[n] changes can be solved.

[0255] Fig.12 is a graph showing a luminance change caused by a reset voltage according to driving timings of a first light emitting signal and a second light emitting signal in a display device according to an embodiment of the present disclosure.

[0256] refer to Fig.12In the display device 100 according to one embodiment of the present disclosure, in case A where both the first light emitting signal EM[nX] and the second light emitting signal EM[n] are simultaneously converted to the low logic level L and the third switch transistor T3 and the fourth switch transistor T4 are thus simultaneously turned on, it can be seen that the reference brightness L for the black grayscale can be maintained only when the difference between the reset voltage VAR and the low potential driving voltage VSSEL is less than or equal to approximately -0.7V. ref .

[0257] On the other hand, in case B where the first light emitting signal EM[nX] is converted to the low logic level L before the second light emitting signal EM[n] and the third switching transistor T3 is thus turned on before the fourth switching transistor T4, it can be seen that the reference brightness L for the black grayscale can be maintained even when the difference between the reset voltage VAR and the low potential driving voltage VSSEL is less than or equal to about -0.4V. ref .

[0258] That is, before the second light emitting signal EM[n] is converted to the low logic level L, the first light emitting signal EM[nX] applied to the third switch transistor T3 is converted to the low logic level L during the first light emitting control period P1, so that the voltage level of the source electrode of the driving transistor DRT can be reduced. As a result, the black excitation phenomenon that occurs when the voltage level of the anode electrode of the light emitting element ED becomes higher than the turn-on level of the light emitting element ED in the time section where the voltage level of the second light emitting signal EM[n] changes can be reduced and the reset voltage VAR can be stably maintained.

[0259] The process of converting the first light emitting signal EM[nX] applied to the third switching transistor T3 to the low logic level L during the first light emitting control time period P1 before the time point when the second light emitting signal EM[n] is converted to the low logic level L can be equally applied not only to the refresh frame in which the data voltage Vdata is applied to the display panel 110, but also to the skip frame in which the data voltage Vdata is not applied to the display panel 110.

[0260] Fig.13 is a flow chart showing a display driving method according to an embodiment of the present disclosure.

[0261] refer to Fig.13According to an embodiment of the present disclosure, a display driving method may include: step S100 of switching a first mode Mode 1 with a high driving frequency to a second mode Mode 2 with a low driving frequency; step S200 of applying a bias voltage VOBS to a source electrode of a driving transistor DRT; step S300 of applying a driving voltage VDDEL having a level lower than the bias voltage VOBS to the driving transistor DRT through a first light emitting signal EM[nX] during a first light emitting control period P1; step S400 of applying a reset voltage VAR to an anode electrode of a light emitting element ED during the first light emitting control period P1; and step S500 of providing a driving current to the light emitting element ED through a second light emitting signal EM[n] during a second light emitting control period P2 later than the first light emitting control period P1.

[0262] Step S100 of switching the first mode Mode 1 at a high driving frequency to the second mode Mode 2 at a low driving frequency is a process of displaying a still image or a low-speed image, and a specified image can be displayed on the display panel 110 during a refresh frame time period in the second mode, and an image can not be output to the display panel 110 during the remaining skip frame time period.

[0263] Step S200 of applying a bias voltage VOBS to the source electrode of the driving transistor DRT is a process of setting the driving transistor DRT to an on-bias state before the light-emitting element ED emits light, so as to minimize the perception of afterimages caused by hysteresis when the display device 100 operates in the second mode Mode2 with a low driving frequency.

[0264] The process of setting the driving transistor DRT to the on bias state may be performed only once in a refresh frame or a skip frame or may be performed twice or more.

[0265] Step S300 of applying a driving voltage VDDEL having a level lower than the bias voltage VOBS to the driving transistor DRT through the first light-emitting signal EM[nX] during the first light-emitting control period P1 is a process of reducing the voltage level of the source electrode of the driving transistor DRT to the level of the driving voltage VDDEL through the first light-emitting signal EM[nX] before applying a driving current to the light-emitting element ED through the second light-emitting signal EM[n].

[0266] The step S400 of applying the reset voltage VAR to the anode electrode of the light emitting element ED during the first light emission control period P1 is a process of resetting the anode electrode of the light emitting element ED.

[0267] The step S500 of providing a driving current to the light emitting element ED through the second light emitting signal EM[n] during the second light emitting control period P2 later than the first light emitting control period P1 is a process of electrically connecting the driving transistor DRT to the light emitting element ED through the second light emitting signal Em[n], thereby allowing the light emitting element ED to emit light.

[0268] Through this display driving process, the display device 100 of the present disclosure can reduce the voltage level of the source electrode of the driving transistor DRT from the level of the bias voltage VOBS to the level of the driving voltage VDDEL. Therefore, the black excitation phenomenon that occurs when the voltage level of the black gray becomes higher than the conduction level of the light emitting element ED at the time point when the driving current is applied to the light emitting element ED can be reduced, and the reset voltage VAR can be stably maintained.

[0269] The above description and accompanying drawings are only examples of the technical concepts of the present disclosure for the purpose of illustration. Those skilled in the art of the present disclosure will recognize that there may be various modifications and changes (e.g., combinations, splits, substitutions, and configuration changes) without departing from the essential features of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are intended to illustrate the technical concepts of the present disclosure, and the scope of the present disclosure is not limited by the embodiments. The scope of the present disclosure should be interpreted based on the attached claims in a manner that all technical concepts included in the equivalent scope of the claims belong to the present disclosure.

Claims

1. A display device, comprising: Display panel, including: A light emitting element, the light emitting element having an anode electrode and a cathode electrode; a driving transistor configured to provide a driving current to the light emitting element based on a driving voltage; and Multiple luminous signal lines, a light emitting driving circuit configured to provide a plurality of light emitting signals to the display panel through the plurality of light emitting signal lines; and a timing controller configured to operate the display panel at a low driving frequency in a first mode and at a high driving frequency in a second mode, Herein, in the first mode, a bias voltage is applied to the driving transistor and a reset voltage is applied to the anode electrode, and then during a light emission control period, the driving current is applied to the light emitting element through the driving transistor.

2. The display device according to claim 1, wherein: The light emission control period includes a first light emission control period in which the light emitting element does not emit light and a second light emission control period in which the light emitting element emits light. 3 . The display device according to claim 1 , further comprising a gate driving circuit configured to provide a plurality of scanning signals to the display panel through a plurality of gate lines. 4 . The display device according to claim 1 , further comprising a data driving circuit configured to provide a data voltage to the display panel.

5. The display device according to claim 4, wherein: The display panel further includes a plurality of switching transistors configured to control driving of the driving transistor.

6. The display device according to claim 5, wherein: The plurality of switch transistors include: a first switching transistor having a gate electrode to which a first scan signal is applied, a drain electrode connected to the gate electrode of the driving transistor and a storage capacitor, and a source electrode connected to the source electrode of the driving transistor; a second switching transistor having a gate electrode to which a second scan signal is applied, a drain electrode to which the data voltage is applied, and a source electrode connected to the drain electrode of the driving transistor; a third switching transistor having a gate electrode to which the first light emitting signal is applied, a drain electrode to which the driving voltage is applied, and a source electrode connected to the drain electrode of the driving transistor; a fourth switching transistor having a gate electrode to which a second light emitting signal is applied, a drain electrode connected to the source electrode of the driving transistor, and a source electrode connected to the anode electrode of the light emitting element; a fifth switching transistor having a gate electrode to which a third scanning signal is applied, a drain electrode to which the bias voltage is supplied, and a source electrode connected to the source electrode of the driving transistor; and A sixth switching transistor includes a gate electrode to which a fourth scanning signal is applied, a drain electrode to which the reset voltage is supplied, and a source electrode connected to the anode electrode of the light emitting element.

7. The display device according to claim 6, wherein: The first light emission control period is a time section in which the third switch transistor is turned on by the first light emission signal while the fourth switch transistor is turned off.

8. The display device according to claim 6, wherein: The first light emission control period is a time section in which the voltage of the source electrode of the driving transistor is lowered from a level of the bias voltage to a level of the driving voltage.

9. The display device according to claim 6, wherein: The second light emission control period is a time section in which the fourth switch transistor is turned on by the second light emission signal in a state in which the third switch transistor is turned on.

10. The display device according to claim 6, wherein: The third switch transistor and the fourth switch transistor are respectively the nth third switch transistor and the nth fourth switch transistor in the nth sub-pixel, where n is a natural number; The second light emitting signal is a signal applied to the gate electrode of the fourth switching transistor through the nth light emitting signal line; and The first light emitting signal is a signal applied to the gate electrode of the third switching transistor through an (nX)th light emitting signal line, where X is a natural number less than n.

11. The display device according to claim 6, wherein: The fifth switch transistor is an nth fifth switch transistor in the nth sub-pixel, where n is a natural number; The third scanning signal is a signal applied to the gate electrode of the fifth switching transistor through the nth gate line; and The fourth scan signal is a signal applied to the gate electrode of the (n+1)th fifth switching transistor in the (n+1)th sub-pixel through the (n+1)th gate line.

12. The display device according to claim 1, wherein: The bias voltage is applied at a level higher than the driving voltage.

13. The display device according to claim 1, wherein: The first mode includes: a refresh frame period in which a data voltage for driving the light emitting element is applied; and A frame period is skipped, in which the data voltage is not applied.

14. A display panel, comprising: A light emitting element, the light emitting element having an anode electrode and a cathode electrode; a driving transistor configured to provide a driving current to the light emitting element based on a driving voltage; a second switching transistor having a gate electrode, a drain electrode to which a data voltage is applied, and a source electrode connected to the drain electrode of the driving transistor; a third switching transistor having a gate electrode, a drain electrode to which the driving voltage is applied, and a source electrode connected to the drain electrode of the driving transistor; a fourth switching transistor having a gate electrode, a drain electrode connected to the source electrode of the driving transistor, and a source electrode connected to the anode electrode of the light emitting element; as well as a fifth switching transistor having a gate electrode, a drain electrode to which a bias voltage is supplied, and a source electrode connected to the driving transistor, wherein the display panel operates at a low driving frequency in a first mode and at a high driving frequency in a second mode, and Herein, in the first mode, the bias voltage is applied to the driving transistor, and the reset voltage is applied to the anode electrode, and then during a light emission control period, the driving current is applied to the light emitting element through the driving transistor. 15 . The display panel of claim 14 , further comprising a first switching transistor having a gate electrode, a drain electrode connected to the gate electrode of the driving transistor and a storage capacitor, and a source electrode connected to a source electrode of the driving transistor.

16. The display panel according to claim 14 or 15, further comprising a sixth switching transistor having a gate electrode to which a fourth scanning signal is applied, a drain electrode to which the reset voltage is supplied, and a source electrode connected to the anode electrode of the light emitting element.

17. The display panel according to claim 14, wherein: The light emission control period includes a first light emission control period in which the light emitting element does not emit light and a second light emission control period in which the light emitting element emits light.

18. The display panel according to claim 17, wherein: The first light emitting control period is a time period during which the third switching transistor is turned on by the first light emitting signal while the fourth switching transistor is turned off; and The second light emission control period is a time section in which the fourth switch transistor is turned on by the second light emission signal in a state in which the third switch transistor is turned on.

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