Display device

Abstract

The display device includes pixels arranged in rows and columns, a scan driver, and a readout circuit configured to read out electrical characteristics of the pixels through readout lines. The first pixel comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a first organic light emitting diode connected between a second electrode of the seventh transistor and a ground node to which ground voltage is applied. A second organic light emitting diode between the second electrode of the eighth transistor and the ground node; and a third organic light emitting diode connected between the second electrode of the ninth transistor and the ground node.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0087267 filed on July 5, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device, and more particularly, to a display device. Background Art

[0003] The display device may include a display panel configured to display an image and a display driving circuit configured to drive the display panel. The display driver circuit may receive image data from the outside and apply an image signal corresponding to the received image data to a data line of the display panel to drive the display panel. In recent years, the use of an OLED display panel in which each of a plurality of pixels of a pixel array includes an organic light emitting diode (OLED) is increasing.

[0004] The display device may include a plurality of pixels. The plurality of pixels may be arranged in rows and columns. The rows of the plurality of pixels may be connected to a scan driver, and the columns of the plurality of pixels may be connected to a data driver. The scan driver may control the time point at which each of the rows of the plurality of pixels is selected. The data driver may adjust the brightness of the pixels in the selected row. As the display device is reduced and the resolution of the display device is increased, the size of the pixel is reduced. When the size of the pixel is reduced, the range of the amount of current flowing through each pixel may be limited. When the range of the amount of current flowing through each pixel is limited, it may be more difficult to control the brightness of the pixel. Summary of the invention

[0005] One or more embodiments provide a display panel capable of adjusting brightness of a pixel and a display device including the display panel.

[0006] According to one aspect of the embodiments, a display device includes: pixels arranged in rows and columns; a scan driver connected to the rows of pixels, wherein a first row of the rows of pixels is connected to the scan driver through a scan line, a first light-emitting control line, a second light-emitting control line, a third light-emitting control line, a fourth light-emitting control line, an initialization line, and a readout control line; a data driver connected to the columns of pixels, wherein a first column of the columns of pixels is connected to the scan driver through a data line; and a readout circuit connected to the columns of pixels and configured to read out electrical characteristics of the pixels through a readout line, wherein the first column is connected to the readout circuit through a readout line. A first pixel in the pixel includes: a first transistor including a first electrode connected to a first node, a second electrode connected to a third node, and a gate connected to the second node; a second transistor including a first electrode connected to a data line, a second electrode connected to the first node, and a gate connected to a scan line; a third transistor including a first electrode connected to a second node, a second electrode connected to the third node, and a gate connected to the scan line; a fourth transistor including a first electrode connected to a power supply node configured to supply a power supply voltage, a second electrode connected to the first node, and a gate connected to a first light emitting control line; a fifth transistor including a first electrode connected to a readout line, a second electrode connected to a second node, and a gate connected to an initialization line; a sixth transistor including a first electrode connected to a first power supply node configured to supply a power supply voltage, a second electrode connected to the first node, and a gate connected to a first light emitting control line; a first electrode connected to a readout line, a second electrode connected to a third node, and a gate connected to a readout control line; a seventh transistor including a first electrode connected to the third node, a second electrode, and a gate connected to a second light-emitting control line; an eighth transistor including a first electrode connected to the third node, a second electrode, and a gate connected to a third light-emitting control line; a ninth transistor including a first electrode connected to the third node, a second electrode, and a gate connected to a fourth light-emitting control line; a capacitor connected to the first node and the second node; a first organic light-emitting diode connected between the second electrode of the seventh transistor and a ground node; a second organic light-emitting diode between the second electrode of the eighth transistor and the ground node; and a third organic light-emitting diode connected between the second electrode of the ninth transistor and the ground node.

[0007] According to another aspect of the embodiment, a display device includes: a display panel including a plurality of pixels; and a display driving circuit including a scan driver, a data driver and a readout circuit. A first pixel of the plurality of pixels includes: a first transistor, between a first node and a third node, and configured to operate in response to a voltage of a second node; a second transistor, connected between the first node and a first data line, and configured to operate in response to a first scan signal received through a first scan line; a third transistor, connected between the second node and the third node, and configured to operate in response to a fourth scan signal received through a fourth scan line; a fourth transistor, connected between a first driving power source and a first node, and configured to operate in response to a first light emission control signal received through a first light emission control line; a fifth transistor, connected between a readout line and a second node, and configured to operate in response to an initialization signal received through an initialization line; a sixth transistor, connected between a readout line and a third node, and configured to operate in response to a readout control signal received through a readout control line; a seventh transistor, connected between a third node and a first organic light emitting diode, and configured to operate in response to a first light emission control signal received through a second light emission control line; an eighth transistor connected between the third node and the second organic light emitting diode and configured to operate in response to a third light emitting control signal received through the third light emitting control line; a ninth transistor connected between the third node and the third organic light emitting diode and configured to operate in response to a fourth light emitting control signal received through the fourth light emitting control line; a tenth transistor connected between the first node and the second data line and configured to operate in response to a second scan signal received through the second scan line; an eleventh transistor connected between the first node and the third data line and configured to operate in response to a third scan signal received through the third scan line; a capacitor connected between the first node and the second node; a first organic light emitting diode connected between the seventh transistor and the second driving power source; a second organic light emitting diode connected between the eighth transistor and the second driving power source; and a third organic light emitting diode connected between the ninth transistor and the second driving power source. The scan driver is connected to the first pixel through the first scan line, the second scan line, the third scan line, the fourth scan line, the initialization line, the readout control line, the first light emission control line, the second light emission control line, the third light emission control line and the fourth light emission control line. The data driver is connected to the first pixel through the first data line, the second data line and the third data line, and is configured to supply a first data voltage corresponding to the brightness of the first organic light emitting diode through the first data line, supply a second data voltage corresponding to the brightness of the second organic light emitting diode through the second data line, and supply a third data voltage corresponding to the brightness of the third organic light emitting diode through the third data line.The readout circuit is connected to the first pixel through the readout line and is configured to read out an electrical characteristic of the readout line.

[0008] According to another aspect of the embodiment, a display device includes: a display panel including a plurality of pixels; and a display driving circuit including a scan driver, a data driver, and a readout circuit. A first pixel among the plurality of pixels includes: a first transistor connected between a first node and a third node and configured to operate in response to a voltage of a second node; a second transistor connected between the first node and a data line and configured to operate in response to a scan signal received through a scan line; a third transistor connected between the second node and the third node and configured to operate in response to a scan signal; a fourth transistor connected between a first driving power source and a first node and configured to operate in response to a first light emitting control signal received through a first light emitting control line; a sixth transistor connected between a readout line and a third node and configured to operate in response to a readout / initialization control signal received through a readout / initialization control line; a seventh transistor connected between the third node and a first drive power source; and a seventh transistor connected between the first drive power source and a first node and configured to operate in response to a readout / initialization control signal received through a readout / initialization control line. The first organic light emitting diode is connected between the first organic light emitting diode and is configured to operate by operating the second light emitting control signal received through the second light emitting control line; the eighth transistor is connected between the third node and the second organic light emitting diode and is configured to operate in response to the third light emitting control signal received through the third light emitting control line; the ninth transistor is connected between the third node and the third organic light emitting diode and is configured to operate in response to the fourth light emitting control signal received through the fourth light emitting control line; the capacitor is connected between the first node and the second node; the first organic light emitting diode is connected between the seventh transistor and the second driving power supply; the second organic light emitting diode is connected between the eighth transistor and the second driving power supply; and the third organic light emitting diode is connected between the ninth transistor and the second driving power supply. The scan driver is connected to the first pixel through the scan line, the readout / initialization control line, the first light emitting control line, the second light emitting control line, the third light emitting control line and the fourth light emitting control line. The data driver is connected to the first pixel through the data line and is configured to supply a data voltage corresponding to the brightness through the data line. The readout circuit is connected to the first pixel through the readout line and is configured to read out the electrical characteristics of the plurality of pixels through the readout line.

[0009] According to another aspect of the embodiment, a display device includes: pixels arranged in rows and columns; a scan driver connected to the rows of pixels, wherein a first row of the rows of pixels is connected to the scan driver through a scan line, a first light-emitting control line, a second light-emitting control line, a third light-emitting control line, an initialization line, and a readout control line; a data driver connected to the columns of pixels, wherein a first column of the columns of pixels is connected to the scan driver through a data line; and a readout circuit connected to the columns of pixels and configured to read out electrical characteristics of the pixels through a readout line, wherein the first column is connected to the readout circuit through a readout line. A first pixel in the pixels includes: a first transistor including a first electrode connected to a first node, a second electrode connected to a third node, and a gate connected to the second node; a second transistor including a first electrode connected to a data line, a second electrode connected to the first node, and a gate connected to a scan line; a third transistor including a first electrode connected to a second node, a second electrode connected to a third node, and a gate connected to the scan line; a fourth transistor including a first electrode connected to a power supply node configured to supply a power supply voltage, a second electrode connected to the first node, and a gate connected to a first light emitting control line; a fifth transistor including a fifth electrode connected to a readout line, a second electrode connected to a second node, and a gate connected to an initialization line; a sixth transistor including a first electrode connected to a readout line, a second electrode connected to a third node, and a gate connected to a readout control line; a seventh transistor including a first electrode connected to a third node, a second electrode, and a gate connected to a second light emitting control line; an eighth transistor including a first electrode connected to a third node, a second electrode, and a gate connected to a third light emitting control line; a capacitor connected between the first node and the second node; a first organic light emitting diode connected between the second electrode of the seventh transistor and a ground node; and a second organic light emitting diode connected between the second electrode of the eighth transistor and the ground node. The frame of the first pixel includes a first subframe and a second subframe. The first pixel is configured to perform a reset operation, a programming operation, a holding operation, and a light emitting operation on the first organic light emitting diode in the first subframe, and the first pixel is configured to perform a reset operation, a programming operation, a holding operation, and a light emitting operation on the second organic light emitting diode in the second subframe. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects will be more clearly understood through the following description of embodiments in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram of a display device according to an embodiment; Figure 2 is a circuit diagram of an example of a pixel according to an embodiment; Figure 3A is a circuit diagram of a specific example of a pixel; Figure 3B is a circuit diagram of a specific example of a pixel group; Figure 4 is a block diagram of a display device according to an embodiment; Figure 5 is a block diagram of a display device according to an embodiment; Figure 6 is a timing diagram of a plurality of signals for controlling a pixel according to an embodiment; Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E and Figure 7F is a diagram illustrating the operation of a pixel according to an embodiment; Figures 8 to 12 is a timing diagram of a plurality of signals for controlling a pixel according to an embodiment; Fig.13A , Fig. 13B , Fig. 13C , Fig.13D and Fig.13E is a diagram illustrating the operation of a pixel according to an embodiment; Fig.14 It is shown Figure 3B A graph of the driving current of a pixel; Fig.15 is a graph showing a driving current of a pixel according to an embodiment; Fig.16A is a circuit diagram of an example of a pixel according to an embodiment; Fig. 16B is a timing diagram of a plurality of signals for controlling a pixel according to an embodiment; Fig.17 is a circuit diagram of an example of a pixel according to an embodiment; Fig.18 is a circuit diagram of an example of a pixel according to an embodiment; Fig.19 is a circuit diagram of an example of a pixel according to an embodiment; Fig. 20 is a circuit diagram of an example of a pixel according to an embodiment; Fig.21 is a circuit diagram of an example of a pixel according to an embodiment; Fig. 22 is a circuit diagram of an example of a pixel according to an embodiment; Fig.23 is a circuit diagram of an example of a pixel according to an embodiment; Fig.24 is a circuit diagram of an example of a pixel according to an embodiment; Fig.25A , Fig.25B and Fig.25C is a timing diagram of a plurality of signals for controlling a pixel according to an embodiment; Fig.26 is a graph showing changes in driving current corresponding to changes in data voltage of a pixel; Fig. 27 A display device according to an embodiment is shown; Fig.28 shows a display device according to an embodiment; and Fig.29 is a block diagram of an electronic device according to an embodiment. DETAILED DESCRIPTION

[0011] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings. Throughout the specification, the same components are represented by the same reference numerals, and their repeated description is omitted. It will be understood that when an element or layer is referred to as "on" another element or layer, "connected to" or "bonded to" another element or layer, it can be directly on another element or layer, directly connected or bonded to another element or layer, or there may be an intermediate element or layer. In contrast, when an element or layer is referred to as "directly on" another element or layer, "directly connected to" or "directly bonded to" another element or layer, there is no intermediate element or layer. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto, and can be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided herein or is not provided herein but consistent with the present disclosure.

[0012] Figure 1 is a block diagram of a display device according to an embodiment.

[0013] Reference Figure 1 , the display device 100 may include a display driver circuit 110 (which may be referred to as a display driver integrated circuit (IC)) and a display panel 120 .

[0014] In one embodiment, the display device 100 may be installed on an electronic device having an image display function. For example, the electronic device may include a smart phone, a tablet personal computer (PC), a portable multimedia player (PMP), a camera, a wearable device, a television, a digital video disk (DVD) player, a refrigerator, an air conditioner, an air purifier, a set-top box, a robot, a drone, various medical devices, a navigation device, an augmented reality (AR) device, a virtual reality (VR) device, a global positioning system (GPS) receiver, an advanced driver assistance system (ADAS), a vehicle device, furniture, or various measuring devices.

[0015] In one embodiment, the electronic device may include AR glasses, a head mounted display (HMD) device, a VR headset (VRH), or an AR helmet that is a glasses-shaped device worn on the face of a user.

[0016] The display device 100 may display image data received from the host. In one embodiment, the display device 100 may be a device in which the display driver circuit 110 and the display panel 120 are implemented as a single module. For example, the display driver circuit 110 may be mounted on a substrate of the display panel 120. Alternatively, the display driver circuit 110 and the display panel 120 may be electrically connected to each other through a connecting member such as a flexible printed circuit board (FPCB).

[0017] The display panel 120 may be a display unit on which an actual image is displayed. The display panel 120 may be one of various display devices (e.g., an organic light emitting diode (OLED) display, a thin film transistor liquid crystal display (TFT-LCD), a field emission display, and a plasma display panel (PDP)) that may receive an electrically transmitted image signal and display a two-dimensional (2D) image. Hereinafter, it is assumed that the display panel 120 is an OLED display panel (hereinafter, referred to as an OLED) in which each pixel includes an organic light emitting diode. However, the embodiment is not limited thereto, and the display panel 120 may be implemented as a flat panel display of different types or a flexible display panel.

[0018] The display panel 120 may be connected to the scan driver 113 through a plurality of first to seventh conductive lines. For example, the plurality of first conductive lines may include a plurality of scan lines SL. The plurality of second conductive lines may include a plurality of first light emission control lines. The plurality of third conductive lines may include a plurality of second light emission control lines. The plurality of fourth conductive lines may include a plurality of third light emission control lines. The plurality of fifth conductive lines may include a plurality of fourth light emission control lines. The plurality of sixth conductive lines may include a plurality of initialization lines. The plurality of seventh conductive lines may include a plurality of readout control lines. An example in which the display panel 120 is connected to the scan driver 113 through a plurality of first to seventh conductive lines is provided above, but the embodiment is not limited thereto, and in some embodiments, the display panel 120 may be connected to the scan driver 113 through different conductive lines. For example, the display panel 120 may be connected to the scan driver 113 through less than seven groups of multiple conductive lines or more than seven groups of multiple conductive lines.

[0019] The display panel 120 may be connected to the data driver 112 through a plurality of eighth conductive lines. The plurality of eighth conductive lines may include a plurality of data lines DL. The display panel 120 may be connected to the readout circuit 114 through a plurality of ninth conductive lines. The plurality of ninth conductive lines may include a plurality of readout lines ROL.

[0020] The display driver circuit 110 may receive image data IDT from the host. The display driver circuit 110 may convert the image data IDT into a plurality of analog signals (e.g., a plurality of data voltages) for driving the display panel 120. The display driver circuit 110 may apply the plurality of converted analog signals to the display panel 120. Therefore, an image corresponding to the image data IDT may be displayed on the display panel 120.

[0021] The display driver circuit 110 may include a control logic circuit 111, a data driver 112 (or source driver), a scan driver 113 (or gate driver), and a readout circuit 114. The display driver circuit 110 may also include other components (eg, interface circuits, memory, voltage generators, and clock generators).

[0022] In one embodiment, the control logic circuit 111, the data driver 112, the scan driver 113 and the readout circuit 114 may be integrated in one semiconductor chip. Alternatively, the control logic circuit 111, the data driver 112 and the readout circuit 114 may be formed in one semiconductor chip, and the scan driver 113 may be formed in the display panel 120.

[0023] The control logic circuit 111 may control all operations of the display driver circuit 110 and control components of the display driver circuit 110 (eg, a data driver 112 , a scan driver 113 , and a readout circuit 114 ) so that image data IDT received from a host is displayed on the display panel 120 .

[0024] In addition, the control logic circuit 111 may perform an image processing operation for brightness change, size change, and format change on the received image data IDT, or generate data on a new image to be displayed on the display panel 120 based on the received image data IDT. To this end, the control logic circuit 111 may include an intellectual property (IP) block for processing an image. For example, the IP block may include a circuit system for performing a specific function and may have a design including a trade secret.

[0025] The control logic circuit 111 may provide a data driver control signal to the data driver 112. The control logic circuit 111 may control the data driver 112 by using the data driver control signal. The control logic circuit 111 may provide a scan driver control signal to the scan driver 113. The control logic circuit 111 may control the scan driver 113 by using the scan driver control signal. Alternatively, the control logic circuit 111 may control a time point at which the scan driver 113 operates by using a timing signal.

[0026] The data driver 112 may be connected to the columns of the pixels PX through a plurality of data lines DL. The data driver 112 may receive image data from the control logic circuit 111. The image data may be information about the brightness (or luminance) of the pixels in a row. The data driver 112 may convert the received image data into a plurality of image signals (e.g., a plurality of data voltages VD1 to VDm). The data driver 112 may output the plurality of data voltages VD1 to VDm to the display panel 120 through the plurality of data lines DL.

[0027] The data driver 112 may receive image data in units of line data (i.e., in units of data corresponding to a plurality of pixels included in one horizontal line of the display panel). The data driver 112 may convert the line data received from the control logic circuit 111 into a plurality of data voltages VD1 to VDm (m is an integer of 2 or more). The data driver 112 may provide the plurality of data voltages VD1 to VDm corresponding to brightness to the display panel 120 through a plurality of data lines DL.

[0028] The scan driver 113 may be connected to a plurality of control lines. In one embodiment, the scan driver 113 may be connected to rows of pixels PX through a plurality of control lines. The plurality of control lines may include a plurality of scan lines SL, a plurality of first light emission control lines, a plurality of second light emission control lines, a plurality of third light emission control lines, a plurality of fourth light emission control lines, a plurality of initialization lines, and a plurality of readout control lines.

[0029] The scan driver 113 may receive a scan driver control signal from the control logic circuit 111. In response to the scan driver control signal received from the control logic circuit 111, the scan driver 113 may output a plurality of control signals to the display panel 120 through a plurality of control lines. For example, the scan driver 113 may be connected to a plurality of scan lines SL of the display panel 120, and sequentially drive (or select) the plurality of scan lines SL of the display panel 120.

[0030] The scan driver 113 may sequentially provide scan signals S1 to Sn (n is a positive integer of 2 or more) having an active level (e.g., logic low) to the plurality of scan lines SL under the control of the control logic circuit 111. Thus, the plurality of scan lines SL may be sequentially selected, and the plurality of data voltages VD1 to VDm may be applied to the plurality of pixels PX connected to the selected scan lines SL.

[0031] In one embodiment, the scan driver 113 may provide a plurality of control signals to the pixel PX. The plurality of control signals may include a scan signal, a first light emitting control signal, a second light emitting control signal, a third light emitting control signal, a fourth light emitting control signal, an initialization signal, and a readout control signal. For example, the scan driver 113 may provide the scan signal to the pixel PX through the scan line SL. The scan driver 113 may provide the first light emitting control signal to the pixel PX through the first light emitting control line. The scan driver 113 may provide the second light emitting control signal to the pixel PX through the second light emitting control line. The scan driver 113 may provide the third light emitting control signal to the pixel PX through the third light emitting control line. The scan driver 113 may provide the fourth light emitting control signal to the pixel PX through the fourth light emitting control line. The scan driver 113 may provide the initialization signal to the pixel PX through the initialization line. The scan driver 113 may provide the readout control signal to the pixel PX through the readout control line.

[0032] The readout circuit 114 may be connected to the columns of the pixels PX through a plurality of readout lines ROL. For example, the readout circuit 114 may be connected to a plurality of readout lines ROL. The readout circuit 114 may receive a plurality of readout signals RO1 to ROm from the display panel 120 through the plurality of readout lines ROL. In one embodiment, the readout circuit 114 may include an amplifier, a sample / hold circuit, and an analog-to-digital converter (ADC).

[0033] In one embodiment, the readout circuit 114 may read (or sense) the electrical characteristics of each of the plurality of pixels PX. The readout circuit 114 may receive a plurality of readout signals RO1 to ROm through a plurality of readout lines ROL. The plurality of readout signals RO1 to ROm may represent the electrical characteristics of the pixels PX connected to the plurality of readout lines ROL. The readout circuit 114 may receive the readout signals RO1 to ROm corresponding to the selected pixels PX, and perform an analog-to-digital conversion (ADC) operation on the readout signals RO1 to ROm to generate readout data. The readout circuit 114 may provide the generated readout data to the control logic circuit 111.

[0034] For example, the readout circuit 114 may detect a driving current of each of the plurality of pixels PX. The readout circuit 114 may detect a threshold voltage of each of the plurality of pixels PX. The readout circuit 114 may detect a forward voltage of each of the plurality of pixels PX.

[0035] The readout circuit 114 may measure the magnitude of the driving current of each of the plurality of pixels PX. The readout circuit 114 may measure the magnitude of the threshold voltage of each of the plurality of pixels PX. The readout circuit 114 may measure the magnitude of the forward voltage of each of the plurality of pixels PX.

[0036] The display panel 120 may include pixels PX arranged in rows and columns. The display panel 120 may include a plurality of data lines DL, a plurality of scan lines SL, and a plurality of pixels PX arranged between the plurality of data lines DL and the plurality of scan lines SL. Each of the plurality of pixels PX may be connected to the scan line SL and the data line DL corresponding thereto.

[0037] The row of pixels PX may be connected to a plurality of control lines. Each of the plurality of pixels PX may be connected to a scan line, a first light emission control line, a second light emission control line, a third light emission control line, a fourth light emission control line, an initialization line, and a readout control line. Each of the plurality of pixels PX may receive a plurality of control signals (e.g., a first control signal to a seventh control signal) from the scan driver 113 through the plurality of control lines. For example, the first control signal may include a scan signal, the second control signal may include a first light emission control signal, the third control signal may include a second light emission control signal, the fourth control signal may include a third light emission control signal, the fifth control signal may include a fourth light emission control signal, the sixth control signal may include an initialization signal, and the seventh control signal may include a readout control signal.

[0038] Each of the plurality of pixels PX may receive a scan signal through the scan line SL. Each of the plurality of pixels PX may receive a first light emission control signal through a first light emission control line, a second light emission control signal through a second light emission control line, a third light emission control signal through a third light emission control line, a fourth light emission control signal through a fourth light emission control line, an initialization signal through an initialization line, and a readout control signal through a readout control line.

[0039] In one embodiment, the display panel 120 may be connected to a plurality of readout lines ROL. The display panel 120 may provide a plurality of readout signals RO1 to ROm to the readout circuit 114 through the plurality of readout lines ROL.

[0040] Each of the plurality of pixels PX may adjust its brightness in response to a control signal corresponding thereto. For example, each of the plurality of pixels PX may be selected in response to a corresponding one of a plurality of scan signals S1 to Sn. A selected one of the plurality of pixels PX may emit light based on a corresponding one of a plurality of data voltages VD1 to VDm. Each of the plurality of pixels PX may include a light emitting element (e.g., an OLED) and a transistor configured to control the light emitting element.

[0041] In one embodiment, each of the plurality of pixels PX may include a plurality of OLEDs. For example, each of the plurality of pixels PX may include three OLEDs, but the embodiment is not limited thereto. The number of OLEDs included in the pixel PX may be reduced or increased according to the implementation. Each of the plurality of pixels PX may drive the plurality of OLEDs by time division multiplexing.

[0042] Each of the plurality of pixels PX may output light of a preset color, and at least two pixels (e.g., a red pixel, a blue pixel, and a green pixel) that are adjacent to each other in the same line or adjacent lines and output light of different colors may constitute one unit pixel. In this case, the at least two pixels PX included in the unit pixel may be referred to as sub-pixels. The display panel 120 may have an RGB structure in which a red pixel, a blue pixel, and a green pixel constitute one unit pixel. However, the embodiment is not limited thereto, and the display panel 120 may have an RGBW structure in which the unit pixel further includes a white pixel to increase brightness. Alternatively, the unit pixel of the display panel 120 may include a combination of pixels of colors other than red, green, and blue.

[0043] The display panel 120 may be an OLED display panel in which each of the plurality of pixels PX includes an OLED. However, the embodiment is not limited thereto, and the display panel 120 may be implemented as a different type of flat panel display or a flexible display panel.

[0044] Figure 2 is a circuit diagram of an example of a pixel according to the embodiment. Figure 2 The pixel PX1 can be applied to Figure 1 A display device 100 is provided. Figure 1 Each pixel PX may include Figure 2 Pixel PX1.

[0045] Reference Figure 1 and Figure 2, the pixel PX1 may include a first OLED OD1, a second OLED OD2, a third OLED OD3, and a pixel circuit PCIR. The pixel PX1 may include a scan line SL extending in a first direction D1, a first light emission control line EL1 extending in the first direction D1, a second light emission control line EL2 extending in the first direction D1, a third light emission control line EL3 extending in the first direction D1, a fourth light emission control line EL4 extending in the first direction D1, an initialization line INTL extending in the first direction D1, a readout control line RL extending in the first direction D1, a data line DL and a readout line ROL extending in a second direction D2 intersecting the first direction D1, first to ninth transistors T1 to T9, a storage capacitor CST, and first to third OLEDs OD1 to OD3. That is, the pixel PX1 may include three OLEDs, nine transistors, seven control lines extending in the first direction D1 (i.e., a scan line SL, a first light emission control line EL1, a second light emission control line EL2, a third light emission control line EL3, a fourth light emission control line EL4, an initialization line INTL, and a readout control line RL) and two lines extending in the second direction D2 (i.e., a data line DL and a readout line ROL). For example, the first direction D1 may be an X-axis direction, and the second direction D2 may be a Y-axis direction.

[0046] The anode electrode of each of the first to third OLEDs OD1, OD2, and OD3 may be connected to the pixel circuit PCIR, and the cathode electrode of each of the first to third OLEDs OD1, OD2, and OD3 may be connected to the second driving power source ELVSS (or a ground node to which a ground voltage is applied). The first to third OLEDs OD1, OD2, and OD3 may emit light having a brightness corresponding to the amount of current supplied from the pixel circuit PCIR. The brightness of the first to third OLEDs OD1, OD2, and OD3 may be controlled by the voltage of the data line DL (i.e., the data voltage VD). For example, the first OLED OD1 may output red light, the second OLED OD2 may output blue light, and the third OLED OD3 may output green light.

[0047] In response to the data voltage VD, the pixel circuit PCIR may control the amount of current flowing from the first driving power source ELVDD to the second driving power source ELVSS via each of the first to third OLEDs OD1, OD2, and OD3. The pixel circuit PCIR may include a first transistor T1 to a ninth transistor T9 and a storage capacitor CST. At least one of the first transistor T1 to the ninth transistor T9 may be implemented as an oxide semiconductor thin film transistor (TFT) including an active layer including an oxide semiconductor, a low temperature polycrystalline silicon (LTPS) TFT including an active layer including polycrystalline silicon, or a metal oxide semiconductor field effect transistor (MOSFET). In one embodiment, at least one of the first transistor T1 to the ninth transistor T9 may be formed as a P-type transistor. In some embodiments, each of the first transistor T1 to the ninth transistor T9 may be formed as a P-type transistor. However, the embodiment is not limited thereto, and at least one of the first transistor T1 to the ninth transistor T9 may be formed as an N-type transistor. In some embodiments, each of the first transistor T1 to the ninth transistor T9 may be formed as an N-type transistor.

[0048] The first transistor T1 may be referred to as a driving transistor, and may be connected between the first node N1 and the third node N3, and operate in response to the voltage of the second node N2. The first electrode (or first terminal) of the first transistor T1 may be connected to the first node N1, and the second electrode (or second terminal) of the first transistor T1 may be connected to the third node N3. The gate electrode (or gate) of the first transistor T1 may be connected to the second node N2. In response to the voltage of the second node N2, the first transistor T1 may control the amount of current flowing from the first driving power source ELVDD to the second driving power source ELVSS via each of the first to third OLEDs OD1, OD2, and OD3.

[0049] The second transistor T2 (or the selection transistor) may be connected between the data line DL and the first node N1, and operate in response to the scan signal S. A first electrode of the second transistor T2 may be connected to the data line DL, and a second electrode of the second transistor T2 may be connected to the first node N1. A gate electrode of the second transistor T2 may be connected to the scan line SL. In response to the scan signal S provided at an active level through the scan line SL, the second transistor T2 may be turned on. The second transistor T2 may be turned on, and thus, the first node N1 may be electrically connected to the data line DL.

[0050] The third transistor T3 may be connected between the second node N2 and the third node N3, and operate in response to the scan signal S. The first electrode of the third transistor T3 may be connected to the second node N2, and the second electrode of the third transistor T3 may be connected to the third node N3. The gate electrode of the third transistor T3 may be connected to the scan line SL. In response to the scan signal S provided at an effective level through the scan line SL, the third transistor T3 may be turned on. The third transistor T3 may be turned on, and thus, the second node N2 may be electrically connected to the third node N3. That is, the third transistor T3 may be diode-connected to the first transistor T1.

[0051] The fourth transistor T4 may be connected between the first driving power source ELVDD and the first node N1, and operate in response to the first light emission control signal E1. The first electrode of the fourth transistor T4 may be connected to the first driving power source ELVDD (or a power supply node to which the power supply voltage is supplied), and the second electrode of the fourth transistor T4 may be connected to the first node N1. The gate electrode of the fourth transistor T4 may be connected to the first light emission control line EL1. In response to the first light emission control signal E1 provided at an effective level through the first light emission control line EL1, the fourth transistor T4 may be turned on. The fourth transistor T4 may be turned on, and thus, the voltage of the first driving power source ELVDD may be provided (or supplied) to the first node N1.

[0052] The fifth transistor T5 may be connected between the readout line ROL and the second node N2, and operate in response to the initialization signal INT. The first electrode of the fifth transistor T5 may be connected to the readout line ROL, and the second electrode of the fifth transistor T5 may be connected to the second node N2. The gate electrode of the fifth transistor T5 may be connected to the initialization line INTL. In response to the initialization signal INT provided at an effective level through the initialization line INTL, the fifth transistor T5 may be turned on. The fifth transistor T5 may be turned on, and thus, the voltage of the initialization power supply VINT may be provided to the second node N2.

[0053] The sixth transistor T6 may be connected between the readout line ROL and the third node N3, and operate in response to the readout control signal R. A first electrode of the sixth transistor T6 may be connected to the readout line ROL, and a second electrode of the sixth transistor T6 may be connected to the third node N3. A gate electrode of the sixth transistor T6 may be connected to the readout control line RL. In response to the readout control signal R provided at an active level through the readout control line RL, the sixth transistor T6 may be turned on. The sixth transistor T6 may be turned on, and thus, the third node N3 may be electrically connected to the readout line ROL.

[0054] The seventh transistor T7 may be connected between the third node N3 and the first OLED OD1, and operate in response to the second light emitting control signal E2. A first electrode of the seventh transistor T7 may be connected to the third node N3, and a second electrode of the seventh transistor T7 may be connected to the anode electrode of the first OLED OD1. A gate electrode of the seventh transistor T7 may be connected to the second light emitting control line EL2. In response to the second light emitting control signal E2 provided at an effective level through the second light emitting control line EL2, the seventh transistor T7 may be turned on. The seventh transistor T7 may be turned on, and thus, the third node N3 may be electrically connected to the anode electrode of the first OLED OD1.

[0055] The eighth transistor T8 may be connected between the third node N3 and the second OLED OD2, and operate in response to the third light emission control signal E3. A first electrode of the eighth transistor T8 may be connected to the third node N3, and a second electrode of the eighth transistor T8 may be connected to the anode electrode of the second OLED OD2. A gate electrode of the eighth transistor T8 may be connected to the third light emission control line EL3. In response to the third light emission control signal E3 provided at an effective level through the third light emission control line EL3, the eighth transistor T8 may be turned on. The eighth transistor T8 may be turned on, and thus, the third node N3 may be electrically connected to the anode electrode of the second OLED OD2.

[0056] The ninth transistor T9 may be connected between the third node N3 and the third OLED OD3, and operate in response to the fourth light emitting control signal E4. The first electrode of the ninth transistor T9 may be connected to the third node N3, and the second electrode of the ninth transistor T9 may be connected to the anode electrode of the third OLED OD3. The gate electrode of the ninth transistor T9 may be connected to the fourth light emitting control line EL4. In response to the fourth light emitting control signal E4 provided at an effective level through the fourth light emitting control line EL4, the ninth transistor T9 may be turned on. The ninth transistor T9 may be turned on, and therefore, the third node N3 may be electrically connected to the anode electrode of the third OLED OD3. The storage capacitor CST may be connected between the first node N1 and the second node N2.

[0057] In one embodiment, the pixel PX1 may be time-division multiplexed, and one frame may be divided into a plurality of subframes. The number of subframes may be equal to the number of OLEDs included in the pixel PX1. For example, one frame may include three subframes. Each subframe may include a reset interval, a programming interval, a holding interval, and a light-emitting interval. The first subframe may correspond to the first OLED OD1, the second subframe may correspond to the second OLED OD2, and the third subframe may correspond to the third OLED OD3. For example, the pixel PX1 may perform an operation of causing the first OLED OD1 to emit light in the first subframe, an operation of causing the second OLED OD2 to emit light in the second subframe, and an operation of causing the third OLED OD3 to emit light in the third subframe.

[0058] In one embodiment, the pixel PX1 may perform a reset operation in a reset interval. In the reset interval, the voltage of the initialization power supply VINT may be applied to the third node N3 through the readout line ROL. After the reset interval, in the programming interval, the pixel PX1 may perform a programming operation. In the programming interval, the data voltage VD may be applied to the first node N1 through the data line DL. After the programming interval, in the holding interval, the pixel PX1 may perform a holding operation. In the holding interval, the second transistor T2 to the ninth transistor T9 may all be turned off. After the holding interval, in the light-emitting interval, the pixel PX1 may perform a light-emitting operation.

[0059] In one embodiment, the light-emitting interval may include a first light-emitting interval to a third light-emitting interval. In the first light-emitting interval, the pixel PX1 may perform a first light-emitting operation. In the second light-emitting interval, the pixel PX1 may perform a second light-emitting operation. In the third light-emitting interval, the pixel PX1 may perform a third light-emitting operation. In the first light-emitting interval, the fourth transistor T4 and the seventh transistor T7 may be turned on, so that the driving current ID may be supplied to the first OLED OD1, and the first OLED OD1 may emit light having a brightness corresponding to the driving current ID. In the second light-emitting interval, the fourth transistor T4 and the eighth transistor T8 may be turned on, so that the driving current ID may be supplied to the second OLED OD2, and the second OLED OD2 may emit light having a brightness corresponding to the driving current ID. In the third light-emitting interval, the fourth transistor T4 and the ninth transistor T9 may be turned on, so that the driving current ID may be supplied to the third OLED OD3, and the third OLED OD3 may emit light having a brightness corresponding to the driving current ID.

[0060] In one embodiment, the voltage of the first driving power source ELVDD may be higher than the voltage of the second driving power source ELVSS. The voltage of the initialization power source VINT may be lower than the voltage obtained by reducing the threshold voltage VTH of the first transistor T1 from the voltage of the first driving power source ELVDD. That is, the voltage of the initialization power source VINT may be as expressed in Equation 1: [Equation 1] In one embodiment, the pixel PX1 may include a first parasitic capacitor between the gate of the second transistor T2 and the second electrode of the second transistor T2 (ie, the first node N1). The pixel PX1 may include a second parasitic capacitor between the gate of the third transistor T3 and the first electrode of the third transistor T3 (ie, the second node N2). The range of the data voltage VD may increase according to the first parasitic capacitor and the second parasitic capacitor.

[0061] The pixel PX1 can expand the range of the data voltage VD that has been reduced for a small area and a high resolution by using the first parasitic capacitor, the second parasitic capacitor, and the storage capacitor CST. Therefore, the display device 100 can easily adjust the brightness of the pixel.

[0062] In the pixel PX1 according to the embodiment, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 can be operated independently. The scan driver 113 can independently control the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9. The gate of the fourth transistor T4 can be connected to the first light emission control line EL1, the gate of the seventh transistor T7 can be connected to the second light emission control line EL2, the gate of the eighth transistor T8 can be connected to the third light emission control line EL3, and the gate of the ninth transistor T9 can be connected to the fourth light emission control line EL4.

[0063] The fourth transistor T4 may operate in response to the first light emitting control signal E1, the seventh transistor T7 may operate in response to the second light emitting control signal E2, the eighth transistor T8 may operate in response to the third light emitting control signal E3, and the ninth transistor T9 may operate in response to the fourth light emitting control signal E4. The second light emitting control signal E2 may be different from the first light emitting control signal E1, the third light emitting control signal E3 may be different from the first light emitting control signal E1, the third light emitting control signal E3 may be different from the second light emitting control signal E2, the fourth light emitting control signal E4 may be different from the first light emitting control signal E1, the fourth light emitting control signal E4 may be different from the second light emitting control signal E2, and the fourth light emitting control signal E4 may be different from the third light emitting control signal E3. The scan driver 113 may independently control each of the first light emitting control signal E1, the second light emitting control signal E2, the third light emitting control signal E3, and the fourth light emitting control signal E4. Therefore, the display device 100 may implement pulse width modulation (PWM) by adjusting the light emitting time of the first OLED OD1, the second OLED OD2, and the third OLED OD3. Referring to FIG. 25A to FIG. 25C Provides a detailed description of PWM.

[0064] In the pixel PX1 according to the embodiment, the sixth transistor T6 may provide the readout signal RO to the readout circuit (refer to Figure 1 114 in FIG). In response to the readout control signal R, the pixel PX1 may output the readout signal RO to the readout line ROL. That is, the pixel PX1 may perform a readout operation in the readout interval.

[0065] The readout operation may be an operation of testing the electrical characteristics of a pixel. The display device 100 may perform the readout operation in a test operation of a manufacturing process. Alternatively, the readout operation may be used to measure the degree of degradation of the pixel over time when the display device 100 is in use, and to compensate for the degradation.

[0066] In one embodiment, the readout circuit 114 may detect a driving current, a threshold voltage, or a forward voltage. The readout interval may include a first readout interval RO_1 to a fifth readout interval RO_5. The first readout interval RO_1 may be an interval for measuring a driving current ID, the second readout interval RO_2 may be an interval for measuring a threshold voltage VTH, the third readout interval RO_3 may be an interval for measuring a forward voltage VF of the first OLED OD1, the fourth readout interval RO_4 may be an interval for measuring a forward voltage VF of the second OLED OD2, and the fifth readout interval RO_5 may be an interval for measuring a forward voltage VF of the third OLED OD3. A detailed description of the readout operation and the readout intervals is provided below.

[0067] The pixel PX1 may include a plurality of OLEDs. The pixel circuit PCIR may drive the plurality of OLEDs. Therefore, the number of transistors may be reduced compared to a pixel circuit configured to drive one OLED. Therefore, a display device having a small area and high resolution may be provided.

[0068] In one embodiment, the size of the first transistor T1 may be increased. That is, because the number of transistors is reduced, the width / length (W / L) size of the first transistor T1 may be increased when implemented with the same area. Therefore, mismatch performance may be improved.

[0069] As described above, the display device 100 according to the embodiment can expand the range of the data voltage and easily adjust the brightness of the pixel. The display device 100 can control dimming through a pulse amplitude modulation (PAM) scheme and a PWM scheme, and improve the brightness expression (or grayscale). The display device 100 can measure the driving current, threshold voltage or forward voltage at the wafer or package level through a guaranteed design for testability (DFT) path, and implement DFT. By sharing the pixel circuit PCIR between multiple OLEDs, a display device with a small area and high resolution can be provided.

[0070] Figure 3A is a circuit diagram of a specific example of a pixel.

[0071] Reference Figure 3A , the pixel PXa may include an OLED OD and a pixel circuit PCIR. An anode electrode of the OLED OD may be connected to the pixel circuit PCIR, and a cathode electrode of the OLED OD may be connected to a second driving power source ELVSS. The OLED OD may emit light having a brightness corresponding to the amount of current supplied from the pixel circuit PCIR.

[0072] The pixel circuit PCIR may control the amount of current flowing from the first driving power source ELVDD to the second driving power source ELVSS via the OLED OD in response to the data voltage VD. The pixel circuit PCIR may include a first transistor T1, a second transistor T2, and a storage capacitor CST.

[0073] A first electrode of the first transistor T1 may be connected to a first driving power source ELVDD, and a second electrode of the first transistor T1 may be connected to an anode electrode of the OLED OD. A gate electrode of the first transistor T1 may be connected to a second node N2. In response to a voltage of the second node N2, the first transistor T1 may control an amount of current flowing from the first driving power source ELVDD to the second driving power source ELVSS via the OLED OD.

[0074] A first electrode of the second transistor T2 may be connected to the data line DL, and a second electrode of the second transistor T2 may be connected to the second node N2. A gate electrode of the second transistor T2 may be connected to the scan line SL. A storage capacitor CST may be connected between the first node N1 and the second node N2.

[0075] A scan signal (i.e., a scan signal S at an active level) may be applied through the scan line SL. The second transistor T2 may be turned on in response to the scan signal S at an active level. The second transistor T2 may be turned on and provide a data voltage VD provided through the data line DL to the second node N2. The first transistor T1 may provide a driving current ID to the OLED OD in response to the data voltage VD.

[0076] Figure 3B is a circuit diagram of a specific example of a pixel group.

[0077] Reference Figure 3B , the pixel group PG may include a plurality of pixels (e.g., PXb1, PXb2, and PXb3). The first pixel PXb1 may include a first pixel circuit PCIR1 and a first OLED OD1, the second pixel PXb2 may include a second pixel circuit PCIR2 and a second OLED OD2, and the third pixel PXb3 may include a third pixel circuit PCIR3 and a third OLED OD3. The configuration of the first pixel PXb1 will now be described. The following description may also be applied to the second pixel PXb2 and the third pixel PXb3.

[0078] Each of the first to third pixels PXb1 to PXb3 may include a first OLED OD1 and a first pixel circuit PCIR1. The first pixel PXb1 may include a scan line SL, a first light emission control line EL1, a second light emission control line EL2, an initialization line INTL, a readout control line RL, a data line DL (e.g., DL1, DL2, or DL3), a readout line ROL (e.g., ROL1, ROL2, or ROL3), a first to seventh transistors T1 to T7, a storage capacitor CST, and a first OLED OD1. The first pixel PXb1 may include seven transistors, five control lines extending in a first direction (i.e., a scan line SL, a first light emission control line EL1, a second light emission control line EL2, an initialization line INTL, and a readout control line RL) and two lines extending in a second direction (i.e., a data line DL and a readout line ROL).

[0079] An anode electrode of the first OLED OD1 may be connected to the first pixel circuit PCIR1, and a cathode electrode of the first OLED OD1 may be connected to the second driving power source ELVSS. The first OLED OD1 may emit light having brightness corresponding to the amount of current supplied from the first pixel circuit PCIR1. The brightness of the first OLED OD1 may be controlled by a voltage of the first data line DL1 (ie, a first data voltage VD1).

[0080] The first pixel circuit PCIR1 may control the amount of current flowing from the first driving power source ELVDD to the second driving power source ELVSS via the first OLED OD1 in response to the first data voltage VD1. The first pixel circuit PCIR1 may include first to seventh transistors T1 to T7 and a storage capacitor CST.

[0081] The first transistor T1 may be connected between the first node N1 and the third node N3 and operate in response to the voltage of the second node N2. The first transistor T1 may control the amount of current flowing from the first driving power ELVDD to the second driving power ELVSS via the first OLED OD1 in response to the voltage of the second node N2.

[0082] The second transistor T2 may be connected between the first data line DL1 and the first node N1 and operate in response to the scan signal S. The second transistor T2 may be turned on in response to the scan signal S provided at an active level through the scan line SL. The second transistor T2 may be turned on, and thus, the first node N1 may be electrically connected to the first data line DL1.

[0083] The third transistor T3 may be connected between the second node N2 and the third node N3 and operate in response to the scan signal S. The third transistor T3 may be turned on in response to the scan signal S provided at an active level through the scan line SL. The third transistor T3 may be turned on, so that the second node N2 may be electrically connected to the third node N3. That is, the third transistor T3 may be diode-connected to the first transistor T1.

[0084] The fourth transistor T4 may be connected between the first driving power source ELVDD and the first node N1 and operate in response to the first light emission control signal E1. The fourth transistor T4 may be turned on in response to the first light emission control signal E1 provided at an active level through the first light emission control line EL1. The fourth transistor T4 may be turned on, and thus, the voltage of the first driving power source ELVDD may be provided to the first node N1.

[0085] The fifth transistor T5 may be connected between the first readout line ROL1 and the second node N2 and operate in response to the initialization signal INT. The fifth transistor T5 may be turned on in response to the initialization signal INT provided at an active level through the initialization line INTL. The fifth transistor T5 may be turned on, and thus, the voltage of the initialization power supply VINT may be provided to the second node N2.

[0086] The sixth transistor T6 may be connected between the first readout line ROL1 and the third node N3 and operate in response to the readout control signal R. The sixth transistor T6 may be turned on in response to the readout control signal R provided at an active level through the readout control line RL. The sixth transistor T6 may be turned on, and thus, the third node N3 may be electrically connected to the first readout line ROL1. The storage capacitor CST may be connected between the first node N1 and the second node N2.

[0087] The seventh transistor T7 may be connected between the third node N3 and the first OLED OD1 and operate in response to the second light emission control signal E2. The seventh transistor T7 may be turned on in response to the second light emission control signal E2 provided at an active level through the second light emission control line EL2. The seventh transistor T7 may be turned on, and thus, the third node N3 may be electrically connected to the anode electrode of the first OLED OD1.

[0088] Compared with the first pixel PXb1, Figure 2 The pixel PX1 may further include more OLEDs and transistors. Compared with the first pixel PXb1, Figure 2 The pixel PX1 may further include a plurality of OLEDs (eg, OD2 and OD3) and a plurality of transistors (eg, T8 and T9). Each of the eighth transistor T8 and the ninth transistor T9 may be connected between the OLED corresponding thereto and the third node N3. For example, Figure 2 The eighth transistor T8 may be connected between the third node N3 and the second OLED OD2, and Figure 2 The ninth transistor T9 may be connected between the third node N3 and the third OLED OD3.

[0089] The first pixel PXb1 may include an OLED, and Figure 2 The pixel PX1 may include a plurality of OLEDs (eg, OD1, OD2, and OD3). For example, the pixel PX1 may include an OLED. The pixel group PG may include first to third OLEDs OD1 to OD3. The pixel group PG may drive the first to third OLEDs OD1 to OD3 by using the first to third pixel circuits PCIR1 to PCIR3. That is, three pixel circuits may be required to drive three OLEDs. Because Figure 3BEach of the first to third pixel circuits PCIR1 to PCIR3 includes a total of seven transistors, so a total of 21 transistors may be required to drive the first to third OLEDs OD1 to OD3. In contrast, Figure 2 The pixel PX1 of the embodiment can drive the first OLED OD1 to the third OLED OD3 by using the pixel circuit PCIR. That is, one circuit may be required to drive three OLEDs. Since the pixel circuit PCIR of the pixel PX1 includes a total of nine transistors, a total of nine transistors may be required to drive the first OLED OD1 to the third OLED OD3. In the display device according to the embodiment, the number of transistors required for the same number of OLEDs to emit light can be reduced, and therefore, the size of the pixel can be reduced. Therefore, a display device with a small area and high resolution can be provided.

[0090] Figure 4 is a block diagram of a display device according to an embodiment.

[0091] Reference Figure 4 , the display device 100a may include a readout circuit 114, a selection circuit 115 and a display panel 120. For the sake of simplicity, Figure 4 Only the readout circuit 114, the selection circuit 115 and the display panel 120 are shown. However, the embodiment is not limited thereto, and the display device 100a may further include other components (eg, Figure 1 The display device 100a includes a control logic circuit 111, a data driver 112 and a scan driver 113).

[0092] Reference Figure 1 , Figure 2 and Figure 4 , Figure 1 The display driver circuit 110 may further include a selection circuit 115. The selection circuit 115 may connect the readout line ROL to the initialization power source VINT or connect the readout line ROL to the readout circuit 114. That is, the selection circuit 115 may connect the readout line ROL to any one of the initialization power source VINT and the readout circuit 114.

[0093] In the reset section, the selection circuit 115 may be electrically connected to the readout line ROL and the initialization power source VINT. In the reset section, the selection circuit 115 may provide the voltage of the initialization power source VINT to the pixel PX through the readout line ROL.

[0094] In the readout section, the selection circuit 115 may be electrically connected to the readout line ROL and the readout circuit 114. In the readout section, the selection circuit 115 may transmit a plurality of readout signals RO1 to ROm received through the plurality of readout lines ROL to the readout circuit 114.

[0095] Figure 5 is a block diagram of a display device according to an embodiment.

[0096] For the sake of brevity, Figure 5 Only pixels in one column are shown in FIG. 1 , and a readout circuit 114, a selection circuit 115, and a display panel 120 are shown. The display device 100a may also include other components (eg, Figure 1 The display device 100a includes a control logic circuit 111, a data driver 112 and a scan driver 113).

[0097] The first switch SW1 may be connected between the fourth node N4 and the initialization power supply VINT. The first switch SW1 may be connected between the readout line ROL and the initialization power supply node to which the initialization voltage is applied. The second switch SW2 may be connected between the fourth node N4 and the readout circuit 114. The second switch SW2 may be connected between the readout line ROL and the readout circuit 114. The pixel PX may be connected to the fourth node N4 through the corresponding readout line ROL.

[0098] In one embodiment, Figure 1 The scan driver 113 may control the first switch SW1 and the second switch SW2. The scan driver 113 may output a signal for driving the first switch SW1 and the second switch SW2.

[0099] In the reset interval, the first switch SW1 may be turned on and the second switch SW2 may be turned off. When the first switch SW1 is turned on and the second switch SW2 is turned off, the voltage of the initialization power source VINT may be provided to the pixel PX through the readout line ROL.

[0100] In the readout section, the first switch SW1 may be turned off and the second switch SW2 may be turned on. When the first switch SW1 is turned off and the second switch SW2 is turned on, the readout signals RO1 to ROm may be output to the readout circuit 114 through the readout line ROL.

[0101] In the first readout interval, the readout circuit 114 may generate data corresponding to the driving current based on the signal received through the readout line ROL. In the second readout interval, the readout circuit 114 may generate data corresponding to the threshold voltage based on the signal received through the readout line ROL. In the third readout interval, the readout circuit 114 may generate data corresponding to the forward voltage of the first OLED OD1 based on the signal received through the readout line ROL. In the fourth readout interval, the readout circuit 114 may generate data corresponding to the forward voltage of the second OLED OD2 based on the signal received through the readout line ROL. In the fifth readout interval, the readout circuit 114 may generate data corresponding to the forward voltage of the third OLED OD3 based on the signal received through the readout line ROL.

[0102] Figure 6 is a timing diagram of a plurality of signals for controlling a pixel according to an embodiment. 7A to 7F is a diagram showing the operation of a pixel according to an embodiment. A plurality of signals may be provided to Figure 2 The pixel PX1, and refer to Figure 2 Give a description.

[0103] The scan driver 113 may provide a plurality of control signals to the display panel 120 through a plurality of control lines. The scan driver 113 may control the pixel PX1 by using a plurality of control signals. The display device 100 may operate based on a frame. Each frame may include a plurality of subframes. The number of subframes may be equal to the number of OLED ODs in the pixel PX1. Each subframe may include a reset interval RST, a programming interval PRG, a holding interval H, and a light emitting interval EM.

[0104] In one embodiment, the pixel PX1 may be time-division multiplexed. A plurality of light-emitting operations may be performed in one frame of the pixel PX1. For example, in one frame, the pixel PX1 may perform a light-emitting operation on the first OLED OD1, then perform a light-emitting operation on the second OLED OD2, and then perform a light-emitting operation on the third OLED OD3. One frame may be divided into a plurality of subframes, and a reset operation, a programming operation, a holding operation, and a light-emitting operation may be performed in each subframe.

[0105] In one embodiment, the frame may include first to third subframes SF1, SF2, and SF3. The pixel PX1 may include a plurality of OLEDs (e.g., OD1, OD2, and OD3). Since the pixel PX1 includes three OLEDs, the frame may include three subframes (i.e., SF1, SF2, and SF3). The first subframe SF1 may include a reset interval RST, a programming interval PRG, a holding interval H, and a first light-emitting interval EM1. The second subframe SF2 may include a reset interval RST, a programming interval PRG, a holding interval H, and a second light-emitting interval EM2. The third subframe SF3 may include a reset interval RST, a programming interval PRG, a holding interval H, and a third light-emitting interval EM3.

[0106] In each of the subframes SF1 to SF3, the scan driver 113 may output a control signal so that the OLED corresponding to the subframe emits light. For example, the first subframe SF1 may correspond to the first OLED OD1, the second subframe SF2 may correspond to the second OLED OD2, and the third subframe SF3 may correspond to the third OLED OD3. The scan driver 113 may control the first OLED OD1 to emit light in the first subframe SF1, control the second OLED OD2 to emit light in the second subframe SF2, and control the third OLED OD3 to emit light in the third subframe SF3. In the first subframe SF1, the pixel PX1 may perform a reset operation, a programming operation, a holding operation, and a light emitting operation related to the first OLED OD1. In the second subframe SF2, the pixel PX1 may perform a reset operation, a programming operation, a holding operation, and a light emitting operation related to the second OLED OD2. In the third subframe SF3, the pixel PX1 may perform a reset operation, a programming operation, a holding operation, and a light emitting operation related to the third OLED OD3.

[0107] In this regard, a plurality of OLEDs may share the pixel circuit PCIR by time division multiplexing. The pixel circuit PCIR may drive the first OLED OD1 in the first subframe SF1, the pixel circuit PCIR may drive the second OLED OD2 in the second subframe SF2, and the pixel circuit PCIR may drive the third OLED OD3 in the third subframe SF3.

[0108] The scan signal S may be logic high (e.g., at a high level, a first level, an invalid level, or a cut-off level) from the first time point t1 to the fourth time point t4, and the scan signal S may be logic low (e.g., at a low level, a second level, an effective level, or a conduction level) from the fourth time point t4 to the fifth time point t5. The scan signal S may be logic high from the fifth time point t5 to the tenth time point t10. The scan signal S may be logic low from the tenth time point t10 to the eleventh time point t11. The scan signal S may be logic high from the eleventh time point t11 ​​to the sixteenth time point t16. The scan signal S may be logic low from the sixteenth time point t16 to the seventeenth time point t17. The scan signal S may be logic high from the seventeenth time point t17 to the nineteenth time point t19. The scan signal S may change from logic high to logic low at the fourth time point t4, the scan signal S may change from logic low to logic high at the fifth time point t5, the scan signal S may change from logic high to logic low at the tenth time point t10, the scan signal S may change from logic low to logic high at the eleventh time point t11, the scan signal S may change from logic high to logic low at the sixteenth time point t16, and the scan signal S may change from logic low to logic high at the seventeenth time point t17.

[0109] The initialization signal INT may be logic high from the first time point t1 to the second time point t2. The initialization signal INT may be logic low from the second time point t2 to the third time point t3. The initialization signal INT may be logic high from the third time point t3 to the eighth time point t8. The initialization signal INT may be logic low from the eighth time point t8 to the ninth time point t9. The initialization signal INT may be logic high from the ninth time point t9 to the fourteenth time point t14. The initialization signal INT may be logic low from the fourteenth time point t14 to the fifteenth time point t15. The initialization signal INT may be logic high from the fifteenth time point t15 to the nineteenth time point t19. The initialization signal INT may be changed from logic high to logic low at the second time point t2. The initialization signal INT may be changed from logic low to logic high at the third time point t3. The initialization signal INT may be changed from logic high to logic low at the eighth time point t8. The initialization signal INT may be changed from logic low to logic high at the ninth time point t9. The initialization signal INT may be changed from logic high to logic low at the fourteenth time point t14. The initialization signal INT may transition from logic low to logic high at a fifteenth time point t15 .

[0110] The readout control signal R may be logic high from the first time point t1 to the nineteenth time point t19. The first light emitting control signal E1 may be logic low from the first time point t1 to the third time point t3. The first light emitting control signal E1 may be logic high from the third time point t3 to the sixth time point t6. The first light emitting control signal E1 may be logic low from the sixth time point t6 to the ninth time point t9. The first light emitting control signal E1 may be logic high from the ninth time point t9 to the twelfth time point t12. The first light emitting control signal E1 may be logic low from the twelfth time point t12 to the fifteenth time point t15. The first light emitting control signal E1 may be logic high from the fifteenth time point t15 to the eighteenth time point t18. The first light emitting control signal E1 may be logic low from the eighteenth time point t18 to the nineteenth time point t19. The first light-emitting control signal E1 may change from logic low to logic high at the third time point t3, the first light-emitting control signal E1 may change from logic high to logic low at the sixth time point t6, the first light-emitting control signal E1 may change from logic low to logic high at the ninth time point t9, the first light-emitting control signal E1 may change from logic high to logic low at the twelfth time point t12, the first light-emitting control signal E1 may change from logic low to logic high at the fifteenth time point t15, and the first light-emitting control signal E1 may change from logic high to logic low at the eighteenth time point t18.

[0111] The second light emitting control signal E2 may be logic high from the first time point t1 to the sixth time point t6. The second light emitting control signal E2 may be logic low from the sixth time point t6 to the seventh time point t7. The second light emitting control signal E2 may be logic high from the seventh time point t7 to the nineteenth time point t19. The second light emitting control signal E2 may change from logic high to logic low at the sixth time point t6. The second light emitting control signal E2 may change from logic low to logic high at the seventh time point t7.

[0112] The third light emitting control signal E3 may be logic high from the first time point t1 to the twelfth time point t12. The third light emitting control signal E3 may be logic low from the twelfth time point t12 to the thirteenth time point t13. The third light emitting control signal E3 may be logic high from the thirteenth time point t13 to the nineteenth time point t19. The third light emitting control signal E3 may be changed from logic high to logic low at the twelfth time point t12, and the third light emitting control signal E3 may be changed from logic low to logic high at the thirteenth time point t13.

[0113] The fourth light control signal E4 may be logic high from the first time point t1 to the eighteenth time point t18, and may be logic low from the eighteenth time point t18 to the nineteenth time point t19. At the eighteenth time point t18, the fourth light control signal E4 may transition from logic high to logic low.

[0114] The first subframe SF1 may be from the first time point t1 to the seventh time point t7. The reset interval RST of the first subframe SF1 may be from the second time point t2 to the third time point t3, the programming interval PRG of the first subframe SF1 may be from the fourth time point t4 to the fifth time point t5, the holding interval H of the first subframe SF1 may be from the fifth time point t5 to the sixth time point t6, and the light-emitting interval of the first subframe SF1 (i.e., the first light-emitting interval EM1) may be from the sixth time point t6 to the seventh time point t7.

[0115] The second subframe SF2 may be from the seventh time point t7 to the thirteenth time point t13. The reset interval RST of the second subframe SF2 may be from the eighth time point t8 to the ninth time point t9, the programming interval PRG of the second subframe SF2 may be from the tenth time point t10 to the eleventh time point t11, the holding interval H of the second subframe SF2 may be from the eleventh time point t11 ​​to the twelfth time point t12, and the light-emitting interval of the second subframe SF2 (i.e., the second light-emitting interval EM2) may be from the twelfth time point t12 to the thirteenth time point t13.

[0116] The third subframe SF3 may be from the thirteenth time point t13 to the nineteenth time point t19. The reset interval RST of the third subframe SF3 may be from the fourteenth time point t14 to the fifteenth time point t15, the programming interval PRG of the third subframe SF3 may be from the sixteenth time point t16 to the seventeenth time point t17, the holding interval H of the third subframe SF3 may be from the seventeenth time point t17 to the eighteenth time point t18, and the light-emitting interval of the third subframe SF3 (i.e., the third light-emitting interval EM3) may be from the eighteenth time point t18 to the nineteenth time point t19.

[0117] In the reset interval RST of each of the first to third subframes SF1 to SF3, the scan driver 113 may output the same control signal. In the programming interval PRG of each of the first to third subframes SF1 to SF3, the scan driver 113 may output the same control signal. In the holding interval H of each of the first to third subframes SF1 to SF3, the scan driver 113 may output the same control signal.

[0118] In the programming interval PRG of the first subframe SF1, the data driver 112 may output a data voltage VD corresponding to the first OLED OD1. In the programming interval PRG of the second subframe SF2, the data driver 112 may output a data voltage VD corresponding to the second OLED OD2. In the programming interval PRG of the third subframe SF3, the data driver 112 may output a data voltage VD corresponding to the third OLED OD3.

[0119] Reference Figure 6 and Fig. 7A, in the reset interval RST, the scan signal S may be logic high, the initialization signal INT may be logic low, the readout control signal R may be logic high, the first light emitting control signal E1 may be logic low, the second light emitting control signal E2 may be logic high, the third light emitting control signal E3 may be logic high, and the fourth light emitting control signal E4 may be logic high. In this regard, in the reset interval RST, the scan driver 113 may output the scan signal S at an invalid level (e.g., logic level) through the scan line SL, output the initialization signal INT at an effective level through the initialization line INTL, output the readout control signal R at an invalid level through the readout control line RL, output the first light emitting control signal E1 at an effective level through the first light emitting control line EL1, output the second light emitting control signal E2 at an invalid level through the second light emitting control line EL2, output the third light emitting control signal E3 at an invalid level through the third light emitting control line EL3, and output the fourth light emitting control signal E4 at an invalid level through the fourth light emitting control line EL4. Therefore, in the reset interval RST, the second transistor T2 , the third transistor T3 , the sixth transistor T6 , the seventh transistor T7 , the eighth transistor T8 , and the ninth transistor T9 may be turned off, and the fourth transistor T4 and the fifth transistor T5 may be turned on.

[0120] In response to the scan signal S at an invalid level, the second transistor T2 may be turned off. The second transistor T2 may be turned off, and thus, the electrical connection between the data line DL and the first node N1 may be cut off. In response to the scan signal S at an invalid level, the third transistor T3 may be turned off. The third transistor T3 may be turned off, and thus, the electrical connection between the second node N2 and the third node N3 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus, the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the second light emission control signal E2 at an invalid level, the seventh transistor T7 may be turned off. The seventh transistor T7 may be turned off, and thus, the electrical connection between the third node N3 and the first OLED OD1 may be cut off. In response to the third light emission control signal E3 at an invalid level, the eighth transistor T8 may be turned off. The eighth transistor T8 may be turned off, and thus, the electrical connection between the third node N3 and the second OLED OD2 may be cut off. In response to the fourth light emission control signal E4 at an invalid level, the ninth transistor T9 may be turned off. The ninth transistor T9 may be turned off, and thus, an electrical connection between the third node N3 and the third OLED OD3 may be cut off.

[0121] In response to the first light emitting control signal E1 at an effective level, the fourth transistor T4 may be turned on. The fourth transistor T4 may be turned on and supply the voltage of the first driving power supply ELVDD to the first node N1. In response to the initialization signal INT at an effective level, the fifth transistor T5 may be turned on. The fifth transistor T5 may be turned on and supply the initialization power supply VINT supplied through the readout line ROL to the second node N2. That is, the voltage of the gate of the first transistor T1 may be initialized to the voltage of the initialization power supply VINT.

[0122] The storage capacitor CST may be charged with a voltage obtained by reducing the voltage of the initialization power source VINT from the voltage of the first driving power source ELVDD. In this regard, the storage capacitor CST may store a difference between the voltage of the first driving power source ELVDD and the voltage of the initialization power source VINT.

[0123] Reference Figure 6 and Figure 7B , in the programming interval PRG, the scan signal S may be logic low, the initialization signal INT may be logic high, the readout control signal R may be logic high, the first light emitting control signal E1 may be logic high, the second light emitting control signal E2 may be logic high, the third light emitting control signal E3 may be logic high, and the fourth light emitting control signal E4 may be logic high. In this regard, in the programming interval PRG, the scan driver 113 may output the scan signal S at an effective level through the scan line SL, output the initialization signal INT at an ineffective level through the initialization line INTL, output the readout control signal R at an ineffective level through the readout control line RL, output the first light emitting control signal E1 at an ineffective level through the first light emitting control line EL1, output the second light emitting control signal E2 at an ineffective level through the second light emitting control line EL2, output the third light emitting control signal E3 at an ineffective level through the third light emitting control line EL3, and output the fourth light emitting control signal E4 at an ineffective level through the fourth light emitting control line EL4.

[0124] In the programming period PRG, the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , the eighth transistor T8 , and the ninth transistor T9 may be turned off, and the second transistor T2 and the third transistor T3 may be turned on.

[0125] In response to the first light emission control signal E1 at an invalid level, the fourth transistor T4 may be turned off. The fourth transistor T4 may be turned off, and thus, the electrical connection between the first driving power source ELVDD and the first node N1 may be cut off. In response to the initialization signal INT at an invalid level, the fifth transistor T5 may be turned off. The fifth transistor T5 may be turned off, and thus, the electrical connection between the readout line ROL and the second node N2 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus, the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the second light emission control signal E2 at an invalid level, the seventh transistor T7 may be turned off. The seventh transistor T7 may be turned off, and thus, the electrical connection between the third node N3 and the first OLED OD1 may be cut off. In response to the third light emission control signal E3 at an invalid level, the eighth transistor T8 may be turned off. The eighth transistor T8 may be turned off, and thus, the electrical connection between the third node N3 and the second OLED OD2 may be cut off. In response to the fourth light emitting control signal E4 at the inactive level, the ninth transistor T9 may be turned off. The ninth transistor T9 may be turned off, and thus, an electrical connection between the third node N3 and the third OLED OD3 may be cut off.

[0126] The second transistor T2 may be turned on in response to a scan signal S at an effective level. The second transistor T2 may be turned on and provide a data voltage VD provided through the data line DL to the first node N1. The third transistor T3 may be turned on in response to a scan signal S at an effective level. By turning on the third transistor T3, the second node N2 and the third node N3 may be connected to each other, and the third transistor T3 may be diode-connected to the first transistor T1.

[0127] The data voltage VD may be applied to the first node N1, and a voltage reduced from the data voltage VD by the absolute value of the threshold voltage VTH may be applied to the second node N2. The storage capacitor CST may be charged to the threshold voltage VTH. That is, the storage capacitor CST may store the threshold voltage VTH.

[0128] In the programming interval PRG of the first subframe SF1, the data driver 112 may provide the data voltage VD corresponding to the first OLED OD1 to the first node N1 through the data line DL. In the programming interval PRG of the second subframe SF2, the data driver 112 may provide the data voltage VD corresponding to the second OLED OD2 to the first node N1 through the data line DL. In the programming interval PRG of the third subframe SF3, the data driver 112 may provide the data voltage VD corresponding to the third OLED OD3 to the first node N1 through the data line DL.

[0129] Reference Figure 6 and Figure 7C , in the holding interval H, the scan signal S may be logic high, the initialization signal INT may be logic high, the readout control signal R may be logic high, the first light emission control signal E1 may be logic high, the second light emission control signal E2 may be logic high, the third light emission control signal E3 may be logic high, and the fourth light emission control signal E4 may be logic high. In this regard, in the holding interval H, the scan driver 113 may output the scan signal S at an invalid level through the scan line SL, output the initialization signal INT at an invalid level through the initialization line INTL, output the readout control signal R at an invalid level through the readout control line RL, output the first light emission control signal E1 at an invalid level through the first light emission control line EL1, output the second light emission control signal E2 at an invalid level through the second light emission control line EL2, output the third light emission control signal E3 at an invalid level through the third light emission control line EL3, and output the fourth light emission control signal E4 at an invalid level through the fourth light emission control line EL4. In the holding interval H, the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , the eighth transistor T8 , and the ninth transistor T9 may be turned off.

[0130] In response to the scan signal S at an invalid level, the second transistor T2 may be turned off. The second transistor T2 may be turned off, and thus, the electrical connection between the data line DL and the first node N1 may be cut off. In response to the scan signal S at an invalid level, the third transistor T3 may be turned off. The third transistor T3 may be turned off, and thus, the electrical connection between the second node N2 and the third node N3 may be cut off. In response to the first light emission control signal E1 at an invalid level, the fourth transistor T4 may be turned off. The fourth transistor T4 may be turned off, and thus, the electrical connection between the first driving power source ELVDD and the first node N1 may be cut off. In response to the initialization signal INT at an invalid level, the fifth transistor T5 may be turned off. The fifth transistor T5 may be turned off, and thus, the electrical connection between the readout line ROL and the second node N2 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus, the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the second light emission control signal E2 at an invalid level, the seventh transistor T7 may be turned off. The seventh transistor T7 may be turned off, and thus, the electrical connection between the third node N3 and the first OLED OD1 may be cut off. In response to the third light emitting control signal E3 at an inactive level, the eighth transistor T8 may be turned off. The eighth transistor T8 may be turned off, and thus, the electrical connection between the third node N3 and the second OLED OD2 may be cut off. In response to the fourth light emitting control signal E4 at an inactive level, the ninth transistor T9 may be turned off. The ninth transistor T9 may be turned off, and thus, the electrical connection between the third node N3 and the third OLED OD3 may be cut off.

[0131] In one embodiment, the range of the data voltage may be expanded under the influence of the parasitic capacitor. The first parasitic capacitor may be between the gate electrode of the second transistor T2 and the second electrode of the second transistor T2 (i.e., the first node N1). When the scan signal S changes from a logic low to a logic high at the fifth time point t5 (i.e., in the case of a rising edge), the voltage of the first node N1 may be coupled to the scan signal S and rise. The first voltage V1 may be applied to the first node N1. The first voltage V1 may be as expressed in Equation 2. Here, VD represents the data voltage VD applied through the data line DL, and f(A) represents the amplitude of the voltage boosted due to the first parasitic capacitor.

[0132] [Equation 2] The second parasitic capacitor may be between the gate electrode of the third transistor T3 and the first electrode of the third transistor T3 (i.e., the second node N2). When the scan signal S changes from logic low to logic high at the fifth time point t5, the voltage of the second node N2 may be coupled to the scan signal S and rise. The second voltage V2 may be applied to the second node N2. The second voltage V2 may be as expressed in Equation 3. Here, VD represents a data voltage applied through the data line DL, and f(B) represents the magnitude of the voltage boosted by the second parasitic capacitor.

[0133] [Equation 3] When the driving current ID is supplied from the first transistor T1 to any one of the first to third OLEDs OD1 to OD3, the organic light emitting layer of the corresponding OLED may generate light. The intensity of the light may be proportional to the driving current ID. The driving voltage VSG may be expressed as in Equation 4, and the driving current ID may be expressed as in Equation 5. Here, and denotes a constant value, ELVDD denotes a voltage of a first driving power source ELVDD, VD denotes a data voltage VD, VSG denotes a driving voltage VSG of the first transistor T1, VTH denotes a threshold voltage VTH of the first transistor T1, f(A) denotes a magnitude of a voltage boosted due to the first parasitic capacitor, and f(B) denotes a magnitude of a voltage boosted due to the second parasitic capacitor.

[0134] [Equation 4] [Equation 5] The display device 100 can expand the range of the data voltage VD as shown in Equation 6: [Equation 6] In one embodiment, the size of the second transistor T2 may be different from the size of the third transistor T3. The size of the second transistor T2 may be smaller than the size of the third transistor T3. Due to the difference in the size of the transistors, the influence of the parasitic capacitor may be different. Due to the difference in the size of the transistors, the influence of the second parasitic capacitor may be greater than the influence of the first parasitic capacitor. The range of the data voltage VD corresponding to the range of the amount of current flowing through the pixel may be increased. That is, the range of the data voltage VD corresponding to the range of the variation of the driving current ID may be expanded. The control of the brightness or lightness of the pixel may be facilitated by using the data voltage ID.

[0135] Reference Figure 6 and Fig.7D, in the first light-emitting interval EM1, the scan signal S may be logic high, the initialization signal INT may be logic high, the readout control signal R may be logic high, the first light-emitting control signal E1 may be logic low, the second light-emitting control signal E2 may be logic low, the third light-emitting control signal E3 may be logic high, and the fourth light-emitting control signal E4 may be logic high. In the first light-emitting interval EM1, the scan driver 113 may output the scan signal S at an inactive level through the scan line SL, output the initialization signal INT at an inactive level through the initialization line INTL, output the readout control signal R at an inactive level through the readout control line RL, output the first light-emitting control signal E1 at an active level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at an active level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at an inactive level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at an inactive level through the fourth light-emitting control line EL4. In the first light emitting interval EM1 , the second transistor T2 , the third transistor T3 , the fifth transistor T5 , the sixth transistor T6 , the eighth transistor T8 , and the ninth transistor T9 may be turned off, and the fourth transistor T4 and the seventh transistor T7 may be turned on.

[0136] In response to the scan signal S at an invalid level, the second transistor T2 may be turned off. The second transistor T2 may be turned off, and thus, the electrical connection between the data line DL and the first node N1 may be cut off. In response to the scan signal S at an invalid level, the third transistor T3 may be turned off. The third transistor T3 may be turned off, and thus, the electrical connection between the second node N2 and the third node N3 may be cut off. In response to the initialization signal INT at an invalid level, the fifth transistor T5 may be turned off. The fifth transistor T5 may be turned off, and thus, the electrical connection between the readout line ROL and the second node N2 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus, the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the third light emitting control signal E3 at an invalid level, the eighth transistor T8 may be turned off. The eighth transistor T8 may be turned off, and thus, the electrical connection between the third node N3 and the second OLED OD2 may be cut off. In response to the fourth light emitting control signal E4 at an invalid level, the ninth transistor T9 may be turned off. The ninth transistor T9 may be turned off, and thus, an electrical connection between the third node N3 and the third OLED OD3 may be cut off.

[0137] In response to the first light emission control signal E1 at an effective level, the fourth transistor T4 may be turned on. In response to the second light emission control signal E2 at an effective level, the seventh transistor T7 may be turned on. The fourth transistor T4 and the seventh transistor T7 may all be turned on, and thus, a driving current ID corresponding to the data voltage VD may flow through the first OLED OD1. That is, in the first light emission interval EM1, a driving current ID corresponding to the data voltage VD received in the programming interval PRG of the first subframe SF1 may flow through the first OLED OD1.

[0138] Reference Figure 6 and Fig. 7E , in the second light-emitting interval EM2, the scan signal S may be logic high, the initialization signal INT may be logic high, the readout control signal R may be logic high, the first light-emitting control signal E1 may be logic low, the second light-emitting control signal E2 may be logic high, the third light-emitting control signal E3 may be logic low, and the fourth light-emitting control signal E4 may be logic high. In the second light-emitting interval EM2, the scan driver 113 may output the scan signal S at an invalid level through the scan line SL, output the initialization signal INT at an invalid level through the initialization line INTL, output the readout control signal R at an invalid level through the readout control line RL, output the first light-emitting control signal E1 at an effective level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at an invalid level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at an effective level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at an invalid level through the fourth light-emitting control line EL4. In the second light emitting interval EM2 , the second transistor T2 , the third transistor T3 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the ninth transistor T9 may be turned off, and the fourth transistor T4 and the eighth transistor T8 may be turned on.

[0139] In response to the scan signal S at an invalid level, the second transistor T2 may be turned off. The second transistor T2 may be turned off, and thus, the electrical connection between the data line DL and the first node N1 may be cut off. In response to the scan signal S at an invalid level, the third transistor T3 may be turned off. The third transistor T3 may be turned off, and thus, the electrical connection between the second node N2 and the third node N3 may be cut off. In response to the initialization signal INT at an invalid level, the fifth transistor T5 may be turned off. The fifth transistor T5 may be turned off, and thus, the electrical connection between the readout line ROL and the second node N2 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus, the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the second light emitting control signal E2 at an invalid level, the seventh transistor T7 may be turned off. The seventh transistor T7 may be turned off, and thus, the electrical connection between the third node N3 and the first OLED OD1 may be cut off. In response to the fourth light emitting control signal E4 at an invalid level, the ninth transistor T9 may be turned off. The ninth transistor T9 may be turned off, and thus, an electrical connection between the third node N3 and the third OLED OD3 may be cut off.

[0140] In response to the first light emission control signal E1 at an effective level, the fourth transistor T4 may be turned on. In response to the third light emission control signal E3 at an effective level, the eighth transistor T8 may be turned on. The fourth transistor T4 and the eighth transistor T8 may all be turned on, and thus, a driving current ID corresponding to the data voltage VD may flow through the second OLED OD2. That is, in the second light emission interval EM2, a driving current ID corresponding to the data voltage VD received in the programming interval PRG of the second subframe SF2 may flow through the second OLED OD2.

[0141] Reference Figure 6 and Figure 7F, in the third light-emitting interval EM3, the scan signal S may be logic high, the initialization signal INT may be logic high, the readout control signal R may be logic high, the first light-emitting control signal E1 may be logic low, the second light-emitting control signal E2 may be logic high, the third light-emitting control signal E3 may be logic high, and the fourth light-emitting control signal E4 may be logic low. In the third light-emitting interval EM3, the scan driver 113 may output the scan signal S at an invalid level through the scan line SL, output the initialization signal INT at an invalid level through the initialization line INTL, output the readout control signal R at an invalid level through the readout control line RL, output the first light-emitting control signal E1 at an effective level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at an invalid level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at an invalid level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at an effective level through the fourth light-emitting control line EL4. In the third light emitting interval EM3 , the second transistor T2 , the third transistor T3 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may be turned off, and the fourth transistor T4 and the ninth transistor T9 may be turned on.

[0142] In response to the scan signal S at an invalid level, the second transistor T2 may be turned off. The second transistor T2 may be turned off, and thus, the electrical connection between the data line DL and the first node N1 may be cut off. In response to the scan signal S at an invalid level, the third transistor T3 may be turned off. The third transistor T3 may be turned off, and thus, the electrical connection between the second node N2 and the third node N3 may be cut off. In response to the initialization signal INT at an invalid level, the fifth transistor T5 may be turned off. The fifth transistor T5 may be turned off, and thus, the electrical connection between the readout line ROL and the second node N2 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus, the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the second light emission control signal E2 at an invalid level, the seventh transistor T7 may be turned off. The seventh transistor T7 may be turned off, and thus, the electrical connection between the third node N3 and the first OLED OD1 may be cut off. In response to the third light emission control signal E3 at an invalid level, the eighth transistor T8 may be turned off. The eighth transistor T8 may be turned off, and thus, an electrical connection between the third node N3 and the second OLED OD2 may be cut off.

[0143] In response to the first light emitting control signal E1 at an effective level, the fourth transistor T4 may be turned on. In response to the fourth light emitting control signal E4 at an effective level, the ninth transistor T9 may be turned on. The fourth transistor T4 and the ninth transistor T9 may all be turned on, and thus, a driving current ID corresponding to the data voltage VD may flow through the third OLED OD3. That is, in the third light emitting interval EM3, a driving current ID corresponding to the data voltage VD received in the programming interval PRG of the third subframe SF3 may flow through the third OLED OD3.

[0144] As described above, the pixel according to the embodiment can be time-division multiplexed. A plurality of light-emitting operations can be performed in one frame of the pixel. The pixel circuit PCIR can control a plurality of OLEDs by time-division multiplexing.

[0145] Figures 8 to 12 is a timing diagram of a plurality of signals for controlling a pixel according to an embodiment. FIG. 13A to FIG. 13E is a diagram showing the operation of a pixel according to an embodiment. A plurality of signals may be provided to Figure 2 The pixel PX1, and refer to Figure 1 and Figure 2 Give a description.

[0146] In the readout interval, the pixel PX1 may output a readout signal RO through the readout line ROL. In the first readout interval RO_1, the readout circuit 114 may detect the drive current ID. After the hold interval H, the display device 100 may perform a first readout operation instead of the light-emitting operation (the first light-emitting operation to the third light-emitting operation). The first readout operation may represent an operation of detecting the drive current. The display device 100 may perform the first readout operation in the first readout interval RO_1. In the first readout interval RO_1, the pixel PX1 may output the drive current ID to the readout circuit 114 through the readout line ROL.

[0147] In the second readout interval RO_2, the readout circuit 114 may detect the threshold voltage VTH. After the reset interval RST, the display device 100 may perform a second readout operation instead of a programming operation. The second readout operation represents an operation of detecting the threshold voltage VTH. The display device 100 may include a second readout operation in the second readout interval RO_2. In the second readout interval RO_2, the pixel PX1 may output an output voltage VO to the readout circuit 114. The output voltage VO may be as expressed in Equation 7. Here, VD represents the data voltage VD, and VTH represents the threshold voltage VTH of the first transistor T1.

[0148] [Equation 7] In the third readout interval RO_3, the readout circuit 114 may detect the first forward voltage VF1. After the holding interval H of the first subframe SF1, the display device 100 may perform a third readout operation instead of the first light-emitting operation. The third readout operation may represent an operation of detecting the first forward voltage VF1. The display device 100 may perform a third readout operation in the third readout interval RO_3. In the third readout interval RO_3, the pixel PX1 may output the first forward voltage VF1 (or the voltage of the third node N3) to the readout circuit 114. That is, in the third readout interval RO_3, the pixel PX1 may output the first forward voltage VF1, which is a forward voltage corresponding to the first OLED OD1, to the readout circuit 114.

[0149] In the fourth readout interval RO_4, the readout circuit 114 may detect the second forward voltage VF2. After the holding interval H of the second subframe SF2, the display device 100 may perform a fourth readout operation instead of the second light-emitting operation. The fourth readout operation may represent an operation of detecting the second forward voltage VF2. The display device 100 may perform a fourth readout operation in the fourth readout interval RO_4. In the fourth readout interval RO_4, the pixel PX1 may output the second forward voltage VF2 (or the voltage of the third node N3) to the readout circuit 114. That is, in the fourth readout interval RO_4, the pixel PX1 may output the second forward voltage VF2, which is a forward voltage corresponding to the second OLED OD2, to the readout circuit 114.

[0150] In the fifth readout interval RO_5, the readout circuit 114 may detect the third forward voltage VF3. After the holding interval H of the third subframe SF3, the display device 100 may perform a fifth readout operation instead of the third light-emitting operation. The fifth readout operation may represent an operation of detecting the third forward voltage VF3. The display device 100 may perform the fifth readout operation in the fifth readout interval RO_5. In the fifth readout interval RO_5, the pixel PX1 may output the third forward voltage VF3 (or the voltage of the third node N3) to the readout circuit 114. That is, in the fifth readout interval RO_5, the pixel PX1 may output the third forward voltage VF3 as the forward voltage corresponding to the third OLED OD3 to the readout circuit 114.

[0151] Reference Figure 8 and Fig.13A Describes the method for measuring the drive current ID. Figure 2 , Figure 8 and Fig.13A, in the first readout interval RO_1, the scan signal S may be logic high, the initialization signal INT may be logic high, the readout control signal R may be logic low, the first light-emitting control signal E1 may be logic low, the second light-emitting control signal E2 may be logic high, the third light-emitting control signal E3 may be logic high, and the fourth light-emitting control signal E4 may be logic high. In this regard, in the first readout interval RO_1, the scan driver 113 may output the scan signal S at an invalid level through the scan line SL, output the initialization signal INT at an invalid level through the initialization line INTL, output the readout control signal R at an effective level through the readout control line RL, output the first light-emitting control signal E1 at an effective level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at an invalid level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at an invalid level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at an invalid level through the fourth light-emitting control line EL4. In the first readout interval RO_1 , the second transistor T2 , the third transistor T3 , the fifth transistor T5 , the seventh transistor T7 , the eighth transistor T8 , and the ninth transistor T9 may be turned off, and the fourth transistor T4 and the sixth transistor T6 may be turned on.

[0152] In response to the first light emission control signal E1 at an effective level, the fourth transistor T4 may be turned on. In response to the readout control signal R at an effective level, the sixth transistor T6 may be turned on. In response to the scan signal S at an ineffective level, the second transistor T2 may be turned off. In response to the scan signal S at an ineffective level, the third transistor T3 may be turned off. In response to the initialization signal INT at an ineffective level, the fifth transistor T5 may be turned off. In response to the second light emission control signal E2 at an ineffective level, the seventh transistor T7 may be turned off. In response to the third light emission control signal E3 at an ineffective level, the eighth transistor T8 may be turned off. In response to the fourth light emission control signal E4 at an ineffective level, the ninth transistor T9 may be turned off.

[0153] Because the seventh transistor T7 to the ninth transistor T9 are turned off and the sixth transistor T6 is turned on, the driving current ID (i.e., the readout signal RO) can be output to the readout circuit 114 through the readout line ROL. The readout circuit 114 can receive the driving current ID through the readout line ROL. The readout circuit 114 can perform an ADC operation on the received driving current ID and generate readout data. That is, the readout circuit 114 can generate data corresponding to the driving current ID.

[0154] Reference Fig. 9 and Fig. 13B Describes the method of measuring the threshold voltage VTH. Figure 2 , Fig. 9 and Fig. 13B , in the second readout interval RO_2, the scan signal S may be logic low, the initialization signal INT may be logic high, the readout control signal R may be logic low, the first light-emitting control signal E1 may be logic high, the second light-emitting control signal E2 may be logic high, the third light-emitting control signal E3 may be logic high, and the fourth light-emitting control signal E4 may be logic high. In this regard, in the second readout interval RO_2, the scan driver 113 may output the scan signal S at a valid level through the scan line SL, output the initialization signal INT at an invalid level through the initialization line INTL, output the readout control signal R at a valid level through the readout control line RL, output the first light-emitting control signal E1 at an invalid level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at an invalid level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at an invalid level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at an invalid level through the fourth light-emitting control line EL4. In the second readout interval RO_2 , the fourth transistor T4 , the fifth transistor T5 , the seventh transistor T7 , the eighth transistor T8 , and the ninth transistor T9 may be turned off, and the second transistor T2 , the third transistor T3 , and the sixth transistor T6 may be turned on.

[0155] In response to the scan signal S at the effective level, the second transistor T2 may be turned on. In response to the scan signal S at the effective level, the third transistor T3 may be turned on. In response to the readout control signal R at the effective level, the sixth transistor T6 may be turned on. In response to the first light emission control signal E1 at the ineffective level, the fourth transistor T4 may be turned off. In response to the initialization signal INT at the ineffective level, the fifth transistor T5 may be turned off. In response to the second light emission control signal E2 at the ineffective level, the seventh transistor T7 may be turned off. In response to the third light emission control signal E3 at the ineffective level, the eighth transistor T8 may be turned off. In response to the fourth light emission control signal E4 at the ineffective level, the ninth transistor T9 may be turned off.

[0156] In response to the scan signal S at an effective level, the second transistor T2 may be turned on. The second transistor T2 may be turned on, and thus, the data voltage VD may be provided from the data line DL to the first node N1. The data voltage VD may be applied to the first node N1. A voltage reduced from the data voltage VD by the absolute value of the threshold voltage VTH may be applied to the second node N2.

[0157] The third transistor T3 may be turned on in response to the scan signal S at an effective level. By turning on the third transistor T3, the second node N2 and the third node N3 may be connected to each other, and the third transistor T3 may be diode-connected to the first transistor T1. Like the second node N2, a voltage reduced from the data voltage VD by the absolute value of the threshold voltage VTH may be applied to the third node N3.

[0158] The sixth transistor T6 may be turned on in response to the readout control signal R at an active level. The sixth transistor T6 may be turned on, and thus the third node N3 may be electrically connected to the readout line ROL. The output voltage VO may be output through the readout line ROL.

[0159] The readout circuit 114 may receive the output voltage VO through the readout line ROL. The readout circuit 114 may detect the threshold voltage VTH based on the output voltage VO and the data voltage VD. The readout circuit 114 may perform an ADC operation on the threshold voltage VTH and generate readout data. That is, the readout circuit 114 may generate data corresponding to the threshold voltage VTH.

[0160] Reference Fig.10 and Fig. 13C A method for measuring the first forward voltage VF1 is described. Figure 2 , Fig.10 and Fig. 13C , in the third readout interval RO_3, the scan signal S may be logic high, the initialization signal INT may be logic high, the readout control signal R may be logic low, the first light-emitting control signal E1 may be logic low, the second light-emitting control signal E2 may be logic low, the third light-emitting control signal E3 may be logic high, and the fourth light-emitting control signal E4 may be logic high. In this regard, in the third readout interval RO_3, the scan driver 113 may output the scan signal S at an invalid level through the scan line SL, output the initialization signal INT at an invalid level through the initialization line INTL, output the readout control signal R at an effective level through the readout control line RL, output the first light-emitting control signal E1 at an effective level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at an effective level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at an invalid level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at an invalid level through the fourth light-emitting control line EL4. In the third readout interval RO_3 , the second transistor T2 , the third transistor T3 , the fifth transistor T5 , the eighth transistor T8 , and the ninth transistor T9 may be turned off, and the fourth transistor T4 , the sixth transistor T6 , and the seventh transistor T7 may be turned on.

[0161] In response to the first light emission control signal E1 at an effective level, the fourth transistor T4 may be turned on. In response to the readout control signal R at an effective level, the sixth transistor T6 may be turned on. In response to the second light emission control signal E2 at an effective level, the seventh transistor T7 may be turned on. In response to the scan signal S at an ineffective level, the second transistor T2 may be turned off. In response to the scan signal S at an ineffective level, the third transistor T3 may be turned off. In response to the initialization signal INT at an ineffective level, the fifth transistor T5 may be turned off. In response to the third light emission control signal E3 at an ineffective level, the eighth transistor T8 may be turned off. In response to the fourth light emission control signal E4 at an ineffective level, the ninth transistor T9 may be turned off.

[0162] In response to the first light emission control signal E1 at an effective level, the fourth transistor T4 may be turned on. In response to the second light emission control signal E2 at an effective level, the seventh transistor T7 may be turned on. The fourth transistor T4 and the seventh transistor T7 may all be turned on, and thus, the driving current ID may flow through the first OLED OD1. In response to the readout control signal R at an effective level, the sixth transistor T6 may be turned on. The sixth transistor T6 may be turned on, and thus, the third node N3 may be electrically connected to the readout line ROL. The first forward voltage VF1 may be output through the readout line ROL.

[0163] The readout circuit 114 may receive the first forward voltage VF1 through the readout line ROL. The readout circuit 114 may perform an ADC operation on the first forward voltage VF1 and generate readout data. That is, the readout circuit 114 may generate data corresponding to the forward voltage of the first OLED OD1.

[0164] Reference Fig.11 and Fig.13D A method for measuring the second forward voltage VF2 is described. Figure 2 , Fig.11 and Fig.13D, in the fourth readout interval RO_4, the scan signal S may be logic high, the initialization signal INT may be logic high, the readout control signal R may be logic low, the first light-emitting control signal E1 may be logic low, the second light-emitting control signal E2 may be logic high, the third light-emitting control signal E3 may be logic low, and the fourth light-emitting control signal E4 may be logic high. In this regard, in the fourth readout interval RO_4, the scan driver 113 may output the scan signal S at an invalid level through the scan line SL, output the initialization signal INT at an invalid level through the initialization line INTL, output the readout control signal R at an effective level through the readout control line RL, output the first light-emitting control signal E1 at an effective level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at an invalid level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at an effective level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at an invalid level through the fourth light-emitting control line EL4. In the fourth readout interval RO_4 , the second transistor T2 , the third transistor T3 , the fifth transistor T5 , the seventh transistor T7 , and the ninth transistor T9 may be turned off, and the fourth transistor T4 , the sixth transistor T6 , and the eighth transistor T8 may be turned on.

[0165] The fourth transistor T4 may be turned on in response to the first light emission control signal E1 at an effective level. The sixth transistor T6 may be turned on in response to the readout control signal R at an effective level. The eighth transistor T8 may be turned on in response to the third light emission control signal E3 at an effective level. The second transistor T2 may be turned off in response to the scan signal S at an ineffective level. The third transistor T3 may be turned off in response to the scan signal S at an ineffective level. The fifth transistor T5 may be turned off in response to the initialization signal INT at an ineffective level. The seventh transistor T7 may be turned off in response to the second light emission control signal E2 at an ineffective level. The ninth transistor T9 may be turned off in response to the fourth light emission control signal E4 at an ineffective level.

[0166] The fourth transistor T4 may be turned on in response to the first light emission control signal E1 at an effective level. The eighth transistor T8 may be turned on in response to the third light emission control signal E3 at an effective level. The fourth transistor T4 and the eighth transistor T8 may all be turned on, and thus the drive current ID may flow through the second OLED OD2. The sixth transistor T6 may be turned on in response to the readout control signal R at an effective level. The sixth transistor T6 may be turned on, and thus the third node N3 may be electrically connected to the readout line ROL. The second forward voltage VF2 may be output through the readout line ROL.

[0167] The readout circuit 114 may receive the second forward voltage VF2 through the readout line ROL. The readout circuit 114 may perform an ADC operation on the second forward voltage VF2 and generate readout data. That is, the readout circuit 114 may generate data corresponding to the forward voltage of the second OLED OD2.

[0168] Reference Fig.12 and Fig.13E A method for measuring the third forward voltage VF3 is described. Figure 2 , Fig.12 and Fig.13E , in the fifth readout interval RO_5, the scan signal S may be logic high, the initialization signal INT may be logic high, the readout control signal R may be logic low, the first light-emitting control signal E1 may be logic low, the second light-emitting control signal E2 may be logic high, the third light-emitting control signal E3 may be logic high, and the fourth light-emitting control signal E4 may be logic low. In this regard, in the fifth readout interval RO_5, the scan driver 113 may output the scan signal S at an invalid level through the scan line SL, output the initialization signal INT at an invalid level through the initialization line INTL, output the readout control signal R at an effective level through the readout control line RL, output the first light-emitting control signal E1 at an effective level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at an invalid level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at an invalid level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at an effective level through the fourth light-emitting control line EL4. In the fifth readout interval RO_5 , the second transistor T2 , the third transistor T3 , the fifth transistor T5 , the seventh transistor T7 , and the eighth transistor T8 may be turned off, and the fourth transistor T4 , the sixth transistor T6 , and the ninth transistor T9 may be turned on.

[0169] In response to the first light emission control signal E1 at an effective level, the fourth transistor T4 may be turned on. In response to the readout control signal R at an effective level, the sixth transistor T6 may be turned on. In response to the fourth light emission control signal E4 at an effective level, the ninth transistor T9 may be turned on. In response to the scan signal S at an ineffective level, the second transistor T2 may be turned off. In response to the scan signal S at an ineffective level, the third transistor T3 may be turned off. In response to the initialization signal INT at an ineffective level, the fifth transistor T5 may be turned off. In response to the second light emission control signal E2 at an ineffective level, the seventh transistor T7 may be turned off. In response to the third light emission control signal E3 at an ineffective level, the eighth transistor T8 may be turned off.

[0170] In response to the first light emission control signal E1 at an effective level, the fourth transistor T4 may be turned on. In response to the fourth light emission control signal E4 at an effective level, the ninth transistor T9 may be turned on. The fourth transistor T4 and the ninth transistor T9 may all be turned on, and thus, the driving current ID may flow through the third OLED OD3. In response to the readout control signal R at an effective level, the sixth transistor T6 may be turned on. The sixth transistor T6 may be turned on, and thus, the third node N3 may be electrically connected to the readout line ROL. The third forward voltage VF3 may be output through the readout line ROL.

[0171] The readout circuit 114 may receive the third forward voltage VF3 through the readout line ROL. The readout circuit 114 may perform an ADC operation on the third forward voltage VF3 and generate readout data. That is, the readout circuit 114 may generate data corresponding to the forward voltage of the third OLED OD3.

[0172] The display device 100 may detect the electrical characteristics of the pixel during the test operation. The display device 100 may measure (or confirm) the amplitude of the driving current of the pixel PX1 and its distribution. The display device 100 may measure the distribution of the driving transistor (i.e., the first transistor T1) by measuring the threshold voltage VTH. The display device 100 may detect defects of the pixel and ensure current consistency by using the driving current and the threshold voltage. The display device 100 may measure the degree of degradation caused by long-term use of each of the first to third OLEDs OD1, OD2, and OD3 by measuring the amplitude of the forward voltage. DFT may be applied to the display device 100, and therefore, the testability of the pixel PX1 may be ensured even at the wafer and package levels. Therefore, the quality of the semiconductor chip may be maintained and the test efficiency may be improved.

[0173] Fig.14 It is shown Figure 3B A graph of the driving current of a pixel. Fig.15 is a graph showing a driving current of a pixel according to an embodiment.

[0174] The horizontal axis represents time, and the vertical axis represents driving current. Fig.14 Show Figure 3B The driving current of the pixel group PG, Fig.15 Show Figure 2 The driving current of the pixel PX1. Figure 3B and Fig.14, it may be assumed that the first driving current ID1 flows through the first OLED OD1 of the first pixel PXb1, the second driving current ID2 flows through the second OLED OD2 of the second pixel PXb2, and the third driving current ID3 flows through the third OLED OD3 of the third pixel PXb3. It may be assumed that the first current amount I1 is three times the second current amount I2, the third current amount I3 is three times the fourth current amount I4, and the fifth current amount I5 is three times the sixth current amount I6.

[0175] The light-emitting interval EM may be from the first time point t1 to the fourth time point t4. During the light-emitting interval EM, the first drive current ID1 may flow at the second current amount I2. During the light-emitting interval EM, the second drive current ID2 may flow at the fourth current amount I4. During the light-emitting interval EM, the third drive current ID3 may flow at the sixth current amount I6. That is, in one frame, the first to third OLEDs OD1, OD2, and OD3 may continuously emit light.

[0176] Reference Figure 2 and Fig.15 , it may be assumed that a first driving current ID1 flows through the first OLED OD1 of the pixel PX1 , a second driving current ID2 flows through the second OLED OD2 of the pixel PX1 , and a third driving current ID3 flows through the third OLED OD3 of the pixel PX1 .

[0177] The first light emitting interval EM1 may be from the first time point t1 to the second time point t2, the second light emitting interval EM2 may be from the second time point t2 to the third time point t3, and the third light emitting interval EM3 may be from the third time point t3 to the fourth time point t4.

[0178] The first driving current ID1 may flow at a first current amount I1 during the first light-emitting interval EM1. The second driving current ID2 may flow at a third current amount I3 during the second light-emitting interval EM2. The third driving current ID3 may flow at a fifth current amount I5 during the third light-emitting interval EM3. The pixel PX1 may drive a plurality of OLEDs by time division multiplexing. That is, in one frame, the first OLED OD1 may emit light during the first light-emitting interval EM1, and may not emit light during the second light-emitting interval EM2 and the third light-emitting interval EM3. The second OLED OD2 may emit light during the second light-emitting interval EM2, and may not emit light during the first light-emitting interval EM1 and the third light-emitting interval EM3. The third OLED OD3 may emit light during the third light-emitting interval EM3, and may not emit light during the first light-emitting interval EM1 and the second light-emitting interval EM2.

[0179] and Fig.14In contrast, since the light emission time of each of the first to third OLEDs OD1 to OD3 of the pixel PX1 is reduced, the driving current may be increased so that each of the first to third OLEDs OD1 to OD3 may emit light having the same brightness. That is, the first driving current ID1 may flow with a first current amount I1 which is three times the second current amount I2, the second driving current ID2 may flow with a third current amount I3 which is three times the fourth current amount I4, and the third driving current ID3 may flow with a fifth current amount I5 which is three times the sixth current amount I6.

[0180] As described above, the pixel according to the embodiment may include multiple OLEDs by time division multiplexing. That is, multiple OLEDs may share a pixel circuit. In contrast, as the light emission time of each OLED decreases, the driving current may increase so that each OLED may emit light with the same brightness.

[0181] Fig.16A is a circuit diagram of an example of a pixel according to the embodiment. Fig.16A The pixel PX2 can be applied to Figure 1 display device. Figure 1 Each pixel PX may contain Fig.16A The pixel PX2 can be omitted. Figure 2 Components of the pixel PX1 that are the same or similar are described in detail, and differences are mainly described.

[0182] Reference Figure 1 and Fig.16A, the pixel PX2 may include a first OLED OD1, a second OLED OD2, a third OLED OD3 and a pixel circuit PCIR. The pixel PX2 may include a first scan line SL1 extending in a first direction D1, a second scan line SL2 extending in the first direction D1, a third scan line SL3 extending in the first direction D1, a fourth scan line SL4 extending in the first direction D1, a first light emitting control line EL1 extending in the first direction D1, a second light emitting control line EL2 extending in the first direction D1, a third light emitting control line EL3 extending in the first direction D1, a fourth light emitting control line EL4 extending in the first direction D1, an initialization line INTL extending in the first direction D1, a readout control line RL extending in the first direction D1, a first data line DL1 extending in a second direction D2 intersecting the first direction D1, a second data line DL2 extending in the second direction D2, a third data line DL3 extending in the second direction D2, a readout line ROL extending in the second direction D2, first to eleventh transistors T1 to T11, a storage capacitor CST, and first to third OLEDs OD1 to OD3. That is, the pixel PX2 may include three OLEDs, eleven transistors, ten control lines extending in the first direction D1 (i.e., the first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the first light-emitting control line EL1, the second light-emitting control line EL2, the third light-emitting control line EL3, the fourth light-emitting control line EL4, the initialization line INTL and the readout control line RL), and four lines extending in the second direction (i.e., the first data line DL1, the second data line DL2, the third data line DL3 and the readout line ROL).

[0183] The anode electrode of each of the first to third OLEDs OD1, OD2, and OD3 may be connected to the pixel circuit PCIR, and the cathode electrode of each of the first to third OLEDs OD1, OD2, and OD3 may be connected to the second driving power source ELVSS. Each of the first to third OLEDs OD1, OD2, and OD3 may emit light having a brightness corresponding to the amount of current supplied from the pixel circuit PCIR. The brightness of the first OLED OD1 may be controlled by the voltage of the first data line DL1 (i.e., the first data voltage VD1). The brightness of the second OLED OD2 may be controlled by the voltage of the second data line DL2 (i.e., the second data voltage VD2). The brightness of the third OLED OD1 may be controlled by the voltage of the third data line DL3 (i.e., the third data voltage VD3).

[0184] The pixel circuit PCIR may control the amount of current flowing from the first driving power source ELVDD to the second driving power source ELVSS via each of the first to third OLEDs OD1, OD2, and OD3 in response to the data voltage. The pixel circuit PCIR may include first to eleventh transistors T1 to T11 and a storage capacitor CST.

[0185] The first transistor T1 may be connected between the first node N1 and the third node N3 and operate in response to the voltage of the second node N2. The first electrode of the first transistor T1 may be connected to the first node N1, and the second electrode of the first transistor T1 may be connected to the third node N3. The gate electrode of the first transistor T1 may be connected to the second node N2. In response to the voltage of the second node N2, the first transistor T1 may control the amount of current flowing from the first driving power source ELVDD to the second driving power source ELVSS via each of the first to third OLEDs OD1, OD2, and OD3.

[0186] The second transistor T2 may be connected between the first data line DL1 and the first node N1, and operate in response to the first scan signal S1. A first electrode of the second transistor T2 may be connected to the first data line DL1, and a second electrode of the second transistor T2 may be connected to the first node N1. A gate electrode of the second transistor T2 may be connected to the first scan line SL1. In response to the first scan signal S1 provided at an effective level through the first scan line SL1, the second transistor T2 may be turned on. The second transistor T2 may be turned on, and thus, the first node N1 may be electrically connected to the first data line DL1.

[0187] The third transistor T3 may be connected between the second node N2 and the third node N3, and operate in response to the fourth scan signal S4. The first electrode of the third transistor T3 may be connected to the second node N2, and the second electrode of the third transistor T3 may be connected to the third node N3. The gate electrode of the third transistor T3 may be connected to the fourth scan line SL4. In response to the fourth scan signal S4 provided at an effective level through the fourth scan line SL4, the third transistor T3 may be turned on. The third transistor T3 may be turned on, and therefore, the second node N2 may be electrically connected to the third node N3. That is, the third transistor T3 may be diode-connected to the first transistor T1.

[0188] In one embodiment, the scan driver 113 may include an AND circuit. The AND circuit may receive a first scan signal S1, a second scan signal S2, and a third scan signal S3. The AND circuit may generate and output a fourth scan signal S4 by performing an AND operation on the first scan signal S1, the second scan signal S2, and the third scan signal S3. That is, the fourth scan signal S4 may be as represented in Equation 8. Here, S4 represents the fourth scan signal S4, S1 represents the first scan signal S1, S2 represents the second scan signal S2, and S3 represents the third scan signal S3.

[0189] [Equation 8] The fourth transistor T4 may be connected between the first driving power source ELVDD and the first node N1, and operate in response to the first light emission control signal E1. A first electrode of the fourth transistor T4 may be connected to the first driving power source ELVDD, and a second electrode of the fourth transistor T4 may be connected to the first node N1. A gate electrode of the fourth transistor T4 may be connected to the first light emission control line EL1. In response to the first light emission control signal E1 provided at an effective level through the first light emission control line EL1, the fourth transistor T4 may be turned on. The fourth transistor T4 may be turned on, and thus, the voltage of the first driving power source ELVDD may be provided to the first node N1.

[0190] The fifth transistor T5 may be connected between the readout line ROL and the second node N2, and operate in response to the initialization signal INT. A first electrode of the fifth transistor T5 may be connected to the readout line ROL, and a second electrode of the fifth transistor T5 may be connected to the second node N2. A gate electrode of the fifth transistor T5 may be connected to the initialization line INTL. In response to the initialization signal INT provided at an effective level through the initialization line INTL, the fifth transistor T5 may be turned on. The fifth transistor T5 may be turned on, and thus, the voltage of the initialization power supply VINT may be provided to the second node N2.

[0191] The sixth transistor T6 may be connected between the readout line ROL and the third node N3, and operate in response to the readout control signal R. A first electrode of the sixth transistor T6 may be connected to the readout line ROL, and a second electrode of the sixth transistor T6 may be connected to the third node N3. A gate electrode of the sixth transistor T6 may be connected to the readout control line RL. In response to the readout control signal R provided at an active level through the readout control line RL, the sixth transistor T6 may be turned on. The sixth transistor T6 may be turned on, and thus, the third node N3 may be electrically connected to the readout line ROL.

[0192] The seventh transistor T7 may be connected between the third node N3 and the first OLED OD1, and operate in response to the second light emitting control signal E2. A first electrode of the seventh transistor T7 may be connected to the third node N3, and a second electrode of the seventh transistor T7 may be connected to the anode electrode of the first OLED OD1. A gate electrode of the seventh transistor T7 may be connected to the second light emitting control line EL2. In response to the second light emitting control signal E2 provided at an effective level through the second light emitting control line EL2, the seventh transistor T7 may be turned on. The seventh transistor T7 may be turned on, and thus, the third node N3 may be electrically connected to the anode electrode of the first OLED OD1.

[0193] The eighth transistor T8 may be connected between the third node N3 and the second OLED OD2, and operate in response to the third light emission control signal E3. A first electrode of the eighth transistor T8 may be connected to the third node N3, and a second electrode of the eighth transistor T8 may be connected to the anode electrode of the second OLED OD2. A gate electrode of the eighth transistor T8 may be connected to the third light emission control line EL3. In response to the third light emission control signal E3 provided at an effective level through the third light emission control line EL3, the eighth transistor T8 may be turned on. The eighth transistor T8 may be turned on, and thus, the third node N3 may be electrically connected to the anode electrode of the second OLED OD2.

[0194] The ninth transistor T9 may be connected between the third node N3 and the third OLED OD3, and operate in response to the fourth light emitting control signal E4. A first electrode of the ninth transistor T9 may be connected to the third node N3, and a second electrode of the ninth transistor T9 may be connected to the anode electrode of the third OLED OD3. A gate electrode of the ninth transistor T9 may be connected to the fourth light emitting control line EL4. In response to the fourth light emitting control signal E4 provided at an effective level through the fourth light emitting control line EL4, the ninth transistor T9 may be turned on. The ninth transistor T9 may be turned on, and therefore, the third node N3 may be electrically connected to the anode electrode of the third OLED OD3.

[0195] The tenth transistor T10 may be connected between the second data line DL2 and the first node N1, and operate in response to the second scan signal S2. A first electrode of the tenth transistor T10 may be connected to the second data line DL2, and a second electrode of the tenth transistor T10 may be connected to the first node N1. A gate electrode of the tenth transistor T10 may be connected to the second scan line SL2. In response to the second scan signal S2 provided at an effective level through the second scan line SL2, the tenth transistor T10 may be turned on. The tenth transistor T10 is turned on, and therefore, the first node N1 may be electrically connected to the second data line DL2.

[0196] The eleventh transistor T11 may be connected between the third data line DL3 and the first node N1, and operate in response to the third scan signal S3. The first electrode of the eleventh transistor T11 may be connected to the third data line DL3, and the second electrode of the second transistor T2 may be connected to the first node N1. The gate electrode of the eleventh transistor T11 may be connected to the third scan line SL3. In response to the third scan signal S3 provided at an effective level through the third scan line SL3, the eleventh transistor T11 may be turned on. The eleventh transistor T11 may be turned on, and therefore, the first node N1 may be electrically connected to the third data line DL3. The storage capacitor CST may be connected between the first node N1 and the second node N2.

[0197] Similar to Figure 2 The pixel PX1, Fig.16A The pixel PX2 of the third transistor T3 can expand the range of the data voltage. The W / L size of the third transistor T3 can be different from the W / L size of the second transistor T2. In one embodiment, the W / L size of the third transistor T3 can be greater than the W / L size of the second transistor T2. Due to the difference between the sizes of the transistors, the range of the data voltage corresponding to the range of the amount of current flowing through the pixel can be increased. That is, the range of variation of the data voltage VD corresponding to the range of variation of the drive current ID can be expanded. The control of the brightness or lightness of the pixel can be facilitated by using the data voltage.

[0198] Fig. 16B is a timing diagram of a plurality of signals for controlling a pixel according to an embodiment. The plurality of signals may be provided to Fig.16A The pixel PX2, and refer to Fig.16A Give a description.

[0199] The frame may include first to third subframes SF1 to SF3. The first subframe SF1 may include a reset interval RST, a first programming interval PRG1, a holding interval H, and a first light-emitting interval EM1. The second subframe SF2 may include a reset interval RST, a second programming interval PRG2, a holding interval H, and a second light-emitting interval EM2. The third subframe SF3 may include a reset interval RST, a third programming interval PRG3, a holding interval H, and a third light-emitting interval EM3. In the reset interval RST of each of the first to third subframes SF1 to SF3, the scan driver 113 may output the same control signal. In the holding interval H of each of the first to third subframes SF1 to SF3, the scan driver 113 may output the same control signal.

[0200] The first scan signal S1 may be logic high from the first time point t1 to the fourth time point t4. The first scan signal S1 may be logic low from the fourth time point t4 to the fifth time point t5. The first scan signal S1 may be logic high from the fifth time point t5 to the nineteenth time point t19. The first scan signal S1 may change from logic high to logic low at the fourth time point t4, and the first scan signal S1 may change from logic low to logic high at the fifth time point t5.

[0201] The second scan signal S2 may be logic high from the first time point t1 to the tenth time point t10. The second scan signal S2 may be logic low from the tenth time point t10 to the eleventh time point t11. The second scan signal S2 may be logic high from the eleventh time point t11 ​​to the nineteenth time point t19. The second scan signal S2 may change from logic high to logic low at the tenth time point t10, and the second scan signal S2 may change from logic low to logic high at the eleventh time point t11.

[0202] The third scan signal S3 may be logic high from the first time point t1 to the sixteenth time point t16. The third scan signal S3 may be logic low from the sixteenth time point t16 to the seventeenth time point t17. The third scan signal S3 may be logic high from the seventeenth time point t17 to the nineteenth time point t19. The third scan signal S3 may change from logic high to logic low at the sixteenth time point t16, and the third scan signal S3 may change from logic low to logic high at the seventeenth time point t17.

[0203] The fourth scan signal S4 may be logic high from the first time point t1 to the fourth time point t4. The fourth scan signal S4 may be logic low from the fourth time point t4 to the fifth time point t5. The fourth scan signal S4 may be logic high from the fifth time point t5 to the tenth time point t10. The fourth scan signal S4 may be logic low from the tenth time point t10 to the eleventh time point t11. The fourth scan signal S4 may be logic high from the eleventh time point t11 ​​to the sixteenth time point t16. The fourth scan signal S4 may be logic low from the sixteenth time point t16 to the seventeenth time point t17. The fourth scan signal S4 may be logic high from the seventeenth time point t17 to the nineteenth time point t19. The fourth scan signal S4 may change from logic high to logic low at the fourth time point t4. The fourth scan signal S4 may change from logic low to logic high at the fifth time point t5. The fourth scan signal S4 may change from logic high to logic low at the tenth time point t10. The fourth scan signal S4 may transition from logic low to logic high at an eleventh time point t11. The fourth scan signal S4 may transition from logic high to logic low at a sixteenth time point t16. The fourth scan signal S4 may transition from logic low to logic high at a seventeenth time point t17.

[0204] The initialization signal INT may be logic high from the first time point t1 to the second time point t2. The initialization signal INT may be logic low from the second time point t2 to the third time point t3. The initialization signal INT may be logic high from the third time point t3 to the eighth time point t8. The initialization signal INT may be logic low from the eighth time point t8 to the ninth time point t9. The initialization signal INT may be logic high from the ninth time point t9 to the fourteenth time point t14. The initialization signal INT may be logic low from the fourteenth time point t14 to the fifteenth time point t15. The initialization signal INT may be logic high from the fifteenth time point t15 to the nineteenth time point t19. The initialization signal INT may be changed from logic high to logic low at the second time point t2. The initialization signal INT may be changed from logic low to logic high at the third time point t3. The initialization signal INT may be changed from logic high to logic low at the eighth time point t8. The initialization signal INT may be changed from logic low to logic high at the ninth time point t9. The initialization signal INT may be changed from logic high to logic low at the fourteenth time point t14. The initialization signal INT may transition from logic low to logic high at a fifteenth time point t15 .

[0205] The readout control signal R may be logic high from the first time point t1 to the nineteenth time point t19. The first light emitting control signal E1 may be logic low from the first time point t1 to the third time point t3. The first light emitting control signal E1 may be logic high from the third time point t3 to the sixth time point t6. The first light emitting control signal E1 may be logic low from the sixth time point t6 to the ninth time point t9. The first light emitting control signal E1 may be logic high from the ninth time point t9 to the twelfth time point t12. The first light emitting control signal E1 may be logic low from the twelfth time point t12 to the fifteenth time point t15. The first light emitting control signal E1 may be logic high from the fifteenth time point t15 to the eighteenth time point t18. The first light emitting control signal E1 may be logic low from the eighteenth time point t18 to the nineteenth time point t19. The first light emitting control signal E1 may change from logic low to logic high at the third time point t3. The first light emitting control signal E1 may change from logic high to logic low at the sixth time point t6. The first light emitting control signal E1 may be changed from logic low to logic high at a ninth time point t9. The first light emitting control signal E1 may be changed from logic high to logic low at a twelfth time point t12. The first light emitting control signal E1 may be changed from logic low to logic high at a fifteenth time point t15. The first light emitting control signal E1 may be changed from logic high to logic low at an eighteenth time point t18.

[0206] The second light emitting control signal E2 may be logic high from the first time point t1 to the sixth time point t6. The second light emitting control signal E2 may be logic low from the sixth time point t6 to the seventh time point t7. The second light emitting control signal E2 may be logic high from the seventh time point t7 to the nineteenth time point t19. The second light emitting control signal E2 may be changed from logic high to logic low at the sixth time point t6, and the second light emitting control signal E2 may be changed from logic low to logic high at the seventh time point t7.

[0207] The third light emitting control signal E3 may be logic high from the first time point t1 to the twelfth time point t12. The third light emitting control signal E3 may be logic low from the twelfth time point t12 to the thirteenth time point t13. The third light emitting control signal E3 may be logic high from the thirteenth time point t13 to the nineteenth time point t19. The third light emitting control signal E3 may be changed from logic high to logic low at the twelfth time point t12, and the third light emitting control signal E3 may be changed from logic low to logic high at the thirteenth time point t13.

[0208] The fourth light emitting control signal E4 may be logic high from the first time point t1 to the eighteenth time point t18. The fourth light emitting control signal E4 may be logic low from the eighteenth time point t18 to the nineteenth time point t19. At the eighteenth time point t18, the fourth light emitting control signal E4 may transition from logic high to logic low.

[0209] The first subframe SF1 may be from the first time point t1 to the seventh time point t7. The reset interval RST of the first subframe SF1 may be from the second time point t2 to the third time point t3, the programming interval of the first subframe SF1 (i.e., the first programming interval PRG1) may be from the fourth time point t4 to the fifth time point t5, the holding interval H of the first subframe SF1 may be from the fifth time point t5 to the sixth time point t6, and the light-emitting interval of the first subframe SF1 (i.e., the first light-emitting interval EM1) may be from the sixth time point t6 to the seventh time point t7.

[0210] The second subframe SF2 may be from the seventh time point t7 to the thirteenth time point t13. The reset interval RST of the second subframe SF2 may be from the eighth time point t8 to the ninth time point t9, the program interval of the second subframe SF2 (i.e., the second program interval PRG2) may be from the tenth time point t10 to the eleventh time point t11, the holding interval H of the second subframe SF2 may be from the eleventh time point t11 ​​to the twelfth time point t12, and the light-emitting interval of the second subframe SF2 (i.e., the second light-emitting interval EM2) may be from the twelfth time point t12 to the thirteenth time point t13.

[0211] The third subframe SF3 may be from the thirteenth time point t13 to the nineteenth time point t19. The reset interval RST of the third subframe SF3 may be from the fourteenth time point t14 to the fifteenth time point t15, the programming interval of the third subframe SF3 (i.e., the third programming interval PRG3) may be from the sixteenth time point t16 to the seventeenth time point t17, the holding interval H of the third subframe SF3 may be from the seventeenth time point t17 to the eighteenth time point t18, and the light-emitting interval of the third subframe SF3 (i.e., the third light-emitting interval EM3) may be from the eighteenth time point t18 to the nineteenth time point t19.

[0212] In the first programming interval PRG1, the data driver 112 may output a first data voltage VD1 corresponding to the first OLED OD1. In the second programming interval PRG2, the data driver 112 may output a second data voltage VD2 corresponding to the second OLED OD2. In the third programming interval PRG3, the data driver 112 may output a third data voltage VD3 corresponding to the third OLED OD3. In the reset interval RST, the scan driver 113 can output the first scan signal S1 at an invalid level through the first scan line SL1, output the second scan signal S2 at an invalid level through the second scan line SL2, output the third scan signal S3 at an invalid level through the third scan line SL3, output the fourth scan signal S4 at an invalid level through the fourth scan line SL4, output the initialization signal INT at a valid level through the initialization line INTL, output the read control signal R at an invalid level through the read control line RL, output the first light-emitting control signal E1 at a valid level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at an invalid level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at an invalid level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at an invalid level through the fourth light-emitting control line EL4. Therefore, in the reset interval RST, the second transistor T2 , the third transistor T3 , the sixth transistor T6 , the seventh transistor T7 , the eighth transistor T8 , the ninth transistor T9 , the tenth transistor T10 , and the eleventh transistor T11 may be turned off, and the fourth transistor T4 and the fifth transistor T5 may be turned on.

[0213] In response to the first scan signal S1 at an invalid level, the second transistor T2 may be turned off. The second transistor T2 may be turned off, and thus, the electrical connection between the first data line DL1 and the first node N1 may be cut off. In response to the fourth scan signal S4 at an invalid level, the third transistor T3 may be turned off. The third transistor T3 may be turned off, and thus, the electrical connection between the second node N2 and the third node N3 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus, the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the second light emission control signal E2 at an invalid level, the seventh transistor T7 may be turned off. The seventh transistor T7 may be turned off, and thus, the electrical connection between the third node N3 and the first OLED OD1 may be cut off. In response to the third light emission control signal E3 at an invalid level, the eighth transistor T8 may be turned off. The eighth transistor T8 may be turned off, and thus, the electrical connection between the third node N3 and the second OLED OD2 may be cut off. In response to the fourth light emitting control signal E4 at an invalid level, the ninth transistor T9 may be turned off. The ninth transistor T9 may be turned off, and thus, the electrical connection between the third node N3 and the third OLED OD3 may be cut off. In response to the second scan signal S2 at an invalid level, the tenth transistor T10 may be turned off. The tenth transistor T10 may be turned off, and thus, the electrical connection between the second data line DL2 and the first node N1 may be cut off. In response to the third scan signal S3 at an invalid level, the eleventh transistor T11 may be turned off. The eleventh transistor T11 may be turned off, and thus, the electrical connection between the third data line DL3 and the first node N1 may be cut off.

[0214] In response to the first light emitting control signal E1 at an effective level, the fourth transistor T4 may be turned on. The fourth transistor T4 may be turned on, and thus, the voltage of the first driving power supply ELVDD may be provided to the first node N1. In response to the initialization signal INT at an effective level, the fifth transistor T5 may be turned on. The fifth transistor T5 may be turned on and provide the initialization power supply VINT provided through the readout line ROL to the second node N2. That is, the voltage of the gate of the first transistor T1 may be initialized to the voltage of the initialization power supply VINT.

[0215] The storage capacitor CST may be charged with a voltage reduced from the voltage of the first driving power source ELVDD by the voltage of the initialization power source VINT. In this regard, the storage capacitor CST may store the difference between the voltage of the first driving power source ELVDD and the voltage of the initialization power source VINT. In the holding interval H, the scan driver 113 may output a first scan signal S1 at an invalid level through the first scan line SL1, a second scan signal S2 at an invalid level through the second scan line SL2, a third scan signal S3 at an invalid level through the third scan line SL3, a fourth scan signal S4 at an invalid level through the fourth scan line SL4, an initialization signal INT at an invalid level through the initialization line INTL, a readout control signal R at an invalid level through the readout control line RL, a first light emission control signal E1 at an invalid level through the first light emission control line EL1, a second light emission control signal E2 at an invalid level through the second light emission control line EL2, a third light emission control signal E3 at an invalid level through the third light emission control line EL3, and a fourth light emission control signal E4 at an invalid level through the fourth light emission control line EL4. Therefore, in the holding interval H, the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , the eighth transistor T8 , the ninth transistor T9 , the tenth transistor T10 , and the eleventh transistor T11 may be turned off.

[0216] In response to the first scan signal S1 at an invalid level, the second transistor T2 may be turned off. The second transistor T2 may be turned off, and thus, the electrical connection between the first data line DL1 and the first node N1 may be cut off. In response to the fourth scan signal S4 at an invalid level, the third transistor T3 may be turned off. The third transistor T3 may be turned off, and thus, the electrical connection between the second node N2 and the third node N3 may be cut off. In response to the first light emission control signal E1 at an invalid level, the fourth transistor T4 may be turned off. The fourth transistor T4 may be turned off, and thus, the electrical connection between the first driving power source ELVDD and the first node N1 may be cut off. In response to the initialization signal INT at an invalid level, the fifth transistor T5 may be turned off. The fifth transistor T5 may be turned off, and thus, the electrical connection between the readout line ROL and the second node N2 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus, the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the second light emission control signal E2 at an invalid level, the seventh transistor T7 may be turned off. The seventh transistor T7 may be turned off, and thus, the electrical connection between the third node N3 and the first OLED OD1 may be cut off. In response to the third light emission control signal E3 at an invalid level, the eighth transistor T8 may be turned off. The eighth transistor T8 may be turned off, and thus, the electrical connection between the third node N3 and the second OLED OD2 may be cut off. In response to the fourth light emission control signal E4 at an invalid level, the ninth transistor T9 may be turned off. The ninth transistor T9 may be turned off, and thus, the electrical connection between the third node N3 and the third OLED OD3 may be cut off. In response to the second scan signal S2 at an invalid level, the tenth transistor T10 may be turned off. The tenth transistor T10 may be turned off, and thus, the electrical connection between the second data line DL2 and the first node N1 may be cut off. In response to the third scan signal S3 at an invalid level, the eleventh transistor T11 may be turned off. The eleventh transistor T11 may be turned off, and thus, the electrical connection between the third data line DL3 and the first node N1 may be cut off.

[0217] In one embodiment, when at least one of the first to third scan signals S1 to S3 is at an effective level, the fourth scan signal S4 may be at an effective level. For example, in the first programming interval PRG1, because the first scan signal S1 is at an effective level, the fourth scan signal S4 may be at an effective level. In the second programming interval PRG2, because the second scan signal S2 is at an effective level, the fourth scan signal S4 may be at an effective level. In the third programming interval PRG3, because the third scan signal S3 is at an effective level, the fourth scan signal S4 may be at an effective level.

[0218] In the first programming interval PRG1, the scan driver 113 can output the first scan signal S1 at the valid level through the first scan line SL1, output the second scan signal S2 at the invalid level through the second scan line SL2, output the third scan signal S3 at the invalid level through the third scan line SL3, output the fourth scan signal S4 at the valid level through the fourth scan line SL4, output the initialization signal INT at the invalid level through the initialization line INTL, output the read control signal R at the invalid level through the read control line RL, output the first light-emitting control signal E1 at the invalid level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at the invalid level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at the invalid level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at the invalid level through the fourth light-emitting control line EL4. Therefore, in the first programming section PRG1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 may be turned off, and the second transistor T2 and the third transistor T3 may be turned on.

[0219] In response to the first light emission control signal E1 at an invalid level, the fourth transistor T4 may be turned off. The fourth transistor T4 may be turned off, and thus, the electrical connection between the first driving power source ELVDD and the first node N1 may be cut off. In response to the initialization signal INT at an invalid level, the fifth transistor T5 may be turned off. The fifth transistor T5 may be turned off, and thus, the electrical connection between the readout line ROL and the second node N2 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus, the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the second light emission control signal E2 at an invalid level, the seventh transistor T7 may be turned off. The seventh transistor T7 may be turned off, and thus, the electrical connection between the third node N3 and the first OLED OD1 may be cut off. In response to the third light emission control signal E3 at an invalid level, the eighth transistor T8 may be turned off. The eighth transistor T8 may be turned off, and thus, the electrical connection between the third node N3 and the second OLED OD2 may be cut off. In response to the fourth light emitting control signal E4 at an invalid level, the ninth transistor T9 may be turned off. The ninth transistor T9 may be turned off, and thus, the electrical connection between the third node N3 and the third OLED OD3 may be cut off. In response to the second scan signal S2 at an invalid level, the tenth transistor T10 may be turned off. The tenth transistor T10 may be turned off, and thus, the electrical connection between the second data line DL2 and the first node N1 may be cut off. In response to the third scan signal S3 at an invalid level, the eleventh transistor T11 may be turned off. The eleventh transistor T11 may be turned off, and thus, the electrical connection between the third data line DL3 and the first node N1 may be cut off. In response to the first scan signal S1 at an effective level, the second transistor T2 may be turned on. The second transistor T2 may be turned on and provide the first data voltage VD1 provided through the first data line DL1 to the first node N1. In response to the fourth scan signal S4 at an effective level, the third transistor T3 may be turned on. By turning on the third transistor T3 , the second node N2 and the third node N3 may be connected to each other, and thus the third transistor T3 may be diode-connected to the first transistor T1 .

[0220] The first data voltage VD1 may be applied to the first node N1, and a voltage reduced by the absolute value of the threshold voltage VTH from the first data voltage VD1 may be applied to the second node N2. The storage capacitor CST may be charged to the threshold voltage VTH. That is, the storage capacitor CST may store the threshold voltage VTH. In the first programming interval PRG1, the data driver 112 may provide the first data voltage VD1 corresponding to the first OLED OD1 to the first node N1 through the first data line DL1.

[0221] In the second programming interval PRG2, the scan driver 113 can output the first scan signal S1 at an invalid level through the first scan line SL1, output the second scan signal S2 at a valid level through the second scan line SL2, output the third scan signal S3 at an invalid level through the third scan line SL3, output the fourth scan signal S4 at a valid level through the fourth scan line SL4, output the initialization signal INT at an invalid level through the initialization line INTL, output the read control signal R at an invalid level through the read control line RL, output the first light-emitting control signal E1 at an invalid level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at an invalid level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at an invalid level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at an invalid level through the fourth light-emitting control line EL4. Therefore, in the second programming section PRG2, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the eleventh transistor T11 may be turned off, and the third transistor T3 and the tenth transistor T10 may be turned on.

[0222] In response to the first scan signal S1 at an invalid level, the second transistor T2 may be turned off. The second transistor T2 may be turned off, and thus the electrical connection between the first data line DL1 and the first node N1 may be cut off. In response to the first light emission control signal E1 at an invalid level, the fourth transistor T4 may be turned off. The fourth transistor T4 may be turned off, and thus the electrical connection between the first driving power source ELVDD and the first node N1 may be cut off. In response to the initialization signal INT at an invalid level, the fifth transistor T5 may be turned off. The fifth transistor T5 may be turned off, and thus the electrical connection between the readout line ROL and the second node N2 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the second light emission control signal E2 at an invalid level, the seventh transistor T7 may be turned off. The seventh transistor T7 may be turned off, and thus the electrical connection between the third node N3 and the first OLED OD1 may be cut off. In response to the third light emission control signal E3 at an invalid level, the eighth transistor T8 may be turned off. The eighth transistor T8 may be turned off, and thus, the electrical connection between the third node N3 and the second OLED OD2 may be cut off. In response to the fourth light emission control signal E4 at an invalid level, the ninth transistor T9 may be turned off. The ninth transistor T9 may be turned off, and thus, the electrical connection between the third node N3 and the third OLED OD3 may be cut off. In response to the third scan signal S3 at an invalid level, the eleventh transistor T11 may be turned off. The eleventh transistor T11 may be turned off, and thus, the electrical connection between the third data line DL3 and the first node N1 may be cut off.

[0223] In response to the second scan signal S2 at an effective level, the tenth transistor T10 may be turned on. The tenth transistor T10 may be turned on and provide the second data voltage VD2 provided through the second data line DL2 to the first node N1. In response to the fourth scan signal S4 at an effective level, the third transistor T3 may be turned on. By turning on the third transistor T3, the second node N2 and the third node N3 may be connected to each other, and thus, the third transistor T3 may be diode-connected to the first transistor T1.

[0224] The second data voltage VD2 may be applied to the first node N1, and a voltage reduced by the absolute value of the threshold voltage VTH from the second data voltage VD2 may be applied to the second node N2. The storage capacitor CST may be charged to the threshold voltage VTH. That is, the storage capacitor CST may store the threshold voltage VTH. In the second programming interval PRG2, the data driver 112 may provide the second data voltage VD2 corresponding to the second OLED OD2 to the first node N1 through the second data line DL2.

[0225] In the third programming interval PRG3, the scan driver 113 can output the first scan signal S1 at an invalid level through the first scan line SL1, output the second scan signal S2 at an invalid level through the second scan line SL2, output the third scan signal S3 at a valid level through the third scan line SL3, output the fourth scan signal S4 at a valid level through the fourth scan line SL4, output the initialization signal INT at an invalid level through the initialization line INTL, output the read control signal R at an invalid level through the read control line RL, output the first light-emitting control signal E1 at an invalid level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at an invalid level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at an invalid level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at an invalid level through the fourth light-emitting control line EL4. Therefore, in the third programming period PRG3, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 may be turned off, and the third transistor T3 and the eleventh transistor T11 may be turned on.

[0226] In response to the first scan signal S1 at an invalid level, the second transistor T2 may be turned off. The second transistor T2 may be turned off, and thus, the electrical connection between the first data line DL1 and the first node N1 may be cut off. In response to the first light emission control signal E1 at an invalid level, the fourth transistor T4 may be turned off. The fourth transistor T4 may be turned off, and thus, the electrical connection between the first driving power source ELVDD and the first node N1 may be cut off. In response to the initialization signal INT at an invalid level, the fifth transistor T5 may be turned off. The fifth transistor T5 may be turned off, and thus, the electrical connection between the readout line ROL and the second node N2 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus, the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the second light emission control signal E2 at an invalid level, the seventh transistor T7 may be turned off. The seventh transistor T7 may be turned off, and thus, the electrical connection between the third node N3 and the first OLED OD1 may be cut off. In response to the third light emission control signal E3 at the inactive level, the eighth transistor T8 may be turned off. The eighth transistor T8 may be turned off, and thus, the electrical connection between the third node N3 and the second OLED OD2 may be cut off. In response to the fourth light emission control signal E4 at the inactive level, the ninth transistor T9 may be turned off. The ninth transistor T9 may be turned off, and thus, the electrical connection between the third node N3 and the third OLED OD3 may be cut off. In response to the second scan signal S2 at the inactive level, the tenth transistor T10 may be turned off. The tenth transistor T10 may be turned off, and thus, the electrical connection between the second data line DL2 and the first node N1 may be cut off.

[0227] In response to the third scan signal S3 at an effective level, the eleventh transistor T11 may be turned on. The eleventh transistor T11 may be turned on and provide the third data voltage VD3 provided through the third data line DL3 to the first node N1. In response to the fourth scan signal S4 at an effective level, the third transistor T3 may be turned on. By turning on the third transistor T3, the second node N2 and the third node N3 may be connected to each other, and thus the third transistor T3 may be diode-connected to the first transistor T1.

[0228] The third data voltage VD3 may be applied to the first node N1, and a voltage reduced by the absolute value of the threshold voltage VTH from the third data voltage VD3 may be applied to the second node N2. The storage capacitor CST may be charged to the threshold voltage VTH. That is, the storage capacitor CST may store the threshold voltage VTH. In the third programming interval PRG3, the data driver 112 may provide the third data voltage VD3 corresponding to the third OLED OD3 to the first node N1 through the third data line DL3.

[0229] In the first light-emitting interval EM1, the scan driver 113 can output the first scan signal S1 at an invalid level through the first scan line SL1, output the second scan signal S2 at an invalid level through the second scan line SL2, output the third scan signal S3 at an invalid level through the third scan line SL3, output the fourth scan signal S4 at an invalid level through the fourth scan line SL4, output the initialization signal INT at an invalid level through the initialization line INTL, output the read control signal R at an invalid level through the read control line RL, output the first light-emitting control signal E1 at a valid level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at a valid level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at an invalid level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at an invalid level through the fourth light-emitting control line EL4. Therefore, in the first light emitting interval EM1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 may be turned off, and the fourth transistor T4 and the seventh transistor T7 may be turned on.

[0230] In response to the first scan signal S1 at an invalid level, the second transistor T2 may be turned off. The second transistor T2 may be turned off, and thus, the electrical connection between the first data line DL1 and the first node N1 may be cut off. In response to the fourth scan signal S4 at an invalid level, the third transistor T3 may be turned off. The third transistor T3 may be turned off, and thus, the electrical connection between the second node N2 and the third node N3 may be cut off. In response to the initialization signal INT at an invalid level, the fifth transistor T5 may be turned off. The fifth transistor T5 may be turned off, and thus, the electrical connection between the readout line ROL and the second node N2 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus, the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the third light emission control signal E3 at an invalid level, the eighth transistor T8 may be turned off. The eighth transistor T8 may be turned off, and thus, the electrical connection between the third node N3 and the second OLED OD2 may be cut off. In response to the fourth light emission control signal E4 at an invalid level, the ninth transistor T9 may be turned off. The ninth transistor T9 may be turned off, and thus, the electrical connection between the third node N3 and the third OLED OD3 may be cut off. In response to the second scan signal S2 at an inactive level, the tenth transistor T10 may be turned off. In response to the third scan signal S3 at an inactive level, the tenth transistor T10 may be turned off, and thus, the electrical connection between the second data line DL2 and the first node N1 may be cut off. In response to the third scan signal S3 at an inactive level, the eleventh transistor T11 may be turned off. In response to the third scan signal S3 at an inactive level, the eleventh transistor T11 may be turned off. In response to the eleventh transistor T11 may be turned off, and thus, the electrical connection between the third data line DL3 and the first node N1 may be cut off.

[0231] In response to the first light emission control signal E1 at an effective level, the fourth transistor T4 may be turned on. In response to the second light emission control signal E2 at an effective level, the seventh transistor T7 may be turned on. The fourth transistor T4 and the seventh transistor T7 may all be turned on, and thus, a driving current ID corresponding to the first data voltage VD1 (i.e., a first driving current ID1) may flow through the first OLED OD1. That is, in the first light emission interval EM1, a driving current ID corresponding to the first data voltage VD1 received in the first programming interval PRG1 may flow through the first OLED OD1.

[0232] In the second light-emitting interval EM2, the scan driver 113 can output the first scan signal S1 at an invalid level through the first scan line SL1, output the second scan signal S2 at an invalid level through the second scan line SL2, output the third scan signal S3 at an invalid level through the third scan line SL3, output the fourth scan signal S4 at an invalid level through the fourth scan line SL4, output the initialization signal INT at an invalid level through the initialization line INTL, output the read control signal R at an invalid level through the read control line RL, output the first light-emitting control signal E1 at a valid level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at an invalid level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at a valid level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at an invalid level through the fourth light-emitting control line EL4.

[0233] Therefore, in the second light emitting interval EM2, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 may be turned off, and the fourth transistor T4 and the eighth transistor T8 may be turned on.

[0234] In response to the first scan signal S1 at an invalid level, the second transistor T2 may be turned off. The second transistor T2 may be turned off, and thus, the electrical connection between the first data line DL1 and the first node N1 may be cut off. In response to the fourth scan signal S4 at an invalid level, the third transistor T3 may be turned off. The third transistor T3 may be turned off, and thus, the electrical connection between the second node N2 and the third node N3 may be cut off. In response to the initialization signal INT at an invalid level, the fifth transistor T5 may be turned off. The fifth transistor T5 may be turned off, and thus, the electrical connection between the readout line ROL and the second node N2 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus, the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the second light emission control signal E2 at an invalid level, the seventh transistor T7 may be turned off. The seventh transistor T7 may be turned off, and thus, the electrical connection between the third node N3 and the first OLED OD1 may be cut off. In response to the fourth light emission control signal E4 at an invalid level, the ninth transistor T9 may be turned off. The ninth transistor T9 may be turned off, and thus, the electrical connection between the third node N3 and the third OLED OD3 may be cut off. In response to the second scan signal S2 at an inactive level, the tenth transistor T10 may be turned off. In response to the third scan signal S3 at an inactive level, the tenth transistor T10 may be turned off, and thus, the electrical connection between the second data line DL2 and the first node N1 may be cut off. In response to the third scan signal S3 at an inactive level, the eleventh transistor T11 may be turned off. In response to the third scan signal S3 at an inactive level, the eleventh transistor T11 may be turned off. In response to the eleventh transistor T11 may be turned off, and thus, the electrical connection between the third data line DL3 and the first node N1 may be cut off.

[0235] In response to the first light emission control signal E1 at an effective level, the fourth transistor T4 may be turned on. In response to the third light emission control signal E3 at an effective level, the eighth transistor T8 may be turned on. The fourth transistor T4 and the eighth transistor T8 may all be turned on, and thus, a driving current ID corresponding to the second data voltage VD2 (i.e., a second driving current ID2) may flow through the second OLED OD2. That is, in the second light emission interval EM2, a driving current ID corresponding to the second data voltage VD2 received in the second programming interval PRG2 may flow through the second OLED OD2.

[0236] In the third light-emitting interval EM3, the scan driver 113 can output the first scan signal S1 at an invalid level through the first scan line SL1, output the second scan signal S2 at an invalid level through the second scan line SL2, output the third scan signal S3 at an invalid level through the third scan line SL3, output the fourth scan signal S4 at an invalid level through the fourth scan line SL4, output the initialization signal INT at an invalid level through the initialization line INTL, output the read control signal R at an invalid level through the read control line RL, output the first light-emitting control signal E1 at a valid level through the first light-emitting control line EL1, output the second light-emitting control signal E2 at an invalid level through the second light-emitting control line EL2, output the third light-emitting control signal E3 at an invalid level through the third light-emitting control line EL3, and output the fourth light-emitting control signal E4 at a valid level through the fourth light-emitting control line EL4. Therefore, in the third light emitting interval EM3, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the eleventh transistor T11 may be turned off, and the fourth transistor T4 and the ninth transistor T9 may be turned on.

[0237] In response to the first scan signal S1 at an invalid level, the second transistor T2 may be turned off. The second transistor T2 may be turned off, and thus, the electrical connection between the first data line DL1 and the first node N1 may be cut off. In response to the fourth scan signal S4 at an invalid level, the third transistor T3 may be turned off. The third transistor T3 may be turned off, and thus, the electrical connection between the second node N2 and the third node N3 may be cut off. In response to the initialization signal INT at an invalid level, the fifth transistor T5 may be turned off. The fifth transistor T5 may be turned off, and thus, the electrical connection between the readout line ROL and the second node N2 may be cut off. In response to the readout control signal R at an invalid level, the sixth transistor T6 may be turned off. The sixth transistor T6 may be turned off, and thus, the electrical connection between the readout line ROL and the third node N3 may be cut off. In response to the second light emission control signal E2 at an invalid level, the seventh transistor T7 may be turned off. The seventh transistor T7 may be turned off, and thus, the electrical connection between the third node N3 and the first OLED OD1 may be cut off. In response to the third light emission control signal E3 at an invalid level, the eighth transistor T8 may be turned off. The eighth transistor T8 may be turned off, and thus, the electrical connection between the third node N3 and the second OLED OD2 may be cut off. In response to the second scan signal S2 at an inactive level, the tenth transistor T10 may be turned off. In response to the third scan signal S3 at an inactive level, the tenth transistor T10 may be turned off, and thus, the electrical connection between the second data line DL2 and the first node N1 may be cut off. In response to the third scan signal S3 at an inactive level, the eleventh transistor T11 may be turned off. In response to the eleventh transistor T11 may be turned off, and thus, the electrical connection between the third data line DL3 and the first node N1 may be cut off.

[0238] In response to the first light emission control signal E1 at an effective level, the fourth transistor T4 may be turned on. In response to the fourth light emission control signal E4 at an effective level, the ninth transistor T9 may be turned on. The fourth transistor T4 and the ninth transistor T9 may all be turned on, and thus, a driving current ID corresponding to the third data voltage VD3 (i.e., a third driving current ID3) may flow through the third OLED OD3. That is, in the third light emission interval EM3, a driving current ID corresponding to the third data voltage VD3 received in the third programming interval PRG3 may flow through the third OLED OD3.

[0239] Figure 2 The pixel PX1 can be used to drive multiple OLEDs through time division multiplexing. Therefore, the time period of the programming interval PRG of the pixel PX1 can be compared to Figure 3B The time period of the programming interval PRG of each of the pixels PXb1, PXb2, and PXb3 is short. For example, the time period of the programming interval PRG of the pixel PX1 may be Figure 3BThe time period of each of the first to third light emitting intervals EM1, EM2, and EM3 of the pixel PX1 is about 1 / 3 times the time period of the programming interval PRG of each of the pixels PXb1, PXb2, and PXb3. Figure 3B The time period of each of the light emitting intervals of the pixels PXb1, PXb2, and PXb3 is short. For example, the time period of each of the first to third light emitting intervals EM1, EM2, and EM3 of the pixel PX1 may be Figure 3B The time period is 1 / 3 times the time period of the light emitting interval EM of each of the pixels PXb1, PXb2 and PXb3.

[0240] Similar to Figure 2 The pixel PX1, Fig.16A The pixel PX2 of the pixel PX2 can drive a plurality of OLEDs by time division multiplexing. The time period of each of the first light-emitting interval to the third light-emitting interval EM1, EM2 and EM3 of the pixel PX2 can be Figure 3B 1 / 3 times the time period of the light emitting interval EM of each of the pixels PXb1, PXb2, and PXb3. Figure 2 Compared with the pixel PX1, Fig.16A The pixel PX2 may further include a tenth transistor T10, an eleventh transistor T11, a second data line DL2, a third data line DL3, a second scan line SL2, a third scan line SL3, and a fourth scan line SL4. Therefore, the time period of the programming interval PRG of the pixel PX2 may increase. That is, because the number of data lines is increased by the number of OLEDs, the time period of the programming interval PRG of the pixel PX2 may be equal to Figure 3B The time period of the programming interval PRG of each of the pixels PXb1, PXb2, and PXb3 may be three times the time period of the programming interval PRG of the pixel PX1.

[0241] For example, pixels in the same column may share a data line. Because the pixels PX1 share one data line, when the pixels PX1 in the first row connected to the data line DL are performing a programming operation, the pixels PX2 in the second row connected to the data line DL may not perform a programming operation. In contrast, because the pixels PX2 share three data lines, when the pixels PX1 in the first row connected to the first to third data lines DL1 to DL3 perform a programming operation through the first data line DL1, the pixels PX2 in the second row connected to the first to third data lines DL1 to DL3 may perform a programming operation through the second data line DL2. Therefore, the time period of the programming interval PRG of the pixel PX2 may increase.

[0242] Fig.17 is a circuit diagram of an example of a pixel according to the embodiment. Fig.17 The pixel PX3 can be applied to Figure 1 display device. Figure 1 Each pixel PX may include Fig.17 The pixel PX3 can be omitted. Figure 2 Components of the pixel PX1 that are the same or similar are described in detail, and differences are mainly described.

[0243] Reference Figure 1 and Fig.17 , the pixel PX3 may include a first OLED OD1, a second OLED OD2, a third OLED OD3, and a pixel circuit PCIR. The pixel PX3 may include a scan line SL extending in a first direction D1, a first light emitting control line EL1 extending in the first direction D1, a second light emitting control line EL2 extending in the first direction D1, a third light emitting control line EL3 extending in the first direction D1, a fourth light emitting control line EL4 extending in the first direction D1, a readout / initialization control line RL extending in the first direction D1, a data line DL extending in a second direction D2 intersecting the first direction D1, a readout line ROL extending in the second direction D2, first to fourth transistors T1 to T4, sixth to ninth transistors T6 to T9, a storage capacitor CST, and first to third OLEDs OD1 to OD3.

[0244] and Figure 2 Compared with the pixel PX1 of FIG. 1 , the pixel PX3 may not include the fifth transistor T5. The sixth transistor T6 may be connected between the readout line ROL and the third node N3, and operate in response to the readout / initialization control signal R. The first electrode of the sixth transistor T6 may be connected to the readout line ROL, and the second electrode of the sixth transistor T6 may be connected to the third node N3. The gate electrode of the sixth transistor T6 may be connected to the readout / initialization control line RL. In response to the readout / initialization control signal R provided at an effective level through the readout / initialization control line RL, the sixth transistor T6 may be turned on. In the reset interval RST, the sixth transistor T6 may be turned on, and therefore, the voltage of the initialization power supply VINT may be provided to the third node N3. Optionally, in the first readout interval RO_1 to the fifth readout interval RO_5, the sixth transistor T6 may be turned on, and therefore, the third node N3 may be electrically connected to the readout line ROL.

[0245] The pixel PX3 may include eight transistors. The sixth transistor T6 may be turned on in the reset interval RST and the first readout interval RO_1 to the fifth readout interval RO_5. That is, the sixth transistor T6 may control the reset operation and the readout operation. The sixth transistor T6 may be used as the fifth transistor T5. In the reset interval RST, the sixth transistor T6 may provide the voltage of the initialization power supply VINT to the third node N3. In addition, in the first readout interval RO_1 to the fifth readout interval RO_5, the sixth transistor T6 may provide the readout signal RO to the readout circuit 114. The sixth transistor T6 may control both the reset operation and the readout operation, and therefore, the number of transistors may be reduced. By reducing the number of transistors per pixel, the pixel size may be reduced. Therefore, a display device with a small area and high resolution may be provided.

[0246] Fig.18 is a circuit diagram of an example of a pixel according to the embodiment. Fig.18 The pixel PX4 can be applied to Figure 1 display device. Figure 1 Each pixel PX may include Fig.18 The pixel PX4 can be omitted. Figure 2 Components of the pixel PX1 that are the same or similar are described in detail, and differences are mainly described.

[0247] Reference Figure 1 and Fig.18 , the pixel PX4 may include a first OLED OD1, a second OLED OD2, a third OLED OD3, and a pixel circuit PCIR. The pixel PX4 may include a scan line SL extending in a first direction D1, a first light emitting control line EL1 extending in the first direction D1, a second light emitting control line EL2 extending in the first direction D1, a third light emitting control line EL3 extending in the first direction D1, a fourth light emitting control line EL4 extending in the first direction D1, a readout / initialization control line RL extending in the first direction D1, a data line DL extending in a second direction D2 intersecting the first direction D1, a readout line ROL extending in the second direction D2, first to fifth transistors T1 to T5, seventh to ninth transistors T7 to T9, a storage capacitor CST, and first to third OLEDs OD1 to OD3.

[0248] and Figure 2Compared with the pixel PX1 of FIG. 1 , the pixel PX4 may not include the sixth transistor T6. The fifth transistor T5 may be connected between the readout line ROL and the second node N2, and operate in response to the readout / initialization control signal R. The first electrode of the fifth transistor T5 may be connected to the readout line ROL, and the second electrode of the fifth transistor T5 may be connected to the second node N2. The gate electrode of the fifth transistor T5 may be connected to the readout / initialization control line RL. In response to the readout / initialization control signal R provided at an effective level through the readout / initialization control line RL, the fifth transistor T5 may be turned on. In the reset interval RST, the fifth transistor T5 may be turned on, and thus, the voltage of the initialization power supply VINT may be provided to the second node N2. Optionally, in the readout interval, the fifth transistor T5 may be turned on, and thus, the second node N2 may be electrically connected to the readout line ROL.

[0249] Fig.18 The pixel PX4 may include eight transistors. The fifth transistor T5 may be turned on in the reset interval RST and the second readout interval RO_2. That is, the fifth transistor T5 may control the reset operation and the second readout operation. In the reset interval RST, the fifth transistor T5 may provide the voltage of the initialization power supply VINT to the second node N2. In addition, in the second readout interval RO_2, the fifth transistor T5 may provide the readout signal RO to the readout circuit 114. The fifth transistor T5 may control both the reset operation and the second readout operation, and therefore, the number of transistors may be reduced. By reducing the number of transistors per pixel, the pixel size may be reduced. Therefore, a display device with a small area and high resolution may be provided.

[0250] Figure 2 The pixel PX1 may include the sixth transistor T6. Therefore, the display device 100 including the pixel PX1 may perform the first to fifth readout operations. The display device 100 including the pixel PX1 may measure the driving current ID, the threshold voltage VTH, and the forward voltage VF of the pixel PX1.

[0251] In contrast, Fig.18 The pixel PX4 may not include the sixth transistor T6. Therefore, the display device 100 including the pixel PX4 may perform only the second readout operation among the first to fifth readout operations. The display device 100 including the pixel PX4 may measure only the threshold voltage VTH of the pixel PX4.

[0252] Fig.19 is a circuit diagram of an example of a pixel according to the embodiment. Fig.19 The pixel PX5 can be applied to Figure 1 display device. Figure 1 Each pixel PX may include Fig.19 The pixel PX5 can be omitted. Figure 2Components of the pixel PX1 that are the same or similar are described in detail, and differences are mainly described.

[0253] Reference Figure 1 and Fig.19 , the pixel PX5 may include a first OLED OD1, a second OLED OD2, and a pixel circuit PCIR. The pixel PX5 may include a scan line SL extending in a first direction D1, a first light emission control line EL1 extending in the first direction D1, a second light emission control line EL2 extending in the first direction D1, a third light emission control line EL3 extending in the first direction D1, an initialization line INTL extending in the first direction D1, a readout control line RL extending in the first direction D1, a data line DL extending in a second direction D2 intersecting the first direction D1, a readout line ROL extending in the second direction D2, first to eighth transistors T1 to T8, a storage capacitor CST, and the first and second OLEDs OD1 and OD2.

[0254] and Figure 2 Compared with the pixel PX1, the pixel PX5 may not include the third OLED OD3, the ninth transistor T9, and the fourth light emission control line EL4. That is, the pixel PX5 may include two OLEDs, eight transistors, six control lines extending in the first direction D1 (i.e., the scan line SL, the first light emission control line EL1, the second light emission control line EL2, the third light emission control line EL3, the initialization line INTL, and the readout control line RL) and two lines extending in the second direction D2 (i.e., the data line DL and the readout line ROL). As described above, the number of OLEDs included in a pixel may be changed.

[0255] In one embodiment, a frame may include a first subframe and a second subframe. In the first subframe, the pixel PX5 may perform a reset operation, a program operation, a hold operation, and a light emitting operation on the first OLED OD1. In the second subframe, the pixel PX5 may perform a reset operation, a program operation, a hold operation, and a light emitting operation on the second OLED OD2.

[0256] Fig. 20 is a circuit diagram of an example of a pixel according to the embodiment. Fig. 20 The pixel PX6 can be applied to Figure 1 display device. Figure 1 Each pixel PX may include Fig. 20 The pixel PX6 can be omitted. Figure 2 Components of the pixel PX1 that are the same or similar are described in detail, and differences are mainly described.

[0257] Reference Figure 1 and Fig. 20, the pixel PX6 may include a first OLED OD1, a second OLED OD2, a third OLED OD3, a fourth OLED OD4, and a pixel circuit PCIR. The pixel PX6 may include a scan line SL extending in a first direction D1, a first light emitting control line EL1 extending in the first direction D1, a second light emitting control line EL2 extending in the first direction D1, a third light emitting control line EL3 extending in the first direction D1, a fourth light emitting control line EL4 extending in the first direction D1, a fifth light emitting control line EL5 extending in the first direction D1, an initialization line INTL extending in the first direction D1, a readout control line RL extending in the first direction D1, a data line DL extending in a second direction D2 intersecting the first direction D1, a readout line ROL extending in the second direction D2, first to tenth transistors T1 to T10, a storage capacitor CST, and first to fourth OLEDs OD1 to OD4. For example, the first OLED OD1 may output red light, the second OLED OD2 may output blue light, the third OLED OD3 may output green light, and the fourth OLED OD4 may output white light.

[0258] The anode electrode of the fourth OLED OD4 may be connected to the pixel circuit PCIR, and the cathode electrode of the fourth OLED OD4 may be connected to the second driving power source ELVSS. The fourth OLED OD4 may emit light having a brightness corresponding to the amount of current supplied from the pixel circuit PCIR. The brightness of the fourth OLED OD4 may be controlled by the voltage of the data line DL (ie, the data voltage VD).

[0259] The tenth transistor T10 may be connected between the third node N3 and the fourth OLED OD4, and operate in response to the fifth light emitting control signal E5. A first electrode of the tenth transistor T10 may be connected to the third node N3, and a second electrode of the tenth transistor T10 may be connected to the anode electrode of the fourth OLED OD4. A gate electrode of the tenth transistor T10 may be connected to the fifth light emitting control line EL5. In response to the fifth light emitting control signal E5 provided at an effective level through the fifth light emitting control line EL5, the tenth transistor T10 may be turned on. The tenth transistor T10 may be turned on, and thus, the third node N3 may be electrically connected to the anode electrode of the fourth OLED OD4.

[0260] and Figure 2Compared with the pixel PX1, the pixel PX6 may further include a fourth OLED OD4, a tenth transistor T10, and a fifth light emitting control line EL5. That is, the pixel PX6 may include four OLEDs, ten transistors, eight control lines extending in the first direction D1 (i.e., the scan line SL, the first light emitting control line EL1, the second light emitting control line EL2, the third light emitting control line EL3, the fourth light emitting control line EL4, the fifth light emitting control line EL5, the initialization line INTL, and the readout control line RL) and two lines extending in the second direction D2 (i.e., the data line DL and the readout line ROL). That is, because the pixel PX6 is larger than the pixel PX1, the pixel PX6 may further include a fourth OLED OD4, a tenth transistor T10, and a fifth light emitting control line EL5. ... Figure 2 The pixel PX1 has one more OLED, so compared with the pixel PX1, the pixel PX6 may also include a transistor and a light-emitting control line. Figure 2 When the number of transistors is increased compared to the pixel PX2, the number of transistors increased may be equal to the number of OLEDs increased in the pixel PX6. Figure 2 Compared with the pixel PX1, the pixel PX6 may further increase the first number of OLEDs, the first number of transistors, and the first number of light emitting control lines.

[0261] Fig.21 is a circuit diagram of an example of a pixel according to the embodiment. Fig.21 The pixel PX7 can be applied to Figure 1 display device. Figure 1 Each pixel PX may include Fig.21 The pixel PX7 can be omitted. Fig.16A Components of the pixel PX2 that are the same or similar are described in detail, and the differences are mainly described.

[0262] Reference Figure 1 and Fig.21, the pixel PX7 may include a first OLED OD1, a second OLED OD2, a third OLED OD3 and a pixel circuit PCIR. The pixel PX7 may include a first scan line SL1 extending in a first direction D1, a second scan line SL2 extending in the first direction D1, a third scan line SL3 extending in the first direction D1, a fourth scan line SL4 extending in the first direction D1, a first light emitting control line EL1 extending in the first direction D1, a second light emitting control line EL2 extending in the first direction D1, a third light emitting control line EL3 extending in the first direction D1, a fourth light emitting control line EL4 extending in the first direction D1, a readout / initialization control line RL extending in the first direction D1, a first data line DL1 extending in a second direction D2 intersecting the first direction D1, a second data line DL2 extending in the second direction D2, a third data line DL3 extending in the second direction D2, a readout line ROL extending in the second direction D2, first to fourth transistors T1 to T4, sixth to eleventh transistors T6 to T11, a storage capacitor CST, and first to third OLEDs OD1 to OD3. That is, the pixel PX7 may include three OLEDs, ten transistors, nine control lines extending in the first direction D1 (i.e., the first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the first light-emitting control line EL1, the second light-emitting control line EL2, the third light-emitting control line EL3, the fourth light-emitting control line EL4 and the readout / initialization control line RL) and four lines extending in the second direction D2 (i.e., the first data line DL1, the second data line DL2, the third data line DL3 and the readout line ROL).

[0263] and Fig.16A Compared with the pixel PX2 of FIG. 1 , the pixel PX7 may not include the fifth transistor T5. The sixth transistor T6 may be connected between the readout line ROL and the third node N3, and operate in response to the readout / initialization control signal R. The first electrode of the sixth transistor T6 may be connected to the readout line ROL, and the second electrode of the sixth transistor T6 may be connected to the third node N3. The gate electrode of the sixth transistor T6 may be connected to the readout / initialization control line RL. In response to the readout / initialization control signal R provided at an effective level through the readout / initialization control line RL, the sixth transistor T6 may be turned on. In the reset interval RST, the sixth transistor T6 may be turned on, and thus, the voltage of the initialization power supply VINT may be provided to the third node N3. Optionally, in the first readout interval RO_1 to the fifth readout interval RO_5, the sixth transistor T6 may be turned on, and thus, the third node N3 may be electrically connected to the readout line ROL.

[0264] The sixth transistor T6 may be turned on in the reset interval RST and the first readout interval RO_1 to the fifth readout interval RO_5. That is, the sixth transistor T6 may control the reset operation and the readout operation. The sixth transistor T6 may be used as the fifth transistor T5. In the reset interval RST, the sixth transistor T6 may provide the voltage of the initialization power supply VINT to the third node N3. In addition, in the first readout interval RO_1 to the fifth readout interval RO_5, the sixth transistor T6 may provide the readout signal RO to the readout circuit 114. The sixth transistor T6 may control both the reset operation and the readout operation, and therefore, the number of transistors may be reduced. By reducing the number of transistors per pixel, the pixel size may be reduced. Therefore, a display device with a small area and high resolution may be provided.

[0265] Fig. 22 is a circuit diagram of an example of a pixel according to the embodiment. Fig. 22 The pixel PX8 can be applied to Figure 1 display device. Figure 1 Each pixel PX may include Fig. 22 The pixel PX8 can be omitted. Fig.16A Components of the pixel PX2 that are the same or similar are described in detail, and the differences are mainly described.

[0266] Reference Figure 1 and Fig. 22, the pixel PX8 may include a first OLED OD1, a second OLED OD2, a third OLED OD3 and a pixel circuit PCIR. The pixel PX8 may include a first scan line SL1 extending in a first direction D1, a second scan line SL2 extending in the first direction D1, a third scan line SL3 extending in the first direction D1, a fourth scan line SL4 extending in the first direction D1, a first light emitting control line EL1 extending in the first direction D1, a second light emitting control line EL2 extending in the first direction D1, a third light emitting control line EL3 extending in the first direction D1, a fourth light emitting control line EL4 extending in the first direction D1, a readout / initialization control line RL extending in the first direction D1, a first data line DL1 extending in a second direction D2 intersecting the first direction D1, a second data line DL2 extending in the second direction D2, a third data line DL3 extending in the second direction D2, a readout line ROL extending in the second direction D2, first to fifth transistors T1 to T5, seventh to eleventh transistors T7 to T11, a storage capacitor CST, and first to third OLEDs OD1 to OD3. That is, the pixel PX7 may include three OLEDs, ten transistors, nine control lines extending in the first direction D1 (i.e., the first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the first light-emitting control line EL1, the second light-emitting control line EL2, the third light-emitting control line EL3, the fourth light-emitting control line EL4 and the readout / initialization control line RL) and four lines extending in the second direction D2 (i.e., the first data line DL1, the second data line DL2, the third data line DL3 and the readout line ROL).

[0267] and Fig.16A Compared with the pixel PX2 of FIG. 1 , the pixel PX8 may not include the sixth transistor T6. The fifth transistor T5 may be connected between the readout line ROL and the second node N2, and operate in response to the readout / initialization control signal R. The first electrode of the fifth transistor T5 may be connected to the readout line ROL, and the second electrode of the fifth transistor T5 may be connected to the second node N2. The gate electrode of the fifth transistor T5 may be connected to the readout / initialization control line RL. In response to the readout / initialization control signal R provided at an effective level through the readout / initialization control line RL, the fifth transistor T5 may be turned on. In the reset interval RST, the fifth transistor T5 may be turned on, and thus, the voltage of the initialization power supply VINT may be provided to the second node N2. Optionally, in the readout interval, the fifth transistor T5 may be turned on, and thus, the second node N2 may be electrically connected to the readout line ROL.

[0268] The fifth transistor T5 may be turned on in the reset interval RST and the second readout interval RO_2. That is, the fifth transistor T5 may control the reset operation and the second readout operation. In the reset interval RST, the fifth transistor T5 may provide the voltage of the initialization power supply VINT to the second node N2. In addition, in the second readout interval RO_2, the fifth transistor T5 may provide the readout signal RO to the readout circuit 114. The fifth transistor T5 may control both the reset operation and the second readout operation, and therefore, the number of transistors may be reduced. By reducing the number of transistors per pixel, the pixel size may be reduced. Therefore, a display device with a small area and high resolution may be provided.

[0269] Fig.16A The pixel PX2 may include the sixth transistor T6. Therefore, the display device 100 including the pixel PX2 may perform the first to fifth readout operations. The display device 100 including the pixel PX2 may measure the driving current ID, the threshold voltage VTH, and the forward voltage VF of the pixel PX2.

[0270] on the contrary, Fig. 22 The pixel PX8 may not include the sixth transistor T6. The fifth transistor T5 may be used as the sixth transistor T6. Therefore, the display device 100 including the pixel PX8 may only perform the second readout operation among the first to fifth readout operations. The display device 100 including the pixel PX8 may only measure the threshold voltage VTH of the pixel PX8.

[0271] Fig.23 is a circuit diagram of an example of a pixel according to the embodiment. Fig.23 The pixel PX9 can be applied to Figure 1 display device. Figure 1 Each pixel PX may include Fig.23 The pixel PX9 can be omitted. Fig.16A Components of the pixel PX2 that are the same or similar are described in detail, and the differences are mainly described.

[0272] Reference Figure 1 and Fig.23, the pixel PX9 may include a first OLED OD1, a second OLED OD2, and a pixel circuit PCIR. The pixel PX9 may include a first scan line SL1 extending in a first direction D1, a second scan line SL2 extending in the first direction D1, a third scan line SL3 extending in the first direction D1, a first light emission control line EL1 extending in the first direction D1, a second light emission control line EL2 extending in the first direction D1, a third light emission control line EL3 extending in the first direction D1, an initialization line INTL extending in the first direction D1, a readout control line RL extending in the first direction D1, a first data line DL1 extending in a second direction D2 intersecting the first direction D1, a second data line DL2 extending in the second direction D2, a readout line ROL extending in the second direction D2, first to eighth transistors T1 to T8, a tenth transistor T10, a storage capacitor CST, a first OLED OD1, and a second OLED OD2. That is, the pixel PX9 may include two OLEDs, nine transistors, eight control lines extending in the first direction D1 (i.e., a first scan line SL1, a second scan line SL2, a third scan line SL3, a first light-emitting control line EL1, a second light-emitting control line EL2, a third light-emitting control line EL3, an initialization line INTL, and a readout control line RL) and three lines extending in the second direction D2 (i.e., a first data line DL1, a second data line DL2, and a readout line ROL).

[0273] The third transistor T3 may be connected between the second node N2 and the third node N3, and operate in response to the third scan signal S3. The first electrode of the third transistor T3 may be connected to the second node N2, and the second electrode of the third transistor T3 may be connected to the third node N3. The gate electrode of the third transistor T3 may be connected to the third scan line SL3. In response to the third scan signal S3 provided at an effective level through the third scan line SL3, the third transistor T3 may be turned on. The third transistor T3 may be turned on, and therefore, the second node N2 may be electrically connected to the third node N3. That is, the third transistor T3 may be diode-connected to the first transistor T1.

[0274] In one embodiment, the scan driver 113 may include an AND circuit. The AND circuit may receive the first scan signal S1 and the second scan signal S2. The AND circuit may generate and output the third scan signal S3 by performing an AND operation on the first scan signal S1 and the second scan signal S2.

[0275] and Fig.16A Compared with the pixel PX2, the pixel PX9 may not include the third OLED OD3, the ninth transistor T9, the eleventh transistor T11, the fourth scan line SL4, and the fourth light emission control line EL4. The pixel PX9 may include only two OLEDs.

[0276] Fig.24 is a circuit diagram of an example of a pixel according to the embodiment. Fig.24 The pixel PX10 can be applied to Figure 1 display device. Figure 1 Each pixel PX may include Fig.24 The pixel PX10 can be omitted. Fig.16A Components of the pixel PX2 that are the same or similar are described in detail, and the differences are mainly described.

[0277] Reference Figure 1 and Fig.24 , the pixel PX10 may include a first OLED OD1, a second OLED OD2, a third OLED OD3, a fourth OLED OD4 and a pixel circuit PCIR. The pixel PX10 may include a first scan line SL1 extending in a first direction D1, a second scan line SL2 extending in the first direction D1, a third scan line SL3 extending in the first direction D1, a fourth scan line SL4 extending in the first direction D1, a fifth scan line SL5 extending in the first direction D1, a first light emission control line EL1 extending in the first direction D1, a second light emission control line EL2 extending in the first direction D1, a third light emission control line EL3 extending in the first direction D1, a fourth light emission control line EL ... A fifth light emitting control line EL5 extending in the first direction D1, an initialization line INTL extending in the first direction D1, a readout control line RL extending in the first direction D1, a first data line DL1 extending in a second direction D2 intersecting the first direction D1, a second data line DL2 extending in the second direction D2, a third data line DL3 extending in the second direction D2, a fourth data line DL4 extending in the second direction D2, a readout line ROL extending in the second direction D2, first to thirteenth transistors T1 to T13, a storage capacitor CST and first to fourth OLEDs OD1 to OD4. That is, the pixel PX10 may include four OLEDs, thirteen transistors, twelve control lines extending in the first direction D1 (i.e., a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, a fifth scan line SL5, a first light-emitting control line EL1, a second light-emitting control line EL2, a third light-emitting control line EL3, a fourth light-emitting control line EL4, a fifth light-emitting control line EL5, an initialization line INTL, and a readout control line RL) and five lines extending in the second direction D2 (i.e., a first data line DL1, a second data line DL2, a third data line DL3, a fourth data line DL4, and a readout line ROL).

[0278] The third transistor T3 may be connected between the second node N2 and the third node N3, and operate in response to the fifth scan signal S5. The first electrode of the third transistor T3 may be connected to the second node N2, and the second electrode of the third transistor T3 may be connected to the third node N3. The gate electrode of the third transistor T3 may be connected to the fifth scan line SL5. In response to the fifth scan signal S5 provided at an effective level through the fifth scan line SL5, the third transistor T3 may be turned on. The third transistor T3 may be turned on, and therefore, the second node N2 may be electrically connected to the third node N3. That is, the third transistor T3 may be diode-connected to the first transistor T1.

[0279] In one embodiment, the scan driver 113 may include an AND circuit. The AND circuit may receive a first scan signal S1, a second scan signal S2, a third scan signal S3, and a fourth scan signal S4. The AND circuit may generate and output a fifth scan signal S5 by performing an AND operation on the first scan signal S1, the second scan signal S2, the third scan signal S3, and the fourth scan signal S4. That is, the fifth scan signal S5 may be as represented in Equation 9. In Equation 9, S5 represents the fifth scan signal S5, S1 represents the first scan signal S1, S2 represents the second scan signal S2, S3 represents the third scan signal S3, and S4 represents the fourth scan signal S4.

[0280] [Equation 9] The twelfth transistor T12 may be connected between the fourth data line DL4 and the first node N1, and operate in response to the fourth scan signal S4. A first electrode of the twelfth transistor T12 may be connected to the fourth data line DL4, and a second electrode of the twelfth transistor T12 may be connected to the first node N1. A gate electrode of the twelfth transistor T12 may be connected to the fourth scan line SL4. In response to the fourth scan signal S4 provided at an effective level through the fourth scan line SL4, the twelfth transistor T12 may be turned on. The twelfth transistor T12 may be turned on, and therefore, the first node N1 may be electrically connected to the fourth data line DL4.

[0281] The anode electrode of the fourth OLED OD4 may be connected to the pixel circuit PCIR, and the cathode electrode of the fourth OLED OD4 may be connected to the second driving power source ELVSS. The fourth OLED OD4 may emit light having a brightness corresponding to the amount of current supplied from the pixel circuit PCIR. The brightness of the fourth OLED OD4 may be controlled by the voltage of the fourth data line DL4 (ie, the fourth data voltage VD4).

[0282] The thirteenth transistor T13 may be connected between the third node N3 and the fourth OLED OD4, and operate in response to the fifth light emitting control signal E5. A first electrode of the thirteenth transistor T13 may be connected to the third node N3, and a second electrode of the thirteenth transistor T13 may be connected to the anode electrode of the fourth OLED OD4. A gate electrode of the thirteenth transistor T13 may be connected to the fifth light emitting control line EL5. In response to the fifth light emitting control signal E5 provided at an effective level through the fifth light emitting control line EL5, the thirteenth transistor T13 may be turned on. The thirteenth transistor T13 may be turned on, and thus, the third node N3 may be electrically connected to the anode electrode of the fourth OLED OD4.

[0283] and Fig.16A Compared with the pixel PX2, the pixel PX10 may further include a fourth OLED OD4, a twelfth transistor T12, a thirteenth transistor T13, a fifth scan line SL5, a fifth light emitting control line EL5, and a fourth data line DL4.

[0284] FIG. 25A to FIG. 25C is a timing diagram of a plurality of signals for controlling a pixel according to an embodiment.

[0285] Reference Figure 6 , the second light emitting control signal E2 may maintain a logic low during the first light emitting interval EM1. FIG. 25A to FIG. 25C , the second light emitting control signal E2 may be logic high for a predetermined period of time during the first light emitting interval EM1.

[0286] The pixel PX according to the embodiment may adjust the brightness of the first OLED OD1 by using the second light emitting control signal E2. The pixel PX may adjust the light emitting time of the first OLED OD1 by using the second light emitting control signal E2 and improve the brightness representation (or gray scale).

[0287] Fig.25A The first light-emitting interval EM1 of the first frame FRM1 is shown. Fig.25B The first light-emitting interval EM1 of the second frame FRM2 is shown, and Fig.25C The first light emitting interval EM1 of the third frame FRM3 is shown. It can be assumed that the brightness of the first frame FRM1 is higher than that of the second frame FRM2.

[0288] Reference Figure 1 , Figure 2 and Fig.25A , from the first time point t1 to the fourth time point t4, the scan signal S may be logic high, the initialization signal INT may be logic high, the readout control signal R may be logic high, the first light-emitting control signal E1 may be logic low, the third light-emitting control signal E3 may be logic high, and the fourth light-emitting control signal E4 may be logic high.

[0289] The second light emitting control signal E2 may be logic low from the first time point t1 to the third time point t3, and may be logic high from the third time point t3 to the fourth time point t4. The second light emitting control signal E2 may be at an active level during the first period T_1.

[0290] In this regard, in the first light-emitting interval EM1, the scan driver 113 may output a scan signal S at an invalid level through the scan line SL, output an initialization signal INT at an invalid level through the initialization line INTL, output a read control signal R at an invalid level through the read control line RL, output a first light-emitting control signal E1 at a valid level through the first light-emitting control line EL1, output a third light-emitting control signal E3 at an invalid level through the third light-emitting control line EL3, and output a fourth light-emitting control signal E4 at an invalid level through the fourth light-emitting control line EL4.

[0291] During the first light-emitting interval EM1, the fourth transistor T4 may be turned on in response to the first light-emitting control signal E1 at an effective level. From the first time point t1 to the third time point t3, the seventh transistor T7 may be turned on in response to the second light-emitting control signal E2 at an effective level. From the third time point t3 to the fourth time point t4, the seventh transistor T7 may be turned off in response to the second light-emitting control signal E2 at an inactive level. From the first time point t1 to the third time point t3, the driving current ID may be supplied to the first OLED OD1. From the third time point t3 to the fourth time point t4, the supply of the driving current ID to the first OLED OD1 may be cut off.

[0292] Reference Figure 1 , Figure 2 and Fig.25B , from the first time point t1 to the fourth time point t4, the scan signal S may be logic high, the initialization signal INT may be logic high, the readout control signal R may be logic high, the first light-emitting control signal E1 may be logic low, the third light-emitting control signal E3 may be logic high, and the fourth light-emitting control signal E4 may be logic high.

[0293] The second light emitting control signal E2 may be logic low from the first time point t1 to the second time point t2, and the second light emitting control signal E2 may be logic high from the second time point t2 to the fourth time point t4. The second light emitting control signal E2 may be at an active level during the second time period T_2. The second time period T_2 may be shorter than the first time period T_1.

[0294] During the first light-emitting interval EM1, the fourth transistor T4 may be turned on in response to the first light-emitting control signal E1 at an effective level. From the first time point t1 to the second time point t2, the seventh transistor T7 may be turned on in response to the second light-emitting control signal E2 at an effective level. From the second time point t2 to the fourth time point t4, the seventh transistor T7 may be turned off in response to the second light-emitting control signal E2 at an inactive level. From the first time point t1 to the second time point t2, the driving current ID may be supplied to the first OLED OD1. From the second time point t2 to the fourth time point t4, the supply of the driving current ID to the first OLED OD1 may be cut off.

[0295] The first time period T_1 may be longer than the second time period T_2. That is, during the first light emitting interval EM1, the time period (i.e., the first time period T_1) during which the driving current ID flows in the first frame FRM1 may be longer than the time period (i.e., the second time period T_2) during which the driving current ID flows in the second frame FRM2. Therefore, even when the same data voltage VD is applied in the first frame FRM1 and the second frame FRM2, the first frame FRM1 may output a light signal having higher brightness than the second frame FRM2.

[0296] The scan driver 113 may adjust the time period of the interval in which the second light emitting control signal E2 is at an effective level based on the set brightness. The second light emitting control signal E2 may vary according to each frame during the light emitting interval EM. For example, when the brightness set for the first frame FRM1 is different from the brightness set for the second frame FRM2, the time period (e.g., the first time period T_1) in which the second light emitting control signal E2 is at an effective level in the first frame FRM1 may be different from the time period (e.g., the second time period T_2) in which the second light emitting control signal E2 is at an effective level in the second frame FRM2. The second light emitting control signal E2 may vary according to the brightness set for each frame, and thus, the time (e.g., dimming time) in which the driving current ID flows may be adjusted. The pixel PX may output a light signal having a brightness according to the intensity of the driving current ID and the dimming time. The brightness of the first OLED OD1 may be controlled by the voltage of the data line DL (i.e., the data voltage VD) and the time period in which the second light emitting control signal E2 is at an effective level.

[0297] Reference Figure 1 , Figure 2 and Fig.25C , from the first time point t1 to the seventh time point t7, the scan signal S may be logic high, the initialization signal INT may be logic high, the read control signal R may be logic high, the first light emitting control signal E1 may be logic low, the third light emitting control signal E3 may be logic high, and the fourth light emitting control signal E4 may be logic high.

[0298] The second light control signal E2 may be logic low from the first time point t1 to the second time point t2. The second light control signal E2 may be logic high from the second time point t2 to the third time point t3. The second light control signal E2 may be logic low from the third time point t3 to the fourth time point t4. The second light control signal E2 may be logic high from the fourth time point t4 to the fifth time point t5. The second light control signal E2 may be logic low from the fifth time point t5 to the sixth time point t6. The second light control signal E2 may be logic high after the sixth time point t6.

[0299] During the first light-emitting interval EM1, in response to the first light-emitting control signal E1 at the effective level, the fourth transistor T4 may be turned on. From the first time point t1 to the second time point t2, the seventh transistor T7 may be turned on in response to the second light-emitting control signal E2 at the effective level. From the second time point t2 to the third time point t3, the seventh transistor T7 may be turned off in response to the second light-emitting control signal E2 at the ineffective level. From the third time point t3 to the fourth time point t4, the seventh transistor T7 may be turned on in response to the second light-emitting control signal E2 at the effective level. From the fourth time point t4 to the fifth time point t5, the seventh transistor T7 may be turned off in response to the second light-emitting control signal E2 at the ineffective level. From the fifth time point t5 to the sixth time point t6, the seventh transistor T7 may be turned on in response to the second light-emitting control signal E2 at the effective level. From the sixth time point t6 to the seventh time point t7, the seventh transistor T7 may be turned off in response to the second light-emitting control signal E2 at the ineffective level.

[0300] From the first time point t1 to the second time point t2, the driving current ID may be supplied to the first OLED OD1. From the second time point t2 to the third time point t3, the supply of the driving current ID to the first OLED OD1 may be cut off. From the third time point t3 to the fourth time point t4, the driving current ID may be supplied to the first OLED OD1. From the fourth time point t4 to the fifth time point t5, the supply of the driving current ID to the first OLED OD1 may be cut off. From the fifth time point t5 to the sixth time point t6, the driving current ID may be supplied to the first OLED OD1. From the sixth time point t6 to the seventh time point t7, the supply of the driving current ID to the first OLED OD1 may be cut off.

[0301] As mentioned above, refer to Fig.25A , in the first light-emitting interval EM1, the second light-emitting control signal E2 may be at an effective level only in the first time period T_1. Fig.25C, in the first light-emitting interval EM1, the second light-emitting control signal E2 may be at an effective level during a time period from the first time point t1 to the second time point t2, a time period from the third time point t3 to the fourth time point t4, and a time period from the fifth time point t5 to the sixth time point t6. During the first light-emitting interval EM1, the second light-emitting control signal E2 may be switched between a logic low and a logic high. By independently controlling the fourth transistor T4 and the seventh transistor T7, the display device 100 may implement PWM. The display device 100 may adjust the light-emitting time of the first OLED OD1 by using the second light-emitting control signal E2. The brightness of the first OLED OD1 may be adjusted according to the light-emitting time of the first OLED OD1. Therefore, the display device 100 may improve brightness performance (or grayscale).

[0302] The reference signal E2 has been described based on the second light emitting control signal E2 and the first OLED OD1. FIG. 25A to FIG. 25C For example, the light emitting time of the second OLED OD2 may be adjusted by controlling the third light emitting control signal E3, and the light emitting time of the third OLED OD3 may be adjusted by controlling the fourth light emitting control signal E4.

[0303] Fig.26 is a graph showing changes in driving current corresponding to changes in data voltage of a pixel.

[0304] The horizontal axis represents the data voltage VD, and the vertical axis represents the driving current ID. Figure 2 , Figure 3A and Fig.26 , the solid line shows Figure 3A The change of the data voltage VD of the pixel PXa corresponds to the change of the driving current ID, and the alternating long and short dashed lines show the Figure 2 The change in the data voltage VD of the pixel PX1 corresponds to the change in the driving current ID.

[0305] When the driving current ID is within the range of the first current amount I1 to the second current amount I2, the Figure 3A The data voltage VD corresponding to the change of the driving current ID may include the first voltage V1 to the third voltage V3. That is, Figure 3A The variation range of the data voltage VD of the pixel PXa may be a first voltage range VR1.

[0306] When the driving current ID falls within the range of the first current amount I1 to the second current amount I2, the Figure 2Each of the plurality of OLEDs (eg, OD1, OD2, and OD3) of the pixel PX1. The data voltage VD corresponding to the change in the driving current ID may include a second voltage V2 to a fourth voltage V4. That is, Figure 2 The variation range of the data voltage VD of the pixel PX1 may be a second voltage range VR2. The second voltage range VR2 may be greater than the first voltage range VR1.

[0307] Figure 3A The storage capacitor CST of the pixel PXa may be connected between the gate electrode of the first transistor T1 and the first driving power source ELVDD. Figure 2 The storage capacitor CST of the pixel PX1 may be connected between the gate electrode of the first transistor T1 and the second electrode of the fourth transistor T4 (i.e., between the first transistor T1 and the fourth transistor T4). Therefore, the variation range of the data voltage VD corresponding to the variation range of the amount of current of the OLED OD may be expanded. The control of the brightness or lightness of the OLED OD may be facilitated by using the data voltage VD.

[0308] Fig. 27 A display device according to an embodiment is shown.

[0309] Fig. 27 The display device 1000 may include a medium to large display panel 1500 and may be applied to, for example, a television and a monitor. Fig. 27 The display device 1000 may include a timing controller 1100, a source driver 1200, a gate driver 1300, a readout circuit 1400, and a display panel 1500. The source driver 1200 may be connected to the display panel 1500. Figure 1 The data driver 112 is substantially the same as the gate driver 1300. Figure 1 The scan driver 113 is substantially the same as the timing controller 1100. Figure 1 The control logic circuit 111 is basically the same.

[0310] The timing controller 1100 may include at least one IC or module. The timing controller 1100 may communicate with a plurality of source driver ICs SDIC and a plurality of gate driver ICs GDIC via a provided interface.

[0311] The timing controller 1100 may generate a control signal for controlling a driving time point of the plurality of source driver ICs SDIC and the plurality of gate driver ICs GDIC, and provide the control signal to the plurality of source driver ICs SDIC and the plurality of gate driver ICs GDIC.

[0312] The source driver 1200 may include a plurality of source driver ICs SDIC, and the plurality of source driver ICs SDIC may be mounted on a circuit film (e.g., a tape carrier package (TCP), a chip on film (COF), and a flexible printed circuit (FPC)) and attached to the display panel 1500 through a tape automated bonding (TAB) scheme, or mounted on a non-display area of ​​the display panel 1500 through a chip on glass (COG) scheme.

[0313] The gate driver 1300 may include a plurality of gate driver ICs GDIC. The plurality of gate driver ICs GDIC may be mounted on a circuit film and attached to the display panel 1500 through a TAB scheme, or may be mounted on a non-display region of the display panel 1500 through a COG scheme. Alternatively, the gate driver 1300 may be directly formed on a lower substrate of the display panel 1500 through a gate driver in panel (GIP) scheme. The gate driver 1300 may be formed in a non-display region outside a pixel array of the display panel 1500 where pixels are formed. The gate driver 1300 may be formed using the same TFT process as the pixel.

[0314] The readout circuit 1400 may include a plurality of readout ICs (RDICs), and the plurality of readout ICs RDICs may be mounted on a circuit film (eg, TCP, COF, and FPC) and attached to the display panel 1500 through a TAB scheme, or mounted on a non-display area of ​​the display panel 1500 through a COG scheme. Figures 1 to 26 As described above, the readout circuit 1400 can generate readout data by reading out the electrical characteristics of the pixel PX. Fig. 27 The source driver 1200 in the embodiment may be a separate chip, but the embodiment is not limited thereto. At least one of the plurality of source driver ICs SDIC may include a reference Figure 1 The readout circuit described (refer to Figure 1 114 in). The display panel 1500 may include a reference Figures 1 to 26 Describe the pixel PX.

[0315] Fig.28 A display device according to an embodiment is shown.

[0316] Fig.28 The display device 2000 may include a display panel 2200 having a small size and may be applied to, for example, a mobile device (eg, a smart phone, a tablet PC) or a wearable device. Fig.28, the display device 2000 may include a display driving circuit 2100 and a display panel 2200. The display driving circuit 2100 may include at least one IC. The display driving circuit 2100 may be mounted on a circuit film (e.g., TCP, COF, FPC) and attached to the display panel 2200 through a TAB scheme, or mounted on a non-display area (e.g., an area where an image is not displayed) of the display panel 2200 through a COG scheme.

[0317] The display driving circuit 2100 may include a source driver 2110, a gate driver 2120, a readout circuit 2130, and a timing controller 2140. The source driver 2110 may be connected to a gate driver 2120. Figure 1 The data driver 112 is substantially the same as the gate driver 2120. Figure 1 The scan driver 113 is substantially the same as the timing controller 2140. Figure 1 The control logic circuit 111 is basically the same as Figures 1 to 14 As described above, the readout circuit 2130 may generate readout data by reading out electrical characteristics of the pixel PX.

[0318] The display panel 2200 can be Figure 1 The display panel 2200 may include pixels PX, and the pixels PX include reference Figures 1 to 26 Description of OLEDs.

[0319] Fig.29 is a block diagram of an electronic device according to an embodiment.

[0320] Reference Fig.29 , the electronic device 3000 may include a main processor 3100, a touch panel 3200, a touch driver IC (TDI) 3202, a display panel 3300, a display driver IC (DDI) 3302, a system memory 3400, a storage device 3500, an audio processor 3600, a communication block 3700, and an image processor 3800. In one embodiment, the electronic device 3000 may be one of various electronic devices (such as a mobile communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a smart phone, a tablet computer, a laptop computer, and a wearable device), or one of various communication devices supporting wireless communication relay (such as a wireless router and a wireless communication base station). In one embodiment, the electronic device 3000 may also include in addition to Fig.16A Components other than those shown in the figure or components that may be omitted from the electronic device 3000 Fig.15 Some of the components shown in FIG.

[0321] The main processor 3100 may control all operations of the electronic device 3000. The main processor 3100 may control / manage operations of components of the electronic device 3000. The main processor 3100 may process various operations to operate the electronic device 3000.

[0322] The touch panel 3200 may be configured to detect a touch input from a user via control of the TDI 3202. The display panel 3300 may be configured to display image information via control of the DDI 3302. In one embodiment, the display panel 3300 and the DDI 3302 may be configured to be compatible with the embodiment described above. Figures 1 to 26 The display panel 3300 and the DDI 3302 may correspond to the display panel and the display driving circuit described in the embodiment of the present invention. Figures 1 to 26 Describe the method of operation to operate.

[0323] The system memory 3400 may store data used for the operation of the electronic device 3000. For example, the system memory 3400 may include a volatile memory (e.g., static random access memory (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM)) and / or a nonvolatile memory (e.g., phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), and ferroelectric RAM (FRAM)).

[0324] The storage device 3500 may store data regardless of power supply. As an example, the storage device 3500 may include at least one of various non-volatile memories such as flash memory, PRAM, MRAM, ReRAM, and FRAM. As an example, the storage device 3500 may include an embedded memory and / or a removable memory of the electronic device 3000.

[0325] The audio processor 3600 may process an audio signal by using the audio signal processor 3610. The audio processor 3600 may receive an audio input through a microphone 3620 or provide an audio output through a speaker 3630.

[0326] The communication block 3700 may exchange signals with an external device / system through an antenna 3710. A transceiver 3720 and a modulator / demodulator (modem) 3730 of the communication block 3700 may process signals exchanged with an external device / system according to at least one of various wireless communication protocols such as Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMax), Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Bluetooth, Near Field Communication (NFC), Wireless Fidelity (Wi-Fi), and Radio Frequency Identification (RFID).

[0327] The image processor 3800 may receive light through the lens 3810. An image device 3820 and an image signal processor (ISP) 3830 in the image processor 3800 may generate image information about an external object based on the received light.

[0328] In some embodiments, according to example embodiments, Figure 1 , Figure 4 , Figure 5 and Figure 27 to Figure 29 Each component represented by the box shown in can be implemented as various numbers of hardware, software and / or firmware structures that perform the above-mentioned corresponding functions. For example, at least one of these components may include various hardware components, including digital circuits, programmable or non-programmable logic devices or arrays, application-specific integrated circuits (ASICs), transistors, capacitors, logic gates, or other circuit systems using direct circuit structures (such as memory, processors, logic circuits, lookup tables, etc.), which can perform corresponding functions through the control of one or more microprocessors or other control devices. In addition, at least one of these components may include a part of a module, program or code, and a part of a module, program or code contains one or more executable instructions for performing a specified logical function and executed by one or more microprocessors or other control devices. In addition, at least one of these components may also include a processor (such as a central processing unit (CPU), microprocessor, etc. that performs the corresponding function) or may be implemented by a processor (such as a central processing unit (CPU), microprocessor, etc. that performs the corresponding function). The functional aspects of the example embodiments can be implemented in algorithms executed on one or more processors. In addition, the components, elements, modules or units represented by blocks or processing steps may adopt any number of related technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0329] While aspects of the embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A display device, comprising: Pixels, arranged in rows and columns; a scan driver connected to the rows of pixels, wherein a first row of the rows of pixels is connected to the scan driver through a scan line, a first light emission control line, a second light emission control line, a third light emission control line, a fourth light emission control line, an initialization line, and a readout control line; a data driver connected to the columns of pixels, wherein a first column of the columns of pixels is connected to a scan driver through a data line; and a readout circuit connected to the columns of pixels and configured to read out electrical characteristics of the pixels via a readout line, wherein a first column is connected to the readout circuit via the readout line, Wherein, the first pixel among the pixels comprises: a first transistor including a first electrode connected to the first node, a second electrode connected to the third node, and a gate connected to the second node; a second transistor including a first electrode connected to the data line, a second electrode connected to the first node, and a gate connected to the scan line; a third transistor including a first electrode connected to the second node, a second electrode connected to the third node, and a gate connected to the scan line; a fourth transistor including a first electrode connected to a power supply node configured to supply a power supply voltage, a second electrode connected to the first node, and a gate connected to the first light emission control line; a fifth transistor including a first electrode connected to the readout line, a second electrode connected to the second node, and a gate connected to the initialization line; a sixth transistor including a first electrode connected to the readout line, a second electrode connected to the third node, and a gate connected to the readout control line; a seventh transistor including a first electrode connected to the third node, a second electrode, and a gate connected to the second light emitting control line; an eighth transistor including a first electrode connected to the third node, a second electrode, and a gate connected to a third light emitting control line; a ninth transistor including a first electrode connected to the third node, a second electrode, and a gate connected to a fourth light emitting control line; a capacitor connected to the first node and the second node; a first organic light emitting diode connected between the second electrode of the seventh transistor and a ground node; a second organic light emitting diode between the second electrode of the eighth transistor and the ground node; and The third organic light emitting diode is connected between the second electrode of the ninth transistor and the ground node.

2. The display device according to claim 1, wherein: The scan driver is configured to: in a reset interval of the first pixel, output a scan signal at an invalid level through the scan line, output an initialization signal at a valid level through the initialization line, output a readout control signal at an invalid level through the readout control line, output a first light-emitting control signal at a valid level through the first light-emitting control line, output a second light-emitting control signal at an invalid level through the second light-emitting control line, output a third light-emitting control signal at an invalid level through the third light-emitting control line, and output a fourth light-emitting control signal at an invalid level through the fourth light-emitting control line.

3. The display device according to claim 1, wherein: The scan driver is configured to: in a programming interval of a first pixel, output a scan signal at a valid level through a scan line, output an initialization signal at an invalid level through an initialization line, output a readout control signal at an invalid level through a readout control line, output a first light-emitting control signal at an invalid level through a first light-emitting control line, output a second light-emitting control signal at an invalid level through a second light-emitting control line, output a third light-emitting control signal at an invalid level through a third light-emitting control line, and output a fourth light-emitting control signal at an invalid level through a fourth light-emitting control line.

4. The display device according to claim 1, wherein: The scan driver is configured to: in a holding interval of the first pixel, output a scan signal at an invalid level through the scan line, output an initialization signal at an invalid level through the initialization line, output a readout control signal at an invalid level through the readout control line, output a first light-emitting control signal at an invalid level through the first light-emitting control line, output a second light-emitting control signal at an invalid level through the second light-emitting control line, output a third light-emitting control signal at an invalid level through the third light-emitting control line, and output a fourth light-emitting control signal at an invalid level through the fourth light-emitting control line.

5. The display device according to claim 1, wherein: The scan driver is configured to: in a first light-emitting interval of a first pixel, output a scan signal at an invalid level through a scan line, output an initialization signal at an invalid level through an initialization line, output a readout control signal at an invalid level through a readout control line, output a first light-emitting control signal at a valid level through a first light-emitting control line, output a second light-emitting control signal at a valid level through a second light-emitting control line, output a third light-emitting control signal at an invalid level through a third light-emitting control line, and output a fourth light-emitting control signal at an invalid level through a fourth light-emitting control line.

6. The display device according to claim 1, wherein: The scan driver is configured to: in the second light-emitting interval of the first pixel, output a scan signal at an invalid level through the scan line, output an initialization signal at an invalid level through the initialization line, output a readout control signal at an invalid level through the readout control line, output a first light-emitting control signal at a valid level through the first light-emitting control line, output a second light-emitting control signal at an invalid level through the second light-emitting control line, output a third light-emitting control signal at a valid level through the third light-emitting control line, and output a fourth light-emitting control signal at an invalid level through the fourth light-emitting control line.

7. The display device according to claim 1, wherein: The scan driver is configured to: in a third light-emitting interval of the first pixel, output a scan signal at an invalid level through the scan line, output an initialization signal at an invalid level through the initialization line, output a readout control signal at an invalid level through the readout control line, output a first light-emitting control signal at a valid level through the first light-emitting control line, output a second light-emitting control signal at an invalid level through the second light-emitting control line, output a third light-emitting control signal at an invalid level through the third light-emitting control line, and output a fourth light-emitting control signal at a valid level through the fourth light-emitting control line.

8. The display device according to claim 1, wherein: The scan driver is configured to: in a first readout interval of the first pixel, output a scan signal at an invalid level through the scan line, output an initialization signal at an invalid level through the initialization line, output a readout control signal at an effective level through the readout control line, output a first light emission control signal at an effective level through the first light emission control line, output a second light emission control signal at an invalid level through the second light emission control line, output a third light emission control signal at an invalid level through the third light emission control line, and output a fourth light emission control signal at an invalid level through the fourth light emission control line, and The readout circuit is further configured to generate data corresponding to the drive current based on a signal received through the readout line.

9. The display device according to claim 1, wherein: The scan driver is configured to: in a second readout interval of the first pixel, output a scan signal at a valid level through the scan line, output an initialization signal at an invalid level through the initialization line, output a readout control signal at a valid level through the readout control line, output a first light emission control signal at an invalid level through the first light emission control line, output a second light emission control signal at an invalid level through the second light emission control line, output a third light emission control signal at an invalid level through the third light emission control line, and output a fourth light emission control signal at an invalid level through the fourth light emission control line, and The readout circuit is further configured to generate data corresponding to the threshold voltage based on a signal received through the readout line.

10. The display device according to claim 1, wherein: The scan driver is configured to: in a third readout interval of the first pixel, output a scan signal at an invalid level through the scan line, output an initialization signal at an invalid level through the initialization line, output a readout control signal at an effective level through the readout control line, output a first light emission control signal at an effective level through the first light emission control line, output a second light emission control signal at an effective level through the second light emission control line, output a third light emission control signal at an invalid level through the third light emission control line, and output a fourth light emission control signal at an invalid level through the fourth light emission control line, and The readout circuit is further configured to generate data corresponding to the forward voltage of the first organic light emitting diode based on a signal received through the readout line.

11. The display device according to claim 1, wherein: The scan driver is configured to: in a fourth readout interval of the first pixel, output a scan signal at an invalid level through the scan line, output an initialization signal at an invalid level through the initialization line, output a readout control signal at an effective level through the readout control line, output a first light emission control signal at an effective level through the first light emission control line, output a second light emission control signal at an invalid level through the second light emission control line, output a third light emission control signal at an effective level through the third light emission control line, and output a fourth light emission control signal at an invalid level through the fourth light emission control line, and The readout circuit is further configured to generate data corresponding to the forward voltage of the second organic light emitting diode based on a signal received through the readout line.

12. The display device according to claim 1, wherein: The scan driver is configured to: in a fifth readout interval of the first pixel, output a scan signal at an invalid level through the scan line, output an initialization signal at an invalid level through the initialization line, output a readout control signal at an effective level through the readout control line, output a first light emission control signal at an effective level through the first light emission control line, output a second light emission control signal at an invalid level through the second light emission control line, output a third light emission control signal at an invalid level through the third light emission control line, and output a fourth light emission control signal at an effective level through the fourth light emission control line, and The readout circuit is further configured to generate data corresponding to the forward voltage of the third organic light emitting diode based on the signal received through the readout line.

13. The display device according to claim 1, wherein: The scan driver is configured to: in a first light-emitting interval of the first pixel, output a scan signal at an inactive level through the scan line, output an initialization signal at an inactive level through the initialization line, output a readout control signal at an inactive level through the readout control line, output a first light-emitting control signal at an active level through the first light-emitting control line, output a third light-emitting control signal at an inactive level through the third light-emitting control line, and output a fourth light-emitting control signal at an inactive level through the fourth light-emitting control line, and The scan driver is configured to output a second light emitting control signal at a valid level through a second light emitting control line in a first interval of the first light emitting interval, and to output a second light emitting control signal at an invalid level through the second light emitting control line in a second interval of the first light emitting interval.

14. The display device according to claim 1, wherein: The second transistor is smaller than the third transistor.

15. A display device, comprising: A display panel including a plurality of pixels; as well as Display driving circuit, including scanning driver, data driver and readout circuit, Wherein, the first pixel among the plurality of pixels comprises: a first transistor between the first node and the third node and configured to operate in response to a voltage of the second node; a second transistor connected between the first node and the first data line and configured to operate in response to a first scan signal received through the first scan line; a third transistor connected between the second node and the third node and configured to operate in response to a fourth scan signal received through a fourth scan line; a fourth transistor connected between the first driving power source and the first node and configured to operate in response to a first light emission control signal received through the first light emission control line; a fifth transistor connected between the readout line and the second node and configured to operate in response to an initialization signal received through the initialization line; a sixth transistor connected between the readout line and the third node and configured to operate in response to a readout control signal received through the readout control line; a seventh transistor connected between the third node and the first organic light emitting diode and configured to operate in response to a second light emission control signal received through a second light emission control line; an eighth transistor connected between the third node and the second organic light emitting diode and configured to operate in response to a third light emission control signal received through a third light emission control line; a ninth transistor connected between the third node and the third organic light emitting diode and configured to operate in response to a fourth light emission control signal received through a fourth light emission control line; a tenth transistor connected between the first node and the second data line and configured to operate in response to a second scan signal received through the second scan line; an eleventh transistor connected between the first node and the third data line and configured to operate in response to a third scan signal received through the third scan line; a capacitor connected between the first node and the second node; A first organic light emitting diode connected between the seventh transistor and the second driving power source; a second organic light emitting diode connected between the eighth transistor and the second driving power source; and a third organic light emitting diode connected between the ninth transistor and the second driving power source, The scan driver is connected to the first pixel through the first scan line, the second scan line, the third scan line, the fourth scan line, the initialization line, the readout control line, the first light emitting control line, the second light emitting control line, the third light emitting control line and the fourth light emitting control line. wherein the data driver is connected to the first pixel through the first data line, the second data line, and the third data line, and is configured to supply a first data voltage corresponding to the brightness of the first organic light emitting diode through the first data line, supply a second data voltage corresponding to the brightness of the second organic light emitting diode through the second data line, and supply a third data voltage corresponding to the brightness of the third organic light emitting diode through the third data line, and The readout circuit is connected to the first pixel through the readout line and is configured to read out the electrical characteristics of the plurality of pixels through the readout line.

16. The display device according to claim 15, wherein: The scan driver is configured to generate and output a fourth scan signal by performing an AND operation on the first scan signal, the second scan signal, and the third scan signal.

17. The display device according to claim 15, wherein: The scan driver is configured to: in a first programming interval of a first pixel, output a first scan signal at a valid level through a first scan line, output a second scan signal at an invalid level through a second scan line, output a third scan signal at an invalid level through a third scan line, output a fourth scan signal at a valid level through a fourth scan line, output an initialization signal at an invalid level through an initialization line, output a readout control signal at an invalid level through a readout control line, output a first light-emitting control signal at an invalid level through a first light-emitting control line, output a second light-emitting control signal at an invalid level through a second light-emitting control line, output a third light-emitting control signal at an invalid level through a third light-emitting control line, and output a fourth light-emitting control signal at an invalid level through a fourth light-emitting control line.

18. The display device according to claim 15, wherein: The scan driver is configured to: in a second programming interval of the first pixel, output a first scan signal at an invalid level through the first scan line, output a second scan signal at an invalid level through the second scan line, output a third scan signal at an invalid level through the third scan line, output a fourth scan signal at an invalid level through the fourth scan line, output an initialization signal at an invalid level through the initialization line, output a readout control signal at an invalid level through the readout control line, output a first light-emitting control signal at an invalid level through the first light-emitting control line, output a second light-emitting control signal at an invalid level through the second light-emitting control line, output a third light-emitting control signal at an invalid level through the third light-emitting control line, and output a fourth light-emitting control signal at an invalid level through the fourth light-emitting control line.

19. The display device according to claim 15, wherein: The scan driver is configured to: in a third programming interval of the first pixel, output a first scan signal at an invalid level through the first scan line, output a second scan signal at an invalid level through the second scan line, output a third scan signal at an invalid level through the third scan line, output a fourth scan signal at an invalid level through the fourth scan line, output an initialization signal at an invalid level through the initialization line, output a readout control signal at an invalid level through the readout control line, output a first light-emitting control signal at an invalid level through the first light-emitting control line, output a second light-emitting control signal at an invalid level through the second light-emitting control line, output a third light-emitting control signal at an invalid level through the third light-emitting control line, and output a fourth light-emitting control signal at an invalid level through the fourth light-emitting control line.

20. A display device, comprising: Pixels, arranged in rows and columns; a scan driver connected to the rows of pixels, wherein a first row of the rows of pixels is connected to the scan driver through a scan line, a first light emission control line, a second light emission control line, a third light emission control line, an initialization line, and a readout control line; a data driver connected to the columns of pixels, wherein a first column of the columns of pixels is connected to a scan driver through a data line; and a readout circuit connected to the columns of pixels and configured to read out electrical characteristics of the pixels via a readout line, wherein a first column is connected to the readout circuit via the readout line, Wherein, the first pixel among the pixels comprises: a first transistor including a first electrode connected to the first node, a second electrode connected to the third node, and a gate connected to the second node; a second transistor including a first electrode connected to the data line, a second electrode connected to the first node, and a gate connected to the scan line; a third transistor including a first electrode connected to the second node, a second electrode connected to the third node, and a gate connected to the scan line; a fourth transistor including a first electrode connected to a power supply node configured to supply a power supply voltage, a second electrode connected to the first node, and a gate connected to the first light emission control line; a fifth transistor including a fifth electrode connected to the readout line, a second electrode connected to the second node, and a gate connected to the initialization line; a sixth transistor including a first electrode connected to the readout line, a second electrode connected to the third node, and a gate connected to the readout control line; a seventh transistor including a first electrode connected to the third node, a second electrode, and a gate connected to the second light emitting control line; an eighth transistor including a first electrode connected to the third node, a second electrode, and a gate connected to a third light emitting control line; a capacitor connected between the first node and the second node; a first organic light emitting diode connected between the second electrode of the seventh transistor and a ground node; and a second organic light emitting diode connected between the second electrode of the eighth transistor and the ground node, The frame of the first pixel includes a first subframe and a second subframe, and The first pixel is configured to perform a reset operation, a programming operation, a holding operation, and a light-emitting operation on the first organic light-emitting diode in a first subframe, and the first pixel is configured to perform a reset operation, a programming operation, a holding operation, and a light-emitting operation on the second organic light-emitting diode in a second subframe.

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