Grid transfer circuit and display device

Abstract

The invention provides a grid transfer circuit and a display device, the grid transfer circuit comprises multiple stages of grid transfer units, and each stage of grid transfer unit comprises a pre-charging module, a first output module, a second output module, an output pull-down module, a node pull-down module and a stabilizing module, the pre-charging module charges a first node according to a pre-stage transmission signal and a pre-stage grid signal, the first output module outputs a current-stage grid signal according to the potential of the first node and a current-stage first clock signal, and the second output module outputs a current-stage transmission signal according to the potential of the first node and the current-stage first clock signal; the output pull-down module pulls down the first output end according to a post-stage grid signal and a first low level signal, the pull-down module pulls down the first node according to the post-stage grid signal and a second clock signal of the stage, and the stabilizing module is used for maintaining low level. The invention can reduce the falling edge time of the gate signal and improve the image quality of the product.

Description

Technical Field

[0001] The present invention relates to the field of display driving technology, and in particular to a gate transfer circuit and a display device. Background Art

[0002] Display devices, such as liquid crystal displays (LCDs), have gradually replaced traditional cathode ray tube displays due to their many advantages such as being light, thin, energy-efficient, and radiation-free. They are widely used in electronic devices such as high-definition digital televisions, desktop computers, personal digital assistants, laptops, mobile phones, digital cameras, and so on.

[0003] The display device can be provided with a gate transfer circuit to provide a gate signal to the gate line. The high and low level changes of the gate signal can be used to activate or shut down the thin film transistor connected to the gate line, thereby controlling the switching of the pixel and realizing the display of the image. However, in order to avoid abnormal image quality, it is necessary to reduce the falling edge time of the gate signal to improve the signal transmission rate and timing accuracy, thereby replacing the switching element that outputs the gate signal in the gate transfer circuit with a larger switching element, but it will also lead to an increase in the clock load, which will increase the power consumption of the display device. Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the invention

[0004] In view of this, the present invention provides a gate transfer circuit and a display device, which can reduce the falling edge time of the gate signal and improve the product image quality.

[0005] The embodiment of the present invention provides a gate transfer circuit, including a multi-stage gate transfer unit, each stage of the gate transfer unit includes a pre-charging module, a first output module, a second output module, an output pull-down module, a node pull-down module and a stabilization module; the pre-charging module is connected to a first node, and charges the first node according to a previous stage transfer signal and a previous stage gate signal; the first output module is connected to the pre-charging module at the first node, and outputs the gate signal of the current stage at a first output terminal according to the potential of the first node and a first clock signal of the current stage; the second output module is connected to the pre-charging module at the first node, and outputs the gate signal of the current stage at a first output terminal according to the potential of the first node and a first clock signal of the current stage The output pull-down module is connected to the first output module at the first output end, and pulls the first output end down to a low level according to the subsequent gate signal and the first low-level signal; the node pull-down module is connected to the pre-charge module at the first node, and pulls the first node down to a low level according to the subsequent gate signal and the second clock signal of the current stage; the stabilizing module is connected to the first node, the first output end and the second output end, and the stabilizing module is used to maintain the first node, the first output end and the second output end at a low level at the same time when the first node is pulled down to a low level.

[0006] Specifically, the pre-charging module includes a first switching element, which includes a first control end, a first path end and a second path end. The first control end of the first switching element receives the previous stage transfer signal, the first path end of the first switching element receives the previous stage gate signal, and the second path end of the first switching element is connected to the first node.

[0007] Specifically, the first output module includes a second switch element, the second switch element includes a second control end, a third path end and a fourth path end, the second control end of the second switch element is connected to the first node, the third path end of the second switch element receives the first clock signal of the current stage, and the fourth path end of the second switch element is connected to the first output end.

[0008] Specifically, the second output module includes a third switch element, and the third switch element includes a third control end, a fifth path end and a sixth path end. The third control end of the third switch element is connected to the first node, the fifth path end of the third switch element receives the first clock signal of this stage, and the sixth path end of the third switch element is connected to the second output end.

[0009] Specifically, the output pull-down module includes a fourth switching element, the fourth switching element includes a fourth control terminal, a seventh path terminal and an eighth path terminal, the fourth control terminal of the fourth switching element receives the post-stage gate signal, the seventh path terminal of the fourth switching element receives the first output terminal, and the eighth path terminal of the fourth switching element is connected to the first low-level signal.

[0010] Specifically, the node pull-down module includes a fifth switch element, the fifth switch element includes a fifth control end, a ninth path end and a tenth path end, the fifth control end of the fifth switch element receives the subsequent gate signal, the ninth path end of the fifth switch element is connected to the first node, and the tenth path end of the fifth switch element receives the second clock signal of the current stage.

[0011] Specifically, the stabilization module includes a sixth switch element to a nineteenth switch element. The sixth switch element includes a sixth control terminal, an eleventh channel terminal and a twelfth channel terminal, the sixth control terminal of the sixth switch element receives a first control signal, the eleventh channel terminal of the sixth switch element is connected to the sixth control terminal of the sixth switch element, and the twelfth channel terminal of the sixth switch element is connected to the second node. The seventh switch element includes a seventh control terminal, a thirteenth channel terminal and a fourteenth channel terminal, the seventh control terminal of the seventh switch element receives the first control signal, the thirteenth channel terminal of the seventh switch element receives a second low level signal, and the fourteenth channel terminal of the seventh switch element is connected to the third node. The eighth switch element includes an eighth control terminal, a fifteenth channel terminal and a sixteenth channel terminal, the eighth control terminal of the eighth switch element receives a second control signal, the fifteenth channel terminal of the eighth switch element is connected to the third node, and the sixteenth channel terminal of the eighth switch element is connected to the eighth control terminal of the eighth switch element. The ninth switch element includes a ninth control terminal, a seventeenth channel terminal and an eighteenth channel terminal, the ninth control terminal of the ninth switch element receives the second control signal, the seventeenth channel terminal of the ninth switch element is connected to the second node, and the eighteenth channel terminal of the ninth switch element receives the second low level signal. The tenth switch element includes a tenth control terminal, a nineteenth channel terminal and a twentieth channel terminal, the tenth control terminal of the tenth switch element is connected to the first node, the nineteenth channel terminal of the tenth switch element receives the second low level signal, and the twentieth channel terminal of the tenth switch element is connected to the second node. The eleventh switch element includes an eleventh control terminal, a twenty-first channel terminal and a twenty-second channel terminal, the eleventh control terminal of the eleventh switch element is connected to the first node, the twenty-first channel terminal of the eleventh switch element receives the second low level signal, and the twenty-second channel terminal of the eleventh switch element is connected to the third node. The twelfth switch element includes a twelfth control terminal, a twenty-third channel terminal and a twenty-fourth channel terminal, the twelfth control terminal of the twelfth switch element is connected to the second node, the twenty-third channel terminal of the twelfth switch element is connected to the first node, and the twenty-fourth channel terminal of the twelfth switch element receives the second low level signal. The thirteenth switch element includes a thirteenth control terminal, a twenty-fifth channel terminal and a twenty-sixth channel terminal, the thirteenth control terminal of the thirteenth switch element is connected to the third node, the twenty-fifth channel terminal of the thirteenth switch element receives the second low level signal, and the twenty-sixth channel terminal of the thirteenth switch element is connected to the first node.The fourteenth switch element includes a fourteenth control terminal, a twenty-seventh channel terminal and a twenty-eighth channel terminal, the fourteenth control terminal of the fourteenth switch element is connected to the second node, the twenty-seventh channel terminal of the fourteenth switch element is connected to the first output terminal, and the twenty-eighth channel terminal of the fourteenth switch element receives the first low-level signal. The fifteenth switch element includes a fifteenth control terminal, a twenty-ninth channel terminal and a thirtieth channel terminal, the fifteenth control terminal of the fifteenth switch element is connected to the third node, the twenty-ninth channel terminal of the fifteenth switch element is connected to the twenty-eighth channel terminal of the fourteenth switch element, receives the first low-level signal, and the thirtieth channel terminal of the fifteenth switch element is connected to the first output terminal. The sixteenth switch element includes a sixteenth control terminal, a thirty-first channel terminal and a thirty-second channel terminal, the sixteenth control terminal of the sixteenth switch element is connected to the second node, the thirty-first channel terminal of the sixteenth switch element is connected to the second output terminal, and the thirty-second channel terminal of the sixteenth switch element receives the first low-level signal. The seventeenth switch element includes a seventeenth control terminal, a thirty-third channel terminal and a thirty-fourth channel terminal. The seventeenth control terminal of the seventeenth switch element is connected to the third node, the thirty-third channel terminal of the seventeenth switch element is connected to the thirty-second channel terminal of the sixteenth switch element to receive the first low level signal, and the thirty-fourth channel terminal of the seventeenth switch element is connected to the second output terminal.

[0012] Specifically, the first control signal and the second control signal have opposite polarities, and both reverse their polarities once per frame.

[0013] Specifically, the output pull-down module is arranged at the tail end of the gate line, and is connected to the first output end through the gate line.

[0014] An embodiment of the present invention further provides a display device, comprising the above-mentioned gate transfer circuit.

[0015] The gate transfer circuit and display device provided by the present invention include a multi-stage gate transfer unit, each stage of the gate transfer unit includes a pre-charging module, a first output module, a second output module, an output pull-down module, a node pull-down module and a stabilization module, wherein the output pull-down module is connected to the first output module at the first output end, and pulls the first output end down to a low level according to the subsequent gate signal and the first low-level signal. Thus, the gate transfer circuit can output multiple gate signals in sequence, has a strong output capacity and stability, and can reduce the falling edge time of the gate signal without increasing the clock load, thereby improving the product image quality; at the same time, the gate transfer circuit uses fewer unit devices, which can effectively save the layout area and facilitate the narrow frame of the display device.

[0016] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a circuit connection diagram of a gate transfer unit of a gate transfer circuit according to an embodiment of the present invention.

[0018] Figures 2 to 5 yes Figure 1 Timing diagram of the gate transfer unit in four stages.

[0019] Figure 6 FIG. 4 is a cascade circuit diagram of a gate transfer circuit according to an embodiment of the present invention.

[0020] Figure 7 FIG. 4 is a full-stage circuit diagram of a gate transfer circuit according to an embodiment of the present invention.

[0021] Figure 8 and Fig. 9 They are Figure 7 A diagram of clock signals and gate signals in one embodiment.

[0022] Fig.10 yes Figure 1 A schematic diagram of gate signal comparison between a gate transfer unit having a 17T1C structure and a gate transfer unit having a 16T1C structure.

[0023] Fig.11 It is a schematic structural diagram of a gate transfer circuit according to another embodiment of the present invention.

[0024] Fig.12 yes Fig.11 A circuit connection diagram of a gate transfer unit.

[0025] Fig.13 and Fig.14 They are Fig.11 A diagram of clock signals and gate signals in one embodiment. DETAILED DESCRIPTION

[0026] In order to further explain the technical means and effects adopted by the present invention to achieve the intended purpose, the specific implementation methods, methods, steps, structures, characteristics and effects of the gate transfer circuit and display device proposed in the present invention are described in detail below in combination with the accompanying drawings and preferred embodiments.

[0027] Figure 1 FIG. 1 is a circuit connection diagram of a gate transfer unit of a gate transfer circuit according to an embodiment of the present invention. Figure 1The gate transfer circuit of this embodiment includes multiple gate transfer units, and each gate transfer unit includes: a pre-charging module 10, a first output module 20, a second output module 30, an output pull-down module 40, a node pull-down module 50 and a stabilization module 60.

[0028] In the embodiment of the present invention, the gate transfer units may be connected in sequence in a continuous manner or in a sequentially spaced manner. Figure 1 An example is that the gate transfer units are connected in sequence at intervals, for example, the n-th gate transfer unit is respectively connected to the n-2-th gate transfer unit and the n+2-th gate transfer unit, then the current-stage gate signal and the current-stage transfer signal output by the n-th gate transfer unit can be represented by Gn and Zn, respectively, the previous-stage gate signal and the previous-stage transfer signal received by the n-th gate transfer unit can be represented by Gn-2 and Zn-2, respectively, and the subsequent-stage gate transfer signal received by the n-th gate transfer unit can be represented by Gn+2.

[0029] The pre-charging module 10 is connected to the first node Qn, and charges the first node Qn according to the previous stage transfer signal Zn-2 and the previous stage gate signal Gn-2.

[0030] The first output module 20 is connected to the pre-charging module 10 at the first node Qn, and outputs the gate signal Gn of this stage to the connected gate line at the first output terminal according to the potential of the first node Qn and the first clock signal CLK2 of this stage.

[0031] The second output module 30 is connected to the pre-charging module 10 at the first node Qn, and outputs the current stage transfer signal Zn at the second output terminal according to the potential of the first node Qn and the current stage first clock signal CLK2.

[0032] The output pull-down module 40 is connected to the first output module 20 at the first output terminal, and pulls the first output terminal down to a low level according to the rear-stage gate signal Gn+2 and the first low-level signal VGL.

[0033] The node pull-down module 50 is connected to the pre-charging module 10 at the first node Qn, and pulls the first node Qn down to a low level according to the subsequent gate signal Gn+2 and the second clock signal CLK3 of the current stage.

[0034] The stabilizing module 60 is connected to the first node Qn, the first output terminal and the second output terminal. The stabilizing module 60 is used to maintain the first node Qn, the first output terminal and the second output terminal at a low level when the first node Qn is pulled down to a low level.

[0035] It is worth noting that if the n-th gate transfer unit at the beginning of the circuit has no connected previous gate transfer unit, then the external signal circuit needs to provide the previous gate signal Gn-2 and the previous transfer signal Zn-2, and the previous gate signal Gn-2 and the previous transfer signal Zn-2 are provided directly by the timing control circuit or provide the corresponding start signal STV1 through the source drive circuit. If the n-th gate transfer unit at the end of the circuit has no connected subsequent gate transfer unit, then the external signal circuit needs to provide the subsequent gate signal Gn+2, and the subsequent gate signal Gn+2 is provided directly by the timing control circuit or provides the corresponding pull-down signal STV2 through the source drive circuit.

[0036] In one embodiment of the present invention, the pre-charging module 10 may include a first switching element M1, the first switching element M1 includes a first control end, a first path end and a second path end, the first control end of the first switching element M1 receives a previous stage transfer signal Zn-2, the first path end of the first switching element M1 receives a previous stage gate signal Gn-2, and the second path end of the first switching element M1 is connected to the first node Qn.

[0037] In one embodiment of the present invention, the first output module 20 may include a second switch element M2, the second switch element M2 includes a second control end, a third path end and a fourth path end, the second control end of the second switch element M2 is connected to the first node Qn, the third path end of the second switch element M2 receives the first clock signal CLK2 of this stage, and the fourth path end of the second switch element M2 is connected to the first output end.

[0038] In one embodiment of the present invention, the second output module 30 may include a third switch element M3, the third switch element M3 includes a third control end, a fifth path end and a sixth path end, the third control end of the third switch element M3 is connected to the first node Qn, the fifth path end of the third switch element M3 receives the first clock signal CLK2 of this stage, and the sixth path end of the third switch element M3 is connected to the second output end.

[0039] In one embodiment of the present invention, the output pull-down module 40 may include a fourth switch element M4, the fourth switch element M4 includes a fourth control terminal, a seventh path terminal and an eighth path terminal, the fourth control terminal of the fourth switch element M4 receives the subsequent gate signal Gn+2, the seventh path terminal of the fourth switch element M4 is connected to the first output terminal, and the eighth path terminal of the fourth switch element M4 is connected to the first low-level signal VGL.

[0040] In one embodiment of the present invention, the node pull-down module 50 may include a fifth switch element M5, the fifth switch element M5 includes a fifth control end, a ninth path end and a tenth path end, the fifth control end of the fifth switch element M5 receives the subsequent gate signal Gn+2, the ninth path end of the fifth switch element M5 is connected to the first node Qn, and the tenth path end of the fifth switch element M5 receives the second clock signal CLK3 of this stage.

[0041] In one embodiment of the present invention, the stabilization module 60 may include: a sixth switch element M6, a seventh switch element M7, an eighth switch element M8, a ninth switch element M9, a tenth switch element M10, an eleventh switch element M11, a twelfth switch element M12, a thirteenth switch element M13, a fourteenth switch element M14, a fifteenth switch element M15, a sixteenth switch element M16 and a seventeenth switch element M17.

[0042] The sixth switch element M6 includes a sixth control terminal, an eleventh channel terminal and a twelfth channel terminal, the sixth control terminal of the sixth switch element M6 receives the first control signal V1, the eleventh channel terminal of the sixth switch element M6 is connected to the sixth control terminal of the sixth switch element M6, and the twelfth channel terminal of the sixth switch element M6 is connected to the second node QB1. The seventh switch element M7 includes a seventh control terminal, a thirteenth channel terminal and a fourteenth channel terminal, the seventh control terminal of the seventh switch element M7 is connected to the eleventh channel terminal of the sixth switch element M6, receives the first control signal V1, the thirteenth channel terminal of the seventh switch element M7 receives the second low level signal VSQ, and the fourteenth channel terminal of the seventh switch element M7 is connected to the third node QB2. The eighth switch element M8 includes an eighth control terminal, a fifteenth channel terminal and a sixteenth channel terminal, the eighth control terminal of the eighth switch element M8 receives the second control signal V2, the fifteenth channel terminal of the eighth switch element M8 is connected to the third node QB2, and the sixteenth channel terminal of the eighth switch element M8 is connected to the eighth control terminal of the eighth switch element M8. The ninth switch element M9 includes a ninth control terminal, a seventeenth channel terminal, and an eighteenth channel terminal. The ninth control terminal of the ninth switch element M9 is connected to the sixteenth channel terminal of the eighth switch element M8 to receive the second control signal V2. The seventeenth channel terminal of the ninth switch element M9 is connected to the second node QB1. The eighteenth channel terminal of the ninth switch element M9 receives the second low level signal VSQ. The tenth switch element M10 includes a tenth control terminal, a nineteenth channel terminal, and a twentieth channel terminal. The tenth control terminal of the tenth switch element M10 is connected to the first node Qn. The nineteenth channel terminal of the tenth switch element M10 receives the second low level signal VSQ. The twentieth channel terminal of the tenth switch element M10 is connected to the second node QB1. The eleventh switch element M11 includes an eleventh control terminal, a twenty-first channel terminal, and a twenty-second channel terminal. The eleventh control terminal of the eleventh switch element M11 is connected to the first node Qn. The twenty-first channel terminal of the eleventh switch element M11 is connected to the nineteenth channel terminal of the tenth switch element M10 to receive the second low level signal VSQ. The twenty-second channel terminal of the eleventh switch element M11 is connected to the third node QB2.

[0043] The twelfth switch element M12 includes a twelfth control terminal, a twenty-third channel terminal, and a twenty-fourth channel terminal. The twelfth control terminal of the twelfth switch element M12 is connected to the second node QB1, the twenty-third channel terminal of the twelfth switch element M12 is connected to the first node Qn, and the twenty-fourth channel terminal of the twelfth switch element M12 receives the second low level signal VSQ. The thirteenth switch element M13 includes a thirteenth control terminal, a twenty-fifth channel terminal, and a twenty-sixth channel terminal. The thirteenth control terminal of the thirteenth switch element M13 is connected to the third node QB2, the twenty-fifth channel terminal of the thirteenth switch element M13 is connected to the twenty-fourth channel terminal of the twelfth switch element M12, and receives the second low level signal VSQ, and the twenty-sixth channel terminal of the thirteenth switch element M13 is connected to the first node Qn. The fourteenth switch element M14 includes a fourteenth control terminal, a twenty-seventh channel terminal, and a twenty-eighth channel terminal. The fourteenth control terminal of the fourteenth switch element M14 is connected to the second node QB1, the twenty-seventh channel terminal of the fourteenth switch element M14 is connected to the first output terminal, and the twenty-eighth channel terminal of the fourteenth switch element M14 receives the first low level signal VGL. The fifteenth switch element M15 includes a fifteenth control terminal, a twenty-ninth channel terminal, and a thirtieth channel terminal. The fifteenth control terminal of the fifteenth switch element M15 is connected to the third node QB2. The twenty-ninth channel terminal of the fifteenth switch element M15 is connected to the twenty-eighth channel terminal of the fourteenth switch element M14 to receive the first low-level signal VGL. The thirtieth channel terminal of the fifteenth switch element M15 is connected to the first output terminal. The sixteenth switch element M16 includes a sixteenth control terminal, a thirty-first channel terminal, and a thirty-second channel terminal. The sixteenth control terminal of the sixteenth switch element M16 is connected to the second node QB1. The thirty-first channel terminal of the sixteenth switch element M16 is connected to the second output terminal. The thirty-second channel terminal of the sixteenth switch element M16 receives the first low-level signal VGL. The seventeenth switch element M17 includes a seventeenth control terminal, a thirty-third channel terminal and a thirty-fourth channel terminal. The seventeenth control terminal of the seventeenth switch element M17 is connected to the third node QB2, the thirty-third channel terminal of the seventeenth switch element M17 is connected to the thirty-second channel terminal of the sixteenth switch element M16, and receives the first low level signal VGL, and the thirty-fourth channel terminal of the seventeenth switch element M17 is connected to the second output terminal.

[0044] In one embodiment of the present invention, the first control signal V1 and the second control signal V2 are low-frequency clock signals (i.e., their frequencies are lower than the frequency of the clock signal), and the first control signal V1 and the second control signal V2 are alternately high, so that when the first control signal V1 is high, the second control signal V2 is low; when the second control signal V2 is high, the first control signal V1 is low. In one embodiment of the present invention, the first control signal V1 and the second control signal V2 have opposite polarities, and both reverse their polarities once per frame. In the stable stage, the first control signal V1 controls the sixth switch element M6 and the seventh switch element M7 to be turned on, and charges the second node QB1 through the turned-on sixth switch element M6, and discharges the third node QB2 to the second low level signal VSQ through the turned-on seventh switch element M7, or the second control signal V2 controls the eighth switch element M8 and the ninth switch element M9 to be turned on, and charges the third node QB2 through the turned-on eighth switch element M8, and discharges the second node QB1 to the second low level signal VSQ through the turned-on ninth switch element M9. Thus, the first control signal V1 and the second control signal V2 alternately control the second node QB1 and the third node QB2 to be high and low levels, so that the twelfth switch element M12, the fourteenth switch element M14, the sixteenth switch element M16 connected to the second node QB1 and the thirteenth switch element M13, the fifteenth switch element M15, the seventeenth switch element M17 connected to the third node QB2 are alternately turned on. Thus, the first node Qn alternately receives the second low level signal VSQ through the connected twelfth switch element M12 and the thirteenth switch element M13, the first output end alternately receives the first low level signal VGL through the connected fourteenth switch element M14 and the fifteenth switch element M15, and the second output end alternately receives the first level signal VGL through the connected sixteenth switch element M16 and the seventeenth switch element M17, thereby achieving a stable low level effect.

[0045] In an embodiment of the present invention, the gate transfer unit further includes a first capacitor C1 , a first end of the first capacitor C1 is connected to the first node Qn, and a second end of the first capacitor C1 is connected to the first output end.

[0046] In an embodiment of the present invention, the first capacitor C1 may be, but is not limited to, an external capacitor between the first node Qn and the first output terminal. The coupling effect of the capacitor can be used to improve the effect of pulling up the voltage of the first node Qn.

[0047] In one embodiment of the present invention, the duty cycle of the first clock signal CLK2 and the second clock signal CLK3 of this stage may be but is not limited to 50%, and the phase difference between the first clock signal CLK2 and the second clock signal CLK3 of this stage may be but is not limited to a quarter of a cycle.

[0048] In one embodiment of the present invention, the first switch element M1 to the seventeenth switch element M17 may be, but not limited to, an N-type TFT, an NMOS tube or an N-type triode, etc. The corresponding first control terminal to the seventeenth control terminal of the first switch element M1 to the seventeenth switch element M17 are all gate electrodes. The corresponding channel terminals of the first switch element M1 to the seventeenth switch element M17 are drain electrodes or source electrodes.

[0049] Figures 2 to 5 yes Figure 1 The timing diagram of the gate transfer unit in four stages. Figures 1 to 5 , illustrating the working process of the gate transfer unit of this embodiment, the working process of the gate transfer unit includes four stages, namely, a pre-charging stage, an output stage, a pull-down stage, and a stabilization stage: Pre-charge stage: Please refer to Figure 2 In the box, the front-stage transfer signal Zn-2 and the front-stage gate signal Gn-2 jump from low level to high level, the pre-charging module 10 controls the first node Qn to receive the high-level front-stage gate signal Gn-2, and the first node Qn is charged.

[0050] In one embodiment, the front-stage transfer signal Zn-2 and the front-stage gate signal Gn-2 jump from a low level to a high level, the first control end of the first switch element M1 receives the high-level front-stage transfer signal Zn-2 and becomes turned on, the first node Qn receives the high-level front-stage gate signal Gn-2 through the turned-on first switch element M1, and the first node Qn is charged.

[0051] In one embodiment, when the first node Qn is charged and pulled up to a high level, the second control end of the second switch element M2 and the third control end of the third switch element M3 connected to the first node Qn become high levels, and the second switch element M2 and the third switch element M3 become turned on, and the first output module 20 and the second output module 30 enter the working state.

[0052] In one embodiment, when the first node Qn is charged and pulled up to a high level, the tenth control terminal of the tenth switch element M10 and the eleventh control terminal of the eleventh switch element M11 connected to the first node Qn become high levels, and the tenth switch element M10 and the eleventh switch element M11 become conductive, so that the second node QB1 connected to the twentieth channel terminal of the tenth switch element M10 receives the second low level signal VSQ on the nineteenth channel terminal of the tenth switch element M10 through the conductive tenth switch element M10, and at the same time, the third node QB2 connected to the twenty-second channel terminal of the eleventh switch element M11 receives the second low level signal VSQ on the twenty-first channel terminal of the eleventh switch element M11 through the conductive eleventh switch element M11. When the second node QB1 and the third node QB2 are both at a low level, the corresponding control terminals of the twelfth to seventeenth switch elements M12 to M17 are at a low level, and the twelfth to seventeenth switch elements M12 to M17 are in a disconnected state, and the stabilization module 60 enters a non-working state, and stops discharging the first node Qn, the first output terminal, and the second output terminal.

[0053] Output stage: Please refer to Figure 3 In the box, the first node Qn has been pulled up to a high level, the first clock signal CLK2 of this stage jumps from a low level to a high level, and the first output module 20 outputs a high-level gate signal Gn of this stage at the first output terminal according to the high level of the first node Qn and the high level of the first clock signal CLK2 of this stage; at the same time, the second output module 30 outputs a high-level transfer signal Zn of this stage at the second output terminal according to the high level of the first node Qn and the high level of the first clock signal CLK2 of this stage. Afterwards, the rear-stage gate signal Gn+2 jumps from a low level to a high level, and the output pull-down module 40 quickly pulls down the first output terminal to a low level according to the high-level rear-stage gate signal Gn+2 and the first low-level signal VGL, which can effectively reduce the falling edge time of the gate signal without increasing the clock load, thereby improving the product image quality.

[0054] In one embodiment, the first node Qn has been pulled up to a high level, and the second switch element M2 is in a conducting state; the first clock signal CLK2 of this stage jumps from a low level to a high level; the first output terminal receives the high level first clock signal CLK2 of this stage through the turned-on second switch element M2, so that the first output terminal outputs a high level gate signal Gn of this stage. In one embodiment, the first node Qn is also self-charged and pulled up by the first capacitor C1, so that the level of the first node Qn is further increased, and the second switch element M2 is fully turned on.

[0055] In one embodiment, the first node Qn has been pulled up to a high level, and the third switch element M3 is in a conductive state; the first clock signal CLK2 of this stage jumps from a low level to a high level; the second output end receives the high-level first clock signal CLK2 of this stage through the conductive third switch element M3, and thus, the second output end outputs a high-level transfer signal Zn of this stage.

[0056] In one embodiment, the post-stage gate signal Gn+2 jumps from a low level to a high level, the fourth control end of the fourth switch element M4 receives the high-level post-stage gate signal Gn+2, the fourth switch element M4 becomes turned on, and the first output end receives the first low-level signal VGL through the turned-on fourth switch element M4, and is quickly pulled down to a low level, which can effectively reduce the falling edge time of the gate signal without increasing the clock load, thereby improving the product image quality.

[0057] Pull-down phase: Please refer to Figure 4 In the box, when the back-stage gate signal Gn+2 jumps from a low level to a high level, the node pull-down module 50 controls the first node Qn to receive the second clock signal CLK3 of this stage. Then, when the second clock signal CLK3 of this stage jumps from a high level to a low level, the first node Qn is stably pulled down to a low level.

[0058] In one embodiment, when the post-stage gate signal Gn+2 changes from a low level to a high level, the fifth control terminal of the fifth switch element M5 receives the high-level post-stage gate signal Gn+2, and the fifth switch element M5 becomes conductive. Thus, the first node Qn connected to the ninth channel terminal of the fifth switch element M5 receives the second clock signal CLK3 of the current stage on the tenth channel terminal of the fifth switch element M5 through the conductive fifth switch element M5. When the second clock signal CLK3 of the current stage changes from a high level to a low level, the first node Qn is stably pulled down to a low level.

[0059] In one embodiment, when the first node Qn is pulled down to a low level, the second control end of the second switch element M2 and the third control end of the third switch element M3 connected to the first node Qn become low levels, and the second switch element M2 and the third switch element M3 become disconnected, thereby causing the first output module 20 and the second output module 30 to enter a non-working state.

[0060] In one embodiment, when the first node Qn is pulled down to a low level, the tenth control terminal of the tenth switch element M10 and the eleventh control terminal of the eleventh switch element M11 connected to the first node Qn become low levels, and the tenth switch element M10 and the eleventh switch element M11 become disconnected. At the same time, because the first control signal V1 and the second control signal V2 have opposite polarities, the first control signal V1 controls the sixth switch element M6 and the seventh switch element M7 to be turned on, and the second node QB1 is charged through the turned-on sixth switch element M6, and the third node QB2 is discharged to the second low level signal VSQ through the turned-on seventh switch element M7, or the second control signal V2 controls the eighth switch element M8 and the ninth switch element M9 to be turned on, and the third node QB2 is charged through the turned-on eighth switch element M8, and the second node QB1 is discharged to the second low level signal VSQ through the turned-on ninth switch element M9. Thus, the first control signal V1 and the second control signal V2 alternately control the second node QB1 and the third node QB2 to be high and low levels, so that the twelfth switch element M12, the fourteenth switch element M14, the sixteenth switch element M16 connected to the second node QB1 and the thirteenth switch element M13, the fifteenth switch element M15, the seventeenth switch element M17 connected to the third node QB2 are alternately turned on. Thus, the first node Qn alternately receives the second low level signal VSQ through the connected twelfth switch element M12 and the thirteenth switch element M13, the first output terminal alternately receives the first low level signal VGL through the connected fourteenth switch element M14 and the fifteenth switch element M15, and the second output terminal alternately receives the first level signal VGL through the connected sixteenth switch element M16 and the seventeenth switch element M17, so as to achieve a stable low level effect.

[0061] Stabilization phase: Please refer to Figure 5 In the box, that is, in the time period not including the first three stages, the front-stage transfer signal Zn-2 received by the pre-charging module 10 is at a low level, then the pre-charging module 10 enters a non-working state, and similarly, the rear-stage gate signal Gn+2 received by the node pull-down module 50 is at a low level, then the node pull-down module 50 enters a non-working state. Thus, the pre-charging module 10 and the node pull-down module 50 have no effect on the first node Qn, and the stabilizing module 60 can be used to maintain the first node Qn, the first output terminal, and the second output terminal at a low level.

[0062] In one embodiment, in the stable stage, the first node Qn has been pulled down to a low level, the second control end of the second switch element M2 and the third control end of the third switch element M3 connected to the first node Qn are at a low level, and the second switch element M2 and the third switch element M3 are in a disconnected state, thereby causing the first output module 20 and the second output module 30 to enter a non-working state.

[0063] In one embodiment, in the stable stage, the first node Qn has been pulled down to a low level, the tenth control terminal of the tenth switch element M10 and the eleventh control terminal of the eleventh switch element M11 connected to the first node Qn are at a low level, and the tenth switch element M10 and the eleventh switch element M11 are in a disconnected state. At the same time, because the first control signal V1 and the second control signal V2 have opposite polarities, the first control signal V1 controls the sixth switch element M6 and the seventh switch element M7 to be in a conducting state, and charges the second node QB1 through the conducting sixth switch element M6, and discharges the third node QB2 to the second low level signal VSQ through the conducting seventh switch element M7, or the second control signal V2 controls the eighth switch element M8 and the ninth switch element M9 to be in a conducting state, and charges the third node QB2 through the conducting eighth switch element M8, and discharges the second node QB1 to the second low level signal VSQ through the conducting ninth switch element M9. Thus, the first control signal V1 and the second control signal V2 alternately control the second node QB1 and the third node QB2 to be high and low levels, so that the twelfth switch element M12, the fourteenth switch element M14, the sixteenth switch element M16 connected to the second node QB1 and the thirteenth switch element M13, the fifteenth switch element M15, and the seventeenth switch element M17 connected to the third node QB2 are alternately turned on. Thus, the first node Qn alternately receives the second low level signal VSQ through the connected twelfth switch element M12 and the thirteenth switch element M13, the first output terminal alternately receives the first low level signal VGL through the connected fourteenth switch element M14 and the fifteenth switch element M15, and the second output terminal alternately receives the first level signal VGL through the connected sixteenth switch element M16 and the seventeenth switch element M17, so as to achieve a stable low level effect.

[0064] Thus, in the stable stage, no matter how the pre-stage transfer signal Zn-2 and the pre-stage gate signal Gn-2 received by the pre-charging module 10 change, how the post-stage gate signal Gn+2 and the second clock signal CLK3 of the current stage received by the node pull-down module 50 change, and how the first clock signal CLK2 of the current stage received by the first output module 20 and the second output module 30 change, the stabilizing module 60 can maintain the first node Qn, the first output end and the second output end at a low level, and can release the charge of the parasitic capacitance of the second switch element M2 coupled by the clock feedthrough, etc., to ensure the stability of the first node Qn and the output current gate signal Gn and the current transfer signal. In addition, in the pre-charging stage, each voltage pull-up on the first node Qn is performed on the second low-level signal VSQ, so the pull-up voltage is relatively stable, preventing the voltage drift of the first node Qn, making the voltage of the first node Qn more stable, thereby increasing the stability of the circuit and improving the reliability of the display. In one embodiment, the voltages of the second node QB1 and the third node QB2 are more stable, so that the working state of the connected switching elements is also more stable, reducing the influence of the ambient temperature on the circuit, that is, due to the original drift phenomenon, the voltage drift will not exceed a certain threshold when the temperature is too high or too low, causing the connected switching elements to work abnormally; in addition, the voltages of the second node QB1 and the third node QB2 are more stable, which will also broaden the relevant timing design of the second node QB1 and the third node QB2.

[0065] Figure 6 is a cascade circuit diagram of a gate transfer circuit according to an embodiment of the present invention. The gate transfer circuit according to this embodiment includes a plurality of Figure 1 The gate transfer units in the embodiment can be connected in sequence in a continuous manner or in an interval manner. Figure 6 In the example, the nth gate transfer unit is connected to the n-2th gate transfer unit and the n+2th gate transfer unit respectively. The number of gate transfer units in the gate transfer circuit is not limited, and can be 4, 8 or more, such as the number of gate lines. Figure 6In the example, each gate transfer unit receives the previous gate signal Gn-2, the previous transfer signal Zn-2 and the next gate signal Gn+2, and outputs the current gate signal Gn and the current transfer signal Zn, wherein the previous gate signal Gn-2 and the previous transfer signal Zn-2 received by the first two gate transfer units may be the corresponding start-up signal STV1, and the next gate signal Gn+2 received by the last two gate transfer units may be the corresponding pull-down signal STV2. Each gate transfer unit may also share multiple input signals, including a first low-level signal VGL, a second low-level signal VQS, two control signals and a group of clock signals. In one embodiment, when receiving the two control signals, the first control signal V1 received by any gate transfer unit is the second control signal V2 received by the adjacent gate transfer unit. In one embodiment, the group of clock signals is N phase difference clocks, and the phase difference between two adjacent phase difference clocks is one-Nth of a cycle, and N may be 4 or 8, etc. In one embodiment, when receiving the group of clock signals, the phase difference between the first clock signal of the current level received by any gate transfer unit and the first clock signal of the current level received by an adjacent gate transfer unit is one-Nth cycle, and the phase difference between the second clock signal of the current level received by any gate transfer unit and the second clock signal of the current level received by an adjacent gate transfer unit is one-Nth cycle.

[0066] In one embodiment of the present invention, a gate transfer circuit is disposed on one of the left and right sides of the display panel, and a plurality of gate transfer units of the gate transfer circuit are connected to the gate lines in a one-to-one correspondence.

[0067] In one embodiment of the present invention, gate transfer circuits are disposed on both the left and right sides of the display panel, and a plurality of gate lines alternately connect the gate transfer units on the left and the gate transfer units on the right.

[0068] In one embodiment of the present invention, Figure 6 As shown, gate transfer circuits are provided on both sides of the display panel, and gate transfer units are provided at both ends of any gate line. One of the two gate transfer units at both ends of the gate line outputs a gate signal to perform non-double-end charging; or, the two gate transfer units at both ends of the gate line simultaneously output gate signals to perform double-end charging.

[0069] Figure 7: is a full-level circuit diagram of a gate transfer circuit of an embodiment of the present invention. The gate transfer circuit of this embodiment also includes a signal providing module 200, which is used to provide corresponding input signals for multiple gate transfer units. The signal providing module 200 can be composed of a multi-level substrate gate drive circuit and a signal line. In one embodiment, the signal providing module 200 is arranged in the middle of the multiple gate transfer units, so that the multiple gate transfer units can be connected upward and downward respectively, and / or the multiple gate transfer units can be connected to the left and right respectively. Figure 7 Taking the gate transfer circuit shown in FIG. 2 as an example, the upper left side, lower left side, upper right side and lower right side of the signal providing module 200 may be provided with eight gate transfer units, and the eight gate transfer units on each of the four sides realize eight-level output connection. Then, the signal providing module 200 may connect the gate transfer units on each side and provide input signals for each side. Figure 8 In the example, each gate transfer unit receives a previous gate signal Gn-2, a previous transfer signal Zn-2 and a subsequent gate signal Gn+2, and outputs a current gate signal Gn and a current transfer signal Zn, wherein the previous gate signal Gn-2 and the previous transfer signal Zn-2 received by the first two gate transfer units on each side may be the corresponding start-up signal STV1 provided by the signal providing module 200 or other external signal circuits, and the subsequent gate signal Gn+2 received by the last two gate transfer units may be the corresponding pull-down signal STV2 provided by the signal providing module 200 or other external signal circuits. Each gate transfer unit may also share multiple input signals, including a first low-level signal VGL, a second low-level signal VQS, two control signals and a group of clock signals. In one embodiment, when receiving the two control signals, the first control signal V1 received by any gate transfer unit is the second control signal V2 received by the adjacent gate transfer unit. In one embodiment, the group of clock signals is N phase difference clocks, and the phase difference between two adjacent phase difference clocks is one-Nth of a cycle, and N may be 4 or 8, etc.; Figure 8 For example, the group of clock signals is four phase difference clocks, and the phase difference between two adjacent phase difference clocks is one quarter of a cycle, the phase difference between the first clock signal CLK2 of the same level received by any gate transfer unit and the first clock signal CLK2 of the same level received by the adjacent gate transfer unit is one quarter of a cycle, and the phase difference between the second clock signal CLK3 of the same level received by any gate transfer unit and the second clock signal CLK3 of the same level received by the adjacent gate transfer unit is one quarter of a cycle. Fig. 9As shown, multiple gate transfer units of the gate transfer circuit can output the gate signal of this stage in sequence. For example, four consecutive gate transfer units can output the gate signals of this stage Gn-2, Gn-1, Gn and Gn+1 in sequence, and the falling edge time of each gate signal of this stage is short, that is, it is quickly pulled down to a low level.

[0070] Fig.10 yes Figure 1 A schematic diagram comparing gate signals when the gate transfer unit is a 17T1C structure and a gate transfer unit is a 16T1C structure. The gate transfer unit of the gate transfer circuit of an embodiment of the present invention is provided with an output pull-down module 40, such as Figure 1 The structure shown is 17T1C, i.e., 17 switch elements and 1 capacitor. In contrast, a gate transfer unit does not have an output pull-down module 40, but is 16T1C, i.e., 16 switch elements and 1 capacitor. Fig.10 It can be seen that the falling edge time of the gate signal of the gate transfer unit with a 17T1C structure in the embodiment of the present invention is less than that of the gate transfer unit with a 16T1C structure. According to measurement, the falling edge time of the gate signal of the gate transfer unit with a 17T1C structure in the embodiment of the present invention is 5.3 μs, and the falling edge time of the gate signal of the gate transfer unit with a 16T1C structure is 7.7 μs. Therefore, the embodiment of the present invention can reduce the falling edge time of the gate signal without increasing the clock load, thereby improving the image quality of the product.

[0071] Fig.11 It is a schematic structural diagram of a gate transfer circuit according to another embodiment of the present invention. Fig.12 yes Fig.11 A circuit connection diagram of a gate transfer unit 100 is shown in FIG. Fig.11 and Fig.12 The basic structure and principle of the gate transfer circuit of this embodiment and the technical effects produced are basically the same as those of the previous embodiment. For the sake of brief description, the parts not mentioned in this embodiment can refer to the corresponding contents of the previous embodiment. In this embodiment, the difference is that the output pull-down module 40 is arranged at the tail end of the gate line and is connected to the first output terminal through the gate line.

[0072] Specifically, a gate transfer unit 100 is arranged on one side of the display panel, for example, the left side, and the first output end of the gate transfer unit 100 is connected to the left end of a gate line, and the gate line is connected to multiple thin film transistors on the display panel, which will generate corresponding resistance RGate and capacitance Cgate. An output pull-down module 40 is arranged on the other side of the display panel, for example, the right side, and the output pull-down module 40 is connected to the tail end Gn_end of the gate line, and is connected to the first output end through the gate line. Among them, in the output stage of the gate transfer unit 100, the first output terminal outputs a high-level gate signal Gn of the current stage, and then the subsequent gate signal Gn+2 jumps from a low level to a high level, and the fourth control terminal of the fourth switch element M4 in the output pull-down module 40 receives the high-level subsequent gate signal Gn+2, and the fourth switch element M4 becomes a conductive state. The first output terminal receives the first low-level signal VGL through the gate line and the conductive fourth switch element M4, and is quickly pulled down to a low level. The falling edge time of the gate signal can be effectively reduced without increasing the clock load, thereby improving the product image quality. At the same time, the space occupied by the gate transfer unit 100 on one side of the display panel can be reduced, which can effectively save the layout area and facilitate the narrow frame of the display device.

[0073] In one embodiment of the present invention, a gate transfer circuit is provided on one side of the display panel, and a plurality of gate transfer units 100 of the gate transfer circuit are connected one-to-one with the gate lines. A plurality of output pull-down modules 40 are provided on the other side of the display panel, and the output pull-down modules 40 are provided at the end of the gate line and connected to the first output terminal through the gate line.

[0074] In one embodiment of the present invention, Fig.11 As shown, gate transfer circuits are arranged on both sides of the display panel, and the output pull-down module 40 in the gate transfer unit 100 is arranged on the other side. Among the two adjacent gate lines, the left side of the first gate line is connected to the gate transfer unit 100 and the right side is connected to the output pull-down module 40, and the left side of the second gate line is connected to the output pull-down module 40 and the right side is connected to the gate transfer unit 100.

[0075] Fig.13 and Fig.14 They are Fig.11Clock signal diagram and gate signal diagram in one embodiment. In one embodiment, gate transfer circuits are arranged on both sides of the display panel, and the output pull-down module 40 in the gate transfer unit 100 is arranged on the other side. For example, the first-stage gate transfer unit 100 is arranged on the left side of the display panel, and the corresponding output pull-down module 40 is arranged on the right side of the display panel, the second-stage gate transfer unit 100 is arranged on the right side of the display panel, and the corresponding output pull-down module 40 is arranged on the left side of the display panel, ..., and are arranged in sequence. Each gate transfer unit receives the previous gate signal Gn-4, the previous transfer signal Zn-4 and the next gate signal Gn+4, and outputs the current gate signal Gn and the current transfer signal Zn, wherein the previous gate signal Gn-4 and the previous transfer signal Zn-4 received by the first two gate transfer units on each side can be the corresponding start signal STV1, and the next gate signal Gn+4 received by the last two gate transfer units can be the corresponding pull-down signal STV2. Each gate transfer unit may also share multiple input signals, including a first low-level signal VGL, a second low-level signal VQS, two control signals and a group of clock signals. In one embodiment, when receiving the two control signals, the first control signal V1 received by any gate transfer unit is the second control signal V2 received by the adjacent gate transfer unit. In one embodiment, the group of clock signals is N phase difference clocks, and the phase difference between two adjacent phase difference clocks is one-Nth of a cycle, and N can be 4 or 8, etc.; Fig.13 For example, the group of clock signals is eight phase difference clocks, and the phase difference between two adjacent phase difference clocks is one eighth of a cycle. The first phase difference clock CLK1, the third phase difference clock CLK3, the fifth phase difference clock CLK5 and the seventh phase difference clock CLK7 can be set on the left side of the display panel, and the second phase difference clock CLK2, the fourth phase difference clock CLK4, the sixth phase difference clock CLK6 and the eighth phase difference clock CLK8 can be set on the right side of the display panel; the phase difference between the first clock signal CLK2 of the same level received by any gate transfer unit and the first clock signal CLK2 of the same level received by the adjacent gate transfer unit is one eighth of a cycle, and the phase difference between the second clock signal CLK4 of the same level received by any gate transfer unit and the second clock signal CLK4 of the same level received by the adjacent gate transfer unit is one eighth of a cycle. Fig.14 As shown, multiple gate transfer units of the gate transfer circuit can output the gate signals of this stage in sequence. For example, 8 consecutive gate transfer units can output the gate signals of this stage Gn-4, Gn-3, Gn-2, Gn-1, Gn, Gn+1, Gn+2 and Gn+3 in sequence, and the falling edge time of each gate signal of this stage is short, that is, it is quickly pulled down to a low level.

[0076] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes a gate transfer circuit as provided in the above embodiment, for providing a gate signal to a gate line of a display panel. The implementation of the display device can refer to the above embodiment of the gate transfer circuit, and the repeated parts will not be repeated.

[0077] The gate transfer circuit and display device provided by the present invention include a multi-stage gate transfer unit, each stage of the gate transfer unit includes a pre-charging module, a first output module, a second output module, an output pull-down module, a node pull-down module and a stabilization module, wherein the output pull-down module is connected to the first output module at the first output end, and pulls the first output end down to a low level according to the subsequent gate signal and the first low-level signal. Thus, the gate transfer circuit can output multiple gate signals in sequence, has a strong output capacity and stability, and can reduce the falling edge time of the gate signal without increasing the clock load, thereby improving the product image quality; at the same time, the gate transfer circuit uses fewer unit devices, which can effectively save the layout area and facilitate the narrow frame of the display device.

[0078] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the invention without departing from the content of the technical solution of the invention are still within the scope of the technical solution of the present invention.

Claims

1. A gate transfer circuit, comprising a multi-stage gate transfer unit, characterized in that: Each level of the gate transfer unit includes: A pre-charging module (10), the pre-charging module (10) being connected to a first node (Qn) and charging the first node (Qn) according to a previous stage transfer signal and a previous stage gate signal; A first output module (20), the first output module (20) being connected to the pre-charging module (10) at the first node (Qn), and outputting a gate signal of the current stage at a first output terminal according to the potential of the first node (Qn) and a first clock signal of the current stage; A second output module (30), the second output module (30) is connected to the pre-charging module (10) at the first node (Qn), and outputs a current-stage transfer signal at a second output terminal according to the potential of the first node (Qn) and a current-stage first clock signal; an output pull-down module (40), the output pull-down module (40) being connected to the first output module (20) at the first output end, and pulling the first output end down to a low level according to a rear-stage gate signal and a first low-level signal (VGL); A node pull-down module (50), the node pull-down module (50) being connected to the first node (Qn) and the pre-charging module (10), and pulling the first node (Qn) down to a low level according to the subsequent-stage gate signal and the second clock signal of the current stage; A stabilization module (60), the stabilization module (60) being connected to the first node (Qn), the first output end and the second output end, the stabilization module (60) being used for simultaneously maintaining the first node (Qn), the first output end and the second output end at a low level when the first node (Qn) is pulled down to a low level.

2. The gate transfer circuit according to claim 1, characterized in that: The pre-charging module (10) comprises a first switching element (M1), the first switching element (M1) comprises a first control end, a first path end and a second path end, the first control end of the first switching element (M1) receives the previous stage transfer signal, the first path end of the first switching element (M1) receives the previous stage gate signal, and the second path end of the first switching element (M1) is connected to the first node (Qn).

3. The gate transfer circuit according to claim 1, characterized in that: The first output module (20) comprises a second switch element (M2), the second switch element (M2) comprises a second control end, a third path end and a fourth path end, the second control end of the second switch element (M2) is connected to the first node, the third path end of the second switch element (M2) receives the first clock signal of the current stage, and the fourth path end of the second switch element (M2) is connected to the first output end.

4. The gate transfer circuit according to claim 1, characterized in that: The second output module (30) comprises a third switch element (M3), the third switch element (M3) comprises a third control end, a fifth path end and a sixth path end, the third control end of the third switch element (M3) is connected to the first node (Qn), the fifth path end of the third switch element (M3) receives the first clock signal of the current stage, and the sixth path end of the third switch element (M3) is connected to the second output end.

5. The gate transfer circuit according to claim 1, characterized in that: The output pull-down module (40) comprises a fourth switch element (M4), the fourth switch element (M4) comprises a fourth control terminal, a seventh path terminal and an eighth path terminal, the fourth control terminal of the fourth switch element (M4) receives the rear-stage gate signal, the seventh path terminal of the fourth switch element (M4) receives the first output terminal, and the eighth path terminal of the fourth switch element (M4) is connected to the first low-level signal (VGL).

6. The gate transfer circuit according to claim 1, characterized in that: The node pull-down module (50) comprises a fifth switch element (M5), the fifth switch element (M5) comprises a fifth control terminal, a ninth path terminal and a tenth path terminal, the fifth control terminal of the fifth switch element (M5) receives the subsequent gate signal, the ninth path terminal of the fifth switch element (M5) is connected to the first node (Qn), and the tenth path terminal of the fifth switch element (M5) receives the second clock signal of the current stage.

7. The gate transfer circuit according to claim 1, characterized in that: The stabilization module (60) comprises: a sixth switch element (M6), the sixth switch element (M6) comprising a sixth control terminal, an eleventh path terminal and a twelfth path terminal, the sixth control terminal of the sixth switch element (M6) receiving a first control signal, the eleventh path terminal of the sixth switch element (M6) being connected to the sixth control terminal of the sixth switch element (M6), and the twelfth path terminal of the sixth switch element (M6) being connected to the second node (QB1); a seventh switch element (M7), the seventh switch element (M7) comprising a seventh control terminal, a thirteenth path terminal and a fourteenth path terminal, the seventh control terminal of the seventh switch element (M7) being connected to the eleventh path terminal of the sixth switch element (M6) and receiving the first control signal (V1), the thirteenth path terminal of the seventh switch element (M7) receiving the second low level signal (VSQ), and the fourteenth path terminal of the seventh switch element (M7) being connected to the third node (QB2); an eighth switch element (M8), the eighth switch element (M8) comprising an eighth control terminal, a fifteenth path terminal and a sixteenth path terminal, the eighth control terminal of the eighth switch element (M8) receiving a second control signal (V2), the fifteenth path terminal of the eighth switch element (M8) being connected to the third node (QB2), and the sixteenth path terminal of the eighth switch element (M8) being connected to the eighth control terminal of the eighth switch element (M8); a ninth switch element (M9), the ninth switch element (M9) comprising a ninth control terminal, a seventeenth path terminal and an eighteenth path terminal, the ninth control terminal of the ninth switch element (M9) being connected to the sixteenth path terminal of the eighth switch element (M8) and receiving the second control signal (V2), the seventeenth path terminal of the ninth switch element (M9) being connected to the second node (QB1), and the eighteenth path terminal of the ninth switch element (M9) receiving the second low level signal (VSQ); a tenth switch element (M10), the tenth switch element (M10) comprising a tenth control terminal, a nineteenth path terminal and a twentieth path terminal, the tenth control terminal of the tenth switch element (M10) being connected to the first node (Qn), the nineteenth path terminal of the tenth switch element (M10) receiving the second low level signal (VSQ), and the twentieth path terminal of the tenth switch element (M10) being connected to the second node (QB1); an eleventh switch element (M11), the eleventh switch element (M11) comprising an eleventh control terminal, a twenty-first path terminal and a twenty-second path terminal, the eleventh control terminal of the eleventh switch element (M11) being connected to the first node (Qn), the twenty-first path terminal of the eleventh switch element (M11) being connected to the nineteenth path terminal of the tenth switch element (M10) to receive the second low level signal (VSQ), and the twenty-second path terminal of the eleventh switch element (M11) being connected to the third node (QB2); a twelfth switch element (M12), the twelfth switch element (M12) comprising a twelfth control terminal, a twenty-third path terminal and a twenty-fourth path terminal, the twelfth control terminal of the twelfth switch element (M12) being connected to the second node (QB1), the twenty-third path terminal of the twelfth switch element (M12) being connected to the first node (Qn), and the twenty-fourth path terminal of the twelfth switch element (M12) receiving the second low level signal (VSQ); a thirteenth switch element (M13), the thirteenth switch element (M13) comprising a thirteenth control terminal, a twenty-fifth channel terminal and a twenty-sixth channel terminal, the thirteenth control terminal of the thirteenth switch element (M13) being connected to the third node (QB2), the twenty-fifth channel terminal of the thirteenth switch element (M13) being connected to the twenty-fourth channel terminal of the twelfth switch element (M12) to receive the second low level signal (VSQ), and the twenty-sixth channel terminal of the thirteenth switch element (M13) being connected to the first node (Qn); a fourteenth switch element (M14), the fourteenth switch element (M14) comprising a fourteenth control terminal, a twenty-seventh path terminal and a twenty-eighth path terminal, the fourteenth control terminal of the fourteenth switch element (M14) being connected to the second node (QB1), the twenty-seventh path terminal of the fourteenth switch element (M14) being connected to the first output terminal, and the twenty-eighth path terminal of the fourteenth switch element (M14) receiving the first low level signal (VGL); a fifteenth switch element (M15), the fifteenth switch element (M15) comprising a fifteenth control terminal, a twenty-ninth path terminal and a thirtieth path terminal, the fifteenth control terminal of the fifteenth switch element (M15) being connected to the third node (QB2), the twenty-ninth path terminal of the fifteenth switch element (M15) being connected to the twenty-eighth path terminal of the fourteenth switch element (M14) to receive the first low level signal (VGL), and the thirtieth path terminal of the fifteenth switch element (M15) being connected to the first output terminal; a sixteenth switch element (M16), the sixteenth switch element (M16) comprising a sixteenth control terminal, a thirty-first path terminal and a thirty-second path terminal, the sixteenth control terminal of the sixteenth switch element (M16) being connected to the second node, the thirty-first path terminal of the sixteenth switch element (M16) being connected to the second output terminal, and the thirty-second path terminal of the sixteenth switch element (M16) receiving the first low level signal (VGL); A seventeenth switch element (M17), the seventeenth switch element (M17) comprising a seventeenth control terminal, a thirty-third channel terminal and a thirty-fourth channel terminal, the seventeenth control terminal of the seventeenth switch element (M17) is connected to the third node (QB2), the thirty-third channel terminal of the seventeenth switch element (M17) is connected to the thirty-second channel terminal of the sixteenth switch element (M16), receives the first low level signal (VGL), and the thirty-fourth channel terminal of the seventeenth switch element (M17) is connected to the second output terminal.

8. The gate transfer circuit according to claim 7, characterized in that: The first control signal and the second control signal have opposite polarities, and both reverse polarities once per frame.

9. The gate transfer circuit according to claim 1, characterized in that: The output pull-down module (40) is arranged at the tail end of the gate line and is connected to the first output end through the gate line.

10. A display device, characterized in that: Comprising a gate transfer circuit as described in any one of claims 1-9.

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