Data detection method and apparatus

Abstract

The application provides a data detection method and device. The data detection device comprises a rate dematching module, a soft combining module, a decoding checking module, a processor and a first memory. The first memory stores a program. When the program is executed by the processor, at least one of the following steps is implemented: controlling whether to input at least one of a synchronization signal block index and a first synchronization signal block log likelihood probability into the rate dematching module through software or a hardware circuit; controlling whether to obtain the second synchronization signal block log likelihood probability by performing de-secondary scrambling processing and de-repetition rate matching processing on the first synchronization signal block log likelihood probability through the rate dematching module or by performing de-secondary scrambling processing and de-repetition rate matching processing on the first synchronization signal block log likelihood probability through software; and controlling whether to input a system frame number index into the soft combining module through software or a hardware circuit.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to data detection methods and apparatus. Background Technology

[0002] In the fifth generation of wireless communication technology (5G, 5 th In Generation Mobile Communication Technology (GMT), the Physical Broadcast Channel (PBCH) comprises two parts: the PBCH Demodulation Reference Signal (DMRS) and PBCH data. After successfully detecting the Primary Synchronization Signal (PSS) and Secondary Synchronization Signal (SSS), the User Equipment (UE) obtains the Cell Identity, Orthogonal Frequency Division Multiplexing (OFDM) symbol boundary synchronization, and coarse frequency synchronization. Next, blind detection is performed on the PBCH DMRS to obtain at least one candidate Synchronization Signal Block index (SSB index). Then, the PBCH data is detected to obtain the Master Information Block (MIB) message, thereby obtaining the system frame number and half-frame indication to complete the radio frame timing and half-frame timing. At the same time, the time slot and symbol of the current PSS and SSS are determined by the candidate SSB index and the Synchronization Signal Block burst set pattern used in the current frequency band, thus completing the time slot timing.

[0003] The PBCH data detection process is also the PBCH decoding process. The PBCH decoding process includes processes such as descrambling of the second-order scrambling, descrambling of the repetition rate matching, descrambling of sub-block interleaving, descrambling of the system frame number (SFN) mask, decoding of polar codes, and cyclic redundancy check (CRC). To support blind PBCH detection, it also includes processes such as SFN mask generation and log-likelihood-ratio (LLR) soft combining.

[0004] In Long Term Evolution (LTE) systems, the PBCH Transmission Time Interval (TTI) is 40 milliseconds (ms), and the SSB burst set period is fixed at 10ms, with a maximum of 4 merges within one TTI. In 5G systems, the PBCH TTI is 80ms, and the SSB burst set period is variable. During initial cell selection, the SSB burst set period defaults to 20ms, but during cell handover and cell reselection, the SSB burst set period can be any of 5ms, 10ms, 20ms, 40ms, 80ms, or 160ms. Different SSB burst set periods within the same TTI can be soft-combined using LLR (Low-Range Buffer) to improve the signal-to-noise ratio.

[0005] For 5G systems, the PBCH decoding process involves many steps and there are multiple periods in the SSB burst set, which greatly complicates the blind detection process and reduces its flexibility. Summary of the Invention

[0006] This application provides a data detection method and apparatus.

[0007] In a first aspect, embodiments of this application provide a data detection device, comprising: at least one derate matching module, each of the derate matching modules being connected to at least one soft combining module, each soft combining module being connected to a decoding verification module, and at least one processor and a first memory; wherein, the derate matching module is configured to perform de-secondary scrambling and de-repetition rate matching processing on the log-likelihood probability of an input first synchronization signal block according to the synchronization signal block index to obtain a second synchronization signal block log-likelihood probability; the soft combining module is configured to perform de-sub-block interleaving processing, de-system frame number masking processing, and log-likelihood probability soft combining processing on the log-likelihood probability of the second synchronization signal block according to the system frame number index to obtain a third synchronization signal block log-likelihood probability; the decoding verification module is configured to perform decoding processing and cyclic redundancy code verification processing on the log-likelihood probability of the third synchronization signal block to obtain decoded data and verification results; wherein, the derate matching module is configured to perform derate matching and cyclic redundancy code verification processing on the log-likelihood probability of the third synchronization signal block to obtain decoded data and verification results; wherein, the derate matching module is configured to perform derate matching and de-repetition rate matching ... second synchronization signal block to obtain a second synchronization signal block log-likelihood probability. The matching module, the soft merging module, and the decoding verification module are implemented using hardware circuitry. The first memory stores at least one program, which, when executed by the at least one processor, performs at least one of the following steps: controlling whether the synchronization signal block index is input to the de-rate matching module via software or hardware circuitry; controlling whether the log-likelihood probability of the first synchronization signal block is input to the de-rate matching module via software or hardware circuitry; controlling whether the log-likelihood probability of the first synchronization signal block is obtained by performing second-order scrambling and de-repetition rate matching processing on the log-likelihood probability of the first synchronization signal block through the de-rate matching module, or by performing second-order scrambling and de-repetition rate matching processing on the log-likelihood probability of the first synchronization signal block through software; and controlling whether the system frame number index is input to the soft merging module via software or hardware circuitry.

[0008] Secondly, embodiments of this application provide a data detection method, comprising: performing de-scrambling and de-repetition rate matching processing on the log-likelihood probability of an input first synchronization signal block according to the synchronization signal block index using at least one de-rate matching module to obtain a second synchronization signal block log-likelihood probability; wherein different de-rate matching modules correspond to different synchronization signal block indices; performing de-sub-block interleaving, de-system frame number masking, and log-likelihood probability soft merging processing on the log-likelihood probability of the second synchronization signal block according to the system frame number index using at least one soft merging module connected to the same de-rate matching module to obtain a third synchronization signal block log-likelihood probability; wherein different soft merging modules connected to the same de-rate matching module correspond to different system frame number indices; and performing decoding and cyclic redundancy processing on the log-likelihood probability of the third synchronization signal block using a decoding and verification module connected to the soft merging module. The remaining code verification process obtains the decoded data and verification result; wherein, the de-rate matching module, the soft merging module, and the decoding verification module are implemented using hardware circuits; the data detection method further includes at least one of the following steps: controlling whether the synchronization signal block index is input into the de-rate matching module via software or hardware circuits; controlling whether the log-likelihood probability of the first synchronization signal block is input into the de-rate matching module via software or hardware circuits; controlling whether the log-likelihood probability of the first synchronization signal block is obtained by performing de-secondary scrambling and de-repetition rate matching processing on the log-likelihood probability of the first synchronization signal block through the de-rate matching module, or by performing de-secondary scrambling and de-repetition rate matching processing on the log-likelihood probability of the first synchronization signal block through software; controlling whether the system frame number index is input into the soft merging module via software or hardware circuits.

[0009] The data detection device provided in this application embodiment detects PBCH data by combining software and hardware circuits, which improves flexibility. It detects PBCH data by using at least one solution rate matching module and at least one soft merging module, which greatly simplifies the data detection process. Attached Figure Description

[0010] Figure 1 This is a block diagram of a data detection apparatus provided in one embodiment of the present application;

[0011] Figure 2 This is a block diagram of a data detection device, exemplified in this application, which includes a data detection device comprising a solution rate matching module and a soft merging module.

[0012] Figure 3This is a block diagram of another data detection device in this application embodiment, taking a data detection device including a solution rate matching module and a soft merging module as an example;

[0013] Figure 4 A flowchart of a data detection method provided in another embodiment of this application. Detailed Implementation

[0014] To enable those skilled in the art to better understand the technical solution of this application, the data detection method and apparatus provided in this application will be described in detail below with reference to the accompanying drawings.

[0015] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this application.

[0016] Where there is no conflict, the various embodiments of this application and the features thereof may be combined with each other.

[0017] As used herein, the term “and / or” includes any and all combinations of at least one related enumerated entry.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of at least one other feature, integral, step, operation, element, component, and / or group thereof is not excluded.

[0019] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0020] The data detection device and data detection method in this application are proposed based on the problems existing in the PBCH decoding process. However, the data detection device and data detection method in this application are not only applicable to PBCH decoding, but also applicable to the decoding of other data.

[0021] The data detection apparatus and data detection method of this application embodiment can be applied to mobile terminals, computer terminals, or other similar computing devices. For example, they can be applied to communication devices in wireless communication systems, such as user equipment, base stations, or at least one of them.

[0022] Figure 1 This is a block diagram of a data detection device provided in one embodiment of this application.

[0023] Firstly, referring to Figure 1 One embodiment of this application provides a data detection device, which can be installed in a mobile terminal, computer terminal, or other similar computing device. For example, it can be included in a communication device in a wireless communication system, such as at least one user equipment, base station, etc. The data detection device may include: at least one rate matching module, each rate matching module being connected to at least one soft combining module, each soft combining module being connected to a decoding verification module, and at least one processor and a first memory.

[0024] The module includes a rate matching module, which performs descrambling and derepetition rate matching on the input first SSB LLR according to the SSB index to obtain a second SSB LLR; a soft combining module, which performs de-sub-block interleaving, de-SFN masking, and LLR soft combining on the second SSB LLR according to the SFN index to obtain a third SSB LLR; and a decoding and verification module, which performs decoding and CRC processing on the third SSB LLR to obtain the decoded data and verification result.

[0025] The rate matching module, soft merging module, and decoding verification module are implemented using hardware circuits.

[0026] The first memory stores at least one program, which, when executed by at least one processor, performs at least one of the following steps: controlling whether the SSB index is input to the de-rate matching module via software or hardware circuitry; controlling whether the first SSB LLR is input to the de-rate matching module via software or hardware circuitry; controlling whether the first SSB LLR is subjected to de-secondary scrambling and de-repetition rate matching processing to obtain the second SSB LLR via the de-rate matching module, or whether the first SSB LLR is subjected to de-secondary scrambling and de-repetition rate matching processing via software to obtain the second SSB LLR; and controlling whether the SFN index is input to the soft merging module via software or hardware circuitry.

[0027] In some exemplary embodiments, different solution rate matching modules correspond to different SSB indices. That is, in the same data detection process, different SSB indices are input into the solution rate matching module, which is a process of using different SSB indices for blind detection.

[0028] In some exemplary embodiments, different soft-merging modules connected to the same de-rate matching module correspond to different decoding channels, and different soft-merging modules connected to the same de-rate matching module correspond to different SFN indices. That is, when using the same SSB index for data detection, the SFN index input to different soft-merging modules connected to the same de-rate matching module is different, which is the process of using different SFN indices for blind detection.

[0029] In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also performed: determining whether the verification result is successful; if the verification result is successful, ending the PBCH decoding process of this TTI and continuing the PBCH decoding process of the next TTI.

[0030] In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: if the verification result is a verification failure, determine whether all SFN indexes have been traversed; if not, notify the soft merge module to perform de-block interleaving, de-SFN masking, and LLR soft merge processing on the second SSB LLR based on the untraversed SFN indexes to obtain the third SSB LLR.

[0031] In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: if all SFN indices have been traversed, determine whether all SSB indices have been traversed; if not, notify the de-rate matching module to perform de-scrambling and de-repetition rate matching processing on the input first SSB LLR based on the untraversed SSB indices to obtain the second SSB LLR.

[0032] In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: if all SFN indices and all SSB indices have been traversed, the decoding process for the next SSB burstset cycle is performed.

[0033] The data detection device of this application embodiment can be installed in a mobile terminal, computer terminal or similar computing device.

[0034] The data detection device in this application embodiment can perform PBCH decoding during initial cell selection, cell handover, or cell reselection. Initial cell selection occurs when the terminal is powered on or enters a server area from a no-service area. The terminal contacts the base station, selects a suitable cell to camp on, and extracts system messages. Cell handover and cell reselection both involve changing the serving cell. The difference is that cell handover is performed when the terminal is in a call state, while cell reselection is performed when the terminal is in an idle state.

[0035] During initial cell selection, the SSB burst set period is 20ms, the TTI is 4 times the SSB burst set period, and the number of SSB LLRs transmitted within one TTI is 4 times the number of SSB LLRs transmitted within one SSB burst set period.

[0036] However, during cell handover and reselection, the SSB burst set period can be any one of 5ms, 10ms, 20ms, 40ms, 80ms, and 160ms. The number of SSB LLRs transmitted within one TTI is 16, 8, 4, 2, 1, and 1 times the number of SSB LLRs transmitted within one SSB burst set period, respectively, and the corresponding number of SFN indexes are 16, 8, 4, 4, 4, and 4, respectively.

[0037] Within the same Time Interval (TTI), LLR soft combining can be performed on different SSB burst set periods to improve the signal-to-noise ratio (SNR). However, when the SSB burst set period is 80ms or 160ms, SFN masking and LLR soft combining are not required. Taking an SSB burst set period of 20ms and a TTI of 80ms as an example, the first SSB LLR within different SSB burst set periods involves descrambling (secondary scrambling), de-repetition rate matching, de-interleaving (sub-block interleaving), and de-SFN masking (SFN masking) based on the same SSB index, followed by summation, which constitutes the LLR soft combining process.

[0038] In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are further implemented: When the control inputs the SSB index to the de-rate matching module via hardware circuitry, and the control inputs the first SSB LLR to the de-rate matching module via either software or hardware circuitry, and the control performs de-secondary scrambling and de-repetition rate matching processing on the first SSB LLR to obtain a second SSB LLR, and the control inputs the SFN index to the soft combining module via hardware circuitry, the control enables the de-rate matching module, receives the first SSB LLR through the de-rate matching module, performs de-secondary scrambling and de-repetition rate matching processing on the first SSB LLR to obtain a second SSB LLR, and after obtaining a second SSB LLR corresponding to an SSB index, the control notifies the de-rate matching module to send a start instruction to the soft combining module. The soft combining module performs de-sub-block interleaving processing, de-SFN masking processing, and LLR soft combining processing on the second SSB LLR according to the SFN index to obtain a third SSB LLR. Each time the soft combining module obtains a third SSB LLR, it performs de-sub-block interleaving processing, de-SFN masking processing, and LLR soft combining processing on the second SSB LLR to obtain a third SSB LLR. The LLR sends the data to the decoding and verification module for decoding and CRC processing to obtain the decoded data and verification results.

[0039] In some exemplary embodiments, such as Figure 2 and Figure 3 As shown, the de-rate matching module includes: a second-level scrambling code generation unit, used to generate a second-level scrambling code based on the SSB index; a second-level scrambling descrambling unit, used to perform de-scrambling processing on the first SSB LLR based on the second-level scrambling code to obtain a fourth SSB LLR; and a de-repetition rate matching unit, used to perform de-repetition rate matching processing on the fourth SSB LLR to obtain a second SSB LLR.

[0040] In some exemplary embodiments, the data detection device further includes: a first multiplexer (such as...) Figure 2 Mux1 in the middle), the second multiplexer (such as...) Figure 2 At least one of the Mux2 in the list.

[0041] The output of the first multiplexer is connected to the input of the secondary scrambling unit. One input of the first multiplexer is connected to the SSB index input via software, which is connected to the processor. The SSB index output by the front-end hardware circuit is input to the processor, which then inputs the SSB index into the secondary scrambling unit. The other input of the first multiplexer is connected to the SSB index input via the hardware circuit, which means the SSB index output by the front-end hardware circuit is directly input to the secondary scrambling unit.

[0042] The output of the second multiplexer is connected to the input of the second-level descrambling unit. One input of the second multiplexer is connected to the first SSB LLR input via software, which is connected to the processor. The first SSB LLR output from the front-end hardware circuit is input to the processor, which then inputs the first SSB LLR to the second-level descrambling unit. The other input of the second multiplexer is connected to the first SSB LLR input via hardware circuit, which means the first SSB LLR output from the front-end hardware circuit is directly input to the second-level descrambling unit.

[0043] When at least one program is executed by at least one processor, it is specifically used to control whether the SSB index is input to the derate matching module via software or hardware circuitry in the following manner: controlling the first multiplexer to select whether the SSB index is input to the secondary scrambling generation unit via software or hardware circuitry.

[0044] When at least one program is executed by at least one processor, it is specifically used to control whether the first SSB LLR is input to the de-rate matching module via software or hardware circuitry by controlling a second multiplexer to select whether the first SSB LLR is input to the de-secondary scrambling unit via software or hardware circuitry.

[0045] In some exemplary embodiments, such as Figure 2 As shown, the rate matching module further includes: a second memory for storing the second SSB LLR; a third multiplexer (such as...) Figure 2 Mux3 in the middle.

[0046] The output of the third multiplexer is connected to the input of the second memory. One input of the third multiplexer is connected to the de-repetition rate matching unit. The other input of the third multiplexer is connected to the second SSB LLR, which is input through software, i.e., connected to the processor. The second SSB LLR output by the de-repetition rate matching unit is input to the processor, and the processor inputs the second SSB LLR to the other input of the third multiplexer.

[0047] When at least one program is executed by at least one processor, the following steps are also performed: controlling a third multiplexer to select whether to store the second SSB LLR into the second memory via the de-repetition rate matching unit or to write the second SSB LLR into the second memory via software.

[0048] In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are further implemented: when the second SSB LLR is written to the second memory by software, the de-rate matching module is enabled and the soft merging module is disabled; after the de-rate matching module performs de-secondary scrambling and de-repetition rate matching processing on the input first SSBLLR according to the SSB index to obtain the second SSB LLR, the de-rate matching module is disabled and the second SSB LLR is written to the second memory; the soft merging module is enabled.

[0049] In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are further implemented: when the third multiplexer is controlled to select that the second SSB LLR be written to the second memory via software, the second-level scrambling generation unit, the second-level descrambling unit, and the derepetition rate matching unit are controlled to be in an enabled state, and the soft combining module is controlled to be in a disabled state; after the derepetition rate matching unit performs derepetition rate matching processing on the fourth SSB LLR to obtain the second SSB LLR, the second-level scrambling generation unit, the second-level descrambling unit, and the derepetition rate matching unit are controlled to be in a disabled state, the derepetition rate matching unit is controlled to stop writing the second SSB LLR to the second memory, the second SSB LLR output by the derepetition rate matching unit is read, and the second SSB LLR is written to the second memory; the soft combining module is controlled to be in an enabled state.

[0050] In some exemplary embodiments, such as Figure 3 As shown, the rate matching module also includes a third memory for storing the first SSB LLR.

[0051] The output of the second multiplexer is connected to the input of the third memory. The output of the third memory is connected to the input of the second-level descrambling unit. One input of the second multiplexer is connected to the first SSB LLR input via software, which is connected to the processor. The first SSB LLR output from the front-end hardware circuit is input to the processor, which then inputs the first SSB LLR into the third memory. The other input of the second multiplexer is connected to the first SSB LLR input via hardware circuit, which means the first SSB LLR output from the front-end hardware circuit is directly input into the third memory.

[0052] In some exemplary embodiments, the soft combining module includes: an SFN mask generation unit for generating an SFN mask based on an SFN index; a de-block interleaving unit for performing de-block interleaving processing on a second SSB LLR to obtain a fifth SSBLLR; a de-SFN masking unit for performing de-SFN masking processing on the fifth SSB LLR based on the SFN mask to obtain a sixth SSBLLR; an LLR soft combining unit for performing LLR soft combining processing on the sixth SSB LLR and an SSB LLR stored in a fourth memory to obtain a third SSB LLR; or, outputting the sixth SSB LLR as the third SSB LLR; the LLR soft combining unit is further configured to: store the third SSB LLR in a fourth memory; the fourth memory is used to store a third synchronization signal block; a fourth multiplexer (e.g., Figure 2 and Figure 3 Mux4 and the fifth multiplexer (such as...) Figure 2 and Figure 3 (Mux5 in the middle).

[0053] The output of the fourth multiplexer is connected to the input of the LLR soft merging unit. One input of the fourth multiplexer is connected to data 0, and the other input of the fourth multiplexer is connected to the output of the SFN demasking unit.

[0054] The output of the fifth multiplexer is connected to the input of the LLR soft merging unit. One input of the fifth multiplexer is connected to data 0, and the other input of the fifth multiplexer is connected to the output of the fourth memory.

[0055] When at least one program is executed by at least one processor, the following steps are also implemented: controlling the fourth multiplexer to select data 0 or the sixth SSB LLR output from the de-SFN masking unit to be input to the LLR soft merging unit; controlling the fifth multiplexer to select data 0 or the SSB LLR stored in the fourth memory to be input to the LLR soft merging unit; controlling whether the second SSB LLR is subjected to de-sub-block interleaving processing and de-system frame number masking processing through the de-sub-block interleaving unit, the de-SFN masking unit, and the SFN masking generation unit, or whether the second SSB LLR is subjected to de-sub-block interleaving processing and de-SFN masking processing through software.

[0056] In some exemplary embodiments, the data 0 connected to one input of the fourth multiplexer and the data 0 connected to one input of the fifth multiplexer can both be generated by hardware circuitry.

[0057] In some exemplary embodiments, when the fourth multiplexer selects data 0 to be input into the LLR soft combining unit, the sixth SSB LLR output by the de-SFN masking unit is bypassed. When the fifth multiplexer selects the SSB LLR stored in the fourth memory to be input into the LLR soft combining unit, the sixth SSB LLR or the third SSB LLR of the previous SSB burst set cycle stored in the fourth memory is input into the LLR soft combining unit. Then, the sixth SSB LLR or the third SSB LLR of the previous SSB burst set cycle is input into the Polar code decoding unit for decoding. That is, the soft combining result is the sixth SSB LLR or the third SSB LLR of the previous SSB burst set cycle.

[0058] When the fourth multiplexer selects the sixth SSB LLR output from the de-SFN masking unit to be input into the LLR soft-merging unit, that is, the sixth SSB LLR output from the de-SFN masking unit in this SSB burst set cycle is input into the LLR soft-merging unit. When the fifth multiplexer selects data 0 to be input into the LLR soft-merging unit, the SSB LLR stored in the fourth memory is bypassed, and then the sixth SSB LLR output from the de-SFN masking unit in this SSB burst set cycle is input into the Polar code decoding unit for decoding processing. That is, the soft-merging result is the sixth SSB LLR output from the de-SFN masking unit in this SSB burst set cycle.

[0059] When the fourth multiplexer selects the sixth SSB LLR output from the de-SFN masking unit to be input into the LLR soft-merging unit, it means inputting the sixth SSB LLR output from the de-SFN masking unit in the current SSB burst set cycle into the LLR soft-merging unit. When the fifth multiplexer selects the SSB LLR stored in the fourth memory to be input into the LLR soft-merging unit, it means inputting the sixth SSB LLR output from the de-SFN masking unit in the previous SSB burst set cycle stored in the fourth memory into the LLR soft-merging unit. Then, the soft-merging result after performing LLR soft-merging processing on the sixth SSB LLR output from the de-SFN masking unit in the previous SSB burst set cycle or the third SSB LLR from the previous SSB burst set cycle and the sixth SSB LLR output from the de-SFN masking unit in the current SSB burst set cycle is input into the Polar code decoding unit for decoding processing. That is, the soft-merging result is the sixth SSB LLR output from the de-SFN masking unit in the previous SSB burst set cycle or the third SSB LLR from the previous SSB burst set cycle. The result of adding the LLR to the sixth SSB LLR output by the desmearing SFN masking unit in this SSB burst set cycle.

[0060] When the fourth multiplexer selects data 0 as input to the LLR soft merging unit, the sixth SSB LLR output from the SFN masking unit is bypassed. When the fifth multiplexer selects data 0 as input to the LLR soft merging unit, the SSB LLR stored in the fourth memory is bypassed, and the soft merging result is 0.

[0061] In some exemplary embodiments, the LLR soft merge process can be additive.

[0062] As described above, different soft combining requirements can be achieved by controlling the fourth multiplexer and the fifth multiplexer controller to select different data channels. For example, if the BBS burst set period is 80ms and 160ms; or if the BBS burst set period is any one of 5ms, 10ms, 20ms, and 40ms, and the current period is the first BBS burst set period of the TTI, LLR soft combining cannot be performed. In this case, the data 0 can be input into the LLR soft combining unit by controlling the fifth multiplexer controller.

[0063] If the BBS burst set period is any one of 5ms, 10ms, 20ms, or 40ms, and the current period is not the first BBS burst set period of TTI, then LLR soft combining can be performed by controlling the fifth multiplexer to input the sixth SSB LLR output from the desmearing SFN mask unit in the previous SSB burst set period stored in the fourth memory into the LLR soft combining unit.

[0064] In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: whether the generation of the SFN mask, the deinterleaving process, and the de-SFN masking process are implemented through software or through hardware circuitry.

[0065] When the SFN mask generation, sub-block interleaving, and SFN mask de-processing are implemented through software, the de-rate matching module is in an enabled state. After the de-repetition rate matching unit stops writing the second SSB LLR to the second memory, the de-rate matching module is in a disabled state. The second SSB LLR stored in the second memory is read; an SFN mask is generated; the second SSB LLR is de-interleaved according to the generated SFN mask; the SFN mask de-processing is performed to obtain the sixth SSB LLR; and the sixth SSB LLR is written to the fourth memory.

[0066] In this case, the LLR soft merging unit is also used to: read the third SSB LLR of the previous BBS burst set cycle and the sixth SSB LLR of the current BBS burst set cycle stored in the fourth memory, perform LLR soft merging processing to obtain the third SSB LLR of the current BBS burst set cycle, and store the third SSB LLR of the current BBS burst set cycle into the fourth memory.

[0067] In some exemplary embodiments, it also includes: a sixth multiplexer (such as...) Figure 2 and Figure 3 The output of the sixth multiplexer (Mux6) is connected to the input of the SFN mask generation unit. One input of the sixth multiplexer is connected to the SFN index input by software, i.e., connected to the processor, which reads the SFN index from other hardware modules and inputs it. The other input of the sixth multiplexer is connected to the SFN index input by hardware circuitry.

[0068] When at least one program is executed by at least one processor, the following steps are also performed: controlling the sixth multiplexer to select whether the SFN index is input via software or via hardware circuitry.

[0069] In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are further implemented: Before the de-rate matching module performs de-secondary scrambling and de-repetition rate matching on the input first SSB LLR according to the SSB index to obtain the second SSB LLR, in the case of de-block interleaving and de-SFN masking of the second SSB LLR by software, the de-rate matching module is enabled; after the de-rate matching module performs de-secondary scrambling and de-repetition rate matching on the input first SSB LLR according to the SSB index to obtain the second SSB LLR, the de-rate matching module is disabled; the second SSB LLR is read; the second SSB LLR is de-block interleaved and de-SFN masked to obtain the sixth SSB LLR; and the sixth SSB LLR is written to the fourth memory.

[0070] In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are performed: if the verification result is a verification failure, the second SSB LLR stored in the second memory is read for data analysis and error finding, and the third SSB LLR stored in the fourth memory is read for data analysis and error finding.

[0071] In some exemplary embodiments, the number of second memories may be one or more.

[0072] In some exemplary embodiments, the number of third memories may be one or more.

[0073] In some exemplary embodiments, the number of fourth memories may be one or more.

[0074] In some exemplary embodiments, different second memories can be selected by switching using a multiplexer.

[0075] In some exemplary embodiments, different third memories can be selected by switching using a multiplexer.

[0076] In some exemplary embodiments, different fourth memories can be selected by switching using a multiplexer.

[0077] In some exemplary embodiments, the decoding and verification module includes a Polar code decoding unit and a CRC unit.

[0078] The Polar code decoding unit is used to decode the third SSB LLR to obtain the decoded data.

[0079] The CRC unit is used to perform CRC processing on the decoded data to obtain the verification result.

[0080] In some exemplary embodiments, the processor is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the first memory, the second memory, the third memory, or the fourth memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically such as SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH).

[0081] The data detection device provided in this application embodiment detects PBCH data by combining software and hardware circuits, which improves flexibility. It detects PBCH data by using at least one solution rate matching module and at least one soft merging module, which greatly simplifies the data detection process.

[0082] Figure 4 A flowchart of a data detection method provided in another embodiment of this application.

[0083] Secondly, referring to Figure 4 Another embodiment of this application provides a data detection method, which can be applied to mobile terminals, computer terminals, or other similar computing devices. For example, it can be applied to communication equipment in a wireless communication system, where the communication equipment may be at least one of user equipment, base stations, etc. The data detection method includes:

[0084] Step 400: The second SSB LLR is obtained by performing de-scrambling and de-repetition rate matching on the input first SSBLLR according to the SSB index through at least one de-rate matching module; wherein, different de-rate matching modules correspond to different SSB indices.

[0085] In some exemplary embodiments, different decoding rate matching modules correspond to different decoding channels, and different decoding rate matching modules correspond to different SSB indices. That is to say, in the same data detection process, the SSB index input to the decoding rate matching module is different, which is the process of using different SSB indices for blind detection.

[0086] In some exemplary embodiments, different soft-merging modules connected to the same de-rate matching module correspond to different decoding channels, and different soft-merging modules connected to the same de-rate matching module correspond to different SFN indices. That is, when using the same SSB index for data detection, the SFN index input to different soft-merging modules connected to the same de-rate matching module is different, which is the process of using different SFN indices for blind detection.

[0087] In some exemplary embodiments, the process of obtaining a second SSB LLR by performing second-level scrambling and de-repetition rate matching on the input first SSB LLR based on the SSB index through the de-rate matching module includes: generating a second-level scrambling code based on the SSB index by a second-level scrambling code generation unit; performing second-level scrambling on the first SSB LLR based on the second-level scrambling code by a de-scrambling unit to obtain a fourth SSB LLR; and performing de-repetition rate matching on the fourth SSB LLR by a de-repetition rate matching unit to obtain the second SSB LLR.

[0088] In some exemplary embodiments, the input of the SSB index to the secondary scrambling generation unit can be selected by controlling the first multiplexer through software or hardware circuitry.

[0089] In some exemplary embodiments, the first SSB LLR input to the descrambling unit can be selected via software or hardware circuitry by controlling a second multiplexer.

[0090] In some exemplary embodiments, after obtaining the second SSB LLR by performing derepetition rate matching processing on the fourth SSB LLR through the derepetition rate matching unit, the method further includes: selecting, by controlling a third multiplexer, whether to store the second SSB LLR in the second memory through the derepetition rate matching unit or to write the second SSB LLR into the second memory through software.

[0091] In some exemplary embodiments, when the second SSB LLR is written to the second memory via software, the de-rate matching module is enabled and the soft merging module is disabled; after the de-rate matching module performs de-secondary scrambling and de-repetition rate matching processing on the input first SSB LLR according to the SSB index to obtain the second SSB LLR, the de-rate matching module is disabled and the second SSB LLR is written to the second memory; the soft merging module is enabled.

[0092] In some exemplary embodiments, when the third multiplexer is controlled to select that the second SSB LLR be written to the second memory via software, the second-level scrambling generation unit, the second-level descrambling unit, and the derepetition rate matching unit are enabled, and the soft combining module is disabled. After the derepetition rate matching unit performs derepetition rate matching processing on the fourth SSB LLR to obtain the second SSB LLR, the second-level scrambling generation unit, the second-level descrambling unit, and the derepetition rate matching unit are disabled, the derepetition rate matching unit stops writing the second SSB LLR to the second memory, the second SSB LLR output by the derepetition rate matching unit is read, and the second SSB LLR is written to the second memory; the soft combining module is enabled.

[0093] In some exemplary embodiments, when the second SSB LLR is deinterleaved and de-SFN masked by software, the rate matching module is enabled before it performs second-level scrambling and de-repetition rate matching on the input first SSB LLR according to the SSB index to obtain the second SSB LLR; after the rate matching module performs second-level scrambling and de-repetition rate matching on the input first SSB LLR according to the SSB index to obtain the second SSB LLR, the rate matching module is disabled; the second SSB LLR is read; the second SSB LLR is deinterleaved and de-SFN masked to obtain the sixth SSB LLR; and the sixth SSB LLR is written to the fourth memory.

[0094] Step 401: The third SSBLLR is obtained by performing sub-block interleaving, de-SFN masking, and LLR soft merging on the second SSB LLR according to the SFN index through at least one soft merging module connected to the same de-rate matching module; wherein, different soft merging modules connected to the same de-rate matching module correspond to different SFN indices.

[0095] In some exemplary embodiments, the process of obtaining a third SSB LLR by performing de-block interleaving, de-SFN masking, and LLR soft merging on a second SSB LLR based on an SFN index using a soft merging module includes: generating an SFN mask based on an SFN index using an SFN mask generation unit; performing de-block interleaving on the second SSB LLR using a de-block interleaving unit to obtain a fifth SSB LLR; performing de-SFN masking on the fifth SSB LLR based on the SFN mask using a de-SFN masking unit to obtain a sixth SSB LLR; performing LLR soft merging on the sixth SSB LLR and the SSB LLR stored in a fourth memory using an LLR soft merging unit to obtain a third SSB LLR; or, outputting the sixth SSB LLR as the third SSB LLR; storing the third SSB LLR in a fourth memory using an LLR soft merging unit; and storing a third synchronization signal block in the fourth memory.

[0096] In some exemplary embodiments, the fourth multiplexer is controlled to select either data 0 or the sixth SSB LLR output from the de-SFN masking unit as input to the LLR soft merging unit; the fifth multiplexer is controlled to select either data 0 or the SSB LLR stored in the fourth memory as input to the LLR soft merging unit; and the de-interleaving and de-system frame number masking processes of the second SSB LLR are controlled either through the de-block interleaving unit, the de-SFN masking unit, and the SFN masking generation unit, or through software.

[0097] In some exemplary embodiments, when the fourth multiplexer selects data 0 to be input into the LLR soft combining unit, the sixth SSB LLR output by the de-SFN masking unit is bypassed. When the fifth multiplexer selects the SSB LLR stored in the fourth memory to be input into the LLR soft combining unit, the sixth SSB LLR or the third SSB LLR of the previous SSB burst set cycle stored in the fourth memory is input into the LLR soft combining unit. Then, the sixth SSB LLR or the third SSB LLR of the previous SSB burst set cycle is input into the Polar code decoding unit for decoding. That is, the soft combining result is the sixth SSB LLR or the third SSB LLR of the previous SSB burst set cycle.

[0098] When the fourth multiplexer selects the sixth SSB LLR output from the de-SFN masking unit to be input into the LLR soft-merging unit, that is, the sixth SSB LLR output from the de-SFN masking unit in this SSB burst set cycle is input into the LLR soft-merging unit. When the fifth multiplexer selects data 0 to be input into the LLR soft-merging unit, the SSB LLR stored in the fourth memory is bypassed, and then the sixth SSB LLR output from the de-SFN masking unit in this SSB burst set cycle is input into the Polar code decoding unit for decoding processing. That is, the soft-merging result is the sixth SSB LLR output from the de-SFN masking unit in this SSB burst set cycle.

[0099] When the fourth multiplexer selects the sixth SSB LLR output from the de-SFN masking unit to be input into the LLR soft-merging unit, it means inputting the sixth SSB LLR output from the de-SFN masking unit in the current SSB burst set cycle into the LLR soft-merging unit. When the fifth multiplexer selects the SSB LLR stored in the fourth memory to be input into the LLR soft-merging unit, it means inputting the sixth SSB LLR output from the de-SFN masking unit in the previous SSB burst set cycle stored in the fourth memory into the LLR soft-merging unit. Then, the soft-merging result after performing LLR soft-merging processing on the sixth SSB LLR output from the de-SFN masking unit in the previous SSB burst set cycle or the third SSB LLR from the previous SSB burst set cycle and the sixth SSB LLR output from the de-SFN masking unit in the current SSB burst set cycle is input into the Polar code decoding unit for decoding processing. That is, the soft-merging result is the sixth SSB LLR output from the de-SFN masking unit in the previous SSB burst set cycle or the third SSB LLR from the previous SSB burst set cycle. The result of adding the LLR to the sixth SSB LLR output by the desmearing SFN masking unit in this SSB burst set cycle.

[0100] When the fourth multiplexer selects data 0 as input to the LLR soft merging unit, the sixth SSB LLR output from the SFN masking unit is bypassed. When the fifth multiplexer selects data 0 as input to the LLR soft merging unit, the SSB LLR stored in the fourth memory is bypassed, and the soft merging result is 0.

[0101] In some exemplary embodiments, the LLR soft merge process can be additive.

[0102] As described above, different soft combining requirements can be achieved by controlling the fourth multiplexer and the fifth multiplexer controller to select different data channels. For example, if the BBS burst set period is 80ms and 160ms; or if the BBS burst set period is any one of 5ms, 10ms, 20ms, and 40ms, and the current period is the first BBS burst set period of the TTI, LLR soft combining cannot be performed. In this case, the data 0 can be input into the LLR soft combining unit by controlling the fifth multiplexer controller.

[0103] If the BBS burst set period is any one of 5ms, 10ms, 20ms, or 40ms, and the current period is not the first BBS burst set period of TTI, then LLR soft combining can be performed by controlling the fifth multiplexer to input the sixth SSB LLR output from the desmearing SFN mask unit in the previous SSB burst set period stored in the fourth memory into the LLR soft combining unit.

[0104] In some exemplary embodiments, the method further includes: controlling whether the generation of the SFN mask, the deinterleaving of sub-blocks, and the de-SFN masking are implemented through software or through hardware circuitry.

[0105] When the SFN mask generation, sub-block interleaving, and SFN mask de-processing are implemented through software, the de-rate matching module is in an enabled state. After the de-repetition rate matching unit stops writing the second SSB LLR to the second memory, the de-rate matching module is in a disabled state. The second SSB LLR stored in the second memory is read; an SFN mask is generated; the second SSB LLR is de-interleaved according to the generated SFN mask; the SFN mask de-processing is performed to obtain the sixth SSB LLR; and the sixth SSB LLR is written to the fourth memory.

[0106] In this case, the LLR soft merging unit is also used to: read the third SSB LLR of the previous BBS burst set cycle and the sixth SSB LLR of the current BBS burst set cycle stored in the fourth memory, perform LLR soft merging processing to obtain the third SSB LLR of the current BBS burst set cycle, and store the third SSB LLR of the current BBS burst set cycle into the fourth memory.

[0107] In some exemplary embodiments, the method further includes controlling a sixth multiplexer to select whether the SFN index is input via software or via hardware circuitry.

[0108] Step 402: The third SSB LLR is decoded and CRC processed by the decoding and verification module connected to the soft merging module to obtain the decoded data and verification result.

[0109] In some exemplary embodiments, the decoding and CRC processing of the third SSB LLR by the decoding and verification module connected to the soft merging module to obtain the decoded data and verification result includes: decoding the third SSB LLR by the Polar code decoding unit to obtain the decoded data; and performing CRC processing on the decoded data by the CRC unit to obtain the verification result.

[0110] In some exemplary embodiments, the rate matching module, the soft merging module, and the decoding verification module are implemented using hardware circuits.

[0111] In some exemplary embodiments, the data detection method further includes at least one of the following steps: controlling whether to input the SSB index into the de-rate matching module via software or hardware circuitry; controlling whether to input the first SSB LLR into the de-rate matching module via software or hardware circuitry; controlling whether to perform second-order scrambling and de-repetition rate matching processing on the first SSB LLR through the de-rate matching module to obtain the second SSB LLR, or to perform second-order scrambling and de-repetition rate matching processing on the first SSB LLR through software to obtain the second SSB LLR; and controlling whether to input the SFN index into the soft combining module via software or hardware circuitry.

[0112] In some exemplary embodiments, when the control inputs the SSB index to the de-rate matching module via hardware circuitry, and the control inputs the first SSB LLR to the de-rate matching module via either software or hardware circuitry, and the control performs de-secondary scrambling and de-repetition rate matching processing on the first SSB LLR to obtain the second SSB LLR, and the control inputs the SFN index to the soft combining module via hardware circuitry, the control de-rate matching module is in an enabled state. The de-rate matching module receives the first SSB LLR, performs de-secondary scrambling and de-repetition rate matching processing on the first SSB LLR to obtain the second SSB LLR, and after obtaining the second SSB LLR corresponding to an SSB index, it notifies the de-rate matching module to send a start instruction to the soft combining module. The soft combining module performs de-sub-block interleaving, de-SFN masking, and LLR soft combining processing on the second SSB LLR according to the SFN index to obtain the third SSB LLR. Each time the soft combining module obtains a third SSB LLR, it sends the third SSB LLR to the decoding and verification module for decoding and CRC processing to obtain the decoded data and verification result.

[0113] In some exemplary embodiments, after the decoding and cyclic redundancy check (CRC) processing of the third SSB LLR is performed by the decoding and CRC check processing module connected to the soft merging module to obtain the decoded data and the check result, the method further includes: determining whether the check result is successful; if the check result is successful, ending the PBCH decoding process of this TTI and continuing the PBCH decoding process of the next TTI.

[0114] In some exemplary embodiments, if the verification result is a verification failure, it is determined whether all SFN indices have been traversed. If all SFN indices have not been traversed, the soft merging module is notified to perform de-interleaving, de-SFN masking, and LLR soft merging on the second SSB LLR based on the untraversed SFN indices to obtain the third SSB LLR.

[0115] In some exemplary embodiments, if all SFN indices have been traversed, it is determined whether all SSB indices have been traversed. If not, the de-rate matching module is notified to perform de-scrambling and de-repetition rate matching on the input first SSB LLR based on the untraversed SSB indices to obtain the second SSB LLR.

[0116] In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: if all SFN indexes and all SSB indexes have been traversed, the PBCH decoding process of this TTI ends and the PBCH decoding process of the next TTI continues.

[0117] In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: if all SFN indices and all SSB indices have been traversed, the decoding process for the next SSB burstset cycle is performed.

[0118] The data detection method of this application embodiment can be applied to mobile terminals, computer terminals or similar computing devices.

[0119] The data detection method in this application embodiment can perform PBCH decoding during initial cell selection, cell handover, or cell reselection. Initial cell selection occurs when the terminal is powered on or enters a server area from a no-service area. The terminal contacts the base station, selects a suitable cell to camp on, and extracts system messages. Cell handover and cell reselection both involve changing the serving cell. The difference is that cell handover is performed when the terminal is in a call state, while cell reselection is performed when the terminal is in an idle state.

[0120] During initial cell selection, the SSB burst set period is 20ms, the TTI is 4 times the SSB burst set period, and the number of SSB LLRs transmitted within one TTI is 4 times the number of SSB LLRs transmitted within one SSB burst set period.

[0121] However, during cell handover and reselection, the SSB burst set period can be any one of 5ms, 10ms, 20ms, 40ms, 80ms, and 160ms. The number of SSB LLRs transmitted within one TTI is 16, 8, 4, 2, 1, and 1 times the number of SSB LLRs transmitted within one SSB burst set period, respectively, and the corresponding number of SFN indexes are 16, 8, 4, 4, 4, and 4, respectively.

[0122] Within the same TTI, LLR soft combining can be performed on different SSB burst set periods to improve the signal-to-noise ratio. However, when the SSB burst set period is 80ms and 160ms, SFN masking and LLR soft combining are not required. Taking an SSB burst set period of 20ms and a TTI of 80ms as an example, the first SSB LLR within different SSB burst set periods involves descrambling (secondary scrambling), derepetition rate matching, deinterleaving (sub-block interleaving), and descrambling (SFN masking) based on the same SSB index and the same SFN index, followed by summation. This constitutes the LLR soft combining process.

[0123] The specific implementation process of the above data detection method is the same as that of the data detection device in the aforementioned embodiments, and will not be repeated here.

[0124] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0125] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this application as set forth by the appended claims.

Claims

1. A data detection device, comprising: At least one de-rate matching module, each of the de-rate matching modules is connected to at least one soft merging module, each soft merging module is connected to a decoding verification module, and at least one processor and a first memory; The rate matching module is used to perform de-scrambling and de-repetition rate matching on the input first log-likelihood probability of the synchronization signal block according to the synchronization signal block index to obtain the second log-likelihood probability of the synchronization signal block. The soft merging module is used to perform sub-block interleaving processing, system frame number masking processing, and log-likelihood probability soft merging processing on the log-likelihood probability of the second synchronization signal block according to the system frame number index to obtain the log-likelihood probability of the third synchronization signal block. The decoding and verification module is used to perform decoding processing and cyclic redundancy code verification processing on the log-likelihood probability of the third synchronization signal block to obtain the decoded data and verification results. The de-rate matching module, the soft merging module, and the decoding verification module are implemented using hardware circuits. The first memory stores at least one program, which, when executed by the at least one processor, performs at least one of the following steps: The control is implemented by inputting the synchronization signal block index into the derate matching module via software or hardware circuitry. The control is implemented by inputting the log-likelihood probability of the first synchronization signal block into the solution rate matching module via software or hardware circuitry. The control determines whether the second synchronization signal block log likelihood probability is obtained by performing second-order scrambling and de-repetition rate matching on the log likelihood probability of the first synchronization signal through the de-rate matching module, or by performing second-order scrambling and de-repetition rate matching on the log likelihood probability of the first synchronization signal through software. The system frame number index is input into the soft merging module via either software or hardware circuitry.

2. The data detection device according to claim 1, wherein, The solution rate matching module includes: A secondary scrambling code generation unit is used to generate a secondary scrambling code based on the synchronization signal block index; The second-level scrambling unit is used to perform second-level scrambling on the log-likelihood probability of the first synchronization signal block according to the second-level scrambling code to obtain the log-likelihood probability of the fourth synchronization signal block. The de-repetition rate matching unit is used to perform de-repetition rate matching processing on the log-likelihood probability of the fourth synchronization signal block to obtain the log-likelihood probability of the second synchronization signal block. The data detection device further includes at least one of a first multiplexer and a second multiplexer; Wherein, the output terminal of the first multiplexer is connected to the input terminal of the secondary scrambling code generation unit, one input terminal of the first multiplexer is connected to the synchronization signal block index input by software, and the other input terminal of the first multiplexer is connected to the synchronization signal block index input by hardware circuit; Wherein, the output of the second multiplexer is connected to the input of the second-level scrambling unit, one input of the second multiplexer is connected to the log-likelihood probability of the first synchronization signal block input by software, and the other input of the second multiplexer is connected to the log-likelihood probability of the first synchronization signal block input by hardware circuit. When the at least one program is executed by the at least one processor, it is specifically used to implement the control of inputting the synchronization signal block index into the derate matching module via software or hardware circuitry in the following manner: controlling the first multiplexer to select whether to input the synchronization signal block index into the secondary scrambling code generation unit via software or hardware circuitry; When the at least one program is executed by the at least one processor, it is specifically used to implement the control of inputting the log-likelihood probability of the first synchronization signal block into the de-rate matching module via software or hardware circuitry in the following manner: controlling the second multiplexer to select whether to input the log-likelihood probability of the first synchronization signal block into the de-secondary scrambling unit via software or hardware circuitry.

3. The data detection device according to claim 2, wherein the solution rate matching module further comprises: The second memory is used to store the log-likelihood probability of the second synchronization signal block; Third multiplexer; Wherein, the output of the third multiplexer is connected to the input of the second memory, one input of the third multiplexer is connected to the de-repetition rate matching unit, and the other input of the third multiplexer is connected to the log-likelihood probability of the second synchronization signal block input by software; When the at least one program is executed by the at least one processor, the following steps are also performed: The third multiplexer controls whether to store the log-likelihood probability of the second synchronization signal block into the second memory via the de-repetition rate matching unit, or to write the log-likelihood probability of the second synchronization signal block into the second memory via software.

4. The data detection apparatus according to claim 3, when the at least one program is executed by the at least one processor, further comprises the following steps: When the log-likelihood probability of the second synchronization signal block is written to the second memory via software, the solution rate matching module is enabled and the soft merging module is disabled. After the de-rate matching module performs de-scrambling and de-repetition rate matching on the input first synchronization signal block log likelihood probability according to the synchronization signal block index to obtain the second synchronization signal block log likelihood probability, the de-rate matching module is put into a disabled state, and the second synchronization signal block log likelihood probability is written into the second memory. Enable the soft merging module.

5. The data detection device according to claim 2, wherein the solution rate matching module further comprises: The third memory is used to store the log-likelihood probability of the first synchronization signal block.

6. The data detection device according to claim 1, wherein, The soft merging module includes: A system frame number mask generation unit is used to generate a system frame number mask based on the system frame number index. The descaling unit is used to perform descaling processing on the log-likelihood probability of the second synchronization signal block to obtain the log-likelihood probability of the fifth synchronization signal block. The system frame number masking unit is used to perform system frame number masking processing on the log-likelihood probability of the fifth synchronization signal block according to the system frame number mask to obtain the log-likelihood probability of the sixth synchronization signal block. The log-likelihood probability soft-merging unit is used to perform log-likelihood probability soft-merging processing on the log-likelihood probability of the sixth synchronization signal block and the log-likelihood probability of the synchronization signal block stored in the fourth memory to obtain the log-likelihood probability of the third synchronization signal block; or, output the log-likelihood probability of the sixth synchronization signal block as the log-likelihood probability of the third synchronization signal block; the log-likelihood probability soft-merging unit is further used to: store the log-likelihood probability of the third synchronization signal block in the fourth memory; The fourth memory is used to store the third synchronization signal block; Fourth and fifth multiplexers; The output of the fourth multiplexer is connected to the input of the log-likelihood probability soft merging unit. One input of the fourth multiplexer is connected to data 0, and the other input of the fourth multiplexer is connected to the output of the de-system frame number mask unit. The output of the fifth multiplexer is connected to the input of the log-likelihood probability soft merging unit. One input of the fifth multiplexer is connected to data 0, and the other input of the fifth multiplexer is connected to the output of the fourth memory. When the at least one program is executed by the at least one processor, the following steps are also performed: The fourth multiplexer controls whether to select data 0 or the log-likelihood probability of the sixth synchronization signal block output by the de-system frame number mask unit, and inputs it to the log-likelihood probability soft-merging unit. The fifth multiplexer is controlled to select either data 0 or the log-likelihood probability of the synchronization signal block stored in the fourth memory, which is then input to the log-likelihood probability soft-combining unit. The control determines whether the log-likelihood probability of the second synchronization signal block is processed by the de-interleaving unit, the de-system frame number masking unit, and the system frame number masking generation unit through de-interleaving and de-system frame number masking, or by software.

7. The data detection device according to claim 6, further comprising: Sixth multiplexer; The output of the sixth multiplexer is connected to the input of the system frame number mask generation unit. One input of the sixth multiplexer is connected to the system frame number index input by software, and the other input of the sixth multiplexer is connected to the system frame number index input by hardware circuitry. When the at least one program is executed by the at least one processor, the following steps are also performed: The sixth multiplexer is controlled to select whether the system frame number index is input via software or via hardware circuitry.

8. The data detection apparatus according to claim 6, further comprising the following steps when the at least one program is executed by the at least one processor: Before the de-rate matching module performs de-secondary scrambling and de-repetition rate matching on the input first log-likelihood probability of the synchronization signal block according to the synchronization signal block index to obtain the second log-likelihood probability of the synchronization signal block, the de-rate matching module is enabled. After the de-rate matching module performs de-scrambling and de-repetition rate matching processing on the input first synchronization signal block log likelihood probability according to the synchronization signal block index to obtain the second synchronization signal block log likelihood probability, the de-rate matching module is put into a disabled state. Read the log-likelihood probability of the second synchronization signal block; The log-likelihood probability of the second synchronization signal block is obtained by performing sub-block interleaving processing and de-system frame number masking processing on the log-likelihood probability of the second synchronization signal block; Write the log-likelihood probability of the sixth synchronization signal block into the fourth memory.

9. The data detection device according to any one of claims 1-8, wherein, Different solution rate matching modules correspond to different synchronization signal block indices.

10. The data detection device according to any one of claims 1-8, wherein, Different soft merging modules connected to the same solution rate matching module correspond to different system frame number indices.

11. A data detection method, comprising: At least one rate matching module is used to perform de-scrambling and de-repetition rate matching on the input log-likelihood probability of the first synchronization signal block based on the synchronization signal block index to obtain the log-likelihood probability of the second synchronization signal block; wherein, different rate matching modules correspond to different synchronization signal block indices. The third synchronization signal block log likelihood probability is obtained by performing sub-block interleaving, de-system frame number masking, and log likelihood probability soft merging on the second synchronization signal block log likelihood probability according to the system frame number index using at least one soft merging module connected to the same de-rate matching module; wherein, different soft merging modules connected to the same de-rate matching module correspond to different system frame number indices. The decoding and verification module connected to the soft merging module performs decoding and cyclic redundancy code verification on the log-likelihood probability of the third synchronization signal block to obtain the decoded data and verification results. The de-rate matching module, the soft merging module, and the decoding verification module are implemented using hardware circuits. The data detection method further includes at least one of the following steps: The control is implemented by inputting the synchronization signal block index into the derate matching module via software or hardware circuitry. The control is implemented by inputting the log-likelihood probability of the first synchronization signal block into the solution rate matching module via software or hardware circuitry. The control determines whether the second synchronization signal block log likelihood probability is obtained by performing second-order scrambling and de-repetition rate matching on the log likelihood probability of the first synchronization signal through the de-rate matching module, or by performing second-order scrambling and de-repetition rate matching on the log likelihood probability of the first synchronization signal through software. The system frame number index is input into the soft merging module via either software or hardware circuitry.

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