Communication system and communication device
By using buffer queues and pointer mechanisms between the processor and the transmitter, data transmission is achieved without a network card chip, solving the problem of high cost of communication equipment, reducing equipment costs and improving adaptability.
Patent Information
- Application Number
- CN202310822701.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-05
- Publication Date
- 2025-01-07
AI Technical Summary
In existing communication equipment, due to the high cost of network card chips, the equipment costs are high, making it difficult to achieve effective data transmission without network card chips.
Data cache and cache are achieved by using send and receive queues, write description buffer queues and read description buffer queues between processors and transmitters, and using write pointers and read pointers to determine empty buffers and non-empty buffers. Obtaining avoids dependence on network card chips.
In the absence of a network card chip, data transmission between the processor and the transmitter is realized, which reduces the cost of communication equipment and improves the adaptability and flexibility of the equipment.
Smart Images
Figure CN119276821A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of communication technology, and in particular to a communication system and communication equipment. Background Art
[0002] The communication equipment in mobile communication (such as satellite communication) includes a central processing unit (CPU), a network card chip and a field programmable gate array (FPGA).
[0003] In the related technology, the CPU can cache the data to be sent by the CPU to the network card chip through the Data Plane Development Kit (DPDK), and the FPGA can obtain the data from the network card chip; the FPGA can send the data to be received by the CPU to the network card chip, and the CPU can obtain the data from the network card chip.
[0004] In the above-mentioned related technologies, the price of the network card chip that can adapt to DPDK is usually relatively expensive, which leads to a high cost of the communication equipment. Summary of the invention
[0005] The embodiments of the present application provide a communication system and a communication device, which are used to solve the defect of high cost of communication devices in the prior art and achieve the purpose of reducing the cost of communication devices.
[0006] In a first aspect, an embodiment of the present application provides a communication system, including:
[0007] A processor, configured to, in a process of the processor sending data, determine a first empty buffer in a sending queue based on a first write pointer and flag bits of a plurality of write description buffers, cache the data to be sent to the first empty buffer, and send a data fetch message to a transmitter; in a process of the processor receiving data, determine a second non-empty buffer in a receiving queue based on a second read pointer and flag bits of a plurality of read description buffers, and obtain the data to be received from the second non-empty buffer;
[0008] The transmitter is used to, after receiving the data fetch message, determine a first non-empty buffer in the sending queue based on a first read pointer and the flag bits of the multiple write description buffers, and obtain the data to be sent from the first non-empty buffer; when the processor is receiving data, determine a second empty buffer in the receiving queue based on a second write pointer and the flag bits of the multiple read description buffers, and cache the data to be received to the second empty buffer.
[0009] In some embodiments, the sending queue includes a plurality of write buffers, and the plurality of write description buffers correspond one to one with the plurality of write buffers;
[0010] The processor determines a first empty buffer in a sending queue based on a first write pointer and flag bits of a plurality of write description buffers, including:
[0011] Determine whether a flag bit of a write description buffer currently pointed to by the first write pointer among the multiple write description buffers is a first identifier;
[0012] If it is the first identifier, the write buffer corresponding to the write description buffer currently pointed to by the first write pointer in the sending queue is determined as the first empty buffer.
[0013] In some embodiments, the processor is further configured to:
[0014] Add a frame header to the original data to be sent to obtain the data to be sent;
[0015] The frame header includes one or more of the following:
[0016] Header information, used to instruct a target processor receiving the data to be sent to determine whether the original data is data of a target communication process;
[0017] Forwarding information, used to indicate whether the transit processor receiving the data to be sent is the target processor;
[0018] Length information, used by the target processor and / or the transit processor to verify whether the original data is correct;
[0019] Encryption and decryption information, indicating whether the target processor and / or the transit processor encrypts the data to be sent;
[0020] Reserved bytes.
[0021] In some embodiments, after buffering the data to be sent in the first empty buffer, the processor is further configured to:
[0022] Setting the flag bit of the write description buffer currently pointed to by the first write pointer to a second flag;
[0023] Filling attribute information in the write description buffer currently pointed to by the first write pointer, wherein the attribute information is used by the transmitter to obtain data to be sent from the write buffer corresponding to the write description buffer currently pointed to by the first write pointer;
[0024] The first write pointer is increased by a preset value.
[0025] In some embodiments, the attribute information includes one or more of the following:
[0026] The length of the original data;
[0027] the address of the first empty buffer in the transmit queue;
[0028] Reserve space.
[0029] In some embodiments, the transmitter determines a first non-empty buffer in the sending queue based on the first read pointer and flag bits of the plurality of write description buffers, comprising:
[0030] Determine whether the flag bit of the write description buffer currently pointed to by the first read pointer among the multiple write description buffers is a second identifier;
[0031] If it is the second identifier, the write buffer corresponding to the write description buffer currently pointed to by the first read pointer in the sending queue is determined as the first non-empty buffer.
[0032] In some embodiments, the transmitter obtains the data to be sent from the first non-empty buffer, comprising:
[0033] Based on the attribute information in the write description buffer currently pointed to by the first read pointer, the data to be sent is obtained from the first non-empty buffer.
[0034] In some embodiments, after obtaining the data to be sent from the first non-empty buffer, the transmitter is further configured to:
[0035] Setting the flag bit of the write description buffer currently pointed to by the first read pointer to a first flag;
[0036] The first read pointer is increased by a preset value.
[0037] In some embodiments, the transmitter and the processor transmit the data to be sent via a first bus;
[0038] The first bus is any one of the following:
[0039] Serial Rapid Input / Output Bus;
[0040] A high-speed serial computer expansion bus standard.
[0041] In a second aspect, an embodiment of the present application further provides a communication device, comprising: a communication system as described in any one of the above aspects.
[0042] The communication system and communication device provided by the embodiment of the present application, in the process of the processor sending data, the processor determines the first empty buffer in the sending queue based on the first write pointer and the flag bits of multiple write description buffers, caches the data to be sent to the first empty buffer, and sends a data fetch message to the transmitter; the transmitter is used to determine the first non-empty buffer in the sending queue based on the first read pointer and the flag bits of the multiple write description buffers after receiving the data fetch message, and obtains the data to be sent from the first non-empty buffer, so that the processor sends data to the transmitter in the absence of a network card chip. In the process of the processor receiving data, the processor determines the second non-empty buffer in the receiving queue based on the second read pointer and the flag bits of multiple read description buffers, and obtains the data to be received from the second non-empty buffer; the transmitter determines the second empty buffer in the receiving queue based on the second write pointer and the flag bits of multiple read description buffers, and caches the data to be received to the second empty buffer, so that the processor receives the data sent by the transmitter in the absence of a network card chip, saving the cost of the communication equipment. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0044] Figure 1 It is a structural diagram of a high-performance network processing framework based on DPDK in the related technology;
[0045] Figure 2 is a schematic diagram of the structure of a communication system provided in an embodiment of the present application;
[0046] Figure 3 It is a schematic diagram of a process of sending data by a processor provided in an embodiment of the present application;
[0047] Figure 4 It is a schematic diagram of a process of a processor receiving data provided by an embodiment of the present application;
[0048] Figure 5 It is a structural diagram of data forwarding provided in an embodiment of the present application;
[0049] Figure 6 It is a structural diagram of data forwarding provided in an embodiment of the present application. DETAILED DESCRIPTION
[0050] In the embodiments of the present application, the term "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.
[0051] In the embodiments of the present application, the term "plurality" refers to two or more than two, and other quantifiers are similar.
[0052] The communication device in the related art has the following Figure 1 The network processing framework shown.
[0053] Figure 1 Schematic diagram of the structure of a high-performance network processing framework based on DPDK in the related art. Figure 1 As shown, the architecture includes: CPU 1, FPGA, CPU 2, DPDK 1 corresponding to CPU 1, and DPDK 1 corresponding to CPU 2. It should be noted that Figure 1 This example is based on an FPGA and two CPUs. In actual applications, Figure 1 More CPUs and FPGAs can be included.
[0054] In the related art, when CPU 1 sends data to CPU 2, CPU 1 can cache the data to be sent by CPU 1 in NIC chip 1 through DPDK 1. FPGA can obtain data from NIC chip 1 and transmit the data to NIC chip 2, so that CPU 2 can obtain data from NIC chip 2 through DPDK 2.
[0055] In the above-mentioned related technologies, the price of the network card chip that can adapt to DPDK is usually relatively expensive, which leads to Figure 1 The communication equipment of the network processing framework is relatively expensive.
[0056] In order to reduce the cost of communication equipment, an embodiment of the present application discloses a communication system. The communication system provided by the embodiment of the present application is described below in conjunction with specific embodiments.
[0057] Figure 2 Schematic diagram of the structure of the communication system provided by the embodiment of the present application. Figure 2 As shown, the communication system includes a processor 101 and a transmitter 102. The processor is, for example, a CPU, and the transmitter is, for example, an FPGA.
[0058] When the processor sends data, the processor 101 controls the first write pointer and the transmitter 102 controls the first read pointer. When the processor receives data, the processor 101 controls the second read pointer and the transmitter 102 controls the second write pointer.
[0059] In order to implement data transmission (including sending and / or receiving data) between the processor 101 and the transmitter 102, a sending queue, a write description buffer queue, a receiving queue and a read description buffer queue are set in the present application.
[0060] The sending queue includes a plurality of write buffers, and the write description buffer queue includes a plurality of write description buffers. The plurality of write buffers and the plurality of write description buffers correspond one to one.
[0061] The write buffer is used to cache data to be sent by the processor 101, and the flag bit of the corresponding write description buffer is used to indicate whether the write buffer caches data to be sent by the processor 101.
[0062] The receiving queue includes a plurality of read buffers, and the read description buffer queue includes a plurality of read description buffers. The plurality of read buffers and the plurality of read description buffers correspond one to one.
[0063] The read buffer is used to cache data to be received by the processor 101 , and the flag bit of the corresponding read description buffer is used to indicate whether the read buffer caches the data to be received by the processor 101 .
[0064] During the CPU initialization process, the write description buffer queue is completely cleared, and the first read pointer controlled by the FPGA and the first write pointer controlled by the CPU both point to the head of the write description buffer queue; the read description buffer queue is filled with empty read buffers, and the flag bits of each read description buffer in the read description buffer queue are cleared, and the second write pointer controlled by the FPGA and the second read pointer controlled by the CPU both point to the head of the read description buffer queue.
[0065] Combine the following Figure 3 The process of sending data by the processor is described.
[0066] Figure 3 Schematic diagram of the process of sending data by the processor provided in the embodiment of the present application. Figure 3 As shown, it includes: a sending queue and a write description buffer queue. For example, the multiple write buffers included in the sending queue are Buffer-11 to Buffer-15. For example, the multiple write description buffers included in the write description buffer queue are Buffer-21 to Buffer-25. For example, Buffer-11 corresponds to Buffer-21.
[0067] The processor 101 is used to determine a first empty buffer in the sending queue based on the first write pointer (PW1+) and flags of multiple write description buffers, cache the data to be sent to the first empty buffer, and send a data fetch message to the transmitter 102.
[0068] In some embodiments, determining whether a flag bit of a write description buffer currently pointed to by a first write pointer (PW1+) among a plurality of write description buffers is a first flag;
[0069] If it is the first identifier, the write buffer corresponding to the write description buffer currently pointed to by the first write pointer (PW1+) in the sending queue is determined as the first empty buffer.
[0070] Optionally, the first identifier may be 0 or other identifiers.
[0071] For example, the write description buffer currently pointed to by the first write pointer (PW1+) is Buffer-23. If the flag bit of Buffer-23 is the first identifier, Buffer-13 is determined to be the first empty buffer.
[0072] The first identifier indicates that there is no cached data in the buffer corresponding to the description buffer, and the buffer is an empty buffer.
[0073] The transmitter 102 is used to determine a first non-empty buffer in the sending queue based on a first read pointer (PR1+) and flags of a plurality of write description buffers after receiving a data fetch message, and obtain data to be sent from the first non-empty buffer;
[0074] In some embodiments, determining whether a flag bit of a write description buffer currently pointed to by the first read pointer (PR1+) among a plurality of write description buffers is a second flag;
[0075] If it is the second identifier, the write buffer corresponding to the write description buffer currently pointed to by the first read pointer (PR1+) in the sending queue is determined as the first non-empty buffer.
[0076] Optionally, the second identifier may be 1, or may be other identifiers. It should be noted that the second identifier is different from the first identifier.
[0077] For example, the write description buffer currently pointed to by the first read pointer (PR1+) is Buffer-25. If the flag bit of Buffer-25 is the second flag, Buffer-15 is determined to be the first empty buffer.
[0078] The second identifier indicates that the buffer corresponding to the description buffer has data cached therein and is a non-empty buffer.
[0079] Combine the following Figure 4 The process of the processor receiving data is described below.
[0080] Figure 4 Schematic diagram of the process of receiving data by the processor provided in the embodiment of the present application. Figure 4As shown, it includes: a receiving queue and a read description buffer queue. For example, the multiple read buffers included in the receiving queue are Buffer-31 to Buffer-35. For example, the multiple read description buffers included in the read description buffer queue are Buffer-41 to Buffer-45. For example, Buffer-31 corresponds to Buffer-41.
[0081] like Figure 4 As shown, during the process of the processor receiving data, the processor 101 is used to determine a second non-empty buffer in the receiving queue based on the second read pointer (PR2+) and flags of multiple read description buffers, and obtain the data to be received from the second non-empty buffer.
[0082] In some embodiments, determining whether a flag bit of a read description buffer currently pointed to by a second read pointer (PR2+) among a plurality of read description buffers is a second identifier;
[0083] If it is the second identifier, the read buffer corresponding to the read description buffer currently pointed to by the second read pointer (PR2+) in the receiving queue is determined as the second non-empty buffer.
[0084] For example, when the read description buffer currently pointed to by the second read pointer (PR2+) is Buffer-45, if the flag bit of Buffer-45 is the second identifier, Buffer-35 is determined to be the second non-empty buffer.
[0085] The transmitter 102 is used to determine a second empty buffer in the receiving queue based on the second write pointer and flag bits of multiple read description buffers, and cache the to-be-received data into the second empty buffer.
[0086] In some embodiments, determining whether a flag bit of a read description buffer currently pointed to by a second write pointer (PW2+) among a plurality of read description buffers is a first flag;
[0087] If it is the first identifier, the read buffer corresponding to the read description buffer currently pointed to by the second write pointer (PW2+) in the receiving queue is determined as the second empty buffer.
[0088] For example, the read description buffer currently pointed to by the second write pointer (PW2+) is Buffer-44. If the flag bit of Buffer-44 is the first identifier, Buffer-34 is determined to be the second empty buffer.
[0089] In the communication system provided by the embodiment of the present application, in the process of the processor sending data, the processor determines the first empty buffer in the sending queue based on the first write pointer and the flag bits of multiple write description buffers, caches the data to be sent to the first empty buffer, and sends a data fetch message to the transmitter; the transmitter is used to determine the first non-empty buffer in the sending queue based on the first read pointer and the flag bits of the multiple write description buffers after receiving the data fetch message, and obtains the data to be sent from the first non-empty buffer, so that the processor sends data to the transmitter in the absence of a network card chip. In the process of the processor receiving data, the processor determines the second non-empty buffer in the receiving queue based on the second read pointer and the flag bits of the multiple read description buffers, and obtains the data to be received from the second non-empty buffer; the transmitter determines the second empty buffer in the receiving queue based on the second write pointer and the flag bits of the multiple read description buffers, and caches the data to be received to the second empty buffer, so that the processor receives the data sent by the transmitter in the absence of a network card chip, saving the cost of communication equipment.
[0090] In addition, the communication system provided in the embodiment of the present application realizes data transmission between the processor and the transmitter through a sending queue and a receiving queue, as well as multiple write description buffers and multiple read description buffers. Therefore, it can be adapted to application scenarios with a network card chip, and can also be adapted to application scenarios without a network card chip. It is lightweight and has high confidentiality requirements for lightweight satellite aerospace communications, and is suitable for a variety of operating systems (such as Linux, sylixos, etc.).
[0091] In some embodiments, after buffering the data to be sent in the first empty buffer, the processor is further configured to:
[0092] Setting the flag bit of the write description buffer currently pointed to by the first write pointer to the second flag;
[0093] Filling attribute information in the write description buffer currently pointed to by the first write pointer, the attribute information being used by the transmitter to obtain data to be sent from the write buffer corresponding to the write description buffer currently pointed to by the first write pointer;
[0094] The first write pointer is increased by a preset value.
[0095] For example, in the embodiment of the present application, the preset value is 1. Figure 2 On the basis of, the write description buffer currently pointed to by the first write pointer (PW1+) is Buffer-23. If the first write pointer (PW1+) is increased by 1, the write description buffer currently pointed to by the first write pointer (PW1+) is Buffer-24.
[0096] In some embodiments, the attribute information includes one or more of the following:
[0097] The length of the original data;
[0098] an address of a first empty buffer in the transmit queue;
[0099] Reserve space.
[0100] The original data is used to obtain the above-mentioned data to be sent.
[0101] In some embodiments, the transmitter obtains the data to be sent from the first non-empty buffer, including:
[0102] Based on the attribute information in the write description buffer currently pointed to by the first read pointer, the data to be sent is obtained from the first non-empty buffer.
[0103] In some embodiments, after acquiring the data to be sent from the first non-empty buffer, the transmitter is further configured to:
[0104] Setting the flag bit of the write description buffer currently pointed to by the first read pointer to a first flag;
[0105] The first read pointer is increased by a preset value.
[0106] In some embodiments, the transmitter and the processor transmit the data to be sent via the first bus;
[0107] The first bus is any one of the following:
[0108] Serial Rapid Input / Output Bus;
[0109] A high-speed serial computer expansion bus standard.
[0110] Unlike the prior art, in a DPDK-based communication device, only a single bus can be adapted between the CPU and the FPGA. In this application, since DPDK is not used between the CPU and the FPGA, the Serial Rapid I / O (SRIO) and PCIE (PCIE) buses can be adapted between the processor and the transmitter.
[0111] In some embodiments, the processor is further configured to:
[0112] Add a frame header to the original data to be sent to obtain the data to be sent.
[0113] The frame header includes one or more of the following:
[0114] Header information, used to instruct a target processor receiving the data to be sent to determine whether the original data is data of a target communication process;
[0115] Forwarding information, used to indicate whether the transit processor receiving the data to be sent is the target processor;
[0116] Length information, used by the target processor and / or the transit processor to verify whether the original data is correct;
[0117] Encryption and decryption information, indicating whether the target processor and / or transit processor encrypts the data to be sent;
[0118] Reserved bytes.
[0119] For example, the intermediate processor can be Figure 6 In CUP 3, the target processor can be, for example, Figure 6 CUP 2 in.
[0120] Optionally, the length of the header information may be 16 bits, the length of the forwarding information may be 8 bits, the length of the length information may be 16 bits, the length of the encryption and decryption information may be 8 bits, and the length of the reserved bytes may be 16 bits.
[0121] Unlike related technologies, in which a high-performance network processing framework based on DPDK (such as Figure 1 As shown in the figure, it is impossible to freely fill the frame header, so the expected data forwarding cannot be achieved. In the embodiment of the present application, a frame header is added to the original data to be sent to obtain the data to be sent. Since the frame header includes one or more of the header information, forwarding information, length information, encryption and decryption information and reserved bytes, data forwarding can be achieved.
[0122] On the basis of any of the above embodiments, the complete process of the processor sending data is described in detail in combination with 11) to 16) by taking the processor as a CPU and the transmitter as an FPGA as an example.
[0123] 11) When the CPU is about to send data, it determines whether the flag bit of the write description buffer currently pointed to by the first write pointer is the first flag.
[0124] 12) When the flag bit is the first flag, add a frame header to the original data to be sent to obtain the data to be sent, cache the data to be sent in the write buffer corresponding to the write description buffer currently pointed to by the first write pointer in the sending queue (i.e., the first empty buffer), fill the attribute information in the write description buffer currently pointed to by the first write pointer, set the flag bit of the write description buffer currently pointed to by the first write pointer to the second flag, increase the first write pointer by a preset value, and send a data fetch message to the transmitter.
[0125] 13) When the flag is the second flag, it means that the sending queue is full and data sending is stopped.
[0126] 14) After receiving the data fetch message, the FPGA polls to determine whether the flag bit of the write description buffer currently pointed to by the first read pointer is the second flag.
[0127] 15) When the flag bit is the second flag, based on the attribute information stored in the write description buffer currently pointed to by the first read pointer, obtain the data to be sent from the write buffer corresponding to the write description buffer currently pointed to by the first read pointer in the sending queue through direct memory access (DMA), set the flag bit of the write description buffer currently pointed to by the first read pointer to the first flag, and increase the first read pointer by a preset value.
[0128] 16) When the flag is the first mark, it means that the sending queue is an empty queue, and data acquisition stops at this time.
[0129] It should be noted that each time the FPGA receives a data fetch message, it executes 14) to 16).
[0130] On the basis of any of the above embodiments, the complete process of the processor receiving data is described in detail in combination with 21) to 26) by taking the processor as a CPU and the transmitter as an FPGA as an example.
[0131] 21) Before sending data to the CPU, the FPGA determines whether the flag bit of the read description buffer currently pointed to by the second write pointer is the first flag.
[0132] 22) When the flag bit is the first identifier, the data to be received is cached in the read buffer corresponding to the read description buffer currently pointed to by the second write pointer in the receiving queue, the flag bit of the read description buffer currently pointed to by the second write pointer is set to the second identifier, and the second write pointer is increased by a preset value.
[0133] 23) When the flag is the second flag, it means that the receiving queue is full and the FPGA stops sending data.
[0134] 24) The CPU determines whether the flag bit of the read description buffer currently pointed to by the second read pointer is the second identifier.
[0135] 25) When the flag bit is the second identifier, based on the attribute information stored in the read description buffer currently pointed to by the second read pointer, obtain the data to be received from the read buffer corresponding to the read description buffer currently pointed to by the second read pointer in the receiving queue, increase the second read pointer by a preset value, and set the flag bit of the read description buffer currently pointed to by the second read pointer to the first identifier.
[0136] 26) When the flag is the first mark, it means that the receiving queue is an empty queue and data reception is suspended.
[0137] Based on the above embodiments, Figure 5 The data transmission process is explained using two CPUs as an example.
[0138] Figure 5 Schematic diagram of the structure of data forwarding provided by the embodiment of the present application. Figure 5 As shown, it includes: CPU 1, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) 1, FPGA, CPU 2 and DDR SDRAM 2.
[0139] DDR SDRAM 1 includes a sending area 1 and a receiving area 1, and DDR SDRAM 2 includes a sending area 2 and a receiving area 2. Each sending area includes a sending queue and a write description buffer queue, and each receiving area includes a receiving queue and a read description buffer queue.
[0140] For example, CPU 1 can cache the data to be sent to sending area 1, FPGA can obtain the data to be sent from sending area 1, and store the data to be sent to receiving area 2, CPU 2 can obtain the data to be sent from receiving area 2. For example, CPU 2 can also cache the data to be sent to sending area 2, FPGA can obtain the data to be sent from sending area 2, and store the data to be sent to receiving area 1, CPU 1 can obtain the data to be sent from receiving area 1.
[0141] Based on the above embodiments, Figure 6 The data forwarding process is described using three CPUs.
[0142] Figure 6 Schematic diagram of the structure of data forwarding provided by the embodiment of the present application. Figure 6 As shown, it includes: CPU 1, DDR SDRAM 1, FPGA, CPU 2, DDR SDRAM 2, CPU 3 and DDR SDRAM 3.
[0143] For example, DDR SDRAM 1 includes a sending area 1, DDR SDRAM 2 includes a receiving area 2, and DDR SDRAM 3 includes a sending area 3 and a receiving area 3.
[0144] For example, CPU 1 caches the data to be sent to the sending area 1, FPGA can obtain the data to be sent from the sending area 1, and store the data to be sent to the receiving area 3, and CPU 3 can obtain the data to be sent from the receiving area 3. If CPU 3 determines that CPU 3 is not the target processor based on the forwarding information in the frame header of the data to be sent, the data to be sent is sent to the sending area 3, FPGA can obtain the data to be sent from the sending area 3, and store the data to be sent to the receiving area 2, and CPU 2 (for example, the target processor) obtains the data to be sent from the receiving area 2. If CPU 3 determines that CPU 3 is the target processor based on the forwarding information in the frame header of the data to be sent, the data to be sent is processed accordingly (for example, encryption and / or decryption, verification of whether the original data is correct, etc.).
[0145] It should be noted that in order to meet the platform requirements in the embodiment of the present application, the following two operations are performed.
[0146] Operation 1: Implement the platform structure of network card information. The parameters are consistent with the user-mode network card information platform structure. The structure parameters are configured by the user through the socket.
[0147] Operation 2: Provide a network card information platform structure configuration interface for the user state, and provide ioctl to configure the user state registration information to the kernel. The registration information includes:
[0148] Network card chip status (on or off);
[0149] Maximum Transmission Unit (MTU);
[0150] MAC address of the network card chip;
[0151] IP address of the network card chip;
[0152] The subnet mask of the network card chip;
[0153] The starting address and total size of the receive queue in DDR SDRAM;
[0154] The starting address and total size of the transmit queue in DDR SDRAM.
[0155] Unlike the prior art, in the prior art, the high-performance network processing framework based on DPDK cannot meet the platform requirements in the implementation process of UIO technology, resulting in poor code reusability and long development cycle. In the embodiment of the present application, since DPDK is not used, the platform requirements can be met, avoiding problems such as poor code reusability and long development cycle.
[0156] An embodiment of the present application also provides a communication device, including: the communication system in any of the above embodiments.
[0157] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A communication system, characterized in that: include: A processor, configured to determine a first empty buffer in a sending queue based on a first write pointer and flag bits of a plurality of write description buffers during data transmission by the processor, cache the data to be transmitted in the first empty buffer, and send a data fetch message to the transmitter; In the process of receiving data by the processor, based on the second read pointer and flag bits of multiple read description buffers, a second non-empty buffer is determined in the receiving queue, and data to be received is obtained from the second non-empty buffer; The transmitter is configured to, after receiving the data fetch message, determine a first non-empty buffer in the sending queue based on a first read pointer and flag bits of the plurality of write description buffers, and obtain data to be sent from the first non-empty buffer; In the process of the processor receiving data, based on the second write pointer and the flag bits of the multiple read description buffers, a second empty buffer is determined in the receiving queue, and the data to be received is cached in the second empty buffer.
2. The communication system according to claim 1, characterized in that The sending queue includes a plurality of write buffers, and the plurality of write description buffers correspond to the plurality of write buffers one by one; The processor determines a first empty buffer in a sending queue based on a first write pointer and flag bits of a plurality of write description buffers, including: Determine whether a flag bit of a write description buffer currently pointed to by the first write pointer among the multiple write description buffers is a first identifier; If it is the first identifier, the write buffer corresponding to the write description buffer currently pointed to by the first write pointer in the sending queue is determined as the first empty buffer.
3. The communication system according to claim 1 or 2, characterized in that: The processor is further configured to: Add a frame header to the original data to be sent to obtain the data to be sent; The frame header includes one or more of the following: Header information, used to instruct a target processor receiving the data to be sent to determine whether the original data is data of a target communication process; Forwarding information, used to indicate whether the transit processor receiving the data to be sent is the target processor; Length information, used by the target processor and / or the transit processor to verify whether the original data is correct; Encryption and decryption information, indicating whether the target processor and / or the transit processor encrypts the data to be sent; Reserved bytes.
4. The communication system according to claim 3, characterized in that: After buffering the data to be sent into the first empty buffer, the processor is further configured to: Setting the flag bit of the write description buffer currently pointed to by the first write pointer to a second flag; Filling attribute information in the write description buffer currently pointed to by the first write pointer, wherein the attribute information is used by the transmitter to obtain data to be sent from the write buffer corresponding to the write description buffer currently pointed to by the first write pointer; The first write pointer is increased by a preset value.
5. The communication system according to claim 4, characterized in that: The attribute information includes one or more of the following: The length of the original data; the address of the first empty buffer in the transmit queue; Reserve space.
6. The communication system according to claim 2, characterized in that: The transmitter determines a first non-empty buffer in the sending queue based on a first read pointer and flag bits of the plurality of write description buffers, comprising: Determine whether the flag bit of the write description buffer currently pointed to by the first read pointer among the multiple write description buffers is a second identifier; If it is the second identifier, the write buffer corresponding to the write description buffer currently pointed to by the first read pointer in the sending queue is determined as the first non-empty buffer.
7. The communication system according to claim 6, characterized in that: The transmitter obtains the data to be sent from the first non-empty buffer, comprising: Based on the attribute information in the write description buffer currently pointed to by the first read pointer, the data to be sent is obtained from the first non-empty buffer.
8. The communication system according to claim 7, characterized in that: After acquiring the data to be sent from the first non-empty buffer, the transmitter is further configured to: Setting the flag bit of the write description buffer currently pointed to by the first read pointer to a first flag; The first read pointer is increased by a preset value.
9. The communication system according to claim 1 or 2, characterized in that: The transmitter and the processor transmit the data to be sent via a first bus; The first bus is any one of the following: Serial Rapid Input / Output Bus; A high-speed serial computer expansion bus standard.
10. A communication device, characterized in that: include: The communication system according to any one of claims 1 to 9.