Multi-storage gated imaging system

Abstract

The invention relates to a multi-storage gated imaging system. A gated imaging system includes a pulsed illuminator configured to generate a plurality of light pulses and a pixel circuit. The pixel circuit includes: a photodiode configured to collect an image charge photogenerated in response to incident light; a floating diffusion coupled to receive the image charge from the photodiode; a sense node amplifier including a gate terminal coupled to the floating diffusion; and a storage network coupled between the photodiode and the floating diffusion. The storage network includes a plurality of memory nodes coupled in parallel between the photodiode and the floating diffusion. The storage network is configured to capture a plurality of depth slices between two consecutive ones of the light pulses.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors, and particularly, but not exclusively, to complementary metal oxide semiconductor (CMOS) image sensors. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance the functionality, performance metrics, and the like of the image sensors in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design and image acquisition processing. The technology used to manufacture image sensors has continued to advance rapidly. For example, the demand for higher resolution and lower power consumption has driven further miniaturization and integration of these devices.

[0003] A typical image sensor operates in response to image light from an external scene being incident on the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge upon absorbing the image light. The image charge generated by the pixel light can be measured as an analog output image signal on a column bit line that varies as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out from the column bit line as an analog image signal and converted to a digital value to generate a digital image (e.g., image data) representing the external scene. The analog image signals on the bit lines are coupled to a readout circuit that includes an input stage having an analog-to-digital conversion (ADC) circuit to convert those analog image signals from the pixel array into digital image signals. Summary of the invention

[0004] According to one aspect of the present disclosure, a gated imaging system is provided. The gated imaging system includes: a pulsed illuminator configured to generate a plurality of light pulses; and a pixel circuit including: a photodiode configured to collect image charges generated in response to incident light; a floating diffusion coupled to receive the image charges from the photodiode; a sense node amplifier coupled to the floating diffusion; and a storage network coupled between the photodiode and the floating diffusion, the storage network including a plurality of memory nodes coupled between the photodiode and the floating diffusion, wherein the storage network is configured to capture a plurality of depth slices between two consecutive light pulses in the light pulses.

[0005] According to another aspect of the present disclosure, a gated imaging system is provided. The gated imaging system includes: a pulsed illuminator configured to generate a plurality of light pulses; and a pixel circuit including: a photodiode configured to collect image charges photogenerated in response to incident light; and a plurality of depth slice storage circuits coupled to receive the photogenerated image charges from the photodiode, each depth slice storage circuit including: a floating diffusion coupled to receive the image charges from the photodiode; a sense node amplifier coupled to the floating diffusion; and at least one memory node coupled between the photodiode and the floating diffusion, wherein the depth slice storage circuit is configured to capture a plurality of depth slices between two consecutive ones of the light pulses.

[0006] According to another aspect of the present disclosure, a method for operating a pixel circuit is provided. The method includes: configuring a pulsed illuminator to generate a plurality of light pulses; coupling a floating diffusion between a photodiode and a sensing node amplifier, wherein the photodiode is configured to collect image charges generated in response to image light; coupling a storage network between the photodiode and the floating diffusion, wherein the storage network includes: a plurality of memory nodes coupled between the photodiode and the floating diffusion; and configuring the storage network to capture a plurality of depth slices between two consecutive light pulses in the light pulses. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0008] Figure 1 An example of an imaging system according to the teachings of the present disclosure is illustrated.

[0009] Figure 2A and 2B A schematic diagram illustrating an exemplary single storage pixel circuit in accordance with the teachings of the present disclosure is illustrated.

[0010] Figure 3A and 3B Schematic diagrams illustrating other exemplary multi-storage pixel circuits in accordance with the teachings of the present disclosure.

[0011] Figure 4 Illustrated is a timing diagram of a gated imaging system in accordance with the teachings of the present disclosure.

[0012] Figure 5 Illustrated is a timing diagram of an exemplary single storage pixel circuit in accordance with the teachings of the present disclosure.

[0013] Figure 6Illustrated is a timing diagram of an exemplary multi-storage pixel circuit in accordance with the teachings of the present disclosure.

[0014] Throughout the several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the various figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the various figures may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present disclosure. In addition, common but well-known elements that are useful or necessary in commercially feasible embodiments are generally not depicted in order to facilitate a less obstructed view of these various embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] Examples of gated imaging systems with pixel circuits that provide improved gated integration are disclosed. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the examples. However, one skilled in the art will recognize that the techniques described herein may be practiced without one or more of the specific details, or may be practiced with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0016] References throughout this specification to "one example" or "one embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the example is included in at least one example of the present disclosure. Thus, the appearances of the phrases "in one example" or "in one embodiment" in different places throughout the specification do not necessarily refer to the same example. Furthermore, in one or more examples, the particular features, structures, or characteristics may be combined in any suitable manner.

[0017] For ease of description, spatial relative terms (e.g., "below," "below," "above," "below," "above," "upper," "top," "bottom," "left," "right," "center," "middle," etc.) may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the various figures. It should be understood that, in addition to the orientations depicted in the various figures, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the various figures is rotated or flipped, the element described as being "below" or "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can encompass both the orientations above and below. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptors used herein are interpreted accordingly. In addition, it should also be understood that when an element is referred to as being "between" two other elements, the element can be the only element between the two other elements, or one or more intermediate elements may also be present.

[0018] Throughout this specification, several technical terms are used. These terms will assume their ordinary meaning in the art to which they belong, unless otherwise specifically defined herein or the context in which they are used would clearly imply otherwise. It should be noted that in this document, element names and symbols are used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0019] As will be discussed, various examples of gated imaging systems having pixel circuits that provide improved gated integration are disclosed. The gated imaging system includes a pulsed illuminator that illuminates a target object or scene with pulses of light and an electronic gate or shutter that controls the exposure of return light to the pixel. Gated integration involves accumulating multiple return light pulses from a specific distance, creating slices with specific range information ("depth slices"), timing the shutter pulses relative to the illuminator pulses, and using the time taken for each of the light propagation distances. In various examples, each frame may include thousands of slices of dynamic and variable depth that may be added together to form a frame. By precisely timing the gate or shutter to capture only light that has been reflected or scattered back from the target object or scene, the gated imaging system can eliminate noise and interference caused by ambient light or other sources. The gated imaging system is particularly useful for capturing images in fog, rain, and darkness.

[0020] It should be understood that a gated imaging system according to the teachings of the present disclosure can capture and accumulate multiple depth slices before reading out the multiple depth slices, thereby reducing the time delay between depth slices of the same frame and minimizing blur. A gated imaging system according to the teachings of the present disclosure can also capture and read out multiple depth slices between consecutive light pulses, resulting in lower power consumption of the pulsed illuminator. In addition, a gated imaging system according to the teachings of the present disclosure can include multiple storage components, each of which can store different depth slices and prevent information from being mixed.

[0021] Thus, as will be shown and described in various examples below, an exemplary gated imaging system includes a pulsed illuminator configured to generate a plurality of light pulses and a pixel array including a plurality of pixel circuits. Each pixel circuit includes a photodiode configured to collect image charge photogenerated in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a sense node amplifier coupled to the floating diffusion, and a storage network coupled between the photodiode and the floating diffusion. The storage network is configured to capture a plurality of depth slices between two consecutive ones of the light pulses.

[0022] For illustration purposes, Figure 1 An example of an imaging system 100 having a readout circuit 106 according to the teachings of the present disclosure is shown. In particular, Figure 1 The example depicted in illustrative imaging system 100 includes pixel array 102, bit lines 112, control circuitry 110, system controller 111, readout circuitry 106, function logic 108, and pulsed illuminator and controller 130. In one example, pixel array 102 is a two-dimensional (2D) array including a plurality of pixel circuits 104 (e.g., P1, P2, ..., Pn) arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data of a person, place, object, etc., which can then be used to reproduce an image of the person, place, object, etc.

[0023] In various examples, readout circuitry 106 may be configured to read out image signals via column bit lines 112. As will be discussed, in various examples, readout circuitry 106 may include an analog-to-digital converter (ADC) 107 in accordance with the teachings of the present disclosure. In the examples described, the digital image data values ​​produced by the analog-to-digital converter in readout circuitry 106 may then be received by function logic 108. Function logic 108 may simply store the digital image data or even manipulate the digital image data by applying post-process image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, etc.).

[0024] In one example, control circuit 110 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuit 110 may generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with a lighting effect such as a flash. Control circuit 110 and / or system controller 111 may control the operation of a pulsed illuminator and controller 130, which is configured to generate light pulses.

[0025] In one example, the imaging system 100 may be included in a digital camera, a cell phone, a laptop computer, an endoscope, a security camera, or an imaging device for an automobile, etc. In addition, the imaging system 100 may be coupled to other pieces of hardware, such as a processor (general purpose, etc.), a memory element, an output (USB port, wireless transmitter, HDMI port, etc.), a light / flash, an electrical input (keyboard, touch display, track pad, mouse, microphone, etc.), and / or a display. The other hardware may deliver instructions to the imaging system 100, extract image data from the imaging system 100, or process image data supplied by the imaging system 100.

[0026] Figure 2A and 2B A schematic diagram of an exemplary single storage pixel circuit 204 is illustrated in accordance with the teachings of the present disclosure. It should be appreciated that Figure 2A and 2B The pixel circuit 204 may be included in Figure 1 0 and 1. The example of pixel circuitry 104 in imaging system 100 is shown in FIG. 1, and similarly named and numbered elements described above are similarly coupled and function below.

[0027] refer to Figure 2A and 2B , pixel circuit 204 includes a photodiode 214 configured to collect image charge photogenerated in response to incident light, a floating diffusion 218 coupled to receive the image charge from photodiode 214, a transfer transistor 216 coupled between photodiode 214 and floating diffusion 218 to transfer the image charge from photodiode 214 to floating diffusion 218, and a photodiode reset transistor 242 coupled between photodiode 214 and a voltage source AVDD 240. Pixel circuit 204 also includes a sense node amplifier 220 (e.g., a source follower transistor having a gate terminal) coupled to floating diffusion 218 and to voltage source AVDD 240, and a row select transistor 222 coupled between sense node amplifier 220 (e.g., a source terminal of the source follower transistor) and bit line 212.

[0028] Pixel circuit 204 further includes a storage network 250 coupled between transfer transistor 216 and floating diffusion 218, and a network reset transistor 244 coupled between floating diffusion 218 and voltage source AVDD 240. In the illustrated example, storage network 250 includes a first depth slice transistor 252, a memory node 254, and a second depth slice transistor 256 coupled in series between transfer transistor 216 and floating diffusion 218. In various examples, memory node 254 can be a pinned memory node. Figure 2A In FIG, memory node 254 is represented as a third depth slice transistor configured as storage gate SG0. Figure 2B , the memory node 254 is represented as a storage diode SD. The memory node 254 may include other devices or structures for performing storage.

[0029] In various examples, the storage network 250 is configured to capture the Figure 1 130) generated by the pulsed illuminator 130 illustrated in FIG. 13A. In particular, the first depth slice transistor 252 and the second depth slice transistor 256 and the memory node 254 can be configured to allow image charge to flow to a storage component, such as the memory node 254 coupled between the first depth slice transistor 252 and the second depth slice transistor 256. In various examples, it can be appreciated that one or more of the first depth slice transistor 252 and the second depth slice transistor 256 and the memory node 254 can be omitted, and / or one or more additional devices or structures (e.g., transistors, diodes) can be added. For instance, in one example, the first depth slice storage transistor 252 can be omitted. Furthermore, in various examples, any one or more of the illustrated components (e.g., the transfer transistor 216) can be omitted.

[0030] In various examples, the photodiode reset transistor 242 is configured to reset the photodiode 214 each time the storage network 250 captures one or more of the depth slices. A readout circuit (e.g., the readout circuit 106) coupled to the pixel circuit 204 can be configured to read out the depth slices during a readout cycle after the storage network 250 captures the depth slices. In various examples, the network reset transistor 244 is configured to reset the storage network 250 at the end of the readout cycle.

[0031] Figure 3A and 3B Schematic diagram illustrating another exemplary multi-storage pixel circuit 304 according to the teachings of the present disclosure. It should be understood that Figure 3A and 3B The pixel circuit 304 may be included in Figure 1 1. Other examples of one of the pixel circuits 104 in the imaging system 100 are shown in , and similarly named and numbered elements described above are similarly coupled and function below.

[0032] First reference Figure 3A , the illustrated pixel circuit 304 includes a photodiode 314 configured to collect image charge photogenerated in response to incident light, a floating diffusion 318 coupled to receive the image charge from the photodiode 314, a transfer transistor 316 coupled between the photodiode 314 and the floating diffusion 318 to transfer the image charge from the photodiode 314 to the floating diffusion 318, and a photodiode reset transistor 342 coupled between the photodiode 314 and a voltage source AVDD 340. The pixel circuit 304 also includes a sense node amplifier 320 (e.g., a source follower transistor having a gate terminal) coupled to the floating diffusion 318 and to the voltage source AVDD 340, and a row select transistor 322 coupled between the sense node amplifier 320 (e.g., a source terminal of the source follower transistor) and the bit line 312.

[0033] The pixel circuit 304 further includes a storage network 350 coupled between the transfer transistor 316 and the floating diffusion 318, and a network reset transistor 344 coupled between the floating diffusion 318 and the voltage source AVDD 340. In the illustrated example, the storage network 350 includes a plurality of first depth slicing transistors 352a / b / c...n, a plurality of second depth slicing transistors 356a / b / c...n, and a plurality of storage nodes 354a / b / c...n coupled between the transfer transistor 316 and the floating diffusion 318. Although each storage node 354 is Figure 3A 3. Although illustrated as transistors (eg, storage gates SG0 / 1 / 2 . . . N), in various examples, one or more of the memory nodes 354a / b / c . . . n may be storage diodes, such as Figure 2B. In various examples, one or more of the memory nodes 354a / b / c…n may be pinned memory nodes. In various examples, the first depth slice storage transistor 352 and the second depth slice storage transistor 356 and one or more of the memory nodes 354 may be omitted. For example, in one example, the first depth slice storage transistor 352a / b / c…n may be omitted. Furthermore, in various examples, any one or more of the illustrated components (e.g., transfer transistor 316) may be omitted. In various examples, the floating diffusion 318 includes a plurality of floating diffusion portions FD0 319a, FD1 319b, FD2 319c, …, FDA 319n, and each floating diffusion portion 319a / b / c…n of the floating diffusion 318 may be coupled to a corresponding one of the depth slice transistors 356a / b / c…n, as shown.

[0034] In various examples, the storage network 350 is configured to capture the Figure 1 In particular, the depth slicing transistors 352, 356 and the memory node 354 may be configured to allow image charge to flow to a respective storage component, such as the memory node 354 coupled between the respective first depth slicing transistor 352 and the second depth slicing transistor 356 (which in the illustrated example is configured as a storage gate, e.g., SG0 / SG1 / SG2 / etc.).

[0035] Next reference Figure 3B , the illustrated pixel circuit 304 includes a photodiode 314 configured to collect image charge photogenerated in response to incident light, a photodiode reset transistor 342 coupled between the photodiode 314 and a voltage source AVDD 340, a transfer transistor 316 coupled to the photodiode 314, and a plurality of depth slice storage circuits 351a / b / c / etc. In the illustrated embodiment, each depth slice storage circuit 351 includes a floating diffusion FD0 / 1 / 2 / etc. 319a / b / c...n coupled to receive image charge from the photodiode 314, a first depth slice transistor 352a / b / c...n, a storage node 354a / b / c...n, and a second depth slice transistor 356a / b / c...n coupled between the photodiode 314 and the floating diffusion 319a / b / c...n.

[0036] Each depth slice storage circuit 351 may further include a network reset transistor 344a / b / c ... n coupled between the floating diffusion 319a / b / c ... n and the voltage source AVDD 340, a sense node amplifier 320a / b / c ... n (e.g., a source follower transistor having a gate terminal) coupled to the floating diffusion 319a / b / c ... n, and a row select transistor 322a / b / c ... n coupled between the sense node amplifier 320a / b / c ... n (e.g., a source terminal of the source follower transistor) and the bit line 312. In some embodiments, each depth slice storage circuit 351 is coupled to a unique bit line 312. In some embodiments, some or all of the depth slice storage circuits 351 are coupled to the same bit line 312.

[0037] Similar to Figure 3A In the embodiment illustrated in FIG. 1 , the depth slice storage circuit 351 may be configured to capture the depth slices generated by a pulsed illuminator (eg, Figure 1 In particular, the depth slicing transistors 352, 356 and the memory node 354 may be configured to allow image charge to flow to a corresponding storage component, such as the memory node 354 coupled between the respective first depth slicing transistor 352 and the second depth slicing transistor 356 (which in the illustrated example is configured as a storage gate, e.g., SG0 / SG1 / SG2 . . . SGN).

[0038] Although each memory node 354 Figure 3A 3. Although illustrated as transistors (eg, storage gates SG0 / 1 / 2 . . . N), in various examples, one or more of the memory nodes 354a / b / c . . . n may be storage diodes, such as Figure 2B . In various examples, one or more of the memory nodes 354a / b / c ... n can be pinned memory nodes. In various examples, the first depth slice storage transistor 352 and the second depth slice storage transistor 356 and one or more of the memory nodes 354 can be omitted. For example, in one example, the first depth slice storage transistor 352a / b / c ... n can be omitted. Furthermore, in various examples, any one or more of the illustrated components (e.g., transfer transistor 316) can be omitted.

[0039] In various examples, the photodiode reset transistor 342 is configured to reset the photodiode 314 whenever the storage network 350 or the depth slice storage circuit 351 captures one or more of the depth slices. A readout circuit (e.g., the readout circuit 106) coupled to the pixel circuit 304 can be configured to read out the depth slices during a readout cycle after the storage network 350 or the depth slice storage circuit 351 captures a depth slice between two consecutive light pulses. In various examples, the network reset transistor 344 is configured to reset the depth slice transistors 352, 356 and the memory node 354 at the end of the readout cycle.

[0040] Reference together Figure 3A and 3B In various examples, one or more of the depth slice transistors 352, 356 and the memory nodes 354 can be used to transmit and / or store ambient light before or after the depth slice is captured. In various examples, a plurality but not all of the depth slice transistors 352, 356 and / or groups of memory nodes 354 can be configured to share floating diffusions, row select transistors, sense node amplifiers, and bit lines. For example, in each depth slice storage circuit 351, the floating diffusion FD 319 can be coupled to a plurality of memory nodes 354.

[0041] Figure 4 The timing diagram of the gated imaging system according to the teachings of the present invention is illustrated. It should be understood that Figure 4 The timing diagram can be as follows Figure 1 00 and similarly named and numbered elements described above are similarly coupled and function similarly below.

[0042] In the illustrated example, the imaging system is configured to capture first, second, third, and fourth depth slices Slice0 470, Slice1 471, Slice2 472, and Slice3 473 before a readout cycle 480. In various examples, capturing each depth slice takes approximately 1 ms, and the readout cycle 480 lasts approximately 7 to 29 ms.

[0043] This is in contrast to the timing of conventional imaging systems where each depth slice is read out immediately after it is captured. In conventional imaging systems, the final image may contain blur because of the time delay between depth slices. Figure 4 An imaging system operating with the timing diagram illustrated in reduces, if not eliminates, blur by successively capturing depth slices before reading out the depth slices. It should be appreciated that the timing diagram may include fewer or more depth slices captured by the imaging system.

[0044] Figure 5 The timing diagram of an exemplary single storage pixel circuit according to the teachings of the present disclosure is illustrated. It should be understood that Figure 5 The timing diagram of may be an exemplary timing diagram of the pixel circuit 204 as shown in FIG. 2 , and similarly named and numbered elements described above are similarly coupled and function below.

[0045] Pulsed illuminators (e.g. Figure 1 The pulsed illuminator 130 illustrated in FIG. 1 may be configured to generate multiple light pulses. Two such light pulses are shown in the illustrated example. After the rising edge of the first light pulse, a memory node (e.g., a transistor, a diode) included in the memory network of the pixel circuit (e.g., a memory node 254 included in the memory network 250 of the pixel circuit 204) may be configured to pulse for each of the depth slices between two consecutive light pulses. In the illustrated example, a first depth slice Slice0 570, a second depth slice Slice1 571, a third depth slice Slice2 572, and a fourth depth slice Slice3 573 are captured. This allows the image charge collected by the photodiode in response to all depth slices to be integrated in a single storage component, which is convenient in FIG. 1 . Figure 5 554 (eg, in memory node 254).

[0046] In various examples, one of the memory nodes (e.g., one of the memory nodes 354) may be configured to be pulsed after the previous light pulse and long after all depth slices have been captured by the imaging system but still between two consecutive light pulses. This allows the image charge collected by the photodiode in response to ambient light 585 to be integrated in the storage component corresponding to the ambient light memory node. Although as shown, the pulse integration depicted in integrating in storage device 0 554 may overlap with the light pulse 530, in various embodiments, integrating in storage device 0 554 and integrating in storage device A 564 are configured to be pulsed during non-overlapping time periods. In fact, in the illustrated first timing sequence 582 and second timing sequence 584, there is a timing gap 590 between the final pulse integrated in storage device 0 554 (i.e., corresponding to the capture of the fourth depth slice Slice3 573) and the pulse integrated in storage device A 564. The timing gap 590 allows a sufficient integration period for the ambient light 585, which can be used as a black level subtracted from the captured depth slices 570, 571, 572, 573 immediately after readout.

[0047] In a first timing sequence 582 that captures all depth slices between each pair of consecutive light pulses, the cycle repeats with a new light pulse 530 (e.g., a second light pulse in the illustrated example) after a pulse of the ambient light memory node. It should be appreciated that the memory node may capture fewer or more depth slices. In a second timing sequence 584, one or more depth slices may be omitted intermittently. In the illustrated second timing sequence 584, no depth slices are omitted after the first light pulse, slice 0 is omitted after the second light pulse, no depth slices are omitted after the third light pulse, and both slices 0 and 1 are omitted after the fourth light pulse. In various examples, other timing sequences that omit one or more depth slices are used.

[0048] In various examples, the photodiode of the pixel circuit operating according to the illustrated timing diagram can be configured to be reset by a photodiode reset transistor (e.g., photodiode reset transistor 242) whenever a depth slice is captured. In various examples, the storage network including the depth slice storage transistor and the ambient light storage transistor can be configured to be reset by a network reset transistor (e.g., network reset transistor 244) at the end of a readout cycle.

[0049] Figure 6 The timing diagram of an exemplary multi-storage pixel circuit according to the teachings of the present disclosure is illustrated. It should be understood that Figure 6 The timing diagram of may be an exemplary timing diagram of the pixel circuit 304 as shown in FIG. 3 , and similarly named and numbered elements described above are similarly coupled and function below.

[0050] Pulsed illuminator 630 (e.g., Figure 1 The pulsed illuminator 130 illustrated in FIG. 1 may be configured to generate multiple light pulses. Two such light pulses are shown in the illustrated example. After the rising edge of the first light pulse, each of the multiple memory nodes included in the storage network of the pixel circuit (e.g., the memory nodes 354a / b / c…n included in the storage network 350 of the pixel circuit 304) may be configured to pulse for a corresponding one of the depth slices between two consecutive light pulses. In the illustrated example, the first depth slice Slice0 670 is captured via the first memory node 654a, the second depth slice Slice1 671 is captured via the second memory node 654b, the third depth slice Slice2 672 is captured via the third memory node 654c, and the fourth depth slice Slice3 673 is captured via the fourth memory node 654d. This allows the image charge collected by the photodiode in response to each depth slice to be integrated in different storage components, which is Figure 6654a, integrated in storage device 1 654b, integrated in storage device 2 654c, and integrated in storage device 3 654d (eg, in storage nodes 354a / b / c . . . n).

[0051] In various examples, one of the memory nodes (e.g., one of the memory nodes 354) may be configured to be pulsed long after the previous light pulse and after all depth slices have been captured by the imaging system but still between two consecutive light pulses. This allows the image charge collected by the photodiode in response to ambient light 685 to be integrated in the ambient light memory node. Although the pulse integration depicted as integrating in memory device 0 654a, integrating in memory device 1 654b, etc. may overlap with the light pulse 630, as shown, in various embodiments, integrating in memory device 0 654a, integrating in memory device 1 654b, etc., and integrating in memory device A 664 are configured to be pulsed during non-overlapping time periods. In fact, in the illustrated timing sequence 682, there is a timing gap 690 between the pulse corresponding to the last integration of the capture of the fourth depth slice Slice3 673 (i.e., integrating in memory device 3 654d) and the pulse integrated in memory device A 664. The timing gap 690 allows a sufficient integration period for the ambient light 685, which can be used as a black level subtracted from the captured depth slices 670, 671, 672, 673 immediately after readout.

[0052] After the pulse of the memory node is configured to integrate the charge collected by the photodiode in response to ambient light, the cycle described above repeats with a new light pulse 630 (e.g., the second light pulse in the illustrated example). It should be appreciated that fewer or more depth slice storage transistors and / or memory nodes may be used to capture fewer or more depth slices per cycle. For example, four integrations (e.g., 654a-d) may be pulsed between the first light pulse 630 and the second light pulse 630, three integrations (e.g., 654b-d) may be pulsed between the second light pulse 630 and the third light pulse 630, two integrations (e.g., 654c-d) may be pulsed between the third light pulse 630 and the fourth light pulse 630, and one integration (e.g., 654d) may be pulsed between the fourth light pulse 630 and the fifth light pulse 630. In some embodiments, the number of integrations between two consecutive light pulses 630 and the timing of each integration pulse may vary randomly between cycles. In some embodiments, the number of integrations between two consecutive light pulses 630 may vary between cycles in a predictable manner (eg, linearly, exponentially, following a normal distribution, etc.).

[0053] In various examples, the photodiode of a pixel circuit operating according to the illustrated timing diagram can be configured to be reset by a photodiode reset transistor (e.g., photodiode reset transistor 342) whenever a depth slice is captured. In various examples, a storage network including a depth slice storage transistor and an ambient light storage transistor can be configured to be reset by a network reset transistor (e.g., network reset transistor 344) at the end of a readout cycle.

[0054] The single storage pixel circuits illustrated in FIGS. 2 and 5 and the multi-storage pixel circuits illustrated in FIGS. 3 and 6 differ in several respects. For example, the single storage pixel circuit provides a simpler circuit design because only one memory node is required. If a first depth slice transistor and a second depth slice transistor are also included for each memory node, as illustrated in FIGS. 2 and 3 (i.e., a first depth slice transistor 252 / 352 and a second depth slice transistor 256 / 356), the difference in circuit design complexity is amplified. However, because all depth slices are captured and stored in a single storage component in a single storage pixel circuit, the information may become mixed and the depth slices may become less distinguishable. In contrast, different depth slices are captured and stored in different storage components, allowing each depth slice to be read out separately and combined, for example, in a post-processing stage.

[0055] In order for a single storage pixel circuit to capture multiple depth slices, a readout period must be included between the integration of different depth slices, which may introduce blur in the combined image. Moreover, the same depth slice may be integrated multiple times in a single storage pixel circuit and then read out by pulsing a light pulse for each integration. However, this may result in more light pulses (e.g., twice) and longer integration and readout periods (e.g., 50% longer) than if a multiple storage pixel circuit captured and read out the same number of depth slices.

[0056] However, regardless of whether a single storage pixel circuit or a multi-storage pixel circuit is used, an imaging system according to the teachings of the present disclosure provides significant power consumption reduction and blur reduction. The power consumption of a pulsed illuminator can be significant, and because the same light pulse is shared between (or "reused" by) the capture of multiple depth slices, an imaging system according to the teachings of the present disclosure can capture the same number of depth slices with less power than a conventional imaging system that only captures and stores one depth slice between two consecutive light pulses. For example, if a conventional imaging system generates 25 light pulses for a first depth slice, 50 light pulses for a second depth slice, 100 light pulses for a third depth slice, and 200 light pulses for a fourth depth slice (i.e., a total of 375 light pulses), then an imaging system according to the teachings of the present disclosure can capture all four depth slices with only 200 light pulses, resulting in almost a 50% reduction in power consumption. Moreover, because multiple depth slices are accumulated prior to readout (see Figure 4 ), so there are few or no timing gaps between depth slices that cause blur. Alternatively, the imaging system can keep the number of light pulses the same (i.e., 375 total light pulses in the above example), but emit each pulse at a reduced power, allowing the use of a smaller and / or cheaper light source.

[0057] The above description of the illustrated examples of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific examples of the present disclosure are described herein for illustrative purposes, those skilled in the art will recognize that various modifications are possible within the scope of the present disclosure.

[0058] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the present disclosure to the specific examples disclosed in the specification. Rather, the scope of the present disclosure will be determined entirely by the following claims, which will be interpreted in accordance with established principles of claim interpretation.

Claims

1. A gated imaging system, comprising: a pulsed illuminator configured to generate a plurality of light pulses; as well as A pixel circuit comprising: a photodiode configured to collect image charge photogenerated in response to incident light; a floating diffusion coupled to receive the image charge from the photodiode; a sense node amplifier coupled to the floating diffusion; and a storage network coupled between the photodiode and the floating diffusion, the storage network comprising a plurality of storage nodes coupled between the photodiode and the floating diffusion, Wherein the storage network is configured to capture a plurality of depth slices between two consecutive ones of the light pulses. 2 . The gated imaging system of claim 1 , wherein each of the memory nodes is configured to be pulsed for a corresponding one of the depth slices between the two consecutive ones of the light pulses. 3 . The gated imaging system of claim 1 , wherein individual ones of the memory nodes comprise transistors or diodes.

4. The gated imaging system of claim 1 , wherein the pixel circuit further comprises a photodiode reset transistor coupled between the photodiode and a voltage source, wherein the photodiode reset transistor is configured to reset the photodiode each time the storage network captures one of the depth slices.

5. The gated imaging system of claim 1 , wherein the pixel circuit further comprises a network reset transistor coupled between the storage network and a voltage source, wherein the network reset transistor is configured to reset the storage network at the end of a readout cycle.

6. The gated imaging system of claim 1 , further comprising a readout circuit coupled to the pixel circuit and configured to read out the depth slice after the storage network captures the depth slice between two consecutive ones of the light pulses. 7 . The gated imaging system of claim 1 , wherein the pixel circuit is one of a plurality of pixel circuits included in a pixel array.

8. The gated imaging system of claim 1, wherein the floating diffusion comprises a plurality of floating diffusion portions, wherein each floating diffusion portion is coupled to at least one of the memory nodes.

9. The gated imaging system of claim 1, wherein the sense node amplifier comprises a source follower transistor, wherein the floating diffusion is coupled to a gate terminal of the source follower transistor.

10. A gated imaging system, comprising: a pulsed illuminator configured to generate a plurality of light pulses; as well as A pixel circuit comprising: a photodiode configured to collect image charge photogenerated in response to incident light; and a plurality of depth slice storage circuits coupled to receive the photogenerated image charge from the photodiode, each depth slice storage circuit comprising: a floating diffusion coupled to receive the image charge from the photodiode; a sense node amplifier coupled to the floating diffusion; and at least one memory node coupled between the photodiode and the floating diffusion, The depth slice storage circuit is configured to capture a plurality of depth slices between two consecutive ones of the light pulses.

11. The gated imaging system of claim 10, wherein each memory node is configured to be pulsed for a corresponding one of the depth slices between the two consecutive ones of the light pulses.

12. The gated imaging system of claim 10, wherein each depth slice storage circuit further comprises a network reset transistor coupled between the floating diffusion and a voltage source, wherein the network reset transistor is configured to reset the memory node at the end of a readout cycle.

13. The gated imaging system of claim 10, wherein the sense node amplifier comprises a source follower transistor, wherein the floating diffusion is coupled to a gate terminal of the source follower transistor.

14. A method of operating a pixel circuit, comprising: configuring the pulsed illuminator to generate a plurality of light pulses; coupling a floating diffusion between a photodiode configured to collect image charge photogenerated in response to image light and a sense node amplifier; A storage network is coupled between the photodiode and the floating diffusion, the storage network comprising: a plurality of memory nodes coupled between the photodiode and the floating diffusion; and The storage network is configured to capture a plurality of depth slices between two consecutive ones of the light pulses.

15. The method according to claim 14, further comprising: One or more of the memory nodes are configured to be pulsed for a corresponding one of the depth slices between the two consecutive ones of the light pulses.

16. The method according to claim 14, further comprising: Each of the memory nodes is configured to be pulsed for a corresponding one of the depth slices between the two consecutive ones of the light pulses.

17. The method of claim 14, wherein individual ones of the memory nodes comprise transistors or diodes.

18. The method of claim 14, further comprising: coupling a photodiode reset transistor between the photodiode and a voltage source; and The photodiode reset transistor is configured to reset the photodiode each time the storage network captures one of the depth slices.

19. The method of claim 14, further comprising coupling a network reset transistor between the storage network and a voltage source; and The network reset transistor is configured to reset the memory network at the end of a read cycle.

20. The method of claim 14, further comprising: coupling the pixel circuit to a readout circuit; and The readout circuit is configured to read out the depth slice after the storage network captures the depth slice between two consecutive ones of the light pulses.

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